Re: [PATCH 4/4] ARM: dts: Add LCD panel sharp ls037v7dw01 support for omap3-evm and ldp
On 28/05/14 00:14, Tony Lindgren wrote:
FYI, I'm getting this with current linux next:
omapfb omapfb: failed to allocate framebuffer
omapfb omapfb: failed to allocate fbmem
omapfb omapfb: failed to setup omapfb
omapfb: probe of omapfb failed with error -12
You need the attached patch to fix linux-next's dma alloc.
Tomi
From 88275fcdf6e7545e66fe35b822a41c9c017656f2 Mon Sep 17 00:00:00 2001
From: Vlastimil Babka vba...@suse.cz
Date: Fri, 23 May 2014 10:18:56 +0200
Subject: [PATCH]
mm-compaction-properly-signal-and-act-upon-lock-and-need_sched-contention-fix2
Step 1: Change function name and comment between v1 and v2 so that the return
value signals the opposite thing.
Step 2: Change the call sites to reflect the opposite return value.
Step 3: ???
Step 4: Make a complete fool of yourself.
Signed-off-by: Vlastimil Babka vba...@suse.cz
---
mm/compaction.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mm/compaction.c b/mm/compaction.c
index a525cd47a9d5..51750197db11 100644
--- a/mm/compaction.c
+++ b/mm/compaction.c
@@ -237,13 +237,13 @@ static inline bool compact_should_abort(struct compact_control *cc)
if (need_resched()) {
if (cc-mode == MIGRATE_ASYNC) {
cc-contended = true;
- return false;
+ return true;
}
cond_resched();
}
- return true;
+ return false;
}
/* Returns true if the page is within a block suitable for migration to */
--
1.9.1
signature.asc
Description: OpenPGP digital signature
Re: [PATCH 4/4] ARM: dts: Add LCD panel sharp ls037v7dw01 support for omap3-evm and ldp
On 27/05/14 23:59, Tony Lindgren wrote: In case you did not yet do it, here's this patch updated for you. I'm assuming you'll apply this to your panel dts branch. Let me know when the dependencies are in linux next and I'll test it one more time. The omap changes finally hit linux next as of today, so I'm only doing fixes and minimal changes for now. I haven't pushed the dts changes to linux-next as the base branch was missing. Now that it's there, I have pushed the DSS dts changes also. You can do a manual merge if you want to try before linux-next is updated: git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux.git for-next Tomi signature.asc Description: OpenPGP digital signature
Re: [PATCH v2 0/7] mfd: twl4030-power: Enable off-idle configuration when booted with device tree
Here's an updated set of patches to enable low-power idle modes for some omap3 boards when booted with device tree. This series when applied on top of the patches in tread [PATCH 00/11] Fixes for omap PM for making omap3 DT only, or omap-for-v3.16/pm branch. Lee, if these patches look OK to you, please feel free to pick them, preferrably to the immutable branch you already have set up so I can also merge them in to be able to have things working in my branch properly for PM. Whoops, nearly forgot about this patchset. Tony, can you resend it with all your fix-ups please. The 8 doesn't work well with my patch application 'system'. Sure I'll do that. FYI, these kind of patches should apply just fine when piped to git-am --scissors. It's not that - the patches would apply just fine individually. However my mailer stores the patches in date order, so when I use `git am mbox-folder` it attempts to apply them OoO. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] mfd: Immutable branch between MFD and OMAP, due for v3.16
Thanks Tony, here's the pull-request: The following changes since commit 455c6fdbd219161bd09b1165f11699d6d73de11c: Linux 3.14 (2014-03-30 20:40:15 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/mfd-omap-v3.16-1 for you to fetch changes up to 43fef47f94a1ae46fb2720dada32fa3b5547bee2: mfd: twl4030-power: Add a configuration to turn off oscillator during off-idle (2014-05-28 08:06:18 +0100) Second immutable branch between MFD and OMAP due for the v3.16 merge window. Tony Lindgren (7): mfd: twl-core: Fix idle mode signaling for omaps when booted with device tree mfd: twl4030-power: Fix hang on reboot if sleep configuration was loaded earlier mfd: twl4030-power: Fix some defines for SW_EVENTS mfd: twl4030-power: Add generic reset configuration mfd: twl4030-power: Add recommended idle configuration mfd: twl4030-power: Add support for board specific configuration mfd: twl4030-power: Add a configuration to turn off oscillator during off-idle .../devicetree/bindings/mfd/twl4030-power.txt | 17 +- arch/arm/mach-omap2/omap_twl.c | 60 - drivers/mfd/twl-core.c | 15 ++ drivers/mfd/twl4030-power.c| 286 +++-- include/linux/i2c/twl.h| 4 + 5 files changed, 296 insertions(+), 86 deletions(-) -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/5] Smart Card(SC) interface, TI USIM NxP SC phy driver
Changes since v2: * RFC comments are fixed for all * ti-usim: ** synchronous card support is added ** Timeout added for ATR ** BWT configuration ** softreset of IP at initialization added ** PM suspend/resume support added * sc_phy : sync card support is added * ARM: dts: AM43xx: fck clock entry is added to usim v1 cover letter link# https://lkml.org/lkml/2014/1/6/250 v2 cover letter link# https://lkml.org/lkml/2014/1/19/168 Satish Patel (5): sc_phy:SmartCard(SC) PHY interface to SC controller misc: tda8026: Add NXP TDA8026 PHY driver char: ti-usim: Add driver for USIM module on AM43xx ARM: dts: AM43xx: DT entries added for ti-usim ARM: dts: AM43xx-epos-evm: DT entries for ti-usim and phy Documentation/devicetree/bindings/misc/tda8026.txt | 19 + .../devicetree/bindings/ti-usim/ti-usim.txt| 32 + Documentation/sc_phy.txt | 171 ++ arch/arm/boot/dts/am4372.dtsi | 12 + arch/arm/boot/dts/am43x-epos-evm.dts | 31 + drivers/char/Kconfig |7 + drivers/char/Makefile |1 + drivers/char/ti-usim-hw.h | 864 drivers/char/ti-usim.c | 2213 drivers/misc/Kconfig |7 + drivers/misc/Makefile |1 + drivers/misc/tda8026.c | 1258 +++ include/linux/sc_phy.h | 136 ++ include/linux/ti-usim.h| 111 + 14 files changed, 4863 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt create mode 100644 Documentation/devicetree/bindings/ti-usim/ti-usim.txt create mode 100644 Documentation/sc_phy.txt create mode 100644 drivers/char/ti-usim-hw.h create mode 100644 drivers/char/ti-usim.c create mode 100644 drivers/misc/tda8026.c create mode 100644 include/linux/sc_phy.h create mode 100644 include/linux/ti-usim.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 5/5] ARM: dts: AM43xx-epos-evm: DT entries for ti-usim and phy
- Board specific DT entries for TI's USIM - smart card controller of AM43xx
platfrom.These entries are used by USIM driver for various configurations.
- Shutdown line of NXP phy is maped to GPIO5. So enabling same to have support
for NXP phy.
- i2c2 pinmux configuration - NxP tda8026 phy is connected to i2c2 lines
Signed-off-by: Satish Patel satish.pa...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..ecc8b1a 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -115,6 +115,18 @@
;
};
+ usim0_default: usim0_default {
+ pinctrl-single,pins =
+ /* USIM 0 */
+ 0x1B4 (SLEWCTRL_FAST | PULL_DISABLE | MUX_MODE8)
/* CLK0 */
+ 0x1B0 (SLEWCTRL_FAST | PULL_DISABLE | MUX_MODE8)
/* CLK1 */
+ 0x1B8 (SLEWCTRL_FAST | INPUT_EN | PULL_DISABLE |
MUX_MODE8) /* DATA0 */
+ 0x1BC (SLEWCTRL_FAST | INPUT_EN | PULL_DISABLE |
MUX_MODE8) /* DATA1 */
+ 0x1C8 (SLEWCTRL_FAST | INPUT_EN | PULL_UP |
MUX_MODE8) /* IRQn */
+ ;
+ };
+
+
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins =
0x150 (PIN_INPUT | MUX_MODE0) /*
spi0_clk.spi0_clk */
@@ -238,10 +250,24 @@
};
};
+usim0 {
+ pinctrl-names = default;
+ pinctrl-0 = usim0_default;
+ phy = tda8026;
+ phy-slots = 1;
+ status = okay;
+};
+
i2c2 {
pinctrl-names = default;
pinctrl-0 = i2c2_pins;
status = okay;
+ tda8026: tda8026@48 {
+ compatible = nxp,tda8026;
+ reg = 0x48;
+ shutdown-gpio = gpio5 19 GPIO_ACTIVE_HIGH; /* Bank5, pin19
*/
+ interrupts = GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH;
+ };
};
gpio0 {
@@ -260,6 +286,11 @@
status = okay;
};
+gpio5 {
+ status = okay;
+};
+
+
elm {
status = okay;
};
--
1.7.9.5
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Re: [PATCH v2 0/5] Smart Card(SC) interface, TI USIM NxP SC phy driver
On 5/28/2014 6:11 AM, Greg KH wrote: On Fri, May 16, 2014 at 09:14:34AM +0530, Satish Patel wrote: On 1/30/2014 6:35 PM, Greg KH wrote: On Thu, Jan 30, 2014 at 11:22:48AM +0530, Satish Patel wrote: On 1/20/2014 10:03 AM, Satish Patel wrote: Changes from v1: * RFC(v1) comments are fixed ** removed gpio_to_irq as GPIO controller process cell from DT and give it to DT node ** comments on documentation ** few other comments on null checks are resolved * BWT timing configuration is added to ti-usim driver v1 cover letter link# https://lkml.org/lkml/2014/1/6/250 Satish Patel (5): sc_phy:SmartCard(SC) PHY interface to SC controller misc: tda8026: Add NXP TDA8026 PHY driver char: ti-usim: Add driver for USIM module on AM43xx ARM: dts: AM43xx: DT entries added for ti-usim ARM: dts: AM43xx-epos-evm: DT entries for ti-usim and phy Documentation/devicetree/bindings/misc/tda8026.txt | 19 + .../devicetree/bindings/ti-usim/ti-usim.txt| 31 + Documentation/sc_phy.txt | 171 ++ arch/arm/boot/dts/am4372.dtsi | 10 + arch/arm/boot/dts/am43x-epos-evm.dts | 43 + drivers/char/Kconfig |7 + drivers/char/Makefile |1 + drivers/char/ti-usim-hw.h | 863 + drivers/char/ti-usim.c | 1859 drivers/misc/Kconfig |7 + drivers/misc/Makefile |1 + drivers/misc/tda8026.c | 1255 + include/linux/sc_phy.h | 132 ++ include/linux/ti-usim.h| 98 + 14 files changed, 4497 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt create mode 100644 Documentation/devicetree/bindings/ti-usim/ti-usim.txt create mode 100644 Documentation/sc_phy.txt create mode 100644 drivers/char/ti-usim-hw.h create mode 100644 drivers/char/ti-usim.c create mode 100644 drivers/misc/tda8026.c create mode 100644 include/linux/sc_phy.h create mode 100644 include/linux/ti-usim.h Any comments on this patch series ? If not, Can you accept these patches for next merge window It's the middle of this merge window, and I can't accept any patches until after 3.14-rc1 is out, at which point I'll start to work on my patch backlog. Are these to be consider for next submission ? Or you want me to start review cycle one more time. I don't have them in my queue, so please resend. I have resent patches for review. could you consider the same for next merge window ? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/5] ARM: dts: AM43xx: DT entries added for ti-usim
SoC specific DT entries added for TI's USIM - smart card controller of AM43xx
platfrom.
Signed-off-by: Satish Patel satish.pa...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d1f8707..fe830dd 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,18 @@
#size-cells = 1;
status = disabled;
};
+
+ usim0: usim@48034000 {
+ compatible = ti,usim;
+ reg = 0x48034000 0x1000;
+ interrupts = GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH;
+ ti,hwmods = usim0;
+ clocks = usim0_opt_fck, usim0_opt_fck32,
+dpll_per_m2_div4_ck;
+ clock-names = opt_fck, opt_fck32, fck;
+ status = disabled;
+ };
+
};
};
--
1.7.9.5
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[PATCH v3 2/5] misc: tda8026: Add NXP TDA8026 PHY driver
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave device.
The driver also exposes the phy interface
(defined@include/linux/sc_phy.h) for SmartCard controller.
Controller uses this interface to communicate with smart card
inserted to the phy's slot.
Note: gpio irq is not validated as I do not have device with that.
I have validated interrupt with dedicated interrupt line on my device.
Signed-off-by: Satish Patel satish.pa...@ti.com
---
Documentation/devicetree/bindings/misc/tda8026.txt | 19 +
drivers/misc/Kconfig |7 +
drivers/misc/Makefile |1 +
drivers/misc/tda8026.c | 1258
4 files changed, 1285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt
create mode 100644 drivers/misc/tda8026.c
diff --git a/Documentation/devicetree/bindings/misc/tda8026.txt
b/Documentation/devicetree/bindings/misc/tda8026.txt
new file mode 100644
index 000..f115c9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/tda8026.txt
@@ -0,0 +1,19 @@
+TDA8026 smart card slot interface
+
+This is an i2c based smart card interface device forming the electrical
+interface between a microcontroller and smart cards. This device supports
+asynchronous cards (micro controller-based IC cards) as well as synchronous
+cards (mainly memory cards)
+
+Required properties:
+- compatible: nxp,tda8026
+- shutdown-gpio = GPIO pin mapping for SDWNN pin
+- reg = i2c interface address
+
+
+Example:
+tda8026: tda8026@48 {
+compatible = nxp,tda8026;
+reg = 0x48;
+shutdown-gpio = gpio5 19 GPIO_ACTIVE_HIGH;/* Bank5, pin19 */
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8baff0e..80b21d7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -515,6 +515,13 @@ config SRAM
the genalloc API. It is supposed to be used for small on-chip SRAM
areas found on many SoCs.
+config NXP_TDA8026_PHY
+tristate NXP PHY Driver for Smart Card PHY
+depends on I2C=y
+help
+ If you say yes here you get support for the TDA8026 Smart card PHY
+ with I2C interface.
+
source drivers/misc/c2port/Kconfig
source drivers/misc/eeprom/Kconfig
source drivers/misc/cb710/Kconfig
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 7eb4b69..f262c0b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SRAM)+= sram.o
obj-y += mic/
obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
+obj-$(CONFIG_NXP_TDA8026_PHY) += tda8026.o
diff --git a/drivers/misc/tda8026.c b/drivers/misc/tda8026.c
new file mode 100644
index 000..38df33e
--- /dev/null
+++ b/drivers/misc/tda8026.c
@@ -0,0 +1,1258 @@
+/*
+ * tda8026.c - TDA8026 PHY driver for NXP Smart card PHY
+ *
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/moduleparam.h
+#include linux/interrupt.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/mfd/core.h
+#include linux/notifier.h
+#include linux/sc_phy.h
+#include linux/of_gpio.h
+#include linux/of_device.h
+#include linux/delay.h
+
+#define TDA8026_MAX_SLOTS (5)
+#define TDA8026_NUM_SAM_SLOTS (4)
+#define TDA8026_USERCARD_SLOT (1)
+
+#define TDA8026_CSB_ADDR (0x24)
+#define TDA8026_REG0_ADDR (0x20)
+#define TDA8026_REG1_ADDR (0x21)
+#define TDA8026_SLEWRATE_ADDR (0x20)
+#define TDA8026_PRODVER_ADDR (0x20)
+#define TDA8026_INTSTAT_ADDR (0x21)
+
+#define TDA8026_PHY_PRODUCT_VERSION(0xC2)
+
+/* CSB register values */
+#define TDA8026_CSB_PV_INTSTAT_VAL (0x0)
+#define TDA8026_CSB_SLEWRATE_VAL (0x6)
+
+/* Slot REG0 read mode bit fields */
+#define TDA8026_REG0_ACTIVE_MASK (0x80)
+#define TDA8026_REG0_EARLY_MASK(0x40)
+#define TDA8026_REG0_MUTE_MASK (0x20)
+#define TDA8026_REG0_PROT_MASK (0x10)
+#define TDA8026_REG0_SUPL_MASK (0x08)
+#define TDA8026_REG0_CLKSW_MASK(0x04)
+#define TDA8026_REG0_PREL_MASK (0x02)
+#define TDA8026_REG0_PRES_MASK (0x01)
+
+/* Slot REG0 write mode bit fields */
+#define TDA8026_REG0_VCC1V8_MASK
[PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h diff --git a/Documentation/sc_phy.txt b/Documentation/sc_phy.txt new file mode 100644 index 000..d610e26 --- /dev/null +++ b/Documentation/sc_phy.txt @@ -0,0 +1,171 @@ + SmartCard PHY Interface + Satish Patel satish.pa...@ti.com + +This document explains the SmartCard interface between SmartCard +controller and SmartCard phy. Document also describes how-to-use. + +1. Why SmartCard PHY Interface? + +The use of smartcard is increasing in embedded industry. As smartcard +not only prevent duplication but also, brings key based authentication +flow into picture. + +SmartCard standards like EMV(EuroPay-Mastercard-Visa) are becoming +mandatory for payment terminals. + +Till date, most of the SmartCard readers are based on USB serial +interface. Which drives its logic within firmware lies on device. +Few are based on FPGA solutions. But now SoCs are coming up with +inbuilt smartcard controller. e.g. TI-AM43x + +Role of SmartCard controller and SmartCard phy: + +Smartcard Phy: +Forms electrical interface between controller and SmartCard. Phy +enables access to more than one smartcard and in addition it provides +fast deactivation logic when card gets removed from the slot. It can +also generate the signals like card insert/remove/overheat etc. + +Smartcard Controller: +In built mechanism to meet EMV L1 specification (e.g. T=0, T=1 +protocol timings, ATR timeout etc..) for SmartCard transaction. In +addition to this, it has FIFO to store tx/rx bytes, internal state +machine for ATR, Tx/Rx, Synchronous/Asynchronous mode, timing +counters etc.. + +Controller can also have direct interface through which SmartCard +can be connected without phy. + +Below is the brief of SmartCard block diagram from user to h/w +layer. + + +--- +|PC/SC App| +--- +--- --- +|PC/SC F/W| | Visa APP| +--- --- +--- +|IFD Hand.| | EMV L1/L2|| Test App | +--- +User Space + + +- +| SmartCard Controller Driver| +- + | | + | | +- | +| Phy Driver | | +- | + | | +Kernel Space | | + + | | + - + | PHY | |Controller IP | + - +| | + +| | + ___ + ||| + VISA card Master Card Custom Card + + +At present in Linux there is no public interface exist which acts as +bridge between controller and phy. Mostly vendors uses proprietary +solution in such cases. + +2. Introduction to SmartCard PHY interface + +SmartCard PHY interface that exposes phy's capabilities to the smart +card controller. SmartCard controller uses this interface to +communicate with SmartCard via phy. + +Such capabilities are: +1) Some SmartCard phy (e.g. TDA8026-NxP) has multiple slots for smart +cards. This interface enables controller to communicate with specific +SmartCard inserted to the specific phy's slot. + +2) Warm reset to SmartCard inserted to phy slot. + +3) Bit banging of SmartCard pins to support vedor specific memory +cards. Mostly when it comes to sychorous SmartCard + +4) Notification of card insert/remove/overheat etc. + + +3. How to use + +SmartCard PHY: +The SmartCard PHY driver, who wants to be interfaced with SmartCard +controller require to follow below step + +- include sc_phy.h + +- use sc_phy structure as driver(client) data. PHY
[PATCH 3/9] mfd: palmas: Add tps65917 specific definitions and enums
Add tps65917 specific definitions and enums.
Signed-off-by: Keerthy j-keer...@ti.com
---
include/linux/mfd/palmas.h | 793
1 file changed, 793 insertions(+)
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index ccbb21f..52a24a9 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -30,6 +30,8 @@
#define PALMAS_CHIP_ID 0xC035
#define PALMAS_CHIP_CHARGER_ID 0xC036
+#define TPS65917_RESERVED -1
+
#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
((a) == PALMAS_CHIP_ID))
#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
@@ -184,6 +186,27 @@ enum palmas_regulators {
PALMAS_NUM_REGS,
};
+enum tps65917_regulators {
+ /* SMPS regulators */
+ TPS65917_REG_SMPS1,
+ TPS65917_REG_SMPS2,
+ TPS65917_REG_SMPS3,
+ TPS65917_REG_SMPS4,
+ TPS65917_REG_SMPS5,
+ /* LDO regulators */
+ TPS65917_REG_LDO1,
+ TPS65917_REG_LDO2,
+ TPS65917_REG_LDO3,
+ TPS65917_REG_LDO4,
+ TPS65917_REG_LDO5,
+ TPS65917_REG_REGEN1,
+ TPS65917_REG_REGEN2,
+ TPS65917_REG_REGEN3,
+
+ /* Total number of regulators */
+ TPS65917_NUM_REGS,
+};
+
/* External controll signal name */
enum {
PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
@@ -228,6 +251,24 @@ enum palmas_external_requestor_id {
PALMAS_EXTERNAL_REQSTR_ID_MAX,
};
+enum tps65917_external_requestor_id {
+ TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
+ TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
+ TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
+ TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
+ TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
+ TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
+ TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
+ TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
+ TPS65917_EXTERNAL_REQSTR_ID_LDO1,
+ TPS65917_EXTERNAL_REQSTR_ID_LDO2,
+ TPS65917_EXTERNAL_REQSTR_ID_LDO3,
+ TPS65917_EXTERNAL_REQSTR_ID_LDO4,
+ TPS65917_EXTERNAL_REQSTR_ID_LDO5,
+ /* Last entry */
+ TPS65917_EXTERNAL_REQSTR_ID_MAX,
+};
+
struct palmas_pmic_platform_data {
/* An array of pointers to regulator init data indexed by regulator
* ID
@@ -349,6 +390,48 @@ struct palmas_gpadc_result {
#define PALMAS_MAX_CHANNELS 16
+/* Define the tps65917 IRQ numbers */
+enum tps65917_irqs {
+ /* INT1 registers */
+ TPS65917_RESERVED1,
+ TPS65917_PWRON_IRQ,
+ TPS65917_LONG_PRESS_KEY_IRQ,
+ TPS65917_RESERVED2,
+ TPS65917_PWRDOWN_IRQ,
+ TPS65917_HOTDIE_IRQ,
+ TPS65917_VSYS_MON_IRQ,
+ TPS65917_RESERVED3,
+ /* INT2 registers */
+ TPS65917_RESERVED4,
+ TPS65917_OTP_ERROR_IRQ,
+ TPS65917_WDT_IRQ,
+ TPS65917_RESERVED5,
+ TPS65917_RESET_IN_IRQ,
+ TPS65917_FSD_IRQ,
+ TPS65917_SHORT_IRQ,
+ TPS65917_RESERVED6,
+ /* INT3 registers */
+ TPS65917_GPADC_AUTO_0_IRQ,
+ TPS65917_GPADC_AUTO_1_IRQ,
+ TPS65917_GPADC_EOC_SW_IRQ,
+ TPS65917_RESREVED6,
+ TPS65917_RESERVED7,
+ TPS65917_RESERVED8,
+ TPS65917_RESERVED9,
+ TPS65917_VBUS_IRQ,
+ /* INT4 registers */
+ TPS65917_GPIO_0_IRQ,
+ TPS65917_GPIO_1_IRQ,
+ TPS65917_GPIO_2_IRQ,
+ TPS65917_GPIO_3_IRQ,
+ TPS65917_GPIO_4_IRQ,
+ TPS65917_GPIO_5_IRQ,
+ TPS65917_GPIO_6_IRQ,
+ TPS65917_RESERVED10,
+ /* Total Number IRQs */
+ TPS65917_NUM_IRQ,
+};
+
/* Define the palmas IRQ numbers */
enum palmas_irqs {
/* INT1 registers */
@@ -400,6 +483,7 @@ struct palmas_pmic {
int smps123;
int smps457;
+ int smps12;
int range[PALMAS_REG_SMPS10_OUT1];
unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
@@ -2871,6 +2955,715 @@ enum usb_irq_events {
#define PALMAS_GPADC_TRIM150x0E
#define PALMAS_GPADC_TRIM160x0F
+/* TPS65917 Interrupt registers */
+
+/* Registers for function INTERRUPT */
+#define TPS65917_INT1_STATUS 0x00
+#define TPS65917_INT1_MASK 0x01
+#define TPS65917_INT1_LINE_STATE 0x02
+#define TPS65917_INT2_STATUS 0x05
+#define TPS65917_INT2_MASK 0x06
+#define TPS65917_INT2_LINE_STATE 0x07
+#define TPS65917_INT3_STATUS 0x0A
+#define TPS65917_INT3_MASK 0x0B
+#define TPS65917_INT3_LINE_STATE 0x0C
+#define TPS65917_INT4_STATUS 0x0F
+#define TPS65917_INT4_MASK 0x10
+#define TPS65917_INT4_LINE_STATE 0x11
+#define TPS65917_INT4_EDGE_DETECT1
[PATCH 0/9] mfd: tps65917: Add support for for TPS65917 PMIC
The TPS65917 chip is a power management IC for Portable Navigation Systems and Tablet Computing devices. It contains the following components: - Regulators. - GPADC. - Over Temperature warning and Shut down. This patch series adds support for TPS65917 mfd device. At this time only the regulator functionality is made available. The closest drivers are PALMAS series drivers. Hence adapted palmas mfd driver to support the tps65917 PMIC. The register set for SMPSs and LDOs are changed and the ramp delay support is also changed. Bit-field defenitions are changed. Hence added driver data structures for mfd and regulator drivers for palmas and added support for tps65917. The patches are boot tested on DRA72-EVM. The patches are boot tested on OMAP5-UEVM board. Keerthy (9): mfd: Add DT bindings for tps65917 PMIC regulator: palmas: Add tps65917 compatible string mfd: palmas: Add tps65917 specific definitions and enums mfd: palmas: Add tps65917 support regulator: palmas: Shift the reg_info structure definition to the header file mfd: palmas: shift the palmas_sleep_requestor_info structure definition to the header file regulator: palmas: Add palmas_pmic_driver_data structure regulator: palmas: add driver data and modularize the probe regulator: palmas: Add tps65917 PMIC support Documentation/devicetree/bindings/mfd/palmas.txt |2 + .../devicetree/bindings/regulator/palmas-pmic.txt |1 + drivers/mfd/palmas.c | 228 +++-- drivers/regulator/palmas-regulator.c | 1006 +++- include/linux/mfd/palmas.h | 837 5 files changed, 1770 insertions(+), 304 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/9] regulator: palmas: add driver data and modularize the probe
add driver data and modularize the probe.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/mfd/palmas.c | 42 +--
drivers/regulator/palmas-regulator.c | 656 --
2 files changed, 395 insertions(+), 303 deletions(-)
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index f1f31d5..d9a6051 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -25,42 +25,6 @@
#include linux/mfd/palmas.h
#include linux/of_device.h
-#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
- [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
- .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
- .reg_offset = _offset, \
- .bit_pos = _pos,\
- }
-
-static struct palmas_sleep_requestor_info sleep_req_info[] = {
- EXTERNAL_REQUESTOR(REGEN1, 0, 0),
- EXTERNAL_REQUESTOR(REGEN2, 0, 1),
- EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
- EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
- EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
- EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
- EXTERNAL_REQUESTOR(REGEN3, 0, 6),
- EXTERNAL_REQUESTOR(SMPS12, 1, 0),
- EXTERNAL_REQUESTOR(SMPS3, 1, 1),
- EXTERNAL_REQUESTOR(SMPS45, 1, 2),
- EXTERNAL_REQUESTOR(SMPS6, 1, 3),
- EXTERNAL_REQUESTOR(SMPS7, 1, 4),
- EXTERNAL_REQUESTOR(SMPS8, 1, 5),
- EXTERNAL_REQUESTOR(SMPS9, 1, 6),
- EXTERNAL_REQUESTOR(SMPS10, 1, 7),
- EXTERNAL_REQUESTOR(LDO1, 2, 0),
- EXTERNAL_REQUESTOR(LDO2, 2, 1),
- EXTERNAL_REQUESTOR(LDO3, 2, 2),
- EXTERNAL_REQUESTOR(LDO4, 2, 3),
- EXTERNAL_REQUESTOR(LDO5, 2, 4),
- EXTERNAL_REQUESTOR(LDO6, 2, 5),
- EXTERNAL_REQUESTOR(LDO7, 2, 6),
- EXTERNAL_REQUESTOR(LDO8, 2, 7),
- EXTERNAL_REQUESTOR(LDO9, 3, 0),
- EXTERNAL_REQUESTOR(LDOLN, 3, 1),
- EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
-};
-
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
@@ -370,6 +334,8 @@ int palmas_ext_control_req_config(struct palmas *palmas,
int bit_pos;
int ret;
+ struct palmas_pmic_driver_data *pmic_ddata = palmas-pmic_ddata;
+
if (!(ext_ctrl PALMAS_EXT_REQ))
return 0;
@@ -387,8 +353,8 @@ int palmas_ext_control_req_config(struct palmas *palmas,
preq_mask_bit = 2;
}
- bit_pos = sleep_req_info[id].bit_pos;
- reg_add += sleep_req_info[id].reg_offset;
+ bit_pos = pmic_ddata-sleep_req_info[id].bit_pos;
+ reg_add += pmic_ddata-sleep_req_info[id].reg_offset;
if (enable)
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
reg_add, BIT(bit_pos), BIT(bit_pos));
diff --git a/drivers/regulator/palmas-regulator.c
b/drivers/regulator/palmas-regulator.c
index d41f3de..94c9863 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -39,7 +39,7 @@ static const struct regulator_linear_range smps_high_ranges[]
= {
REGULATOR_LINEAR_RANGE(330, 0x7A, 0x7f, 0),
};
-static const struct regs_info palmas_regs_info[] = {
+static struct regs_info palmas_regs_info[] = {
{
.name = SMPS12,
.sname = smps1-in,
@@ -225,6 +225,42 @@ static const struct regs_info palmas_regs_info[] = {
},
};
+#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
+ [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
+ .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
+ .reg_offset = _offset, \
+ .bit_pos = _pos,\
+ }
+
+struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
+ EXTERNAL_REQUESTOR(REGEN1, 0, 0),
+ EXTERNAL_REQUESTOR(REGEN2, 0, 1),
+ EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
+ EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
+ EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
+ EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
+ EXTERNAL_REQUESTOR(REGEN3, 0, 6),
+ EXTERNAL_REQUESTOR(SMPS12, 1, 0),
+ EXTERNAL_REQUESTOR(SMPS3, 1, 1),
+ EXTERNAL_REQUESTOR(SMPS45, 1, 2),
+ EXTERNAL_REQUESTOR(SMPS6, 1, 3),
+ EXTERNAL_REQUESTOR(SMPS7, 1, 4),
+ EXTERNAL_REQUESTOR(SMPS8, 1, 5),
+ EXTERNAL_REQUESTOR(SMPS9, 1, 6),
+ EXTERNAL_REQUESTOR(SMPS10, 1, 7),
+ EXTERNAL_REQUESTOR(LDO1, 2, 0),
+ EXTERNAL_REQUESTOR(LDO2, 2, 1),
+ EXTERNAL_REQUESTOR(LDO3, 2, 2),
+ EXTERNAL_REQUESTOR(LDO4, 2, 3),
+ EXTERNAL_REQUESTOR(LDO5, 2, 4),
+ EXTERNAL_REQUESTOR(LDO6, 2, 5),
+ EXTERNAL_REQUESTOR(LDO7, 2, 6),
+ EXTERNAL_REQUESTOR(LDO8, 2, 7),
+ EXTERNAL_REQUESTOR(LDO9, 3, 0),
+ EXTERNAL_REQUESTOR(LDOLN, 3, 1),
+ EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
+};
+
static unsigned int palmas_smps_ramp_delay[4] = {0, 1, 5000, 2500};
#define
[PATCH 9/9] regulator: palmas: Add tps65917 PMIC support
Add tps65917 PMIC support.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/regulator/palmas-regulator.c | 387 ++
1 file changed, 387 insertions(+)
diff --git a/drivers/regulator/palmas-regulator.c
b/drivers/regulator/palmas-regulator.c
index 94c9863..98c4532 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -225,6 +225,94 @@ static struct regs_info palmas_regs_info[] = {
},
};
+static struct regs_info tps65917_regs_info[] = {
+ {
+ .name = SMPS1,
+ .sname = smps1-in,
+ .vsel_addr = TPS65917_SMPS1_VOLTAGE,
+ .ctrl_addr = TPS65917_SMPS1_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
+ },
+ {
+ .name = SMPS2,
+ .sname = smps2-in,
+ .vsel_addr = TPS65917_SMPS2_VOLTAGE,
+ .ctrl_addr = TPS65917_SMPS2_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
+ },
+ {
+ .name = SMPS3,
+ .sname = smps3-in,
+ .vsel_addr = TPS65917_SMPS3_VOLTAGE,
+ .ctrl_addr = TPS65917_SMPS3_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
+ },
+ {
+ .name = SMPS4,
+ .sname = smps4-in,
+ .vsel_addr = TPS65917_SMPS4_VOLTAGE,
+ .ctrl_addr = TPS65917_SMPS4_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
+ },
+ {
+ .name = SMPS5,
+ .sname = smps5-in,
+ .vsel_addr = TPS65917_SMPS5_VOLTAGE,
+ .ctrl_addr = TPS65917_SMPS5_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
+ },
+ {
+ .name = LDO1,
+ .sname = ldo1-in,
+ .vsel_addr = TPS65917_LDO1_VOLTAGE,
+ .ctrl_addr = TPS65917_LDO1_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
+ },
+ {
+ .name = LDO2,
+ .sname = ldo2-in,
+ .vsel_addr = TPS65917_LDO2_VOLTAGE,
+ .ctrl_addr = TPS65917_LDO2_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
+ },
+ {
+ .name = LDO3,
+ .sname = ldo3-in,
+ .vsel_addr = TPS65917_LDO3_VOLTAGE,
+ .ctrl_addr = TPS65917_LDO3_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
+ },
+ {
+ .name = LDO4,
+ .sname = ldo4-in,
+ .vsel_addr = TPS65917_LDO4_VOLTAGE,
+ .ctrl_addr = TPS65917_LDO4_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
+ },
+ {
+ .name = LDO5,
+ .sname = ldo5-in,
+ .vsel_addr = TPS65917_LDO5_VOLTAGE,
+ .ctrl_addr = TPS65917_LDO5_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
+ },
+ {
+ .name = REGEN1,
+ .ctrl_addr = TPS65917_REGEN1_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
+ },
+ {
+ .name = REGEN2,
+ .ctrl_addr = TPS65917_REGEN2_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
+ },
+ {
+ .name = REGEN3,
+ .ctrl_addr = TPS65917_REGEN3_CTRL,
+ .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
+ },
+};
+
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
@@ -261,6 +349,29 @@ struct palmas_sleep_requestor_info palma_sleep_req_info[]
= {
EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
};
+#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos)\
+ [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
+ .id = TPS65917_EXTERNAL_REQSTR_ID_##_id,\
+ .reg_offset = _offset, \
+ .bit_pos = _pos,\
+ }
+
+static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
+ EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
+ EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
+ EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
+ EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
+ EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
+ EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
+
[PATCH 7/9] regulator: palmas: Add palmas_pmic_driver_data structure
Add palmas_pmic_driver_data structure.
Signed-off-by: Keerthy j-keer...@ti.com
---
include/linux/mfd/palmas.h | 25 +
1 file changed, 25 insertions(+)
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 8d68452..70f0695 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -53,6 +53,8 @@ struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
struct palmas_usb;
+struct palmas_pmic_driver_data;
+struct palmas_pmic_platform_data;
enum palmas_usb_state {
PALMAS_USB_STATE_DISCONNECT,
@@ -76,6 +78,8 @@ struct palmas {
struct mutex irq_lock;
struct regmap_irq_chip_data *irq_data;
+ struct palmas_pmic_driver_data *pmic_ddata;
+
/* Child Devices */
struct palmas_pmic *pmic;
struct palmas_gpadc *gpadc;
@@ -107,6 +111,27 @@ struct regs_info {
int sleep_id;
};
+struct palmas_pmic_driver_data {
+ int smps_start;
+ int smps_end;
+ int ldo_begin;
+ int ldo_end;
+ int max_reg;
+ struct regs_info *palmas_regs_info;
+ struct of_regulator_match *palmas_matches;
+ struct palmas_sleep_requestor_info *sleep_req_info;
+ int (*smps_register)(struct palmas_pmic *pmic,
+struct palmas_pmic_driver_data *ddata,
+struct palmas_pmic_platform_data *pdata,
+const char *pdev_name,
+struct regulator_config config);
+ int (*ldo_register)(struct palmas_pmic *pmic,
+ struct palmas_pmic_driver_data *ddata,
+ struct palmas_pmic_platform_data *pdata,
+ const char *pdev_name,
+ struct regulator_config config);
+};
+
struct palmas_gpadc_platform_data {
/* Channel 3 current source is only enabled during conversion */
int ch3_current;
--
1.7.9.5
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/9] mfd: palmas: Add tps65917 support
Add tps65917 PMIC support. tps65917 is a subset of palmas PMIC.
Some of the register definitions and the interrupt mappings
are different.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/mfd/palmas.c | 176 --
1 file changed, 171 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index d280d78..485d755 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -92,6 +92,133 @@ static const struct regmap_config
palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
},
};
+static const struct regmap_irq tps65917_irqs[] = {
+ /* INT1 IRQs */
+ [TPS65917_RESERVED1] = {
+ .mask = TPS65917_RESERVED,
+ },
+ [TPS65917_PWRON_IRQ] = {
+ .mask = TPS65917_INT1_STATUS_PWRON,
+ },
+ [TPS65917_LONG_PRESS_KEY_IRQ] = {
+ .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
+ },
+ [TPS65917_RESERVED2] = {
+ .mask = TPS65917_RESERVED,
+ },
+ [TPS65917_PWRDOWN_IRQ] = {
+ .mask = TPS65917_INT1_STATUS_PWRDOWN,
+ },
+ [TPS65917_HOTDIE_IRQ] = {
+ .mask = TPS65917_INT1_STATUS_HOTDIE,
+ },
+ [TPS65917_VSYS_MON_IRQ] = {
+ .mask = TPS65917_INT1_STATUS_VSYS_MON,
+ },
+ [TPS65917_RESERVED3] = {
+ .mask = TPS65917_RESERVED,
+ },
+ /* INT2 IRQs*/
+ [TPS65917_RESERVED4] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 1,
+ },
+ [TPS65917_OTP_ERROR_IRQ] = {
+ .mask = TPS65917_INT2_STATUS_OTP_ERROR,
+ .reg_offset = 1,
+ },
+ [TPS65917_WDT_IRQ] = {
+ .mask = TPS65917_INT2_STATUS_WDT,
+ .reg_offset = 1,
+ },
+ [TPS65917_RESERVED5] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 1,
+ },
+ [TPS65917_RESET_IN_IRQ] = {
+ .mask = TPS65917_INT2_STATUS_RESET_IN,
+ .reg_offset = 1,
+ },
+ [TPS65917_FSD_IRQ] = {
+ .mask = TPS65917_INT2_STATUS_FSD,
+ .reg_offset = 1,
+ },
+ [TPS65917_SHORT_IRQ] = {
+ .mask = TPS65917_INT2_STATUS_SHORT,
+ .reg_offset = 1,
+ },
+ [TPS65917_RESERVED6] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 1,
+ },
+ /* INT3 IRQs */
+ [TPS65917_GPADC_AUTO_0_IRQ] = {
+ .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
+ .reg_offset = 2,
+ },
+ [TPS65917_GPADC_AUTO_1_IRQ] = {
+ .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
+ .reg_offset = 2,
+ },
+ [TPS65917_GPADC_EOC_SW_IRQ] = {
+ .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
+ .reg_offset = 2,
+ },
+ [TPS65917_RESREVED6] = {
+ .mask = TPS65917_RESERVED6,
+ .reg_offset = 2,
+ },
+ [TPS65917_RESERVED7] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 2,
+ },
+ [TPS65917_RESERVED8] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 2,
+ },
+ [TPS65917_RESERVED9] = {
+ .mask = TPS65917_RESERVED,
+ .reg_offset = 2,
+ },
+ [TPS65917_VBUS_IRQ] = {
+ .mask = TPS65917_INT3_STATUS_VBUS,
+ .reg_offset = 2,
+ },
+ /* INT4 IRQs */
+ [TPS65917_GPIO_0_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_0,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_1_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_1,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_2_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_2,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_3_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_3,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_4_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_4,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_5_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_5,
+ .reg_offset = 3,
+ },
+ [TPS65917_GPIO_6_IRQ] = {
+ .mask = TPS65917_INT4_STATUS_GPIO_6,
+ .reg_offset = 3,
+ },
+ [TPS65917_RESERVED10] = {
+ .mask = TPS65917_RESERVED10,
+ .reg_offset = 3,
+ },
+};
+
static const struct regmap_irq palmas_irqs[] = {
/* INT1 IRQs */
[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
@@ -232,6 +359,19 @@ static struct regmap_irq_chip palmas_irq_chip = {
PALMAS_INT1_MASK),
};
+static struct regmap_irq_chip tps65917_irq_chip = {
+ .name = tps65917,
+ .irqs = tps65917_irqs,
+ .num_irqs = ARRAY_SIZE(tps65917_irqs),
+
+
[PATCH 5/9] regulator: palmas: Shift the reg_info structure definition to the header file
Shift the reg_info structure definition to the header file.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/regulator/palmas-regulator.c |9 -
include/linux/mfd/palmas.h |9 +
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/palmas-regulator.c
b/drivers/regulator/palmas-regulator.c
index 9602eba..d41f3de 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -27,15 +27,6 @@
#include linux/of_platform.h
#include linux/regulator/of_regulator.h
-struct regs_info {
- char*name;
- char*sname;
- u8 vsel_addr;
- u8 ctrl_addr;
- u8 tstep_addr;
- int sleep_id;
-};
-
static const struct regulator_linear_range smps_low_ranges[] = {
REGULATOR_LINEAR_RANGE(50, 0x1, 0x6, 0),
REGULATOR_LINEAR_RANGE(51, 0x7, 0x79, 1),
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 52a24a9..150a6314 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -88,6 +88,15 @@ struct palmas {
u8 pwm_muxed;
};
+struct regs_info {
+ char*name;
+ char*sname;
+ u8 vsel_addr;
+ u8 ctrl_addr;
+ u8 tstep_addr;
+ int sleep_id;
+};
+
struct palmas_gpadc_platform_data {
/* Channel 3 current source is only enabled during conversion */
int ch3_current;
--
1.7.9.5
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[PATCH 6/9] mfd: palmas: shift the palmas_sleep_requestor_info structure definition to the header file
shift the palmas_sleep_requestor_info structure definition to the header file.
Signed-off-by: Keerthy j-keer...@ti.com
---
drivers/mfd/palmas.c | 10 --
include/linux/mfd/palmas.h | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index 485d755..f1f31d5 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -25,16 +25,6 @@
#include linux/mfd/palmas.h
#include linux/of_device.h
-#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
- PALMAS_EXT_CONTROL_ENABLE2 |\
- PALMAS_EXT_CONTROL_NSLEEP)
-
-struct palmas_sleep_requestor_info {
- int id;
- int reg_offset;
- int bit_pos;
-};
-
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 150a6314..8d68452 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -88,6 +88,16 @@ struct palmas {
u8 pwm_muxed;
};
+#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
+ PALMAS_EXT_CONTROL_ENABLE2 |\
+ PALMAS_EXT_CONTROL_NSLEEP)
+
+struct palmas_sleep_requestor_info {
+ int id;
+ int reg_offset;
+ int bit_pos;
+};
+
struct regs_info {
char*name;
char*sname;
--
1.7.9.5
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[PATCH 2/9] regulator: palmas: Add tps65917 compatible string
Add tps65917 compatible string. Signed-off-by: Keerthy j-keer...@ti.com --- .../devicetree/bindings/regulator/palmas-pmic.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt index 42e6b6b..725393c 100644 --- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt +++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt @@ -7,6 +7,7 @@ Required properties: ti,twl6037-pmic ti,tps65913-pmic ti,tps65914-pmic + ti,tps65917-pmic and also the generic series names ti,palmas-pmic - interrupt-parent : The parent interrupt controller which is palmas. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/9] mfd: Add DT bindings for tps65917 PMIC
Add DT bindings for tps65917 PMIC. Signed-off-by: Keerthy j-keer...@ti.com --- Documentation/devicetree/bindings/mfd/palmas.txt |2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt index e5f0f83..eda8989 100644 --- a/Documentation/devicetree/bindings/mfd/palmas.txt +++ b/Documentation/devicetree/bindings/mfd/palmas.txt @@ -6,6 +6,7 @@ twl6037 (palmas) tps65913 (palmas) tps65914 (palmas) tps659038 +tps65917 Required properties: - compatible : Should be from the list @@ -16,6 +17,7 @@ Required properties: ti,tps65914 ti,tps80036 ti,tps659038 + ti,tps65917 and also the generic series names ti,palmas - interrupt-controller : palmas has its own internal IRQs -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 01/10] platform_data: edma: Be precise with the paRAM struct
On 05/27/2014 06:03 PM, Joel Fernandes wrote: On 05/27/2014 05:22 AM, Peter Ujfalusi wrote: On 05/27/2014 12:32 AM, Olof Johansson wrote: [..] I came across this patch when I was looking at a pull request from Sekhar for EDMA cleanups, and it made me look closer at the contents of this file. The include/linux/platform_data/ directory is meant to hold platform_data definitions for drivers, and nothing more. platform_data/edma.h also contains a whole bunch of interface definitions for the driver. They do not belong there, and should be moved to a different include file. That also includes the above struct, because as far as I can tell it's a runtime state structure, not something that is passed in with platform data. Can someone please clean this up? Thanks. I think Joel is working on to move/merge the code from arch/arm/common/edma.c to drivers/dma/edma.c Yes, I am planning to work on that soon. But there is an issue, more on that discussed below.. I'm sure within this work he is going to clean up the header file as well. Agreed. The private API should not be expored in any header and should be exclusive for the EDMA dmaengine driver ideally. As a first step I think the non platform_data content can be moved as include/linux/edma.h or probably as ti-edma.h? sound/soc/davinci/davinci-pcm.c: This still uses the EDMA private API in arch/arm/common/edma.c. Peter, any idea when the private usage will be removed fully, and we switch to dmaengine for ASoC? Before that can happen, we can't clean up or do any merges. We have the edma-pcm platform driver upstream already which I'm using locally for a long time now on AM335x/AM437x. I'm planning to send a patch to do the same upstream after the 3.16 window closes. But, davinci-pcm has a mode called 'ping-pong' which is not available via dmaengine and this mode is used by several daVinci SoCs to overcome buffer underflow/overflow issues. This mode essentially means in playback case: dma_ch1 dma_ch2 SDRAM --- SRAM --- McASP ch1 is to move a block of samples to SRAM from where ch2 will copy the samples word by word to McASP. If we move all davinci SoCs to use the edma-pcm, we are going to loose this mode. As a note: the edma-pcm is confirmed to work fine on the tested daVinci boards. I think what we need to do first: find a board which is using ping-pong mode, put under stress test in: - davinci-pcm, ping-pong mode - davinci-pcm, no ping-pong mode - edma-pcm and see how edma-pcm behaves compared to the davinci-pcm. One of the issue with davinci-pcm is that in non ping-pong mode it reconfigures the eDMA after every period, which is a bad thing. The dmaengine implementation does not need to do that, so we might be fine there. What I'd like to do is fold the private API into the dmaengine driver and eliminate the need to expose the private API, thus also getting rid of the interface declarations Olof referred to. thanks, -Joel -- Péter -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 3/6] ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x
In DRA7x SoCs, the CONTROL_MODULE_CORE sub block in the control module has a
few register fields which perform gating or muxing of clocks.
These gate/muxes are generally SoC level clocks entering an IP, which didn't
manage to make it in the clock management related registers for the IP.
Other OMAP SOCs don't seem to have clock related register fields in the control
module.
We create a new table and function to init ctrl-core IPS as clock providers.
This, along with scrm clock providers, are initialized in of_control_init().
We add a compatible string for dra7-ctrl-core in the DT match table.
Signed-off-by: Archit Taneja arc...@ti.com
---
arch/arm/mach-omap2/control.c | 22 +-
arch/arm/mach-omap2/control.h | 2 +-
arch/arm/mach-omap2/io.c | 2 +-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 12cd736..d9567bc 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -592,7 +592,27 @@ static struct of_device_id omap_scrm_dt_match_table[] = {
{ }
};
-int __init of_scrm_init(void)
+static int __init of_scrm_init(void)
{
return of_prcm_module_init(omap_scrm_dt_match_table);
}
+
+static struct of_device_id omap_ctrl_core_dt_match_table[] = {
+ { .compatible = ti,dra7-ctrl-core },
+ { }
+};
+
+static int __init of_ctrl_core_init(void)
+{
+ return of_prcm_module_init(omap_ctrl_core_dt_match_table);
+}
+
+int __init of_control_init(void)
+{
+ int ret;
+
+ ret = of_scrm_init();
+ ret |= of_ctrl_core_init();
+
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 5d695f1..405979e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -428,7 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void);
-int of_scrm_init(void);
+int of_control_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
#else
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c78e2b8..49e344b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -725,7 +725,7 @@ int __init omap_clk_init(void)
if (!omap_clk_soc_init)
return 0;
- ret = of_scrm_init();
+ ret = of_control_init();
if (ret)
return ret;
--
1.8.3.2
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[RFC v2 5/6] ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core
The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.
The DESHDCP clock is enabled/disabled at the DSS boundary by the bit
DSS_DESHDCP_CLKEN in CTRL_CORE_CONTROL_IO_2.
Add dss_deshdcp gate-clock node under dra7-ctrl-core. There are separate bit
fields for enabling and disabling the clock. We just map the enable bit since
this clock doesn't cause any impact if left enabled.
Signed-off-by: Archit Taneja arc...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index cfb8fc7..a1653ba 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2007,6 +2007,16 @@
};
};
+ctrl_core_clocks {
+ dss_deshdcp_clk: dss_deshdcp_clk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = l3_iclk_div;
+ ti,bit-shift = 0;
+ reg = 0x0558;
+ };
+};
+
cm_core_clockdomains {
coreaon_clkdm: coreaon_clkdm {
compatible = ti,clockdomain;
--
1.8.3.2
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[RFC v2 6/6] CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init
The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.
This is because the DSS IP is designed in such a way that if DES-HDCP block
can't transition from idle state, the entire DSS clock domain also cannot
transition from idle to enabled. DES-HDCP block needs the DESHDCP clock
enabled to transition from idle successfully.
We enable the deshdcp clock in dra7xx_clk_init() which happens before omap
hwmods are setup. This clock is effectively a gate clock with the parent as
DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock
domain and hence doesn't have a clock node associated to it. Since
DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's
parent as l3_iclk_div.
Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only
a very few flops get this clock all the time. So there is negligible impact.
Signed-off-by: Archit Taneja arc...@ti.com
---
drivers/clk/ti/clk-7xx.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index f7e4073..3f73a02 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, dss_hdmi_clk, dss_hdmi_clk),
DT_CLK(NULL, dss_video1_clk, dss_video1_clk),
DT_CLK(NULL, dss_video2_clk, dss_video2_clk),
+ DT_CLK(NULL, dss_deshdcp_clk, dss_deshdcp_clk),
DT_CLK(NULL, gpio1_dbclk, gpio1_dbclk),
DT_CLK(NULL, gpio2_dbclk, gpio2_dbclk),
DT_CLK(NULL, gpio3_dbclk, gpio3_dbclk),
@@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
int __init dra7xx_dt_clk_init(void)
{
int rc;
- struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+ struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
ti_dt_clocks_register(dra7xx_clks);
@@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to configure GMAC DPLL!\n, __func__);
+ dss_deshdcp_ck = clk_get_sys(NULL, dss_deshdcp_clk);
+ rc = clk_prepare_enable(dss_deshdcp_ck);
+ if (rc)
+ pr_err(%s: failed to enable DESHDCP clock\n, __func__);
+
return rc;
}
--
1.8.3.2
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[RFC v2 4/6] ARM: dts: Add ctrl-core DT node for DRA7
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the
CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register
fields which configure clocks. The remainder of the registers are related to
pad configurations or cross-bar configurations, and therefore aren't mapped.
Signed-off-by: Archit Taneja arc...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 149b550..14d1905 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -148,6 +148,19 @@
};
};
+ ctrl_core: ctrl_core@4a002000 {
+ compatible = ti,dra7-ctrl-core;
+ reg = 0x4a002000 0x6d0;
+
+ ctrl_core_clocks: clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ ctrl_core_clockdomains: clockdomains {
+ };
+ };
+
counter32k: counter@4ae04000 {
compatible = ti,omap-counter32k;
reg = 0x4ae04000 0x40;
--
1.8.3.2
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[RFC v2 1/6] CLK: TI: clockdomain: add support for retrying init
From: Tero Kristo t-kri...@ti.com
Retry init is needed if clockdomains are registered before the corresponding
clocks are ready. In this case, the clockdomain info is added to a list
which will be processed once the clockdomains for next PRCM module are
processed.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/prm_common.c | 3 +-
drivers/clk/ti/clockdomain.c | 77 ++--
include/linux/clk/ti.h | 2 +-
3 files changed, 68 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4c4ab9..56462af 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -523,10 +523,9 @@ int __init of_prcm_init(void)
mem = of_iomap(np, 0);
clk_memmaps[memmap_index] = mem;
ti_dt_clk_init_provider(np, memmap_index);
+ ti_dt_clockdomains_setup(np);
memmap_index++;
}
- ti_dt_clockdomains_setup();
-
return 0;
}
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index f1e0038..29fa543 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -24,26 +24,60 @@
#undef pr_fmt
#define pr_fmt(fmt) %s: fmt, __func__
-static void __init of_ti_clockdomain_setup(struct device_node *node)
+struct clkdm_init_item {
+ struct device_node *node;
+ int index;
+ struct list_head link;
+};
+
+static LIST_HEAD(retry_list);
+
+static int of_ti_init_clk_clkdm(struct device_node *node, int index)
{
struct clk *clk;
struct clk_hw *clk_hw;
- const char *clkdm_name = node-name;
+
+ clk = of_clk_get(node, index);
+
+ if (IS_ERR_OR_NULL(clk)) {
+ pr_debug(%s[%d] = %08x\n, node-name, index, (u32)clk);
+ return -EBUSY;
+ }
+
+ if (__clk_get_flags(clk) CLK_IS_BASIC) {
+ pr_warn(can't setup clkdm for basic clk %s\n,
+ __clk_get_name(clk));
+ return -EINVAL;
+ }
+
+ clk_hw = __clk_get_hw(clk);
+ to_clk_hw_omap(clk_hw)-clkdm_name = node-name;
+ omap2_init_clk_clkdm(clk_hw);
+
+ return 0;
+}
+
+static void __init of_ti_clockdomain_setup(struct device_node *node)
+{
int i;
int num_clks;
+ struct clkdm_init_item *retry;
+ int ret;
num_clks = of_count_phandle_with_args(node, clocks, #clock-cells);
for (i = 0; i num_clks; i++) {
- clk = of_clk_get(node, i);
- if (__clk_get_flags(clk) CLK_IS_BASIC) {
- pr_warn(can't setup clkdm for basic clk %s\n,
- __clk_get_name(clk));
+ ret = of_ti_init_clk_clkdm(node, i);
+
+ if (ret == -EBUSY) {
+ retry = kzalloc(sizeof(*retry), GFP_KERNEL);
+ if (!retry)
+ return;
+ retry-node = node;
+ retry-index = i;
+ list_add(retry-link, retry_list);
continue;
}
- clk_hw = __clk_get_hw(clk);
- to_clk_hw_omap(clk_hw)-clkdm_name = clkdm_name;
- omap2_init_clk_clkdm(clk_hw);
}
}
@@ -61,10 +95,31 @@ static struct of_device_id ti_clkdm_match_table[]
__initdata = {
* called after rest of the DT clock init has completed and all
* clock nodes have been registered.
*/
-void __init ti_dt_clockdomains_setup(void)
+void __init ti_dt_clockdomains_setup(struct device_node *node)
{
struct device_node *np;
- for_each_matching_node(np, ti_clkdm_match_table) {
+ struct device_node *clkdms;
+ struct clkdm_init_item *retry, *tmp;
+ int ret;
+
+ clkdms = of_get_child_by_name(node, clockdomains);
+ if (!clkdms)
+ return;
+
+ list_for_each_entry_safe(retry, tmp, retry_list, link) {
+ pr_debug(retry-init: %s [%d]\n, retry-node-name,
+retry-index);
+ ret = of_ti_init_clk_clkdm(retry-node, retry-index);
+ if (!ret) {
+ list_del(retry-link);
+ kfree(retry);
+ }
+ }
+
+ for_each_child_of_node(clkdms, np) {
+ if (!of_match_node(ti_clkdm_match_table, np))
+ continue;
+
of_ti_clockdomain_setup(np);
}
}
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 4a21a87..20dd7c0 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -263,7 +263,7 @@ void omap3_clk_lock_dpll5(void);
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
void ti_dt_clk_init_provider(struct device_node *np, int index);
-void ti_dt_clockdomains_setup(void);
+void
[RFC v2 0/6] ARM: dts: Add a new clk provider, and implement dss_deshdcp clock with it
This series tries to create CONTROL_MODULE_CORE as a new clock provider, and create a clock using it required by DSS on DRA7. The previous revision of the series added the new clock provider within prcm driver code itself. Suggestions were made by Paul and Tero to move it to control module driver code. I picked up 2 patches from Tero's WIP branch below, and added DRA7's control module core block as a clock provider. The DSS_DESHDCP clock is easy to implement after that. https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip Archit Taneja (5): ARM: PRCM: split PRCM module init to their own driver files ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x ARM: dts: Add ctrl-core DT node for DRA7 ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init Tero Kristo (1): CLK: TI: clockdomain: add support for retrying init arch/arm/boot/dts/dra7.dtsi | 13 ++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 + arch/arm/mach-omap2/cm_common.c | 18 + arch/arm/mach-omap2/control.c| 35 arch/arm/mach-omap2/control.h| 1 + arch/arm/mach-omap2/io.c | 4 ++ arch/arm/mach-omap2/prcm-common.h| 5 +++ arch/arm/mach-omap2/prm_common.c | 55 +++--- drivers/clk/ti/clk-7xx.c | 8 +++- drivers/clk/ti/clockdomain.c | 77 ++-- include/linux/clk/ti.h | 2 +- 11 files changed, 192 insertions(+), 36 deletions(-) -- 1.8.3.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 2/6] ARM: PRCM: split PRCM module init to their own driver files
Currently, clock providers coming from CM, PRM, and SCRM are all initialized in
prm_common.c.
Move the DT-match tables to their respective files, and create separate init
functions for each module.
Originally worked on by: Tero Kristo t-kri...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Signed-off-by: Archit Taneja arc...@ti.com
---
arch/arm/mach-omap2/cm_common.c | 18 ++
arch/arm/mach-omap2/control.c | 15 +++
arch/arm/mach-omap2/control.h | 1 +
arch/arm/mach-omap2/io.c | 4 +++
arch/arm/mach-omap2/prcm-common.h | 5
arch/arm/mach-omap2/prm_common.c | 52 +++
6 files changed, 74 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 40b3b5a..8506990 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -14,6 +14,7 @@
#include linux/kernel.h
#include linux/init.h
#include linux/errno.h
+#include linux/of.h
#include cm2xxx.h
#include cm3xxx.h
@@ -138,3 +139,20 @@ int cm_unregister(struct cm_ll_data *cld)
return 0;
}
+
+static struct of_device_id omap_cm_dt_match_table[] = {
+ { .compatible = ti,omap3-cm },
+ { .compatible = ti,omap4-cm1 },
+ { .compatible = ti,omap4-cm2 },
+ { .compatible = ti,omap5-cm-core-aon },
+ { .compatible = ti,omap5-cm-core },
+ { .compatible = ti,dra7-cm-core-aon },
+ { .compatible = ti,dra7-cm-core },
+ { }
+};
+
+
+int __init of_cm_init(void)
+{
+ return of_prcm_module_init(omap_cm_dt_match_table);
+}
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 44bb4d5..12cd736 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -581,3 +581,18 @@ void omap3_ctrl_set_iva_bootmode_idle(void)
OMAP343X_CONTROL_IVA2_BOOTMOD);
}
#endif /* CONFIG_ARCH_OMAP3 CONFIG_PM */
+
+static struct of_device_id omap_scrm_dt_match_table[] = {
+ { .compatible = ti,am3-scrm },
+ { .compatible = ti,am4-scrm },
+ { .compatible = ti,omap2-scrm },
+ { .compatible = ti,omap3-scrm },
+ { .compatible = ti,omap4-scrm },
+ { .compatible = ti,omap5-scrm },
+ { }
+};
+
+int __init of_scrm_init(void)
+{
+ return of_prcm_module_init(omap_scrm_dt_match_table);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index da05480..5d695f1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -428,6 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void);
+int of_scrm_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
#else
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f14f9ac..c78e2b8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -725,6 +725,10 @@ int __init omap_clk_init(void)
if (!omap_clk_soc_init)
return 0;
+ ret = of_scrm_init();
+ if (ret)
+ return ret;
+
ret = of_prcm_init();
if (!ret)
ret = omap_clk_soc_init();
diff --git a/arch/arm/mach-omap2/prcm-common.h
b/arch/arm/mach-omap2/prcm-common.h
index 0e841fd..a68d98e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -493,6 +493,8 @@ struct omap_prcm_irq_setup {
.priority = _priority \
}
+struct of_device_id;
+
extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
struct omap_prcm_irq_setup *irq_setup);
@@ -500,6 +502,9 @@ extern int omap_prcm_event_to_irq(const char *event);
extern void omap_prcm_irq_prepare(void);
extern void omap_prcm_irq_complete(void);
+int of_prcm_module_init(struct of_device_id *match_table);
+int of_cm_init(void);
+
# endif
#endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 56462af..85fc9f9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -470,25 +470,18 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
-static struct of_device_id omap_prcm_dt_match_table[] = {
- { .compatible = ti,am3-prcm },
- { .compatible = ti,am3-scrm },
- { .compatible = ti,am4-prcm },
- { .compatible = ti,am4-scrm },
+static struct of_device_id omap_prm_dt_match_table[] = {
{ .compatible = ti,omap3-prm },
- { .compatible = ti,omap3-cm },
- { .compatible = ti,omap3-scrm },
- { .compatible = ti,omap4-cm1 },
{ .compatible = ti,omap4-prm },
- { .compatible = ti,omap4-cm2 },
- { .compatible = ti,omap4-scrm },
{ .compatible = ti,omap5-prm },
- { .compatible =
Re: [PATCH 0/3] ARM: OMAP5+: Support Duty Cycle Correction(DCC)
On Mon 26 May 2014 01:32:08 AM CDT, Tero Kristo wrote: On 05/24/2014 12:07 AM, Mike Turquette wrote: Quoting Nishanth Menon (2014-05-16 03:45:57) Hi, This patch series has been carried over in vendor kernel for quiet few years now. Unfortunately, it was very recently re-discovered and upstream kernel is noticed to be broken for OMAP5 1.5GHz - at least we are operating DPLL at frequency higher than what it was intended to be when CPUFreq is enabled. Thankfully, with nominal voltage(we dont use AVS yet in upstream for the mentioned platforms) and margins in trimming, we have so far not crashed - but I strongly suspect this might be some boundary case survival. DCC also exists in OMAP4. In some cases customers used it, in other cases we just ran the PLL way out of spec and the mpu_clk would divide by 2. Is this broken for OMAP4 as well? Yes, its broken. This series does not address the OMAP4 needs for it, but can be expanded later by just defining a proper clock type with OMAP4 specific DCC rate limits etc. for it. We would need properly functioning DVFS for OMAP4 panda first though I guess... (support for the TPS regulator.) Panda does not need DCC. Panda uses 4430 and Panda-ES uses 4460. neither of which need DCC (DPLLs are trimmed for required frequencies there) - 4430 never had DCC, 4460 had broken DCC. 4470 (which is not upstream and does not have a panda variant) is the only one needing DCC at higher frequencies, and that needs an entirely different scheme(compared to OMAP5+) as mentioned by Tero if 4470 ever gets supported upstream. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
On Tue, May 27, 2014 at 8:54 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Nishanth Menon (2014-05-15 05:33:13)
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 4:25 AM, Roger Quadros rog...@ti.com wrote:
On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote:
Hi Nishanth,
On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote:
On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I
kis...@ti.com wrote:
Hi Roger,
On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
Hi Kishon,
On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
APLL used by PCIE phy can either use external clock as input or
the clock
from DPLL. Added support for the APLL to use external clock as
input here.
Cc: Rajendra Nayak rna...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++
drivers/phy/phy-ti-pipe3.c | 75
++
2 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index bc9afb5..d50f8ee 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -76,6 +76,10 @@ Required properties:
* dpll_ref_m2 - external dpll ref clk
* phy-div - divider for apll
* div-clk - apll clock
+ * apll_mux - mux for pcie apll
+ * refclk_ext - external reference clock for pcie apll
+ - ti,ext-clk: To specifiy if PCIE apll should use external
clock. Applicable
+ only to PCIE PHY.
Instead of specifying both clock sources dpll_ref_clock,
refclk_ext and then specifying a 3rd control option ti,ext-clk
to select one of the 2 sources, why can't the DT just supply one
clock source, i.e. the one that is being used in the board
instance? The driver should then just configure the clock rate
that is needed at that node. Shouldn't the clock framework
automatically take care of muxing and parent rates?
Want the dt to have all the clocks used by the controller.
ti,ext-clk should
go in the board dt file (suggested by Nishanth).
The point is at some point later if some one wants to change the
clock source,
it should be a simple enabling ti,ext-clk flag instead of finding
the clock
phandle etc..
Wonder if that is implicit by the presence of refclk_ext in the
clocks provided?
IMO the presence of refclk_ext is useless unless the board
indicates it
provides the clock source.
refclk_ext holds phandle for *fixed-clock*, so irrespective of
whether the
board provides a clock or not, it can have that handle for
configuring in PRCM.
However if the board does not provide the clock source, configuring
refclk_ext
in PRCM is useless.
I think what Nishant meant is that if refclk_ext is provided it
means that the driver
should use that over dpll_ref_clock so no need of a separate
ti,ext-clk flag.
yes, thank you for clarifying - it does indeed redundant to have
ti,ext-clk. and apologies on being a little obscure in the comment.
Irrespective of whether external reference clock is used or not, all DRA7
(apll) has an input for external reference clock (and also a PRCM
register for
programming it) and it has to be specified in dt no?
Why is that a binding for ti-phy? that is a problem for the APLL clock
driver (selecting it's own source). PHY properties should describe
itself - let the bindings of the APLL describe itself. please dont
mix the two up.
The apll clock node is like this
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = mux-clock;
clocks = dpll_pcie_ref_m2ldo_ck, pciesref_acs_clk_ck;
#clock-cells = 0;
reg = 0x4a00821c 0x4;
bit-mask = 0x80;
};
The external reference clock is denoted by *pciesref_acs_clk_ck*.
refclk_ext holds the phandle to *pciesref_acs_clk_ck* and is used in
clk_set_parent to set the parent of apll mux.
So, How about this: if refclk_ext is not defined, dont do setparent,
if it is defined, do setparent.
in short:
Optional Properties:
* refclk_ext - external reference clock for pcie apll - if defined,
used as the parent to apll_mux
That said, my problem in general with this approach(which many folks
have taken of describing parent of clock X in hardware block binding
for Y) is the following:
The binding now has dependency on clock tree hierarchy. What if
towmorrow, we have a tree where refclk_ext parent of muxZ parent of
apll_mux? the
Re: [GIT PULL] mfd: Immutable branch between MFD and OMAP, due for v3.16
* Lee Jones lee.jo...@linaro.org [140528 00:14]: Thanks Tony, here's the pull-request: The following changes since commit 455c6fdbd219161bd09b1165f11699d6d73de11c: Linux 3.14 (2014-03-30 20:40:15 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/mfd-omap-v3.16-1 for you to fetch changes up to 43fef47f94a1ae46fb2720dada32fa3b5547bee2: mfd: twl4030-power: Add a configuration to turn off oscillator during off-idle (2014-05-28 08:06:18 +0100) Second immutable branch between MFD and OMAP due for the v3.16 merge window. Thanks a lot, this will make it easier for me to chase down potential PM related regressions ;) I'm merging this for testing only into the linux-omap master branch, no need for me to include it into any of my upstream heading branches. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] omap dt fixes and and clocks for v3.16 merge window
The following changes since commit d712ff63b18309c939396f593510fbcccbafb9e4: ARM: dts: Enable mcpdm and mcbsp1 on DuoVero (2014-05-19 17:20:31 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.16/dt-part3 for you to fetch changes up to 43369f0fe81044427f6b1eedeb16bf8c74c86d48: Merge branch 'for-v3.16/clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v3.16/dt-v2 (2014-05-28 10:14:48 -0700) Most likely the last pull request from me for omap changes for v3.16 that's dts fixes for clocks and enabling few features that were still being discussed earlier: - A bunch of omap clock related dts fixes queued by Tero Kristo. - Enable parallel nand on am437x that was not merged earlier as I requested more information about the muxing for it. And we need to also enable ecc hardware support for am43xx. - Enable the modem support for n900 that was dropped earlier because we had to fix the related hwmod entry first with patch ARM: OMAP2+: Fix ssi hwmod entry to allow idling. - And finally, add the omap2 clock dts files. These will allow us to enable the dt clocks and drop the legacy clocks for omap2 with a follow-up patch once the related clock driver binding changes are merged. Afzal Mohammed (1): ARM: dts: AM4372: clk: efuse based crystal frequency detect Christoph Fritz (2): ARM: dts: omap3: set mcbsp2 status ARM: dts: omap3 a83x: fix duplicate usb pin config Dave Gerlach (1): ARM: dts: am43xx-clocks: use ti, fixed-factor-clock for dpll_per_clkdcoldo Gilles Chanteperdrix (1): ARM: dts: omap4: add twd clock to DT Laurent Pinchart (2): ARM: dts: use ti,fixed-factor-clock for dpll4_m5x2_mul_ck ARM: dts: set 'ti,set-rate-parent' for dpll4_m5 path Pekon Gupta (2): ARM: OMAP2+: gpmc: enable BCH_HW ecc-scheme for AM43xx platforms ARM: dts: am437x-gp-evm: add support for parallel NAND flash Peter Ujfalusi (2): ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodes ARM: dts: omap54xx-clocks: Correct abe_iclk clock node Poddar, Sourav (2): ARM: dts: am33xx-clock: Fix ehrpwm tbclk data ARM: dts: am43x-clock: add tbclk data for ehrpwm Sebastian Reichel (2): ARM: dts: omap3-n900: Add SSI support ARM: dts: omap3-n900: Add modem support Tero Kristo (1): ARM: dts: omap2 clock data Tomi Valkeinen (2): ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path Tony Lindgren (2): ARM: OMAP2+: Fix ssi hwmod entry to allow idling Merge branch 'for-v3.16/clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v3.16/dt-v2 arch/arm/boot/dts/am33xx-clocks.dtsi | 30 +- arch/arm/boot/dts/am437x-gp-evm.dts| 108 +++ arch/arm/boot/dts/am43xx-clocks.dtsi | 75 +- arch/arm/boot/dts/omap2420-clocks.dtsi | 270 ++ arch/arm/boot/dts/omap2420.dtsi| 26 + arch/arm/boot/dts/omap2430-clocks.dtsi | 344 arch/arm/boot/dts/omap2430.dtsi| 26 + arch/arm/boot/dts/omap24xx-clocks.dtsi | 1244 arch/arm/boot/dts/omap3-lilly-a83x.dtsi|7 +- arch/arm/boot/dts/omap3-n900.dts | 65 ++ arch/arm/boot/dts/omap3.dtsi | 45 + arch/arm/boot/dts/omap34xx.dtsi| 11 + arch/arm/boot/dts/omap36xx-clocks.dtsi |2 +- arch/arm/boot/dts/omap36xx.dtsi| 11 + arch/arm/boot/dts/omap3xxx-clocks.dtsi |7 +- arch/arm/boot/dts/omap4.dtsi |1 + arch/arm/boot/dts/omap54xx-clocks.dtsi | 58 +- arch/arm/mach-omap2/gpmc-nand.c|2 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |9 +- drivers/clk/ti/clk-43xx.c |6 + 20 files changed, 2254 insertions(+), 93 deletions(-) create mode 100644 arch/arm/boot/dts/omap2420-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap2430-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap24xx-clocks.dtsi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP baseline test results for v3.15-rc7
Hi Aaro, On Tue, 27 May 2014, Aaro Koskinen wrote: Hi Paul, On Tue, May 27, 2014 at 04:59:16PM +, Paul Walmsley wrote: Here are some basic OMAP test results for Linux v3.15-rc7. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v3.15-rc7/20140526221127/ This is great stuff, as always, but just curious, why are the N800 booting results not reported? Based on your logs you are still booting it...? That test run was broken. Not only did it omit the N800 test, it also tested v3.15-rc6, rather than v3.15-rc7 - hence the 0 difference in the size report from v3.15-rc6. The tests are being rerun and will be reposted. Thanks for the sharp-eyed attention - - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote:
+/**
+ * struct sc_phy - The basic smart card phy structure
+ *
+ * @dev: phy device
+ * @pdata: pointer to phy's private data structure
+ * @set_config: called to set phy's configuration
+ * @get_config: called to get phy's configuration
+ * @activate_card: perform smart card activation
+ * @deactivate_card: perform smart card de-activation
+ * @warm_reset: execute smart card warm reset sequence
+ * @register_card_activity_cb: register call back to phy device.
+ * This call back will be called on card insert or remove event
+ *
+ * smart card controller uses this interface to communicate with
+ * smart card via phy.Some smart card phy has multiple slots for
+ * cards. This inerface also enables controller to communicate with
+ * one or more smart card connected over phy.
+ */
+struct sc_phy {
+ /* phy's device pointer */
+ struct device *dev;
So this is the parent, right? Why not embed a struct device into this
structure as well, further streaching out the device tree.
+
+ /* phy's private data */
+ void *pdata;
If you do the above, then this pointer is not needed.
+
+ /* notify data, passed by interface user as a part of
+ * register_notify API. Data should be passed back when
+ * notification raised to the interface user
+ */
+ void *notify_data;
What makes this different from the pdata?
+
+ int (*set_config)(struct sc_phy *phy, u8 slot,
+ enum sc_phy_config attr, int value);
+ int (*get_config)(struct sc_phy *phy, u8 slot, enum
+ sc_phy_config attr);
+ int (*activate_card)(struct sc_phy *phy, u8 slot);
+ int (*deactivate_card)(struct sc_phy *phy, u8 slot);
+ int (*get_syncatr)(struct sc_phy *phy, u8 slot, u8 len, char *atr);
+ int (*warm_reset)(struct sc_phy *phy, u8 slot);
+ int (*register_notify)(struct sc_phy *phy,
+ struct notifier_block *nb, void *notify_data);
+ int (*unregister_notify)(struct sc_phy *phy,
+ struct notifier_block *nb);
+};
+
+#endif /* __SC_PHY_H__ */
--
1.7.9.5
--
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Re: [PATCH v3 2/5] misc: tda8026: Add NXP TDA8026 PHY driver
On Wed, May 28, 2014 at 02:27:14PM +0530, Satish Patel wrote:
TDA8026 is a SmartCard PHY from NXP.
The PHY interfaces with the main processor over the
I2C interface and acts as a slave device.
The driver also exposes the phy interface
(defined@include/linux/sc_phy.h) for SmartCard controller.
Controller uses this interface to communicate with smart card
inserted to the phy's slot.
Note: gpio irq is not validated as I do not have device with that.
I have validated interrupt with dedicated interrupt line on my device.
Signed-off-by: Satish Patel satish.pa...@ti.com
---
Documentation/devicetree/bindings/misc/tda8026.txt | 19 +
drivers/misc/Kconfig |7 +
drivers/misc/Makefile |1 +
drivers/misc/tda8026.c | 1258
4 files changed, 1285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/tda8026.txt
create mode 100644 drivers/misc/tda8026.c
diff --git a/Documentation/devicetree/bindings/misc/tda8026.txt
b/Documentation/devicetree/bindings/misc/tda8026.txt
new file mode 100644
index 000..f115c9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/tda8026.txt
@@ -0,0 +1,19 @@
+TDA8026 smart card slot interface
+
+This is an i2c based smart card interface device forming the electrical
+interface between a microcontroller and smart cards. This device supports
+asynchronous cards (micro controller-based IC cards) as well as synchronous
+cards (mainly memory cards)
+
+Required properties:
+- compatible: nxp,tda8026
+- shutdown-gpio = GPIO pin mapping for SDWNN pin
+- reg = i2c interface address
+
+
+Example:
+tda8026: tda8026@48 {
+ compatible = nxp,tda8026;
+ reg = 0x48;
+ shutdown-gpio = gpio5 19 GPIO_ACTIVE_HIGH;/* Bank5, pin19 */
+ };
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8baff0e..80b21d7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -515,6 +515,13 @@ config SRAM
the genalloc API. It is supposed to be used for small on-chip SRAM
areas found on many SoCs.
+config NXP_TDA8026_PHY
+tristate NXP PHY Driver for Smart Card PHY
+depends on I2C=y
+help
+ If you say yes here you get support for the TDA8026 Smart card PHY
+ with I2C interface.
+
source drivers/misc/c2port/Kconfig
source drivers/misc/eeprom/Kconfig
source drivers/misc/cb710/Kconfig
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 7eb4b69..f262c0b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_SRAM) += sram.o
obj-y+= mic/
obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
+obj-$(CONFIG_NXP_TDA8026_PHY)+= tda8026.o
diff --git a/drivers/misc/tda8026.c b/drivers/misc/tda8026.c
new file mode 100644
index 000..38df33e
--- /dev/null
+++ b/drivers/misc/tda8026.c
@@ -0,0 +1,1258 @@
+/*
+ * tda8026.c - TDA8026 PHY driver for NXP Smart card PHY
+ *
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/moduleparam.h
+#include linux/interrupt.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/mfd/core.h
+#include linux/notifier.h
+#include linux/sc_phy.h
+#include linux/of_gpio.h
+#include linux/of_device.h
+#include linux/delay.h
I think you just broke the build if this driver is enabled now right?
Not good :(
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Re: [PATCH v3 1/5] sc_phy:SmartCard(SC) PHY interface to SC controller
On Wed, May 28, 2014 at 02:27:13PM +0530, Satish Patel wrote: SmartCard controller uses this interface to communicate with SmartCard via PHY Some SmartCard PHY has multiple slots for cards. This inerface also enables controller to communicate with one or more SmartCard connected over phy. interface structure includes following APIs - set/get config - activate/deactivate smart card - warm reset - register_notify (for card insert/remove/overheat) - unregister_notify Signed-off-by: Satish Patel satish.pa...@ti.com --- Documentation/sc_phy.txt | 171 ++ include/linux/sc_phy.h | 136 2 files changed, 307 insertions(+) create mode 100644 Documentation/sc_phy.txt create mode 100644 include/linux/sc_phy.h These are .h files, but where is the api functions that use these structures defined at? confused, greg k-h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
OMAP baseline test results for v3.15-rc7 (corrected)
Here are some basic OMAP test results for Linux v3.15-rc7. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v3.15-rc7/20140528121000/ Test summary Build: zImage: Pass (14/14): multi_v7_defconfig, omap2plus_defconfig, omap2plus_defconfig_am33xx_only, omap2plus_defconfig_2430sdp_only, omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, omap2plus_defconfig_n800_only_a, omap2plus_defconfig_n800_multi_omap2xxx, omap2plus_defconfig_omap2_4_only, omap2plus_defconfig_omap3_4_only, rmk_omap3430_ldp_allnoconfig, rmk_omap3430_ldp_oldconfig, rmk_omap4430_sdp_allnoconfig, rmk_omap4430_sdp_oldconfig Build: uImage+dtb: Pass ( 9/ 9): omap2plus_defconfig_am33xx_only/am335x-bone, omap2plus_defconfig/omap4-panda, omap2plus_defconfig/omap4-panda-es, omap2plus_defconfig/am3517-evm, omap2plus_defconfig/omap2430-sdp, omap2plus_defconfig/omap3-beagle, omap2plus_defconfig/omap3-beagle-xm, omap2plus_defconfig/omap3-evm-37xx, omap2plus_defconfig/omap4-var-som Build: uImage: Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only, omap1_defconfig_5912osk_only Boot to userspace: FAIL ( 2/13): 2430sdp, cmt3517 skip ( 2/13): 5912osk, 4460varsomom Pass ( 9/13): 2420n800, 3517evm, 3530es3beagle, 3730beaglexm, 37xxevm, 4430es2panda, 4460pandaes, am335xbone, am335xbonelt PM: chip retention via suspend: FAIL ( 3/ 7): 2430sdp, 4430es2panda, 4460varsomom Pass ( 4/ 7): 3530es3beagle, 3730beaglexm, 37xxevm, 4460pandaes PM: chip retention via dynamic idle: FAIL ( 7/ 7): 2430sdp, 3530es3beagle, 3730beaglexm, 37xxevm, 4430es2panda, 4460pandaes, 4460varsomom PM: chip off except CORE via suspend: FAIL ( 1/ 1): 3730beaglexm PM: chip off except CORE via dynamic idle: FAIL ( 1/ 1): 3730beaglexm PM: chip off via suspend: FAIL ( 5/ 5): 3530es3beagle, 37xxevm, 4430es2panda, 4460pandaes, 4460varsomom PM: chip off via dynamic idle: FAIL ( 5/ 5): 3530es3beagle, 37xxevm, 4430es2panda, 4460pandaes, 4460varsomom vmlinux object size (delta in bytes from test_v3.15-rc6 (4b660a7f5c8099d88d1a43d8ae138965112592c7)): text data bsstotal kernel +2145 +136 -64+2217 omap1_defconfig +2177 +104 -64+2217 omap1_defconfig_1510innovator_only +2177 +104 -64+2217 omap1_defconfig_5912osk_only +6097 +160 -144+6113 multi_v7_defconfig +6445 +32 -56+6421 omap2plus_defconfig +2125 +64 -40+2149 omap2plus_defconfig_2430sdp_only +2293 +32 -56+2269 omap2plus_defconfig_am33xx_only +2361 +32 -56+2337 omap2plus_defconfig_am43xx_only +2349 +32 -56+2325 omap2plus_defconfig_cpupm +2425 +32 -56+2401 omap2plus_defconfig_dra7xx_only +144 +640 +208 omap2plus_defconfig_n800_multi_omap2xxx +144 +640 +208 omap2plus_defconfig_n800_only_a +23490 -56+2293 omap2plus_defconfig_no_pm +6513 +32 -56+6489 omap2plus_defconfig_omap2_4_only +2361 +32 -56+2337 omap2plus_defconfig_omap3_4_only +2361 +32 -56+2337 omap2plus_defconfig_omap5_only +9600 +96 rmk_omap3430_ldp_allnoconfig +2061 +88 -64+2085 rmk_omap3430_ldp_oldconfig +9600 +96 rmk_omap4430_sdp_allnoconfig +2422 +112 -56+2478 rmk_omap4430_sdp_oldconfig Boot-time memory difference (delta in bytes from test_v3.15-rc6 (4b660a7f5c8099d88d1a43d8ae138965112592c7)) avail rsrvd high freed board kconfig -8k 8k . . 2430sdpomap2plus_defconfig -8k 8k . 4k 3517evmomap2plus_defconfig -8k 8k . 4k 3530es3beagle omap2plus_defconfig -8k 8k . 4k 3730beaglexm omap2plus_defconfig -8k 8k . 4k 37xxevmomap2plus_defconfig -8k 8k . 4k 4430es2panda omap2plus_defconfig -8k 8k . 4k 4460pandaesomap2plus_defconfig Aaro Koskinen's sharp eyes pointed out that 2420n800 test results weren't being summarized in the header of these test reports. This has been now fixed. As I was looking into what he pointed out, I discovered also that the previous v3.15-rc7 test report was broken - it tested v3.15-rc6 instead - hence the zero-byte differences in the vmlinux object sizes. This has been corrected in this report, which does in fact test v3.15-rc7. -- To unsubscribe from this list: send
Re: [PATCHv3] arm: dts: am43x-clock: add tbclk data for ehrpwm.
On Mon, May 19, 2014 at 6:20 AM, Tero Kristo t-kri...@ti.com wrote:
On 05/05/2014 10:49 AM, Tero Kristo wrote:
On 05/01/2014 10:00 PM, Mike Turquette wrote:
Quoting Tero Kristo (2014-04-29 07:51:14)
On 04/29/2014 05:15 PM, Sourav Poddar wrote:
We need tbclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Acked-by: Tero Kristo t-kri...@ti.com
Looks good to me.
Tero, just to be clear, are you planning on batching up OMAPish clock
patches and sending a pull request (once they have been reviewed on the
list)?
No, I haven't been planning on sending a pull-req, as I believe you
still want to ack the TI related clock driver patches yourself also. If
you want to change the setup I am of course willing to negotiate the
terms. :)
-Tero
So, based on our discussions, this is now queued for 3.15-rc/clk-dt.
I don't want to cross threads, so we'll work out the details of the
for-3.16 stuff in the Pending clock and hwmod patches thread.
However, after this next merge window I am happy to move to a pull
request-based model for OMAP clock patches, since things should slowly
start to settle down.
Regards,
Mike
-Tero
Thanks,
Mike
---
v2-v3
- correct bitshifting
arch/arm/boot/dts/am43xx-clocks.dtsi | 48
++
drivers/clk/ti/clk-43xx.c|6 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..42d7b1f 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,54 @@
clock-mult = 1;
clock-div = 1;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 0;
+ reg = 0x0664;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 1;
+ reg = 0x0664;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 4;
+ reg = 0x0664;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 5;
+ reg = 0x0664;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 6;
+ reg = 0x0664;
+ };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..527a43d 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, func_12m_clk, func_12m_clk),
DT_CLK(NULL, vtp_clk_div, vtp_clk_div),
DT_CLK(NULL, usbphy_32khz_clkmux, usbphy_32khz_clkmux),
+ DT_CLK(48300200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48302200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(48304200.ehrpwm, tbclk, ehrpwm2_tbclk),
+ DT_CLK(48306200.ehrpwm, tbclk, ehrpwm3_tbclk),
+ DT_CLK(48308200.ehrpwm, tbclk, ehrpwm4_tbclk),
+ DT_CLK(4830a200.ehrpwm, tbclk, ehrpwm5_tbclk),
{ .node_name = NULL },
};
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[PATCH V2 0/2] power: twl4030_charger: cleanup to handle various battery handling error conditions
Hi, This issue was originally reported by Russell on OMAP3-LDP platform, and original attempt to solve this by Felipe[1] did not quiet work, follow on attempt[2] seems to be effective, but in this resend, I have added an shutdown attempt in case things dont quiet look right. Based on: v3.15-rc7 Tests: ldp boot with battery: http://slexy.org/raw/s20StiV4xr ldp boot with a/c charger, no battery: http://slexy.org/raw/s2UfjIkZKG ldp boot with a/c charger+battery, remove battery: http://slexy.org/raw/s2yFTVlrWJ ^^ - this is not exactly a safe test to perform :).. Nishanth Menon (2): power: twl4030_charger: detect battery presence prior to enabling charger power: twl4030_charger: attempt to power off in case of critical events drivers/power/twl4030_charger.c | 70 +++ 1 file changed, 64 insertions(+), 6 deletions(-) [1] https://patchwork.kernel.org/patch/4002371/ [2] https://patchwork.kernel.org/patch/4124751/ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/2] power: twl4030_charger: attempt to power off in case of critical events
Attempt to power off in case of critical events such as battery removal,
over voltage events.
There is no guarentee that we'd be in a safe scenario here, but the very
least we can try to do is to power off the device to prevent damage to
the system instead of just printing a message and hoping for the best.
NOTE: twl4030 should attempt some form of recovery, but just depending
on that is never a safe alternative.
Signed-off-by: Nishanth Menon n...@ti.com
---
new patch. original attempt was: https://patchwork.kernel.org/patch/4002371/
NOTE: we dont have poweroff support yet enabled on LDP, but it just needs
relevant dts entry.
drivers/power/twl4030_charger.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
index 2598c58..ed0dbd2 100644
--- a/drivers/power/twl4030_charger.c
+++ b/drivers/power/twl4030_charger.c
@@ -22,6 +22,7 @@
#include linux/power_supply.h
#include linux/notifier.h
#include linux/usb/otg.h
+#include linux/reboot.h
#include linux/regulator/machine.h
#define TWL4030_BCIMSTATEC 0x02
@@ -332,6 +333,7 @@ static irqreturn_t twl4030_bci_interrupt(int irq, void *arg)
struct twl4030_bci *bci = arg;
u8 irqs1, irqs2;
int ret;
+ bool power_off = false;
ret = twl_i2c_read_u8(TWL4030_MODULE_INTERRUPTS, irqs1,
TWL4030_INTERRUPTS_BCIISR1A);
@@ -352,20 +354,34 @@ static irqreturn_t twl4030_bci_interrupt(int irq, void
*arg)
}
/* various monitoring events, for now we just log them here */
- if (irqs1 (TWL4030_TBATOR2 | TWL4030_TBATOR1))
+ if (irqs1 (TWL4030_TBATOR2 | TWL4030_TBATOR1)) {
dev_warn(bci-dev, battery temperature out of range\n);
+ power_off = true;
+ }
- if (irqs1 TWL4030_BATSTS)
+ if (irqs1 TWL4030_BATSTS) {
dev_crit(bci-dev, battery disconnected\n);
+ power_off = true;
+ }
- if (irqs2 TWL4030_VBATOV)
+ if (irqs2 TWL4030_VBATOV) {
dev_crit(bci-dev, VBAT overvoltage\n);
+ power_off = true;
+ }
- if (irqs2 TWL4030_VBUSOV)
+ if (irqs2 TWL4030_VBUSOV) {
dev_crit(bci-dev, VBUS overvoltage\n);
+ power_off = true;
+ }
- if (irqs2 TWL4030_ACCHGOV)
+ if (irqs2 TWL4030_ACCHGOV) {
dev_crit(bci-dev, Ac charger overvoltage\n);
+ power_off = true;
+ }
+
+ /* Try to shutdown the system */
+ if (power_off)
+ orderly_poweroff(true);
return IRQ_HANDLED;
}
--
1.7.9.5
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[PATCH V2 1/2] power: twl4030_charger: detect battery presence prior to enabling charger
TWL4030's Battery Charger seems to be designed for non-hotpluggable
batteries.
If battery is not present in the system, BATSTS is always set with the
expectation that software will take actions to move to a required safe
state (could be power down or disable various charger paths).
It does not seem possible even by manipulating the edge detection
of the event (using BCIEDR2 register) to have a consistent hotplug
handling. This seems to be the result of BATSTS interrupt generated
when the thermistor of the battery pack is disconnected from the
dedicated ADIN1 pin. Clearing the status just results in the status
being regenerated by the monitoring ADC(MADC) and disabling the
edges of event just makes hotplug no longer function. The only
other option is to disable the detection of the MADC by disabling
BCIMFEN4::BATSTSMCHGEN (battery presence detector) - but then, we can
never again detect battery reconnection.
So, detect battery presence based on precharge(which is hardware
automatic state) or default main charger configuration at the time of
probe and enable charger logic only if battery was present.
Reported-by: Russell King li...@arm.linux.org.uk
Tested-by: Tony Lindgren t...@atomide.com
Signed-off-by: Nishanth Menon n...@ti.com
---
V2: just a rebase, picked up tony's tested-by, minor formatting fix
V1: https://patchwork.kernel.org/patch/4124751/
drivers/power/twl4030_charger.c | 44 ++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
index f141088..2598c58 100644
--- a/drivers/power/twl4030_charger.c
+++ b/drivers/power/twl4030_charger.c
@@ -28,10 +28,13 @@
#define TWL4030_BCIICHG0x08
#define TWL4030_BCIVAC 0x0a
#define TWL4030_BCIVBUS0x0c
+#define TWL4030_BCIMFSTS3 0x0F
#define TWL4030_BCIMFSTS4 0x10
#define TWL4030_BCICTL10x23
#define TWL4030_BB_CFG 0x12
+#define TWL4030_BCIMFSTS1 0x01
+
#define TWL4030_BCIAUTOWEN BIT(5)
#define TWL4030_CONFIG_DONEBIT(4)
#define TWL4030_BCIAUTOUSB BIT(1)
@@ -52,6 +55,9 @@
#define TWL4030_BBISEL_500uA 0x02
#define TWL4030_BBISEL_1000uA 0x03
+#define TWL4030_BATSTSPCHG BIT(2)
+#define TWL4030_BATSTSMCHG BIT(6)
+
/* BCI interrupts */
#define TWL4030_WOVF BIT(0) /* Watchdog overflow */
#define TWL4030_TMOVF BIT(1) /* Timer overflow */
@@ -145,6 +151,35 @@ static int twl4030bci_read_adc_val(u8 reg)
}
/*
+ * Check if Battery Pack was present
+ */
+static int twl4030_is_battery_present(struct twl4030_bci *bci)
+{
+ int ret;
+ u8 val = 0;
+
+ /* Battery presence in Main charge? */
+ ret = twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, val, TWL4030_BCIMFSTS3);
+ if (ret)
+ return ret;
+ if (val TWL4030_BATSTSMCHG)
+ return 0;
+
+ /*
+* OK, It could be that bootloader did not enable main charger,
+* pre-charge is h/w auto. So, Battery presence in Pre-charge?
+*/
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PRECHARGE, val,
+ TWL4030_BCIMFSTS1);
+ if (ret)
+ return ret;
+ if (val TWL4030_BATSTSPCHG)
+ return 0;
+
+ return -ENODEV;
+}
+
+/*
* Check if VBUS power is present
*/
static int twl4030_bci_have_vbus(struct twl4030_bci *bci)
@@ -541,8 +576,14 @@ static int __init twl4030_bci_probe(struct platform_device
*pdev)
bci-irq_chg = platform_get_irq(pdev, 0);
bci-irq_bci = platform_get_irq(pdev, 1);
- platform_set_drvdata(pdev, bci);
+ /* Only proceed further *IF* battery is physically present */
+ ret = twl4030_is_battery_present(bci);
+ if (ret) {
+ dev_crit(pdev-dev, Battery was not detected:%d\n, ret);
+ goto fail_no_battery;
+ }
+ platform_set_drvdata(pdev, bci);
bci-ac.name = twl4030_ac;
bci-ac.type = POWER_SUPPLY_TYPE_MAINS;
bci-ac.properties = twl4030_charger_props;
@@ -633,6 +674,7 @@ fail_chg_irq:
fail_register_usb:
power_supply_unregister(bci-ac);
fail_register_ac:
+fail_no_battery:
kfree(bci);
return ret;
--
1.7.9.5
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