Re: [next-20150119]regression (mm)?
Felipe Balbi wrote: Hi, On Mon, Jan 19, 2015 at 10:42:04AM -0600, Nishanth Menon wrote: Most platforms seem broken intoday's next tag. https://github.com/nmenon/kernel-test-logs/tree/next-20150119 (defconfig: omap2plus_defconfig) [7.166600] [ cut here ] [7.171676] WARNING: CPU: 0 PID: 54 at mm/mmap.c:2859 exit_mmap+0x1a8/0x21c() [7.179194] Modules linked in: [7.182479] CPU: 0 PID: 54 Comm: init Not tainted 3.19.0-rc5-next-20150119-2-gfdefcded1272 #1 [7.191863] Hardware name: Generic AM33XX (Flattened Device Tree) [7.198318] [c00153f0] (unwind_backtrace) from [c0011a74] (show_stack+0x10/0x14) [7.206528] [c0011a74] (show_stack) from [c0580150] (dump_stack+0x78/0x94) [7.214191] [c0580150] (dump_stack) from [c003d4d0] (warn_slowpath_common+0x7c/0xb4) [7.222751] [c003d4d0] (warn_slowpath_common) from [c003d524] (warn_slowpath_null+0x1c/0x24) [7.232038] [c003d524] (warn_slowpath_null) from [c012de64] (exit_mmap+0x1a8/0x21c) [7.240536] [c012de64] (exit_mmap) from [c003abb8] (mmput+0x44/0xec) [7.247612] [c003abb8] (mmput) from [c0151368] (flush_old_exec+0x300/0x5a4) [7.255357] [c0151368] (flush_old_exec) from [c0195c10] (load_elf_binary+0x2ec/0x1144) [7.264111] [c0195c10] (load_elf_binary) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.273311] [c0150ea0] (search_binary_handler) from [c019554c] (load_script+0x260/0x280) [7.282232] [c019554c] (load_script) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.291066] [c0150ea0] (search_binary_handler) from [c0151f0c] (do_execveat_common+0x538/0x6c4) [7.300628] [c0151f0c] (do_execveat_common) from [c01520c4] (do_execve+0x2c/0x34) [7.308881] [c01520c4] (do_execve) from [c000e5e0] (ret_fast_syscall+0x0/0x4c) [7.316881] ---[ end trace 3b8a46b1b280f423 ]--- seems like it's caused by: b316feb3c37ff19cddcaf1f6b5056c633193257d is the first bad commit Adding Kiryl to the loop. git bisect start # good: [ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc] Linux 3.19-rc5 git bisect good ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc # bad: [a0d4287f787889e59db0fd295853a0f1f55d0699] Add linux-next specific files for 20150119 git bisect bad a0d4287f787889e59db0fd295853a0f1f55d0699 # good: [1c2f70b77b8ca77f10c59d479d009e07359d00d2] Merge remote-tracking branch 'drm/drm-next' git bisect good 1c2f70b77b8ca77f10c59d479d009e07359d00d2 # good: [73c1390843223d8bfc85795c560c36b3d0ffee40] Merge remote-tracking branch 'leds/for-next' git bisect good 73c1390843223d8bfc85795c560c36b3d0ffee40 # good: [7bc6bef35d48e91ad796b6eead7304998842c782] Merge remote-tracking branch 'pinctrl/for-next' git bisect good 7bc6bef35d48e91ad796b6eead7304998842c782 # bad: [45e1eaa38732ffa3de0d18fe95d2d2b960a7c777] lib: bitmap: change bitmap_shift_right to take unsigned parameters git bisect bad 45e1eaa38732ffa3de0d18fe95d2d2b960a7c777 # good: [c82a73a0369a7dd6dcfaf9e6bd572a4e5deda223] mm, page_alloc: reduce number of alloc_pages* functions' parameters git bisect good c82a73a0369a7dd6dcfaf9e6bd572a4e5deda223 # bad: [0b1c810fbc4bbff7e314dd6ff91c2b4af499199d] mm: don't split THP page when syscall is called git bisect bad 0b1c810fbc4bbff7e314dd6ff91c2b4af499199d # good: [54faa439355a9ae476a446429967e9e38f04363e] oom, PM: make OOM detection in the freezer path raceless git bisect good 54faa439355a9ae476a446429967e9e38f04363e # bad: [b6c9f11c6b6993303067f7c04a73258226a6e77e] mm/compaction: add tracepoint to observe behaviour of compaction defer git bisect bad b6c9f11c6b6993303067f7c04a73258226a6e77e # good: [9ce5d3fb13a80f28db450de4ecf2727893e99c93] mm: pagemap_read: limit scan to virtual region being asked git bisect good 9ce5d3fb13a80f28db450de4ecf2727893e99c93 # bad: [1a7a376546ca56e7750987c15d0c7541c17a512c] mm/compaction: change tracepoint format from decimal to hexadecimal git bisect bad 1a7a376546ca56e7750987c15d0c7541c17a512c # bad: [4081187ff19cf2186010c003939c17d70d0bbb27] page_writeback: put account_page_redirty() after set_page_dirty() git bisect bad 4081187ff19cf2186010c003939c17d70d0bbb27 # bad: [b316feb3c37ff19cddcaf1f6b5056c633193257d] mm: account pmd page tables to the process git bisect bad b316feb3c37ff19cddcaf1f6b5056c633193257d # first bad commit: [b316feb3c37ff19cddcaf1f6b5056c633193257d] mm: account pmd page tables to the process I've added a dump_mm() call when the bug happens followed by a while (true) loop (to avoid constant reprinting of the same thing), here's what I get: [7.235903] [ cut here ] [7.240881] WARNING: CPU: 0 PID: 58 at mm/mmap.c:2859 exit_mmap+0x1b4/0x218() [7.248369] Modules linked in: ipv6 autofs4 [7.252792] CPU: 0 PID: 58 Comm: systemd Not tainted 3.19.0-rc5-next-20150119-dirty #888 [7.261274] Hardware name
Re: [PATCH v9 3/3] clk: Add floor and ceiling constraints to clock rates
On 01/19, Tomeu Vizoso wrote:
Adds a way for clock consumers to set maximum and minimum rates. This can be
used for thermal drivers to set ceiling rates, or by misc. drivers to set
floor rates to assure a minimum performance level.
Changes the signature of the determine_rate callback by adding the
parameters floor_rate and ceiling_rate.
Commit text needs the s/floor/min and s/ceiling/max treatment
too.
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f2a1ff3..55b3124 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1026,6 +1051,28 @@ static unsigned long clk_core_round_rate_nolock(struct
clk_core *clk,
else
return clk-rate;
}
+unsigned long __clk_determine_rate(struct clk_hw *hw,
+unsigned long rate,
+unsigned long min_rate,
+unsigned long max_rate)
+{
+ unsigned long parent_rate = 0;
+ struct clk_core *core = hw-core;
+ struct clk_hw *parent_hw;
+
+ if (!core-ops-determine_rate)
+ return 0;
+
+ if (core-parent) {
+ parent_rate = core-parent-rate;
+ parent_hw = core-parent-hw;
+ }
+
+ return core-ops-determine_rate(core-hw, rate,
+ min_rate, max_rate,
+ parent_rate, parent_hw);
+}
+EXPORT_SYMBOL_GPL(__clk_determine_rate);
Maybe I misled you with the API name. I was thinking more along
the lines of clk_round_rate() and this new function ending up
calling clk_core_round_rate(), but clk_round_rate() would call it
with whatever range the clock is constrained to while this new
function would allow driver authors to specify the range. It
should be easy enough to add min/max to clk_core_round_rate()
given that it's a private API in this file.
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[GIT PULL] Urgent omap4 legacy interrupt regression fix for v3.19-rc series
The following changes since commit 7ac72746aa9bb305fa74b44ec73eae99bbbe9b66: ARM: dts: Revert disabling of smc91x for n900 (2015-01-06 08:49:57 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.19/gic-regression-v2 for you to fetch changes up to 0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559: ARM: OMAP: Work around hardcoded interrupts (2015-01-17 08:56:12 -0800) A rather urgent pull request to fix omap4 legacy interrupts. The legacy interrupts on omap4 got broken when gic got changed to use irq_domain_add_linear() instead of the irq_domain_add_legacy(). We still have the hardcoded legacy IRQ numbers in use in several places, most notably the in the legacy DMA. It took a while to figure out what the problem was and how it should be fixed for the -rc series. Also include is a regression fix for the dra7 dwc3 suspend. Felipe Balbi (1): arm: boot: dts: dra7: enable dwc3 suspend PHY quirk Marc Zyngier (1): ARM: OMAP: Work around hardcoded interrupts arch/arm/boot/dts/dra7.dtsi| 6 ++ arch/arm/mach-omap2/common.h | 1 + arch/arm/mach-omap2/omap4-common.c | 32 ++ arch/arm/mach-omap2/omap_hwmod.c | 10 -- arch/arm/mach-omap2/omap_hwmod.h | 1 + arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 5 + arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 1 + arch/arm/mach-omap2/prcm-common.h | 1 + arch/arm/mach-omap2/prm44xx.c | 5 - arch/arm/mach-omap2/prm_common.c | 14 +++-- arch/arm/mach-omap2/twl-common.c | 7 ++- 11 files changed, 77 insertions(+), 6 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] Urgent omap4 legacy interrupt regression fix for v3.19-rc series
On Mon, Jan 19, 2015 at 03:09:51PM -0800, Tony Lindgren wrote: The following changes since commit 7ac72746aa9bb305fa74b44ec73eae99bbbe9b66: ARM: dts: Revert disabling of smc91x for n900 (2015-01-06 08:49:57 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.19/gic-regression-v2 for you to fetch changes up to 0fb22a8fb7f3bc1b00a36d4a97ce4f93191f7559: ARM: OMAP: Work around hardcoded interrupts (2015-01-17 08:56:12 -0800) A rather urgent pull request to fix omap4 legacy interrupts. The legacy interrupts on omap4 got broken when gic got changed to use irq_domain_add_linear() instead of the irq_domain_add_legacy(). We still have the hardcoded legacy IRQ numbers in use in several places, most notably the in the legacy DMA. It took a while to figure out what the problem was and how it should be fixed for the -rc series. Also include is a regression fix for the dra7 dwc3 suspend. Merged. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH] arm: omap: hwmod: add debugfs interface
On Fri, 5 Dec 2014, Felipe Balbi wrote: By exposing the details of hwmod structures to debugfs we can much more easily verify that changes to hwmod data is correct and won't cause regressions. The idea is that this can be used to check the state of one hwmod, verify hwmod sysc fields, etc. For example, this will be used to move some of the sysc fields to DT and later verify that they are correct pre- and post-patch. Signed-off-by: Felipe Balbi ba...@ti.com This one had a bunch of unnecessary includes and checkpatch issues (below). I cleaned those up here and have queued the result (also below) for v3.20. - Paul CHECK: extern prototypes should be avoided in .h files #61: FILE: arch/arm/mach-omap2/omap_hwmod.h:772: +extern int __init omap_hwmod_debug_init(void); WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 CHECK: Alignment should match open parenthesis #116: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:44: +static int __init omap_hwmod_create_files(struct omap_hwmod *oh, + struct dentry *dir) CHECK: Alignment should match open parenthesis #129: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:57: + file = debugfs_create_u8(response_lat, S_IRUGO, dir, + oh-response_lat); CHECK: Alignment should match open parenthesis #134: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:62: + file = debugfs_create_u8(rst_lines_cnt, S_IRUGO, dir, + oh-rst_lines_cnt); CHECK: Alignment should match open parenthesis #139: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:67: + file = debugfs_create_u8(opt_clks_cnt, S_IRUGO, dir, + oh-opt_clks_cnt); CHECK: Alignment should match open parenthesis #164: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:92: + file = debugfs_create_u8(_postsetup_state, S_IRUGO, dir, + oh-_postsetup_state); ERROR: need consistent spacing around '*' (ctx:WxV) #173: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:101: + dentry *dir) ^ CHECK: Alignment should match open parenthesis #186: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:114: + file = debugfs_create_x32(rev_offs, S_IRUGO, subdir, + sysc-rev_offs); CHECK: Alignment should match open parenthesis #191: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:119: + file = debugfs_create_x32(sysc_offs, S_IRUGO, subdir, + sysc-sysc_offs); CHECK: Alignment should match open parenthesis #196: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:124: + file = debugfs_create_x32(syss_offs, S_IRUGO, subdir, + sysc-syss_offs); CHECK: Alignment should match open parenthesis #201: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:129: + file = debugfs_create_x16(sysc_flags, S_IRUGO, subdir, + sysc-sysc_flags); CHECK: Alignment should match open parenthesis #206: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:134: + file = debugfs_create_u8(srst_udelay, S_IRUGO, subdir, + sysc-srst_udelay); WARNING: line over 80 characters #210: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:138: + file = debugfs_create_x8(idlemodes, S_IRUGO, subdir, sysc-idlemodes); CHECK: Alignment should match open parenthesis #222: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:150: +static int __init omap_hwmod_create_class_files(struct omap_hwmod_class *class, + struct dentry *dir) CHECK: Alignment should match open parenthesis #247: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:175: +static int __init omap_hwmod_create_irq_files(struct omap_hwmod_irq_info *irqs, + struct dentry *dir) CHECK: Alignment should match open parenthesis #263: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:191: + file = debugfs_create_u16(irqs[i].name, S_IRUGO, subdir, + irqs[i].irq); CHECK: Alignment should match open parenthesis #273: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:201: +static int __init omap_hwmod_create_dma_files(struct omap_hwmod_dma_info *dmas, + struct dentry *dir) CHECK: Alignment should match open parenthesis #289: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:217: + file = debugfs_create_u16(dmas[i].name, S_IRUGO, subdir, + dmas[i].dma_req); CHECK: Alignment should match open parenthesis #299: FILE: arch/arm/mach-omap2/omap_hwmod_debugfs.c:227: +static int __init omap_hwmod_debugfs_create_subdir(struct omap_hwmod *oh, + void *data) total: 1 errors, 2 warnings, 17 checks, 305 lines checked Your patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. [PATCH] arm: omap: hwmod: add debugfs interface By exposing the details of hwmod structures to debugfs
[PATCH v2 2/5] usb: dwc3: add revision number DWC3_REVISION_300A
Add the contstant for v3.00a dwc3 IP detection
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
drivers/usb/dwc3/core.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4bb9aa6..8090249 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -776,6 +776,7 @@ struct dwc3 {
#define DWC3_REVISION_260A 0x5533260a
#define DWC3_REVISION_270A 0x5533270a
#define DWC3_REVISION_280A 0x5533280a
+#define DWC3_REVISION_300A 0x5533300a
enum dwc3_ep0_next ep0_next_event;
enum dwc3_ep0_state ep0state;
--
1.7.9.5
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[PATCH v2 3/5] usb: dwc3: Add quirk for Synopsis device disconnection errata
Synopsis Designware USB3 IP earlier than v3.00a which is configured in silicon
with DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1, would need a specific quirk to prevent
xhci host controller from dying when device is disconnected.
Since DWC_USB3_SUSPEND_ON_DISCONNECT_EN is an IP configuration whose state
cannot be checked from software in runtime, it has to be enabled via platform
data or device tree.
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
Documentation/devicetree/bindings/usb/dwc3.txt | 17 +
drivers/usb/dwc3/core.c|6 ++
drivers/usb/dwc3/core.h|1 +
drivers/usb/dwc3/host.c|4
drivers/usb/dwc3/platform_data.h |1 +
5 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index cd7f045..1b78b29 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -37,6 +37,23 @@ Optional properties:
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold
+ - snps,has_suspend_on_disconnect: true when IP is configured in silicon with
+ DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1, it can inject a
+ specific quirk to prevent xhci host controller from
+ dying when usb device is disconnected from root hub.
+ Since DWC_USB3_SUSPEND_ON_DISCONNECT_EN is an IP
+ configuration whose state cannot be checked from
+ software in runtime, it has to be enabled via platform
+ data or device tree.
+
+ xhci host dying symptom here is caused by that
+ DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1
+ configuration makes IP auto-suspended after PORTCSC is
+ cleared when usb device detached, then an asynchronous
+ disconnection procedure might fail using endpoint
+ command that suspened IP won't have any response to.
+
+ this issue is fixed when IP version = 3.00a.
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 25ddc39..fbceab1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -838,6 +838,9 @@ static int dwc3_probe(struct platform_device *pdev)
snps,tx_de_emphasis_quirk);
of_property_read_u8(node, snps,tx_de_emphasis,
tx_de_emphasis);
+
+ dwc-suspend_on_disconnect_quirk = of_property_read_bool(node,
+ snps,has_suspend_on_disconnect);
} else if (pdata) {
dwc-maximum_speed = pdata-maximum_speed;
dwc-has_lpm_erratum = pdata-has_lpm_erratum;
@@ -864,6 +867,9 @@ static int dwc3_probe(struct platform_device *pdev)
dwc-tx_de_emphasis_quirk = pdata-tx_de_emphasis_quirk;
if (pdata-tx_de_emphasis)
tx_de_emphasis = pdata-tx_de_emphasis;
+
+ dwc-suspend_on_disconnect_quirk =
+ pdata-has_suspend_on_disconnect;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8090249..d7458ff 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -832,6 +832,7 @@ struct dwc3 {
unsignedtx_de_emphasis_quirk:1;
unsignedtx_de_emphasis:2;
+ unsignedsuspend_on_disconnect_quirk:1;
};
/* --
*/
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index 12bfd3c..9c42074 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -53,6 +53,10 @@ int dwc3_host_init(struct dwc3 *dwc)
pdata.usb3_lpm_capable = 1;
#endif
+ if ((dwc-revision DWC3_REVISION_300A)
+ dwc-suspend_on_disconnect_quirk)
+ pdata.delay_portcsc_clear = 1;
+
ret = platform_device_add_data(xhci, pdata, sizeof(pdata));
if (ret) {
dev_err(dwc-dev, couldn't add platform data to xHCI
device\n);
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index a3a3b6d..69562f1 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -44,4 +44,5 @@ struct dwc3_platform_data {
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
+ unsigned has_suspend_on_disconnect:1;
};
--
1.7.9.5
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[PATCH v2 1/5] usb: dwc3: add Fujitsu Specific Glue layer
This patch adds support for Synopsis DesignWare USB3 IP Core found
on Fujitsu Socs.
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
.../devicetree/bindings/usb/fujitsu-dwc3.txt | 33
drivers/usb/dwc3/Kconfig | 11 ++
drivers/usb/dwc3/Makefile |1 +
drivers/usb/dwc3/dwc3-mb86s70.c| 206
4 files changed, 251 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/fujitsu-dwc3.txt
create mode 100644 drivers/usb/dwc3/dwc3-mb86s70.c
diff --git a/Documentation/devicetree/bindings/usb/fujitsu-dwc3.txt
b/Documentation/devicetree/bindings/usb/fujitsu-dwc3.txt
new file mode 100644
index 000..be091eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fujitsu-dwc3.txt
@@ -0,0 +1,33 @@
+FUJITSU GLUE COMPONENTS
+
+MB86S7x DWC3 GLUE
+- compatible: Should be fujitsu,mb86s70-dwc3
+- clocks: from common clock binding, handle to usb clock.
+- clock-names: Should contain the following:
+ core Master/Core clock needs to run at a minimum of 125 MHz to
+ support a 4 Gbps IN or 4 Gbps OUT
+ transfer at a given time.
+
+Sub-nodes:
+The dwc3 core should be added as subnode to MB86S7x dwc3 glue.
+- dwc3 :
+ The binding details of dwc3 can be found in:
+ Documentation/devicetree/bindings/usb/dwc3.txt
+
+Example device nodes:
+
+ usb3host: mb86s70_usb3host {
+ compatible = fujitsu,mb86s70-dwc3;
+ clocks = clk_alw_1_1;
+ clock-names = core;
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges;
+
+ dwc3@3220 {
+ compatible = synopsys,dwc3;
+ reg = 0 0x3230 0x10;
+ interrupts = 0 412 0x4,
+ 0 414 0x4;
+ };
+ };
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 58b5b2c..3390d42 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -61,6 +61,17 @@ config USB_DWC3_EXYNOS
Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
say 'Y' or 'M' if you have one such device.
+config USB_DWC3_MB86S70
+ tristate MB86S70 Designware USB3 Platform code
+ default USB_DWC3
+ help
+ MB86S7X SOC ship with DesignWare Core USB3 IP inside,
+ this implementation also integrated Fujitsu USB PHY inside
+ this Core USB3 IP.
+
+ say 'Y' or 'M' if you have one such device.
+
+
config USB_DWC3_PCI
tristate PCIe-based Platforms
depends on PCI
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index bb34fbc..05d1de2 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_USB_DWC3_PCI)+= dwc3-pci.o
obj-$(CONFIG_USB_DWC3_KEYSTONE)+= dwc3-keystone.o
obj-$(CONFIG_USB_DWC3_QCOM)+= dwc3-qcom.o
obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
+obj-$(CONFIG_USB_DWC3_MB86S70) += dwc3-mb86s70.o
diff --git a/drivers/usb/dwc3/dwc3-mb86s70.c b/drivers/usb/dwc3/dwc3-mb86s70.c
new file mode 100644
index 000..301be76
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-mb86s70.c
@@ -0,0 +1,206 @@
+/**
+ * dwc3-mb86s70.c - Fujitsu mb86s70 DWC3 Specific Glue layer
+ *
+ * Copyright (c) 2013 - 2014 FUJITSU SEMICONDUCTOR LIMITED
+ * http://jp.fujitsu.com/group/fsl
+ *
+ * Authors: Alice Chan alice.c...@tw.fujitsu.com
+ * Sneeker Yeh sneeker@tw.fujitsu.com
+ * based on dwc3-exynos.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/module.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/dma-mapping.h
+#include linux/interrupt.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/pm_runtime.h
+#include linux/clk.h
+
+struct dwc3_mb86s70 {
+ struct device *dev;
+ struct clk *clks[5];
+ u8 clk_cnt;
+};
+
+static int dwc3_mb86s70_clk_control(struct device *dev, bool on)
+{
+ struct dwc3_mb86s70 *priv = dev_get_drvdata(dev);
+ int ret, i = priv-clk_cnt;
+
+ if (!on)
+ goto clock_off;
+
+ for (i = 0; i priv-clk_cnt; i++) {
+ ret = clk_prepare_enable(priv-clks[i]);
+ if (ret) {
+ dev_err(dev, failed to enable clock[%d]\n, i);
+ on = ret;
+ goto clock_off;
+ }
+ }
+
+ return 0;
+
+clock_off:
+ for (; i 0;)
+ clk_disable_unprepare(priv-clks[--i]);
+
+ return on;
+}
+
+static int
Re: [GIT PULL] ARM: OMAP: hwmod fixes for v3.19-rc
Hi Tony On Mon, 19 Jan 2015, Tony Lindgren wrote: * Paul Walmsley p...@pwsan.com [150104 15:38]: The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672: Linux 3.19-rc1 (2014-12-20 17:08:50 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/for-v3.19-rc/omap-fixes-a for you to fetch changes up to 99d076b747455449b2eec9e37f3fb0bfdf51af32: MAINTAINERS: add maintainer for OMAP hwmod data (2015-01-02 16:24:27 -0700) For v3.19-rc, fix some hwmod structure details for the OMAP DSS modules for DRA7xx and AM43xx. Also update the MAINTAINERS file to encourage folks to cc me on hwmod data patches. Basic build, boot, and PM testlogs are available here: http://www.pwsan.com/omap/testlogs/omap-fixes-a-for-v3.19-rc/20150103144242/ Paul, got any updates on this? Anyways, I'll just untag this email as you asked me to wait on pulling this. At this point I think I will just requeue the remaining two valid patches for v3.20. Thanks for the ping - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Hi Marc,
On Monday 19 January 2015 03:14 PM, Marc Zyngier wrote:
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
I tested this patch series on SMDK5250 board.
With the addition of #interrupt-cells = 3;in PMU device node S2R is
working on Exynos5250 based SMDK board.
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
As I know Exynos3250, S2R support has been added in kgene/for-next and
should work as expected so we may need to do update exynos_wkup_irq
for exynos3250 and remove it from this list, so that it's S2R should not
break. I am adding concern engineer (+cc: Chanwoo Choi) in the loop.
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
Thanks,
Pankaj Dubey
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Re: [PATCH 1/5] ARM: AM43xx: hwmod: add VPFE hwmod entries
Hi
On Thu, 18 Dec 2014, Lad, Prabhakar wrote:
From: Benoit Parrot bpar...@ti.com
this patch adds VPFE HWMOD data for AM43xx.
Signed-off-by: Benoit Parrot bpar...@ti.com
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: Lad, Prabhakar prabhakar.cse...@gmail.com
...
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 56
++
arch/arm/mach-omap2/prcm43xx.h | 3 +-
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index fea01aa..bd9067e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
...
@@ -750,6 +788,22 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi =
{
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am43xx_vpfe0_hwmod,
+ .clk= l3_gclk,
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
+ .master = am33xx_l3_main_hwmod,
+ .slave = am43xx_vpfe1_hwmod,
+ .clk= l3_gclk,
+ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
am33xx_l4_wkup__synctimer,
am43xx_l4_ls__timer8,
@@ -848,6 +902,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[]
__initdata = {
am43xx_l4_ls__dss,
am43xx_l4_ls__dss_dispc,
am43xx_l4_ls__dss_rfbi,
+ am43xx_l3__vpfe0,
+ am43xx_l3__vpfe1,
NULL,
};
According to SPRUHL7 Figure 14-1 VPFE Integration and Table 14-2 VPFE
Connectivity Attributes, a VPFE has two interconnect ports per instance:
one L4-Per port as a register target, and one L3 port as a DMA initiator.
It's unclear to me whether the L3 port can also serve as a register
target, but Section 2.1 ARM Cortex-A9 Memory Map, Table 4-1 L3
Master-Slave Connectivity, and Figure 4-2 L4 Topology suggest that it
cannot.
So if that's correct, there should be two more struct omap_hwmod_ocp_if
records added in this patch for the register target ports that are
connected to the L4. DSS is a good example: see am43xx_dss__l3_main and
am43xx_l4_ls__dss in this same file.
- Paul
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Re: [PATCH v4 16/21] DT: exynos: update PMU binding
Hi Marc,
On Monday 19 January 2015 03:14 PM, Marc Zyngier wrote:
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
Need to add #interrupt-cells property here.
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
Thanks,
Pankaj Dubey
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Re: [PATCH] ARM: OMAP: DRA7: hwmod: Make gpmc software supervised as the smart idle is broken
Hi Tony,
On Tuesday 13 January 2015 02:21 PM, Keerthy wrote:
This patch fixes: 'omap_hwmod: gpmc: _wait_target_disable failed'
error during suspend.
This is because smart idle is broken.
Tested in dra7-evm D1 board.
Ping on this.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 9cdd8b8..29e55fe 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -826,7 +826,8 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
.name = gpmc,
.class = dra7xx_gpmc_hwmod_class,
.clkdm_name = l3main1_clkdm,
- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+ HWMOD_SWSUP_SIDLE),
.main_clk = l3_iclk_div,
.prcm = {
.omap4 = {
Regards,
Keerthy
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Re: [PATCH v4 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
On Mon, Jan 19, 2015 at 09:43:56AM +, Marc Zyngier wrote: Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Note that the GIC isn't really stacked on top of the LIC. Each IRQ is presented to both the LIC and the GIC (as an SPI). The LIC is only used to wakeup the CPU in case the GIC is not powered. The LIC can also generate interrupts towards the AVP/ARM7, but that's outside the scope of Linux ofcourse. The LIC can also be used to force an IRQ and that forced IRQ will be propagated to the GIC. (see also figure 2, page 36 of the Tegra K1 TRM) Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP2+: hwmod: print error if wait_target_ready() failed
On Fri, 19 Dec 2014, Lokesh Vutla wrote: Fixed pr_debug to pr_err when hwmod returns an error when enabling a module. Signed-off-by: Lokesh Vutla lokeshvu...@ti.com Thanks, queued for v3.20 with Roger's ack. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP: DRA7: hwmod: Make gpmc software supervised as the smart idle is broken
On Tue, 20 Jan 2015, Keerthy wrote:
On Tuesday 13 January 2015 02:21 PM, Keerthy wrote:
This patch fixes: 'omap_hwmod: gpmc: _wait_target_disable failed'
error during suspend.
This is because smart idle is broken.
Tested in dra7-evm D1 board.
Ping on this.
Signed-off-by: Keerthy j-keer...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 9cdd8b8..29e55fe 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -826,7 +826,8 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
.name = gpmc,
.class = dra7xx_gpmc_hwmod_class,
.clkdm_name = l3main1_clkdm,
- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+ HWMOD_SWSUP_SIDLE),
.main_clk = l3_iclk_div,
.prcm = {
.omap4 = {
Thanks, queued for v3.20.
Note that I cannot test this since I don't have a DRA7xx board.
- Paul
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[PATCH] MAINTAINERS: add omap2plus_defconfig under OMAP SUPPORT
omap2plus_defconfig is also part of the OMAP Support maintained, because of that it's best to list it under OMAP SUPPORT on MAINTAINERS so people know to Cc linux-omap when patching that file. Reported-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Signed-off-by: Felipe Balbi ba...@ti.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 97de006f38f0..abc6281892e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6783,6 +6783,7 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap2plus_defconfig F: drivers/i2c/busses/i2c-omap.c F: drivers/irqchip/irq-omap-intc.c F: drivers/mfd/*omap*.c -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MAINTAINERS: add omap2plus_defconfig under OMAP SUPPORT
Hello Felipe, On Mon, Jan 19, 2015 at 10:45 PM, Felipe Balbi ba...@ti.com wrote: omap2plus_defconfig is also part of the OMAP Support maintained, because of that it's best to list it under OMAP SUPPORT on MAINTAINERS so people know to Cc linux-omap when patching that file. Reported-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Signed-off-by: Felipe Balbi ba...@ti.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 97de006f38f0..abc6281892e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6783,6 +6783,7 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap2plus_defconfig While been there, could you please also add omap1_defconfig? Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] MAINTAINERS: add omap2plus_defconfig under OMAP SUPPORT
On Mon, Jan 19, 2015 at 10:52:56PM +0100, Javier Martinez Canillas wrote: Hello Felipe, On Mon, Jan 19, 2015 at 10:45 PM, Felipe Balbi ba...@ti.com wrote: omap2plus_defconfig is also part of the OMAP Support maintained, because of that it's best to list it under OMAP SUPPORT on MAINTAINERS so people know to Cc linux-omap when patching that file. Reported-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Signed-off-by: Felipe Balbi ba...@ti.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 97de006f38f0..abc6281892e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6783,6 +6783,7 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap2plus_defconfig While been there, could you please also add omap1_defconfig? Sure, Tony, is that ok ? -- balbi signature.asc Description: Digital signature
Re: [PATCH] MAINTAINERS: add omap2plus_defconfig under OMAP SUPPORT
* Felipe Balbi ba...@ti.com [150119 13:59]: On Mon, Jan 19, 2015 at 10:52:56PM +0100, Javier Martinez Canillas wrote: Hello Felipe, On Mon, Jan 19, 2015 at 10:45 PM, Felipe Balbi ba...@ti.com wrote: omap2plus_defconfig is also part of the OMAP Support maintained, because of that it's best to list it under OMAP SUPPORT on MAINTAINERS so people know to Cc linux-omap when patching that file. Reported-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Signed-off-by: Felipe Balbi ba...@ti.com --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 97de006f38f0..abc6281892e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6783,6 +6783,7 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap2plus_defconfig While been there, could you please also add omap1_defconfig? Sure, Tony, is that ok ? Oh yeah that would be nice :) Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT
omap2plus_defconfig and omap1_defconfig are also part of the OMAP Support maintained, because of that it's best to list them under OMAP SUPPORT on MAINTAINERS so people know to Cc linux-omap when patching them. Reported-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Signed-off-by: Felipe Balbi ba...@ti.com --- Add omap1_defconfig too MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 97de006f38f0..7423e9759187 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6783,6 +6783,8 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git S: Maintained F: arch/arm/*omap*/ +F: arch/arm/configs/omap1_defconfig +F: arch/arm/configs/omap2plus_defconfig F: drivers/i2c/busses/i2c-omap.c F: drivers/irqchip/irq-omap-intc.c F: drivers/mfd/*omap*.c -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 00/21] irqchip: gic: killing gic_arch_extn and co, slowly
The gic_arch_extn hack that a number of platform use has been nagging me for too long. It is only there for the benefit of a few platform, and yet it impacts all GIC users. Moreover, it gives people the wrong idea (let's use it to put some new custom hack in there...). But now that stacked irq domains have been merged into 3.19, the time has come for gic_arch_extn to meet the Big Bit Bucket. This patch series takes several steps towards the elimination of gic_arch_extn: - moves Tegra's legacy interrupt controller support to drivers/irqchip, implementing a stacked domain on top of the standard GIC. - OMAP, imx6 and exynos are also converted to stacked domains, but their implementation is left in place (the code is far too intricately mixed with other details of the platform for me to even try to move it). Some OMAP variants get a special treatment as we also kill the crossbar horror (more on that below). - shmobile, ux500 and zynq are only slightly modified. - The GIC itself is cleaned up, and some other bits and bobs are adjusted for a good measure. About the TI crossbar: - The allocation of interrupts in this domain is fairly similar to what we do for MSI (see the GICv2m driver), and stacked domains have proved to be a fitting solution. - The current description in DT is currently entierely inaccurate, and as we're already breaking it for the WUGEN block, we might as well do it again for the crossbar. - The way crossbar, WUGEN and GIC interract is quite complex (this is effectively a stack of three interrupt controllers with interesting exceptions and braindead routing), and stacked domains are the right abstraction for that. - Other platforms (Freescale Vybrid) are starting to come up with the same type of things, and it'd be good to avoid them following the same broken model. - It removes a few lines from the code base so it can't completely be a bad idea! So this patch series does exactly that: make the crossbar a stacked interrupt controller that only takes care of setting up the routing, fix the DTs to represent the actual HW, and remove a bit of the craziness from the GIC code. It is worth realizing that: - I haven't been able to test this as much as I would have wanted to (it's only been tested on tegra2, omap4 and omap5). - I've created DT bindings when needed, updated existing ones, but I haven't created a binding for platforms that already used an undocumented one (imx6, I'm looking at you). - I've relaxed quite a bit of the locking in the GIC code. I believe this is safe, but someone else should give it a long hard look. - This actively *breaks* existing setups. Once you boot a new kernel with an old DT, suspend/resume *will* be broken. Old kernels on a new DT won't even boot! You've been warned. This really outline the necessity of actually describing the HW in device trees... As for the patches, they are on top of 3.19-rc3 + the patch posted here [4]. I've pushed the code to: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die I'm still targetting 3.20 for this, but obviously things are getting quite tight. I'd very much like to hear from the maintainers about their views concerning this series. Thanks, M. * From v4 [3]: - Rebased on top of the patch working around hardcoded IRQ on OMAP4/5 [4] - Fixed more iMX6 DTs (Stephan) - Fixed Exynos4/5 DTs * From v2 [2]: - Addressed numerous comments from Thierry - Merged bug fixes from Nishanth - Merged bug fix from Stefan * From v1 [1]: - Rebased on 3.19-rc3 - Fixed a number of additional platforms - Added crossbar conversion to stacked domains - Merged bug fixes from Nishanth [4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317286.html [3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315385.html [2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314041.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307338.html Marc Zyngier (21): ARM: tegra: irq: nuke leftovers from non-DT support irqchip: tegra: add DT-based support for legacy interrupt controller ARM: tegra: skip gic_arch_extn setup if DT has a LIC node ARM: tegra: update DTs to expose legacy interrupt controller DT: tegra: add binding for the legacy interrupt controller ARM: tegra: remove old LIC support genirq: Add irqchip_set_wake_parent irqchip: crossbar: convert dra7 crossbar to stacked domains DT: update ti,irq-crossbar binding irqchip: GIC: get rid of routable domain DT: arm,gic: kill arm,routable-irqs DT: omap4/5: add binding for the wake-up generator ARM: omap: convert wakeupgen to stacked domains ARM: imx6: convert GPC to stacked domains ARM: exynos4/5: convert pmu wakeup to stacked domains DT: exynos: update PMU binding irqchip: gic: add an entry point to set up irqchip flags ARM: shmobile: remove use of
[PATCH v4 08/21] irqchip: crossbar: convert dra7 crossbar to stacked domains
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 3 +-
arch/arm/boot/dts/dra7-evm.dts | 2 +-
arch/arm/boot/dts/dra7.dtsi | 35 +++---
arch/arm/boot/dts/dra72-evm.dts | 1 -
arch/arm/boot/dts/dra72x.dtsi | 3 +-
arch/arm/boot/dts/dra74x.dtsi | 5 +-
arch/arm/mach-omap2/omap4-common.c | 4 -
drivers/irqchip/irq-crossbar.c | 207 ++--
include/linux/irqchip/irq-crossbar.h| 11 --
9 files changed, 146 insertions(+), 125 deletions(-)
delete mode 100644 include/linux/irqchip/irq-crossbar.h
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda..c2241c2 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -335,7 +335,6 @@
mcp_rtc: rtc@6f {
compatible = microchip,mcp7941x;
reg = 0x6f;
- interrupt-parent = gic;
interrupts = GIC_SPI 2 IRQ_TYPE_LEVEL_LOW; /* IRQ_SYS_1N */
pinctrl-names = default;
@@ -358,7 +357,7 @@
uart3 {
status = okay;
- interrupts-extended = gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x248;
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..048cfeb 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -423,7 +423,7 @@
status = okay;
pinctrl-names = default;
pinctrl-0 = uart1_pins;
- interrupts-extended = gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
+ interrupts-extended = crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH,
dra7_pmx_core 0x3e0;
};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..6f90673 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,14 +13,13 @@
#include skeleton.dtsi
#define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = 1;
#size-cells = 1;
compatible = ti,dra7xx;
- interrupt-parent = gic;
+ interrupt-parent = crossbar_mpu;
aliases {
i2c0 = i2c1;
@@ -50,18 +49,19 @@
GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
gic: interrupt-controller@48211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
#interrupt-cells = 3;
- arm,routable-irqs = 192;
reg = 0x48211000 0x1000,
0x48212000 0x1000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
/*
@@ -91,8 +91,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x100,
0x4500 0x1000;
- interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 4
IRQ_TYPE_LEVEL_HIGH,
+ gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -344,7 +344,7 @@
uart1: serial@4806a000 {
compatible = ti,omap4-uart;
reg = 0x4806a000 0x100;
- interrupts-extended = gic GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
+ interrupts-extended = crossbar_mpu GIC_SPI 67
IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = uart1;
clock-frequency = 4800;
status = disabled;
@@ -355,7 +355,7 @@
uart2: serial@4806c000 {
compatible = ti,omap4-uart;
reg = 0x4806c000 0x100;
- interrupts-extended = gic GIC_SPI 68
IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH;
[PATCH v4 02/21] irqchip: tegra: add DT-based support for legacy interrupt controller
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked IRQ domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, something that was sorely missing from
the mach-tegra implementation.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip/irq-tegra.c | 368
2 files changed, 369 insertions(+)
create mode 100644 drivers/irqchip/irq-tegra.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9516a32..59f34be 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04)+= irq-hip04.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG)+= irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000..e1ac65e
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,368 @@
+/*
+ * Driver code for Tegra's Legacy Interrupt Controller
+ *
+ * Author: Marc Zyngier marc.zyng...@arm.com
+ *
+ * Heavily based on the original arch/arm/mach-tegra/irq.c code:
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ * Colin Cross ccr...@android.com
+ *
+ * Copyright (C) 2010,2013, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/io.h
+#include linux/irq.h
+#include linux/irqdomain.h
+#include linux/of_address.h
+#include linux/slab.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+#include irqchip.h
+
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR 0x14
+#define ICTLR_CPU_IEP_FIR_SET 0x18
+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
+
+#define ICTLR_CPU_IER 0x20
+#define ICTLR_CPU_IER_SET 0x24
+#define ICTLR_CPU_IER_CLR 0x28
+#define ICTLR_CPU_IEP_CLASS0x2C
+
+#define ICTLR_COP_IER 0x30
+#define ICTLR_COP_IER_SET 0x34
+#define ICTLR_COP_IER_CLR 0x38
+#define ICTLR_COP_IEP_CLASS0x3c
+
+#define TEGRA_MAX_NUM_ICTLRS 5
+
+static unsigned int num_ictlrs;
+
+struct tegra_ictlr_soc {
+ unsigned int num_ictlrs;
+};
+
+static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
+ .num_ictlrs = 4,
+};
+
+static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
+ .num_ictlrs = 5,
+};
+
+static const struct of_device_id ictlr_matches[] = {
+ { .compatible = nvidia,tegra30-ictlr, .data = tegra30_ictlr_soc },
+ { .compatible = nvidia,tegra20-ictlr, .data = tegra20_ictlr_soc },
+ { }
+};
+
+struct tegra_ictlr_info {
+ void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
+#ifdef CONFIG_PM_SLEEP
+ u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+ u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+ u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+};
+
+static struct tegra_ictlr_info *lic;
+
+static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long
reg)
+{
+ void __iomem *base = d-chip_data;
+ u32 mask;
+
+ mask = BIT(d-hwirq % 32);
+ writel_relaxed(mask, base + reg);
+}
+
+static void tegra_mask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
+ irq_chip_mask_parent(d);
+}
+
+static void tegra_unmask(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
+ irq_chip_unmask_parent(d);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
+ irq_chip_eoi_parent(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+ tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
+ return irq_chip_retrigger_hierarchy(d);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+ u32 irq = d-hwirq;
+ u32 index, mask;
+
+ index = (irq / 32);
+ mask = BIT(irq % 32);
+ if (enable)
+ lic-ictlr_wake_mask[index] |= mask;
+ else
+ lic-ictlr_wake_mask[index] = ~mask;
+
+
[PATCH v4 07/21] genirq: Add irqchip_set_wake_parent
This proves to be useful with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index d09ec7a..3057c48 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -460,6 +460,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
extern int irq_chip_set_affinity_parent(struct irq_data *data,
const struct cpumask *dest,
bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..eb9a4ea 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
return -ENOSYS;
}
+
+/**
+ * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @on:Whether to set or reset the wake-up capability of this
irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+ data = data-parent_data;
+ if (data-chip-irq_set_wake)
+ return data-chip-irq_set_wake(data, on);
+
+ return -ENOSYS;
+}
#endif
/**
--
2.1.4
--
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[PATCH v4 01/21] ARM: tegra: irq: nuke leftovers from non-DT support
The GIC is now always initialized from DT on tegra, and there is no point in keeping non-DT init code. Acked-by: Thierry Reding tred...@nvidia.com Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/irq.c | 8 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ab95f53..7f87a50 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -283,13 +283,5 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_set_wake = tegra_set_wake; gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; - /* -* Check if there is a devicetree present, since the GIC will be -* initialized elsewhere under DT. -*/ - if (!of_have_populated_dt()) - gic_init(0, 29, distbase, - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - tegra114_gic_cpu_pm_registration(); } -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 04/21] ARM: tegra: update DTs to expose legacy interrupt controller
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++-
arch/arm/boot/dts/tegra30.dtsi | 16 +++-
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 4296b53..f58a3d9 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -8,7 +8,7 @@
/ {
compatible = nvidia,tegra114;
- interrupt-parent = gic;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra114-host1x, simple-bus;
@@ -134,6 +134,19 @@
0x50046000 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
+ };
+
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra114-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50,
+ 0x60004400 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
timer@60005000 {
@@ -766,5 +779,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..db85695 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -10,7 +10,7 @@
/ {
compatible = nvidia,tegra124;
- interrupt-parent = gic;
+ interrupt-parent = lic;
#address-cells = 2;
#size-cells = 2;
@@ -173,6 +173,7 @@
0x0 0x50046000 0x0 0x2000;
interrupts = GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH);
+ interrupt-parent = gic;
};
gpu@0,5700 {
@@ -190,6 +191,18 @@
status = disabled;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra124-ictlr, nvidia,tegra30-ictlr;
+ reg = 0x0 0x60004000 0x0 0x100,
+ 0x0 0x60004100 0x0 0x100,
+ 0x0 0x60004200 0x0 0x100,
+ 0x0 0x60004300 0x0 0x100,
+ 0x0 0x60004400 0x0 0x100;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
+ };
+
timer@0,60005000 {
compatible = nvidia,tegra124-timer, nvidia,tegra20-timer;
reg = 0x0 0x60005000 0x0 0x400;
@@ -955,5 +968,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW),
GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW);
+ interrupt-parent = gic;
};
};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d8..362bb21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -7,7 +7,7 @@
/ {
compatible = nvidia,tegra20;
- interrupt-parent = intc;
+ interrupt-parent = lic;
host1x@5000 {
compatible = nvidia,tegra20-host1x, simple-bus;
@@ -142,6 +142,7 @@
timer@50004600 {
compatible = arm,cortex-a9-twd-timer;
+ interrupt-parent = intc;
reg = 0x50040600 0x20;
interrupts = GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH);
@@ -154,6 +155,7 @@
0x50040100 0x0100;
interrupt-controller;
#interrupt-cells = 3;
+ interrupt-parent = intc;
};
cache-controller@50043000 {
@@ -165,6 +167,17 @@
cache-level = 2;
};
+ lic: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr;
+ reg = 0x60004000 0x100,
+ 0x60004100 0x50,
+ 0x60004200 0x50,
+ 0x60004300 0x50;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
+
timer@60005000 {
compatible = nvidia,tegra20-timer;
reg = 0x60005000 0x60;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 99475f6..6bea674 100644
[PATCH v4 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +---
arch/arm/mach-tegra/irq.h | 6 --
3 files changed, 2 insertions(+), 220 deletions(-)
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index ee79808..81dc950 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -31,21 +31,6 @@
#define TEGRA_ARM_INT_DIST_BASE0x50041000
#define TEGRA_ARM_INT_DIST_SIZESZ_4K
-#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
-#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
-#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
-#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
-
-#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300
-#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64
-
-#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
-#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
-
#define TEGRA_TMR1_BASE0x60005000
#define TEGRA_TMR1_SIZESZ_8
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1593c4c..3b9098d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -30,43 +30,9 @@
#include board.h
#include iomap.h
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS0x3c
-
-#define FIRST_LEGACY_IRQ 32
-#define TEGRA_MAX_NUM_ICTLRS 5
-
#define SGI_MASK 0x
-static int num_ictlrs;
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
-};
-
#ifdef CONFIG_PM_SLEEP
-static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
-static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
-
-static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
static void __iomem *tegra_gic_cpu_base;
#endif
@@ -83,140 +49,7 @@ bool tegra_pending_sgi(void)
return false;
}
-static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
-{
- void __iomem *base;
- u32 mask;
-
- BUG_ON(irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32);
-
- base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
-
- __raw_writel(mask, base + reg);
-}
-
-static void tegra_mask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR);
-}
-
-static void tegra_unmask(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET);
-}
-
-static void tegra_ack(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static void tegra_eoi(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR);
-}
-
-static int tegra_retrigger(struct irq_data *d)
-{
- if (d-hwirq FIRST_LEGACY_IRQ)
- return 0;
-
- tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET);
-
- return 1;
-}
-
#ifdef CONFIG_PM_SLEEP
-static int tegra_set_wake(struct irq_data *d, unsigned int enable)
-{
- u32 irq = d-hwirq;
- u32 index, mask;
-
- if (irq FIRST_LEGACY_IRQ ||
- irq = FIRST_LEGACY_IRQ + num_ictlrs * 32)
- return -EINVAL;
-
- index = ((irq - FIRST_LEGACY_IRQ) / 32);
- mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- if (enable)
- ictlr_wake_mask[index] |= mask;
- else
- ictlr_wake_mask[index] = ~mask;
-
- return 0;
-}
-
-static int tegra_legacy_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i num_ictlrs; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- /* Save interrupt state */
- cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
- cpu_iep[i] =
[PATCH v4 05/21] DT: tegra: add binding for the legacy interrupt controller
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000..1099fe0
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as ictlr, hence the name of the binding.
+
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+
+Required properties:
+
+- compatible : should be: nvidia,tegrachip-ictlr. The LIC on
+ subsequent SoCs remained backwards-compatible with Tegra30, so on
+ Tegra generations later than Tegra30 the compatible value should
+ include nvidia,tegra30-ictlr.
+- reg : Specifies base physical address and size of the registers.
+ Each controller must be described separately (Tegra20 has 4 of them,
+ whereas Tegra30 and later have 5
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+ are explicitly forbidden.
+
+Example:
+
+ ictlr: interrupt-controller@60004000 {
+ compatible = nvidia,tegra20-ictlr, nvidia,tegra-ictlr;
+ reg = 0x60004000 64,
+ 0x60004100 64,
+ 0x60004200 64,
+ 0x60004300 64;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = intc;
+ };
--
2.1.4
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[PATCH v4 09/21] DT: update ti,irq-crossbar binding
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
Required properties:
- compatible : Should be ti,irq-crossbar
- reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt
controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be
routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
- crossbar_mpu: @4a02 {
+ crossbar_mpu: crossbar@4a002a48 {
compatible = ti,irq-crossbar;
reg = 0x4a002a48 0x130;
ti,max-irqs = 160;
ti,max-crossbar-sources = 400;
ti,reg-size = 2;
- ti,irqs-reserved = 0 1 2 3 5 6 131 132 139 140;
+ ti,irqs-reserved = 0 1 2 3 5 6 131 132;
ti,irqs-skip = 10 133 139 140;
};
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further
details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = GIC_SPI request_number interrupt_level
-When the request number is between 0 to that described by
-ti,max-crossbar-sources, it is assumed to be a crossbar mapping. If the
-request_number is greater than ti,max-crossbar-sources, then it is mapped as
a
-quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH;
...
};
-
- device_y@0x4a033000 {
- /* Direct mapped GIC SPI 1 used */
- interrupts = GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH;
- ...
- };
--
2.1.4
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[PATCH v4 16/21] DT: exynos: update PMU binding
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 1e1979b..d698e74 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -28,10 +28,23 @@ Properties:
- clocks : list of phandles and specifiers to all input clocks listed in
clock-names property.
+Optional properties:
+
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+
+- interrupt-controller: indicate that said PMU is an interrupt controller
+
+- interrupt-parent: a phandle indicating which interrupt controller
+ this PMU signals interrupts to.
+
Example :
pmu_system_controller: system-controller@1004 {
compatible = samsung,exynos5250-pmu, syscon;
reg = 0x1004 0x5000;
+ interrupt-controller;
+ interrupt-parent = gic;
#clock-cells = 1;
clock-names = clkout0, clkout1, clkout2, clkout3,
clkout4, clkout8, clkout9;
--
2.1.4
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[PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++-
arch/arm/boot/dts/imx6sl.dtsi | 6 +-
arch/arm/boot/dts/imx6sx.dtsi | 6 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 119 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 4fc03b7..aff9ded 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -82,7 +83,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
dma_apbh: dma-apbh@0011 {
@@ -122,6 +123,7 @@
compatible = arm,cortex-a9-twd-timer;
reg = 0x00a00600 0x20;
interrupts = 1 13 0xf01;
+ interrupt-parent = intc;
clocks = clks IMX6QDL_CLK_TWD;
};
@@ -694,8 +696,11 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e0..0d0962b 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -95,7 +96,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
ocram: sram@0090 {
@@ -603,7 +604,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
gpr: iomuxc-gpr@020e {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee..dabaf89 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
interrupt-controller;
reg = 0x00a01000 0x1000,
0x00a00100 0x100;
+ interrupt-parent = intc;
};
clocks {
@@ -131,7 +132,7 @@
#address-cells = 1;
#size-cells = 1;
compatible = simple-bus;
- interrupt-parent = intc;
+ interrupt-parent = gpc;
ranges;
pmu {
@@ -700,7 +701,10 @@
gpc: gpc@020dc000 {
compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
reg = 0x020dc000 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
interrupts = GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
};
iomuxc: iomuxc@020e {
diff --git
[PATCH v4 15/21] ARM: exynos4/5: convert pmu wakeup to stacked domains
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I stronly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/exynos4.dtsi| 4 ++
arch/arm/boot/dts/exynos5250.dtsi | 4 ++
arch/arm/boot/dts/exynos5420.dtsi | 4 ++
arch/arm/mach-exynos/exynos.c | 14 ++---
arch/arm/mach-exynos/suspend.c| 122 ++
5 files changed, 129 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..0e7d74e 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -141,6 +141,9 @@
pmu_system_controller: system-controller@1002 {
compatible = samsung,exynos4210-pmu, syscon;
reg = 0x1002 0x4000;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
dsi_0: dsi@11C8 {
@@ -253,6 +256,7 @@
rtc@1007 {
compatible = samsung,s3c6410-rtc;
reg = 0x1007 0x100;
+ interrupt-parent = pmu_system_controller;
interrupts = 0 44 0, 0 45 0;
clocks = clock CLK_RTC;
clock-names = rtc;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 0a229fc..1dc5f6b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -194,6 +194,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
@@ -230,6 +233,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 517e50f..35ecd36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -309,6 +309,7 @@
rtc: rtc@101E {
clocks = clock CLK_RTC;
clock-names = rtc;
+ interrupt-parent = pmu_system_controller;
status = disabled;
};
@@ -748,6 +749,9 @@
clock-names = clkout16;
clocks = clock CLK_FIN_PLL;
#clock-cells = 1;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ interrupt-parent = gic;
};
sysreg_system_controller: syscon@1005 {
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..e417fdc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -175,16 +175,15 @@ static void __init exynos_init_io(void)
exynos_map_io();
}
+/*
+ * Apparently, these SoCs are not able to wake-up from suspend using
+ * the PMU. Too bad. Should they suddenly become capable of such a
+ * feat, the matches below should be moved to suspend.c.
+ */
static const struct of_device_id exynos_dt_pmu_match[] = {
{ .compatible = samsung,exynos3250-pmu },
- { .compatible = samsung,exynos4210-pmu },
- { .compatible = samsung,exynos4212-pmu },
- { .compatible = samsung,exynos4412-pmu },
- { .compatible = samsung,exynos4415-pmu },
- { .compatible = samsung,exynos5250-pmu },
{ .compatible = samsung,exynos5260-pmu },
{ .compatible = samsung,exynos5410-pmu },
- { .compatible = samsung,exynos5420-pmu },
{ /*sentinel*/ },
};
@@ -195,9 +194,6 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
-
- if (!pmu_base_addr)
- panic(failed to find exynos pmu register\n);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd..b325ecd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -18,7 +18,9 @@
#include linux/syscore_ops.h
#include linux/cpu_pm.h
#include linux/io.h
[PATCH v4 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = 3;
#address-cells = 1;
interrupt-controller;
- arm,routable-irqs = 160;
reg = 0xfff11000 0x1000,
0xfff10100 0x100;
};
--
2.1.4
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[PATCH v4 10/21] irqchip: GIC: get rid of routable domain
The only user of the so called routable domain functionality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d617ee5..9c30a76 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -795,15 +795,12 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_domain_set_info(d, irq, hw, gic_chip, d-host_data,
handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- gic_routable_irq_domain_ops-map(d, irq, hw);
}
return 0;
}
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
- gic_routable_irq_domain_ops-unmap(d, irq);
}
static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -822,16 +819,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0]) {
- ret = gic_routable_irq_domain_ops-xlate(d, controller,
-intspec,
-intsize,
-out_hwirq,
-out_type);
-
- if (IS_ERR_VALUE(ret))
- return ret;
- }
+ if (!intspec[0])
+ *out_hwirq += 16;
*out_type = intspec[2] IRQ_TYPE_SENSE_MASK;
@@ -888,37 +877,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
- return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
- unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
- struct device_node *controller,
- const u32 *intspec, unsigned int intsize,
- unsigned long *out_hwirq,
- unsigned int *out_type)
-{
- *out_hwirq += 16;
- return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
- .map = gic_routable_irq_domain_map,
- .unmap = gic_routable_irq_domain_unmap,
- .xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
- gic_default_routable_irq_domain_ops;
-
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
@@ -926,7 +884,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
int gic_irqs, irq_base, i;
- int nr_routable_irqs;
BUG_ON(gic_nr = MAX_GIC_NR);
@@ -982,15 +939,9 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
gic-gic_irqs = gic_irqs;
if (node) { /* DT case */
- const struct irq_domain_ops *ops =
gic_irq_domain_hierarchy_ops;
-
- if (!of_property_read_u32(node, arm,routable-irqs,
- nr_routable_irqs)) {
- ops = gic_irq_domain_ops;
- gic_irqs = nr_routable_irqs;
- }
-
- gic-domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+ gic-domain = irq_domain_add_linear(node, gic_irqs,
+
gic_irq_domain_hierarchy_ops,
+ gic);
} else {/* Non-DT case */
/*
* For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 71d706d..3978c5b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -115,11 +115,5 @@ int gic_get_cpu_id(unsigned int cpu);
void gic_migrate_target(unsigned int new_cpu_id);
unsigned long gic_get_sgir_physaddr(void);
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
- (const struct irq_domain_ops *ops)
-{
- gic_routable_irq_domain_ops = ops;
-}
[PATCH v4 03/21] ARM: tegra: skip gic_arch_extn setup if DT has a LIC node
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Acked-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 12
arch/arm/mach-tegra/tegra.c | 1 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7f87a50..1593c4c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -255,11 +255,22 @@ static void tegra114_gic_cpu_pm_registration(void)
static void tegra114_gic_cpu_pm_registration(void) { }
#endif
+static const struct of_device_id tegra_ictlr_match[] __initconst = {
+ { .compatible = nvidia,tegra20-ictlr },
+ { .compatible = nvidia,tegra30-ictlr },
+ { }
+};
+
void __init tegra_init_irq(void)
{
int i;
void __iomem *distbase;
+ if (of_find_matching_node(NULL, tegra_ictlr_match))
+ goto skip_extn_setup;
+
+ tegra_legacy_irq_syscore_init();
+
distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f;
@@ -283,5 +294,6 @@ void __init tegra_init_irq(void)
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+skip_extn_setup:
tegra114_gic_cpu_pm_registration();
}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af..c33fba7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -82,7 +82,6 @@ static void __init tegra_dt_init_irq(void)
{
tegra_init_irq();
irqchip_init();
- tegra_legacy_irq_syscore_init();
}
static void __init tegra_dt_init(void)
--
2.1.4
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Re: [patch-net-next v3 2/2] net: ethernet: cpsw: don't requests IRQs we don't use
On Sun, Jan 18, 2015 at 01:07:50AM -0500, David Miller wrote: From: Felipe Balbi ba...@ti.com Date: Fri, 16 Jan 2015 10:11:12 -0600 CPSW never uses RX_THRESHOLD or MISC interrupts. In fact, they are always kept masked in their appropriate IRQ Enable register. Instead of allocating an IRQ that never fires, it's best to remove that code altogether and let future patches implement it if anybody needs those. Signed-off-by: Felipe Balbi ba...@ti.com Applied. looks like randconfig caught a build break. Do you want an incremental patch or this patch again with the fix in it ? -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 3/5] usb: dwc3: Add quirk for Synopsis device disconnection errata
Hi,
On Mon, Jan 19, 2015 at 03:56:47PM +0800, Sneeker Yeh wrote:
Synopsis Designware USB3 IP earlier than v3.00a which is configured in silicon
with DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1, would need a specific quirk to
prevent
xhci host controller from dying when device is disconnected.
Since DWC_USB3_SUSPEND_ON_DISCONNECT_EN is an IP configuration whose state
cannot be checked from software in runtime, it has to be enabled via platform
data or device tree.
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
Documentation/devicetree/bindings/usb/dwc3.txt | 17 +
drivers/usb/dwc3/core.c|6 ++
drivers/usb/dwc3/core.h|1 +
drivers/usb/dwc3/host.c|4
drivers/usb/dwc3/platform_data.h |1 +
5 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index cd7f045..1b78b29 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -37,6 +37,23 @@ Optional properties:
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold
+ - snps,has_suspend_on_disconnect: true when IP is configured in silicon with
+ DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1, it can inject a
+ specific quirk to prevent xhci host controller from
+ dying when usb device is disconnected from root hub.
+ Since DWC_USB3_SUSPEND_ON_DISCONNECT_EN is an IP
+ configuration whose state cannot be checked from
+ software in runtime, it has to be enabled via platform
+ data or device tree.
+
+ xhci host dying symptom here is caused by that
+ DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1
+ configuration makes IP auto-suspended after PORTCSC is
+ cleared when usb device detached, then an asynchronous
+ disconnection procedure might fail using endpoint
+ command that suspened IP won't have any response to.
+
+ this issue is fixed when IP version = 3.00a.
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 25ddc39..fbceab1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -838,6 +838,9 @@ static int dwc3_probe(struct platform_device *pdev)
snps,tx_de_emphasis_quirk);
of_property_read_u8(node, snps,tx_de_emphasis,
tx_de_emphasis);
+
+ dwc-suspend_on_disconnect_quirk = of_property_read_bool(node,
+ snps,has_suspend_on_disconnect);
} else if (pdata) {
dwc-maximum_speed = pdata-maximum_speed;
dwc-has_lpm_erratum = pdata-has_lpm_erratum;
@@ -864,6 +867,9 @@ static int dwc3_probe(struct platform_device *pdev)
dwc-tx_de_emphasis_quirk = pdata-tx_de_emphasis_quirk;
if (pdata-tx_de_emphasis)
tx_de_emphasis = pdata-tx_de_emphasis;
+
+ dwc-suspend_on_disconnect_quirk =
+ pdata-has_suspend_on_disconnect;
}
/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8090249..d7458ff 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -832,6 +832,7 @@ struct dwc3 {
unsignedtx_de_emphasis_quirk:1;
unsignedtx_de_emphasis:2;
+ unsignedsuspend_on_disconnect_quirk:1;
you're missing the comment on the structure and these should be
alphabetically sorted.
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index 12bfd3c..9c42074 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -53,6 +53,10 @@ int dwc3_host_init(struct dwc3 *dwc)
pdata.usb3_lpm_capable = 1;
#endif
+ if ((dwc-revision DWC3_REVISION_300A)
+ dwc-suspend_on_disconnect_quirk)
+ pdata.delay_portcsc_clear = 1;
+
ret = platform_device_add_data(xhci, pdata, sizeof(pdata));
if (ret) {
dev_err(dwc-dev, couldn't add platform data to xHCI
device\n);
diff --git a/drivers/usb/dwc3/platform_data.h
b/drivers/usb/dwc3/platform_data.h
index a3a3b6d..69562f1 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -44,4 +44,5 @@ struct dwc3_platform_data {
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
+ unsigned
Re: [PATCH v2 4/5] xhci: Platform: Set Synopsis device disconnection quirk based on platform data
On Mon, Jan 19, 2015 at 03:56:48PM +0800, Sneeker Yeh wrote:
If an xhci platform has Synopsis device disconnection errata then enable
XHCI_DISCONNECT_QUIRK quirk flag.
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
drivers/usb/host/xhci-plat.c |3 +++
include/linux/usb/xhci_pdriver.h |4
2 files changed, 7 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 08d402b..40beb95 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -147,6 +147,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
if ((node of_property_read_bool(node, usb3-lpm-capable)) ||
(pdata pdata-usb3_lpm_capable))
xhci-quirks |= XHCI_LPM_SUPPORT;
+
+ if (pdata pdata-delay_portcsc_clear)
+ xhci-quirks |= XHCI_DISCONNECT_QUIRK;
/*
* Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
* is called by usb_add_hcd().
diff --git a/include/linux/usb/xhci_pdriver.h
b/include/linux/usb/xhci_pdriver.h
index 376654b..a37a3a5 100644
--- a/include/linux/usb/xhci_pdriver.h
+++ b/include/linux/usb/xhci_pdriver.h
@@ -18,10 +18,14 @@
*
* @usb3_lpm_capable:determines if this xhci platform supports USB3
* LPM capability
+ * @delay_portcsc_clear: determines if Synopsis USB3 core has errata in
+ * DWC_USB3_SUSPEND_ON_DISCONNECT_EN=1 hardware
+ * configuration.
*
*/
struct usb_xhci_pdata {
unsignedusb3_lpm_capable:1;
+ unsigneddelay_portcsc_clear:1;
previous patch won't build before this is applied. That's a problem.
Please shuffle things around so that each and every patch builds and
works on its own.
We cannot break bisectability ;-)
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH v2 2/5] usb: dwc3: add revision number DWC3_REVISION_300A
Hi,
On Mon, Jan 19, 2015 at 03:56:46PM +0800, Sneeker Yeh wrote:
Add the contstant for v3.00a dwc3 IP detection
Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com
---
drivers/usb/dwc3/core.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4bb9aa6..8090249 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -776,6 +776,7 @@ struct dwc3 {
#define DWC3_REVISION_260A 0x5533260a
#define DWC3_REVISION_270A 0x5533270a
#define DWC3_REVISION_280A 0x5533280a
+#define DWC3_REVISION_300A 0x5533300a
looking at Synopsys Solvnet for this IP, it shows that current version
is 2.90a. There's no 3.00a. Paul, John, is there a 3.00a version of the
DWC USB3 IP ?
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH v2 1/5] usb: dwc3: add Fujitsu Specific Glue layer
On Mon, Jan 19, 2015 at 03:56:45PM +0800, Sneeker Yeh wrote: This patch adds support for Synopsis DesignWare USB3 IP Core found on Fujitsu Socs. Signed-off-by: Sneeker Yeh sneeker@tw.fujitsu.com if this is moved after patch 3, you don't need to patch it again to add the quirk ;-) -- balbi signature.asc Description: Digital signature
Re: [PATCH 1/5] mfd: tps65218: make INT[12] and STATUS registers volatile
On Sun, Jan 18, 2015 at 09:52:14AM +, Lee Jones wrote: On Fri, 26 Dec 2014, Felipe Balbi wrote: STATUS register can be modified by the HW, so we should bypass cache because of that. In the case of INT[12] registers, they are the ones that actually clear the IRQ source at the time they are read. If we rely on the cache for them, we will never be able to clear the interrupt, which will cause our IRQ line to be disabled due to IRQ throttling. Fixes: 44b4dc6 mfd: tps65218: Add driver for the TPS65218 PMIC Cc: sta...@vger.kernel.org # v3.15+ Cc: Keerthy j-keer...@ti.com Cc: Lee Jones lee.jo...@linaro.org Signed-off-by: Felipe Balbi ba...@ti.com --- drivers/mfd/tps65218.c | 11 +++ 1 file changed, 11 insertions(+) Sorry for the delay. It's difficult to get a WiFi signal 2000m up in an Austrian mountain. :) now you're just making excuses ;-) Applied now, thanks. thanks :-) -- balbi signature.asc Description: Digital signature
[PATCH 1/1] ARM: dts: dra72-evm: Add qspi device
These add device tree entry for qspi device on dra72-evm.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
This patch is tested on linux-next and the boot logs is here [1]
[1] - http://pastebin.ubuntu.com/9783555/
---
arch/arm/boot/dts/dra72-evm.dts | 77 +
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d0..cacddd7 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -121,6 +121,18 @@
0x418 (MUX_MODE15)/* wakeup0.off */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk
*/
+ 0x78 (PIN_INPUT | MUX_MODE1)/* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1)/* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1)/* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1)/* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk
*/
+ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
+ ;
+ };
};
i2c1 {
@@ -461,3 +473,68 @@
pinctrl-0 = dcan1_pins_default;
pinctrl-1 = dcan1_pins_sleep;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = QSPI.SPL;
+ reg = 0x 0x1;
+ };
+ partition@1 {
+ label = QSPI.SPL.backup1;
+ reg = 0x0001 0x0001;
+ };
+ partition@2 {
+ label = QSPI.SPL.backup2;
+ reg = 0x0002 0x0001;
+ };
+ partition@3 {
+ label = QSPI.SPL.backup3;
+ reg = 0x0003 0x0001;
+ };
+ partition@4 {
+ label = QSPI.u-boot;
+ reg = 0x0004 0x0010;
+ };
+ partition@5 {
+ label = QSPI.u-boot-spl-os;
+ reg = 0x0014 0x0008;
+ };
+ partition@6 {
+ label = QSPI.u-boot-env;
+ reg = 0x001c 0x0001;
+ };
+ partition@7 {
+ label = QSPI.u-boot-env.backup1;
+ reg = 0x001d 0x001;
+ };
+ partition@8 {
+ label = QSPI.kernel;
+ reg = 0x001e 0x080;
+ };
+ partition@9 {
+ label = QSPI.file-system;
+ reg = 0x009e 0x0162;
+ };
+ };
+};
--
2.2.1.62.g3f15098
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Re: [PATCH RESEND v8 1/2] clk: Make clk API return per-user struct clk instances
On 17 January 2015 at 02:02, Stephen Boyd sb...@codeaurora.org wrote:
On 01/12, Tomeu Vizoso wrote:
Moves clock state to struct clk_core, but takes care to change as little API
as
possible.
struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.
The struct clk that clk_get_parent() returns isn't owned by the caller, but
by
the clock implementation, so the former shouldn't call clk_put() on it.
Because some boards in mach-omap2 still register clocks statically, their
clock
registration had to be updated to take into account that the clock
information
is stored in struct clk_core now.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
Looks mostly good. Missing some NULL checks mostly.
Sorry about that, I should have been more careful there.
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f4963b7..7eddfd8 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -114,7 +123,7 @@ static struct hlist_head *orphan_list[] = {
+static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
int level)
{
if (!c)
return;
@@ -122,14 +131,14 @@ static void clk_summary_show_one(struct seq_file *s,
struct clk *c, int level)
[...]
-static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
+static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
int level)
{
- struct clk *child;
+ struct clk_core *child;
if (!c)
return;
@@ -172,7 +181,7 @@ static const struct file_operations clk_summary_fops = {
.release= single_release,
};
-static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
+static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
{
if (!c)
return;
@@ -180,14 +189,14 @@ static void clk_dump_one(struct seq_file *s, struct
clk *c, int level)
[...]
-static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
+static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int
level)
{
- struct clk *child;
+ struct clk_core *child;
if (!c)
return;
@@ -418,19 +427,20 @@ static int __init clk_debug_init(void)
[...]
/* caller must hold prepare_lock */
-static void clk_unprepare_unused_subtree(struct clk *clk)
+static void clk_unprepare_unused_subtree(struct clk_core *clk)
{
- struct clk *child;
+ struct clk_core *child;
if (!clk)
return;
@@ -453,9 +463,9 @@ static void clk_unprepare_unused_subtree(struct clk *clk)
}
/* caller must hold prepare_lock */
-static void clk_disable_unused_subtree(struct clk *clk)
+static void clk_disable_unused_subtree(struct clk_core *clk)
{
- struct clk *child;
+ struct clk_core *child;
unsigned long flags;
if (!clk)
Note: These NULL checks look bogus. No need to fix them here, but
a patch to remove them would be nice.
Indeed.
@@ -532,48 +542,59 @@ late_initcall_sync(clk_disable_unused);
[...]
+
+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
+{
+ struct clk_core *parent;
+
+ parent = clk_core_get_parent_by_index(clk-core, index);
I suppose clk could be NULL here (although this is mostly a
clk-provider function). At least before we would return NULL in
such a case so we should keep the same behavior instead of NULL
deref.
Agreed.
+
+ return !parent ? NULL : parent-hw-clk;
+}
EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
@@ -593,9 +614,14 @@ unsigned long __clk_get_rate(struct clk *clk)
out:
return ret;
}
+
+unsigned long __clk_get_rate(struct clk *clk)
+{
+ return clk_core_get_rate_nolock(clk-core);
Oops. clk can be NULL here. We should check for that and return
0.
Agreed.
+}
EXPORT_SYMBOL_GPL(__clk_get_rate);
@@ -630,7 +656,12 @@ out:
return !!ret;
}
-bool __clk_is_enabled(struct clk *clk)
+bool __clk_is_prepared(struct clk *clk)
+{
+ return clk_core_is_prepared(clk-core);
Oops. clk can be NULL here. Return false if so. Or drop the
function entirely? It looks like it may become unused.
Are you thinking of anything specific that the alchemy arch can do
instead of calling __clk_is_prepared?
+}
@@ -650,12 +681,17 @@ bool __clk_is_enabled(struct clk *clk)
out:
return !!ret;
}
+
+bool __clk_is_enabled(struct clk *clk)
+{
+ return clk_core_is_enabled(clk-core);
Oops. clk can be NULL here. Return false if so.
Agreed.
+}
EXPORT_SYMBOL_GPL(__clk_is_enabled);
@@ -762,7 +805,12 @@ void __clk_unprepare(struct clk *clk)
if (clk-ops-unprepare)
clk-ops-unprepare(clk-hw);
- __clk_unprepare(clk-parent);
+ clk_core_unprepare(clk-parent);
+}
+
+void __clk_unprepare(struct clk *clk)
+{
+ clk_core_unprepare(clk-core);
OOps. clk can be NULL here. Bail
[PATCH v4 13/21] ARM: omap: convert wakeupgen to stacked domains
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the WUGEN HW block, kernels with this patch applied
won't have any suspend-resume facility when booted with old DTs,
and old kernels with updated DTs won't even boot.
On a platform with this patch applied, the system looks like
this:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 0 0 WUGEN 37 gp_timer
19: 233799 155916 GIC 27 arch_timer
23: 0 0 WUGEN 9 l3-dbg-irq
24: 1 0 WUGEN 10 l3-app-irq
27:282 0 WUGEN 13 omap-dma-engine
44: 0 0 4ae1.gpio 13 DMA
294: 0 0 WUGEN 20 gpmc
297:506 0 WUGEN 56 4807.i2c
298: 0 0 WUGEN 57 48072000.i2c
299: 0 0 WUGEN 61 4806.i2c
300: 0 0 WUGEN 62 4807a000.i2c
301: 8 0 WUGEN 60 4807c000.i2c
308: 2439 0 WUGEN 74 OMAP UART2
312:362 0 WUGEN 83 mmc2
313:502 0 WUGEN 86 mmc0
314: 13 0 WUGEN 94 mmc1
350: 0 0 PRCM pinctrl, pinctrl
406: 35155709 0 GIC 109 ehci_hcd:usb1
407: 0 0 WUGEN 7 palmas
409: 0 0 WUGEN 119 twl6040
410: 0 0 twl6040 5 twl6040_irq_ready
411: 0 0 twl6040 0 twl6040_irq_th
IPI0: 0 1 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 95334 902334 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4:479648 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/am4372.dtsi | 11 ++-
arch/arm/boot/dts/am437x-gp-evm.dts | 1 -
arch/arm/boot/dts/am437x-sk-evm.dts | 1 -
arch/arm/boot/dts/am43x-epos-evm.dts | 1 -
arch/arm/boot/dts/dra7.dtsi | 12 ++-
arch/arm/boot/dts/dra72x.dtsi | 2 +-
arch/arm/boot/dts/dra74x.dtsi | 2 +-
arch/arm/boot/dts/omap4-duovero.dtsi | 2 -
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 +-
arch/arm/boot/dts/omap4-sdp.dts | 8 +-
arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 -
arch/arm/boot/dts/omap4.dtsi | 18 -
arch/arm/boot/dts/omap5-cm-t54.dts| 1 -
arch/arm/boot/dts/omap5-uevm.dts | 2 -
arch/arm/boot/dts/omap5.dtsi | 26 ---
arch/arm/mach-omap2/omap-wakeupgen.c | 125 +++---
arch/arm/mach-omap2/omap-wakeupgen.h | 1 -
arch/arm/mach-omap2/omap4-common.c| 17 ++--
18 files changed, 162 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index b62a1cd..9d672a7 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -15,7 +15,7 @@
/ {
compatible = ti,am4372, ti,am43;
- interrupt-parent = gic;
+ interrupt-parent = wakeupgen;
aliases {
@@ -48,6 +48,15 @@
#interrupt-cells = 3;
reg = 0x48241000 0x1000,
0x48240100 0x0100;
+ interrupt-parent = gic;
+ };
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
};
l2-cache-controller@48242000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 7eaae4c..69f2313 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -280,7 +280,6 @@
reg = 0x24;
compatible = ti,tps65218;
interrupts = GIC_SPI 7 IRQ_TYPE_NONE; /* NMIn */
- interrupt-parent = gic;
interrupt-controller;
#interrupt-cells = 2;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 53bbfc9..029bade 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -334,7 +334,6 @@
tps@24 {
compatible = ti,tps65218;
reg = 0x24;
- interrupt-parent = gic;
interrupts = GIC_SPI 7
Re: [PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains
Am Montag, den 19.01.2015, 09:44 + schrieb Marc Zyngier:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++-
arch/arm/boot/dts/imx6sl.dtsi | 6 +-
arch/arm/boot/dts/imx6sx.dtsi | 6 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 119 insertions(+), 31 deletions(-)
[...]
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
-void imx_gpc_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 5f3602e..838da3c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -22,6 +22,7 @@
#define GPC_PGC_CPU_PDN 0x2a0
#define IMR_NUM 4
+#define GPC_MAX_IRQS (IMR_NUM * 32)
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
@@ -56,17 +57,17 @@ void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
- unsigned int idx = d-hwirq / 32 - 1;
+ unsigned int idx = d-hwirq / 32;
u32 mask;
- /* Sanity check for SPI irq */
- if (d-hwirq 32)
- return -EINVAL;
-
mask = 1 d-hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] ~mask;
+ /*
+ * Do *not* call into the parent, as the GIC doesn't have any
+ * wake-up facility...
+ */
return 0;
}
@@ -96,7 +97,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
void __iomem *reg;
u32 val;
- reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val = ~(1 hwirq % 32);
writel_relaxed(val, reg);
@@ -107,7 +108,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
void __iomem *reg;
u32 val;
- reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val |= 1 (hwirq % 32);
writel_relaxed(val, reg);
@@ -115,37 +116,115 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
static void imx_gpc_irq_unmask(struct irq_data *d)
{
- /* Sanity check for SPI irq */
- if (d-hwirq 32)
- return;
-
imx_gpc_hwirq_unmask(d-hwirq);
+ irq_chip_unmask_parent(d);
}
static void imx_gpc_irq_mask(struct irq_data *d)
{
- /* Sanity check for SPI irq */
- if (d-hwirq 32)
- return;
-
imx_gpc_hwirq_mask(d-hwirq);
+ irq_chip_mask_parent(d);
+}
+
+static struct irq_chip imx_gpc_chip = {
+ .name = GPC,
+ .irq_eoi= irq_chip_eoi_parent,
+ .irq_mask = imx_gpc_irq_mask,
+ .irq_unmask = imx_gpc_irq_unmask,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_wake = imx_gpc_irq_set_wake,
+};
+
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+ struct device_node *controller,
+ const u32 *intspec,
+ unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ if (domain-of_node != controller)
+ return -EINVAL; /* Shouldn't happen, really... */
+ if (intsize != 3)
+ return -EINVAL; /* Not GIC compliant */
+ if (intspec[0] != 0)
+ return -EINVAL; /* No PPI should point to this domain */
+
+ *out_hwirq = intspec[1];
+ *out_type = intspec[2];
+ return 0;
+}
+
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+ unsigned int irq,
+ unsigned int nr_irqs, void *data)
+{
+ struct of_phandle_args *args = data;
+ struct
Re: beaglebone black: is mem=... broken?
On Sun, Jan 18, 2015 at 06:38:46PM +0100, Geert Uytterhoeven wrote:
The boot loader copied the DT to the end of real RAM, not to the end of
the 256 MiB block? Hence the kernel accesses unmapped memory
when checking the FDT header?
actually everything is below 256M since physical memory starts at
0x8000:
U-Boot# printenv loadaddr
loadaddr=0x8200
U-Boot# printenv fdtaddr
fdtaddr=0x8800
U-Boot# load mmc 0:1 ${loadaddr} zimage
reading zimage
5694816 bytes read in 318 ms (17.1 MiB/s)
U-Boot# load mmc 0:1 ${fdtaddr} am335x-boneblack.dtb
reading am335x-boneblack.dtb
29985 bytes read in 10 ms (2.9 MiB/s)
U-Boot# setenv bootargs console=ttyO0,115200n8 root=/dev/mmcblk0p2 ro
rootfstype=ext4 rootwait debug earlyprintk mem=256M
U-Boot# bootz ${loadaddr} - ${fdtaddr}
Kernel image @ 0x8200 [ 0x00 - 0x56e560 ]
## Flattened Device Tree blob at 8800
Booting using the fdt blob at 0x8800
Loading Device Tree to 8fff5000, end 8520 ... OK
Starting kernel ...
hangs there, and after i reset i found the aforementioned oops in __log_buf.
Here is without the mem= argument:
U-Boot SPL 2015.01 (Jan 16 2015 - 10:20:36)
MMC: block number 0x100 exceeds max(0x0)
MMC: block number 0x200 exceeds max(0x0)
*** Error - No Valid Environment Area found
Using default environment
U-Boot 2015.01 (Jan 16 2015 - 10:20:36)
Watchdog enabled
I2C: ready
DRAM: 512 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net: ethaddr not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 0
U-Boot# load mmc 0:1 ${loadaddr} zimage
reading zimage
5694816 bytes read in 318 ms (17.1 MiB/s)
U-Boot# load mmc 0:1 ${fdtaddr} am335x-boneblack.dtb
reading am335x-boneblack.dtb
29985 bytes read in 11 ms (2.6 MiB/s)
U-Boot# setenv bootargs console=ttyO0,115200n8 root=/dev/mmcblk0p2 ro
rootfstype=ext4 rootwait debug earlyprintk
U-Boot# bootz ${loadaddr} - ${fdtaddr}
Kernel image @ 0x8200 [ 0x00 - 0x56e560 ]
## Flattened Device Tree blob at 8800
Booting using the fdt blob at 0x8800
Loading Device Tree to 8fff5000, end 8520 ... OK
Starting kernel ...
[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 3.19.0-rc4-1-g45aa0b7 (flag@luxor) (gcc
version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP Fri Jan 16 10:33:22 CET5
...
--
bye,
p.
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[PATCH v4 20/21] ARM: zynq: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 26f92c2..82734d5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -188,7 +188,7 @@ static void __init zynq_map_io(void)
static void __init zynq_irq_init(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
}
--
2.1.4
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[PATCH v4 12/21] DT: omap4/5: add binding for the wake-up generator
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000..43effa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as WUGEN-MPU, hence the name of the binding.
+
+Reguired properties:
+
+- compatible : should contain at least ti,omap4-wugen-mpu or
+ ti,omap5-wugen-mpu
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+ to.
+
+Notes:
+
+- Because this HW ultimately routes interrupts to the GIC, the
+ interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+ are explicitly forbiden.
+
+Example:
+
+ wakeupgen: interrupt-controller@48281000 {
+ compatible = ti,omap5-wugen-mpu, ti,omap4-wugen-mpu;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48281000 0x1000;
+ interrupt-parent = gic;
+ };
--
2.1.4
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[PATCH v4 18/21] ARM: shmobile: remove use of gic_arch_extn.irq_set_wake
shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.
It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function.
Acked-by: Simon Horman horms+rene...@verge.net.au
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-shmobile/intc-sh73a0.c | 7 +--
arch/arm/mach-shmobile/setup-r8a7779.c | 7 +--
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c
b/arch/arm/mach-shmobile/intc-sh73a0.c
index 9e36180..fd63ae6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,11 +252,6 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void
*dev_id)
return IRQ_HANDLED;
}
-static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
#define PINTER0_PHYS 0xe69000a0
#define PINTER1_PHYS 0xe69000a4
#define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -318,8 +313,8 @@ void __init sh73a0_init_irq(void)
void __iomem *gic_cpu_base = IOMEM(0xf100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
- gic_arch_extn.irq_set_wake = sh73a0_set_wake;
register_intc_controller(intcs_desc);
register_intc_controller(intc_pint0_desc);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c
b/arch/arm/mach-shmobile/setup-r8a7779.c
index 6156d17..989de2d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -713,14 +713,9 @@ void __init r8a7779_init_late(void)
}
#ifdef CONFIG_USE_OF
-static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
-{
- return 0; /* always allow wakeup */
-}
-
void __init r8a7779_init_irq_dt(void)
{
- gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
irqchip_init();
--
2.1.4
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[PATCH v4 19/21] ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flags
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index dbb2970..6ced0f6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,7 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
*/
void __init ux500_init_irq(void)
{
- gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+ gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
irqchip_init();
/*
--
2.1.4
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[PATCH v4 21/21] irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 files changed, 56 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 23fe3be..78d4dee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
#define NR_GIC_CPU_IF 8
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
-/*
- * Supported arch specific GIC irq extension.
- * Default make them NULL.
- */
-struct irq_chip gic_arch_extn = {
- .irq_eoi= NULL,
- .irq_mask = NULL,
- .irq_unmask = NULL,
- .irq_retrigger = NULL,
- .irq_set_type = NULL,
- .irq_set_wake = NULL,
-};
-
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
@@ -155,32 +142,18 @@ static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
(gic_irq(d) / 32) * 4);
- if (gic_arch_extn.irq_mask)
- gic_arch_extn.irq_mask(d);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 (gic_irq(d) % 32);
- raw_spin_lock(irq_controller_lock);
- if (gic_arch_extn.irq_unmask)
- gic_arch_extn.irq_unmask(d);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET +
(gic_irq(d) / 32) * 4);
- raw_spin_unlock(irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(irq_controller_lock);
- gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(irq_controller_lock);
- }
-
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -196,23 +169,13 @@ static int gic_set_type(struct irq_data *d, unsigned int
type)
if (type != IRQ_TYPE_LEVEL_HIGH type != IRQ_TYPE_EDGE_RISING)
return -EINVAL;
- raw_spin_lock(irq_controller_lock);
-
- if (gic_arch_extn.irq_set_type)
- gic_arch_extn.irq_set_type(d, type);
-
gic_configure_irq(gicirq, type, base, NULL);
- raw_spin_unlock(irq_controller_lock);
-
return 0;
}
static int gic_retrigger(struct irq_data *d)
{
- if (gic_arch_extn.irq_retrigger)
- return gic_arch_extn.irq_retrigger(d);
-
/* the genirq layer expects 0 if we can't retrigger in hardware */
return 0;
}
@@ -244,21 +207,6 @@ static int gic_set_affinity(struct irq_data *d, const
struct cpumask *mask_val,
}
#endif
-#ifdef CONFIG_PM
-static int gic_set_wake(struct irq_data *d, unsigned int on)
-{
- int ret = -ENXIO;
-
- if (gic_arch_extn.irq_set_wake)
- ret = gic_arch_extn.irq_set_wake(d, on);
-
- return ret;
-}
-
-#else
-#define gic_set_wake NULL
-#endif
-
static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
u32 irqstat, irqnr;
@@ -321,7 +269,6 @@ static struct irq_chip gic_chip = {
#ifdef CONFIG_SMP
.irq_set_affinity = gic_set_affinity,
#endif
- .irq_set_wake = gic_set_wake,
};
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
@@ -985,7 +932,6 @@ void __init gic_init_bases(unsigned int gic_nr, int
irq_start,
set_handle_irq(gic_handle_irq);
}
- gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 36ec4ae..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -95,8 +95,6 @@
struct device_node;
-extern struct irq_chip gic_arch_extn;
-
void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
--
2.1.4
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[PATCH v4 17/21] irqchip: gic: add an entry point to set up irqchip flags
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dreaded gic_arch_extn.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 5 +
include/linux/irqchip/arm-gic.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9c30a76..23fe3be 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.xlate = gic_irq_domain_xlate,
};
+void gic_set_irqchip_flags(unsigned long flags)
+{
+ gic_chip.flags |= flags;
+}
+
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset, struct device_node *node)
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3978c5b..36ec4ae 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -97,6 +97,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
+void gic_set_irqchip_flags(unsigned long flags);
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
--
2.1.4
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Re: [PATCH v4 14/21] ARM: imx6: convert GPC to stacked domains
On 19/01/15 10:47, Lucas Stach wrote:
Am Montag, den 19.01.2015, 09:44 + schrieb Marc Zyngier:
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: Stefan Agner ste...@agner.ch
Acked-by: Stefan Agner ste...@agner.ch
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++-
arch/arm/boot/dts/imx6sl.dtsi | 6 +-
arch/arm/boot/dts/imx6sx.dtsi | 6 +-
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/gpc.c | 127
arch/arm/mach-imx/mach-imx6q.c | 1 -
arch/arm/mach-imx/mach-imx6sl.c | 1 -
arch/arm/mach-imx/mach-imx6sx.c | 1 -
8 files changed, 119 insertions(+), 31 deletions(-)
[...]
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -102,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
-void imx_gpc_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 5f3602e..838da3c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -22,6 +22,7 @@
#define GPC_PGC_CPU_PDN 0x2a0
#define IMR_NUM 4
+#define GPC_MAX_IRQS(IMR_NUM * 32)
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
@@ -56,17 +57,17 @@ void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
-unsigned int idx = d-hwirq / 32 - 1;
+unsigned int idx = d-hwirq / 32;
u32 mask;
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return -EINVAL;
-
mask = 1 d-hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] ~mask;
+/*
+ * Do *not* call into the parent, as the GIC doesn't have any
+ * wake-up facility...
+ */
return 0;
}
@@ -96,7 +97,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
void __iomem *reg;
u32 val;
-reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val = ~(1 hwirq % 32);
writel_relaxed(val, reg);
@@ -107,7 +108,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
void __iomem *reg;
u32 val;
-reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
val = readl_relaxed(reg);
val |= 1 (hwirq % 32);
writel_relaxed(val, reg);
@@ -115,37 +116,115 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
static void imx_gpc_irq_unmask(struct irq_data *d)
{
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return;
-
imx_gpc_hwirq_unmask(d-hwirq);
+irq_chip_unmask_parent(d);
}
static void imx_gpc_irq_mask(struct irq_data *d)
{
-/* Sanity check for SPI irq */
-if (d-hwirq 32)
-return;
-
imx_gpc_hwirq_mask(d-hwirq);
+irq_chip_mask_parent(d);
+}
+
+static struct irq_chip imx_gpc_chip = {
+.name = GPC,
+.irq_eoi= irq_chip_eoi_parent,
+.irq_mask = imx_gpc_irq_mask,
+.irq_unmask = imx_gpc_irq_unmask,
+.irq_retrigger = irq_chip_retrigger_hierarchy,
+.irq_set_wake = imx_gpc_irq_set_wake,
+};
+
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+struct device_node *controller,
+const u32 *intspec,
+unsigned int intsize,
+unsigned long *out_hwirq,
+unsigned int *out_type)
+{
+if (domain-of_node != controller)
+return -EINVAL; /* Shouldn't happen, really... */
+if (intsize != 3)
+return -EINVAL; /* Not GIC compliant */
+if (intspec[0] != 0)
+return -EINVAL; /* No PPI should point to this domain */
+
+*out_hwirq = intspec[1];
+*out_type = intspec[2];
+return 0;
+}
+
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+ unsigned int irq,
+ unsigned int nr_irqs, void *data)
+{
+struct of_phandle_args *args = data;
+struct of_phandle_args parent_args;
Re: [PATCH RESEND v8 2/2] clk: Add floor and ceiling constraints to clock rates
On 17 January 2015 at 02:57, Stephen Boyd sb...@codeaurora.org wrote:
On 01/12, Tomeu Vizoso wrote:
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7eddfd8..2793bd7 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1013,8 +1015,8 @@ static unsigned long clk_core_round_rate_nolock(struct
clk_core *clk,
if (clk-ops-determine_rate) {
parent_hw = parent ? parent-hw : NULL;
- return clk-ops-determine_rate(clk-hw, rate, parent_rate,
- parent_hw);
+ return clk-ops-determine_rate(clk-hw, rate, 0, ULONG_MAX,
+ parent_rate, parent_hw);
} else if (clk-ops-round_rate)
return clk-ops-round_rate(clk-hw, rate, parent_rate);
else if (clk-flags CLK_SET_RATE_PARENT)
@@ -1453,8 +1458,20 @@ static struct clk_core *clk_calc_new_rates(struct
clk_core *clk,
/* find the closest rate and parent clk/rate */
if (clk-ops-determine_rate) {
+ hlist_for_each_entry(clk_user, clk-clks, child_node) {
+ floor_rate = max(floor_rate,
+ clk_user-floor_constraint);
+ }
+
+ hlist_for_each_entry(clk_user, clk-clks, child_node) {
+ ceiling_rate = min(ceiling_rate,
+clk_user-ceiling_constraint);
+ }
I would think we need to do this in the clk_round_rate() path as
well. We can't just pass 0 and ULONG_MAX there or we'll determine
one rate here and another rate in round_rate(), violating the
contract between set_rate() and round_rate().
Right, I have added a test for this.
+
parent_hw = parent ? parent-hw : NULL;
new_rate = clk-ops-determine_rate(clk-hw, rate,
+ floor_rate,
+ ceiling_rate,
best_parent_rate,
parent_hw);
parent = parent_hw ? parent_hw-core : NULL;
We should enforce a constraint if the clk is using the
round_rate() op too. If the .round_rate() op returns some rate
within range it should be ok. Otherwise we can fail the rate
change because it's out of range.
Ok.
We'll also need to introduce some sort of
clk_core_determine_rate(core, rate, min, max) so that clock
providers can ask parent clocks to find a rate within some range
that they can tolerate. If we update __clk_mux_determine_rate()
we can see how that would work out.
Ok, I'm testing this case as well now.
@@ -1660,13 +1657,92 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
[...]
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_core_set_rate(clk-core, rate);
clk could be NULL.
+}
EXPORT_SYMBOL_GPL(clk_set_rate);
+int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long
max)
+{
+ int ret = 0;
Check for NULL clk.
+
+/**
+ * clk_set_floor_rate - set a minimum clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired minimum clock rate in Hz
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_floor_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_set_rate_range(clk, rate, clk-ceiling_constraint);
clk could be NULL.
+}
+EXPORT_SYMBOL_GPL(clk_set_floor_rate);
+
+/**
+ * clk_set_ceiling_rate - set a maximum clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired maximum clock rate in Hz
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_ceiling_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_set_rate_range(clk, clk-floor_constraint, rate);
clk could be NULL.
+}
+EXPORT_SYMBOL_GPL(clk_set_ceiling_rate);
+
static struct clk_core *clk_core_get_parent(struct clk_core *core)
{
struct clk_core *parent;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2e65419..ae5c800 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -175,9 +175,12 @@ struct clk_ops {
unsigned long parent_rate);
long(*round_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
- long(*determine_rate)(struct clk_hw *hw, unsigned long
rate,
- unsigned long *best_parent_rate,
- struct clk_hw **best_parent_hw);
+ long(*determine_rate)(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long floor_rate,
+ unsigned long ceiling_rate,
I wonder if we should call this min_rate and
Re: [PATCH 0/2] Minimal FAPLL clock support for dm816x
Quoting Mike Turquette (2015-01-14 14:06:49) Quoting Tony Lindgren (2015-01-13 14:51:26) Hi all, Here's a minimal support for the FAPLL (Flying Adder PLL) on dm816x which is a omap variant. Tony, Patches look fine to me. I'll give it a few days for Paul or Tero to comment if they have any concerns. Applied to clk-next. Regards, Mike Also, flying adder pll is a pretty badass pll name. Regards, Mike Regards, Tony Tony Lindgren (2): clk: ti: Add support for FAPLL on dm816x clk: ti: Initialize clocks for dm816x .../devicetree/bindings/clock/ti/fapll.txt | 33 ++ drivers/clk/ti/Makefile| 1 + drivers/clk/ti/clk-3xxx.c | 8 +- drivers/clk/ti/clk-816x.c | 53 +++ drivers/clk/ti/fapll.c | 410 + 5 files changed, 498 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/fapll.txt create mode 100644 drivers/clk/ti/clk-816x.c create mode 100644 drivers/clk/ti/fapll.c -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [next-20150119]regression (mm)?
On 01/19/2015 10:59 AM, Tyler Baker wrote: I can confirm, I am observing the same issue in my lab. 15 platforms failed to boot on next-20150119. http://kernelci.org/boot/?next-20150119fail http://kernelci.org/boot/all/job/next/kernel/next-20150119/ I see many platforms succeed in lab-khilman, but fails in your farm as well :( For example: http://storage.kernelci.org/next/next-20150119/arm-imx_v6_v7_defconfig/lab-khilman/boot-imx6q-wandboard.txt has the same errors, but marked success. http://storage.kernelci.org/next/next-20150119/arm-imx_v6_v7_defconfig/lab-tbaker/boot-imx6q-wandboard.txt is marked fail. I suppose this is much worse than the pass status indicates. On Monday, 19 January 2015, Nishanth Menon n...@ti.com mailto:n...@ti.com wrote: Hi, Most platforms seem broken intoday's next tag. https://github.com/nmenon/kernel-test-logs/tree/next-20150119 (defconfig: omap2plus_defconfig) [7.166600] [ cut here ] [7.171676] WARNING: CPU: 0 PID: 54 at mm/mmap.c:2859 exit_mmap+0x1a8/0x21c() [7.179194] Modules linked in: [7.182479] CPU: 0 PID: 54 Comm: init Not tainted 3.19.0-rc5-next-20150119-2-gfdefcded1272 #1 [7.191863] Hardware name: Generic AM33XX (Flattened Device Tree) [7.198318] [c00153f0] (unwind_backtrace) from [c0011a74] (show_stack+0x10/0x14) [7.206528] [c0011a74] (show_stack) from [c0580150] (dump_stack+0x78/0x94) [7.214191] [c0580150] (dump_stack) from [c003d4d0] (warn_slowpath_common+0x7c/0xb4) [7.222751] [c003d4d0] (warn_slowpath_common) from [c003d524] (warn_slowpath_null+0x1c/0x24) [7.232038] [c003d524] (warn_slowpath_null) from [c012de64] (exit_mmap+0x1a8/0x21c) [7.240536] [c012de64] (exit_mmap) from [c003abb8] (mmput+0x44/0xec) [7.247612] [c003abb8] (mmput) from [c0151368] (flush_old_exec+0x300/0x5a4) [7.255357] [c0151368] (flush_old_exec) from [c0195c10] (load_elf_binary+0x2ec/0x1144) [7.264111] [c0195c10] (load_elf_binary) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.273311] [c0150ea0] (search_binary_handler) from [c019554c] (load_script+0x260/0x280) [7.282232] [c019554c] (load_script) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.291066] [c0150ea0] (search_binary_handler) from [c0151f0c] (do_execveat_common+0x538/0x6c4) [7.300628] [c0151f0c] (do_execveat_common) from [c01520c4] (do_execve+0x2c/0x34) [7.308881] [c01520c4] (do_execve) from [c000e5e0] (ret_fast_syscall+0x0/0x4c) [7.316881] ---[ end trace 3b8a46b1b280f423 ]--- -- Regards, Nishanth Menon ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org javascript:; http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/4] ARM: dts: Add minimal support for dm8168-evm
* Matthijs van Duin matthijsvand...@gmail.com [150117 14:41]: On 17 January 2015 at 19:14, Tony Lindgren t...@atomide.com wrote: Oh OK. And looks like dm814x trm claims to have PINCNTL[7:0] bits for MUXMODE instead of just bits [2:0]? However, the datasheet's table of possible mux modes per pin has as column headers: 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80. (mode 0, called safe mode is mentioned separately) For compatibility sake I'm personally more inclined to consider them modes 0-7 with safe mode being -1. Oh, and I just remembered: while 811x is mostly compatible with 814x, it has up to 12 mux modes per pin. So replace byte-write by u16-write in my previous post ;-) Luckily those can be defined which ever way in pinctrl single just by changing the pinctrl-single,register-width entry. Got any generic naming in mind for the helper macro we could use? I've already been pondering what to call this family, since architecturally they do very clearly form a fairly close family related to, but also clearly distinct from, the omap4/5 line. As you may notice from my spreadsheet I already generally prefer to use their names (Netra, Centaurus, Subarctic, Aegis), both because names are rather more memorable and distinguishable for humans than 4-digit numbers and because each actually has a flurry of wildly different part codes depending on which subsystems happen to fail the factory test and get disabled (which may of course be a big deal featurewise but is rather irrelevant to the kernel). Still leaves four names to unify... I may be biased but I'm leaning towards Centauroid: Centaurus (814x) seems to have a fairly central position, being memory-map compatible with the there other members (i.e. no subsystem/peripheral of Centaurus overlaps a different one of another device), while the same is not true between Netra (816x) and subarctic (335x). I suspect this may be because Centaurus and Netra form a single product line (DM81xx) iin one market segment (video) while Centaurus and Subarctic form a single product line (DRA6xx) in another market segment (automotive). Well sounds like no need to start messing with the existing ti81xx defines excemt maybe rename cpu_is_ti81xx to soc_is_dm81xx and so on. There are only very few places referencing that now. Cool, that certainly helps. To me it looks dm814x needs it's own clock driver for the source clocks, but after that the dividers are similar to dm816x and am33xx. Have not looked at the am814x beyond that though. dm814x you mean... the downfeatured Sitara version got called am387x, naturally. ;-) Yes I mean dm814x sorry :) The biggest architectural differences between three chips are indeed in PRCM, where each member has its own peculiarities: Netra and Centaurus both have the simple but clean omap4-subset PRCM. No fancy auto-management by hardware but at least a clean well-organised interface, with the biggest blemish being the register-swap in PRM_SGX. (Subarctic's PRCM is of course shocking in contrast, being organized by sort -R, incompatibility with the omap4/5 register layouts, and a seemingly endless supply of novel ways of being inconsistent.) Uhh yeah. Netra however has the FAPLL experiment, which apparently wasn't a success so while Centaurus retained much of the clock tree it reverted to using normal PLLs by replacing the FAPLLs with its PLL subsystem containing additional clock muxes to sort of glue it onto the existing clock tree, making the clock tree a bit messier. (Especially older versions of the TRM were very confusing to those unfamiliar with this Netra-heritage since FAPLL names were still all over the place.) In line with the fully software managed tradition, it seems to wire *all* control/status signals of the PLLs directly into registers. They can be slightly fickle (and mucking up the MPU PLL can leave you pretty screwed, especially since the watchdog reset doesn't reset the PLLs). Hmm I sort of got the idea that dm814x and dm816x were done about the same time. Are you saying dm814x was actually done after dm816x? Also important: Centaurus has very similar Ethernet subsystem to that of subarctic, though some components are a slightly older minor revision. In violation of what a minor revision normally means, they are however software-incompatible thanks to moving blocks of registers around to different offsets, and some per-port settings became global or vice versa. This however seems to be a tradition for the 3-port gigabit switch subsystem: out of curiosity I examined the ones in other TI SoCs, and it turns out that literally *all* of them have different, incompatible register layouts (sometimes also extending to the switch table entries and/or DMA descriptors). Yeah this davinci_emac vs cpsw stuff is messy and I noticed too that the registers are different. Other than this, the subsystems and peripherals are mostly familiar
[PATCH 1/5] extcon: gpio-usb: Introduce gpio usb extcon driver
This driver observes the USB ID pin connected over a GPIO and
updates the USB cable extcon states accordingly.
The existing GPIO extcon driver is not suitable for this purpose
as it needs to be taught to understand USB cable states and it
can't handle more than one cable per instance.
For the USB case we need to handle 2 cable states.
1) USB (attach/detach)
2) USB-Host (attach/detach)
This driver can be easily updated in the future to handle VBUS
events in case it happens to be available on GPIO for any platform.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/extcon/extcon-usb.txt | 20 ++
drivers/extcon/Kconfig | 7 +
drivers/extcon/Makefile| 1 +
drivers/extcon/extcon-gpio-usb.c | 225 +
4 files changed, 253 insertions(+)
create mode 100644 Documentation/devicetree/bindings/extcon/extcon-usb.txt
create mode 100644 drivers/extcon/extcon-gpio-usb.c
diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb.txt
b/Documentation/devicetree/bindings/extcon/extcon-usb.txt
new file mode 100644
index 000..171c5a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/extcon/extcon-usb.txt
@@ -0,0 +1,20 @@
+USB Extcon device
+
+This is a virtual device used to generate USB cable states from the USB ID pin
+connected to a GPIO pin.
+
+Required properties:
+- compatible: Should be linux,extcon-usb
+- id-gpio: gpio for USB ID pin. See gpio binding.
+
+Example:
+ extcon_usb1 {
+ compatible = linux,extcon-usb;
+ id-gpio = gpio6 1 GPIO_ACTIVE_HIGH;
+ }
+
+ usb@1 {
+ ...
+ extcon = extcon_usb1;
+ ...
+ };
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index 6a1f7de..8106a83 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -35,6 +35,13 @@ config EXTCON_GPIO
Say Y here to enable GPIO based extcon support. Note that GPIO
extcon supports single state per extcon instance.
+config EXTCON_GPIO_USB
+ tristate USB GPIO extcon support
+ depends on GPIOLIB
+ help
+ Say Y here to enable GPIO based USB cable detection extcon support.
+ Used typically if GPIO is used for USB ID pin detection.
+
config EXTCON_MAX14577
tristate MAX14577/77836 EXTCON Support
depends on MFD_MAX14577
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 0370b42..bae594b 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_EXTCON_MAX8997) += extcon-max8997.o
obj-$(CONFIG_EXTCON_PALMAS)+= extcon-palmas.o
obj-$(CONFIG_EXTCON_RT8973A) += extcon-rt8973a.o
obj-$(CONFIG_EXTCON_SM5502)+= extcon-sm5502.o
+obj-$(CONFIG_EXTCON_GPIO_USB) += extcon-gpio-usb.o
diff --git a/drivers/extcon/extcon-gpio-usb.c b/drivers/extcon/extcon-gpio-usb.c
new file mode 100644
index 000..aeb2298
--- /dev/null
+++ b/drivers/extcon/extcon-gpio-usb.c
@@ -0,0 +1,225 @@
+/**
+ * drivers/extcon/extcon_gpio_usb.c - USB GPIO extcon driver
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Roger Quadros rog...@ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/extcon.h
+#include linux/extcon/extcon-gpio.h
+#include linux/gpio.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/irq.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_gpio.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/workqueue.h
+
+#define USB_GPIO_DEBOUNCE_MS 20 /* ms */
+
+struct usb_extcon_info {
+ struct device *dev;
+ struct extcon_dev *edev;
+
+ struct gpio_desc *id_gpiod;
+ int id_irq;
+
+ unsigned long debounce_jiffies;
+ struct delayed_work wq_detcable;
+};
+
+/* List of detectable cables */
+enum {
+ EXTCON_CABLE_USB = 0,
+ EXTCON_CABLE_USB_HOST,
+
+ EXTCON_CABLE_END,
+};
+
+static const char *usb_extcon_cable[] = {
+ [EXTCON_CABLE_USB] = USB,
+ [EXTCON_CABLE_USB_HOST] = USB-Host,
+ NULL,
+};
+
+static void usb_extcon_detect_cable(struct work_struct *work)
+{
+ int id;
+ struct usb_extcon_info *info;
+ const char **cable_names;
+
+ info = container_of(to_delayed_work(work), struct usb_extcon_info,
+wq_detcable);
+ cable_names = info-edev-supported_cable;
+
+ /* check ID and update cable state */
+ id =
Re: [next-20150119]regression (mm)?
On 19 January 2015 at 09:04, Nishanth Menon n...@ti.com wrote: On 01/19/2015 10:59 AM, Tyler Baker wrote: I can confirm, I am observing the same issue in my lab. 15 platforms failed to boot on next-20150119. http://kernelci.org/boot/?next-20150119fail http://kernelci.org/boot/all/job/next/kernel/next-20150119/ I see many platforms succeed in lab-khilman, but fails in your farm as well :( For example: http://storage.kernelci.org/next/next-20150119/arm-imx_v6_v7_defconfig/lab-khilman/boot-imx6q-wandboard.txt has the same errors, but marked success. http://storage.kernelci.org/next/next-20150119/arm-imx_v6_v7_defconfig/lab-tbaker/boot-imx6q-wandboard.txt is marked fail. I suppose this is much worse than the pass status indicates. I agree. I believe this boots were marked as 'passed' because the platforms eventually reached userspace despite the kernel spewing errors. I've re-run a few of my boots, and sometimes the platform reaches userspace, other times it hangs. On Monday, 19 January 2015, Nishanth Menon n...@ti.com mailto:n...@ti.com wrote: Hi, Most platforms seem broken intoday's next tag. https://github.com/nmenon/kernel-test-logs/tree/next-20150119 (defconfig: omap2plus_defconfig) [7.166600] [ cut here ] [7.171676] WARNING: CPU: 0 PID: 54 at mm/mmap.c:2859 exit_mmap+0x1a8/0x21c() [7.179194] Modules linked in: [7.182479] CPU: 0 PID: 54 Comm: init Not tainted 3.19.0-rc5-next-20150119-2-gfdefcded1272 #1 [7.191863] Hardware name: Generic AM33XX (Flattened Device Tree) [7.198318] [c00153f0] (unwind_backtrace) from [c0011a74] (show_stack+0x10/0x14) [7.206528] [c0011a74] (show_stack) from [c0580150] (dump_stack+0x78/0x94) [7.214191] [c0580150] (dump_stack) from [c003d4d0] (warn_slowpath_common+0x7c/0xb4) [7.222751] [c003d4d0] (warn_slowpath_common) from [c003d524] (warn_slowpath_null+0x1c/0x24) [7.232038] [c003d524] (warn_slowpath_null) from [c012de64] (exit_mmap+0x1a8/0x21c) [7.240536] [c012de64] (exit_mmap) from [c003abb8] (mmput+0x44/0xec) [7.247612] [c003abb8] (mmput) from [c0151368] (flush_old_exec+0x300/0x5a4) [7.255357] [c0151368] (flush_old_exec) from [c0195c10] (load_elf_binary+0x2ec/0x1144) [7.264111] [c0195c10] (load_elf_binary) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.273311] [c0150ea0] (search_binary_handler) from [c019554c] (load_script+0x260/0x280) [7.282232] [c019554c] (load_script) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.291066] [c0150ea0] (search_binary_handler) from [c0151f0c] (do_execveat_common+0x538/0x6c4) [7.300628] [c0151f0c] (do_execveat_common) from [c01520c4] (do_execve+0x2c/0x34) [7.308881] [c01520c4] (do_execve) from [c000e5e0] (ret_fast_syscall+0x0/0x4c) [7.316881] ---[ end trace 3b8a46b1b280f423 ]--- -- Regards, Nishanth Menon ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org javascript:; http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog -- Regards, Nishanth Menon -- Tyler Baker Tech Lead, LAVA Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [next-20150119]regression (mm)?
Hi, On Mon, Jan 19, 2015 at 10:42:04AM -0600, Nishanth Menon wrote: Most platforms seem broken intoday's next tag. https://github.com/nmenon/kernel-test-logs/tree/next-20150119 (defconfig: omap2plus_defconfig) [7.166600] [ cut here ] [7.171676] WARNING: CPU: 0 PID: 54 at mm/mmap.c:2859 exit_mmap+0x1a8/0x21c() [7.179194] Modules linked in: [7.182479] CPU: 0 PID: 54 Comm: init Not tainted 3.19.0-rc5-next-20150119-2-gfdefcded1272 #1 [7.191863] Hardware name: Generic AM33XX (Flattened Device Tree) [7.198318] [c00153f0] (unwind_backtrace) from [c0011a74] (show_stack+0x10/0x14) [7.206528] [c0011a74] (show_stack) from [c0580150] (dump_stack+0x78/0x94) [7.214191] [c0580150] (dump_stack) from [c003d4d0] (warn_slowpath_common+0x7c/0xb4) [7.222751] [c003d4d0] (warn_slowpath_common) from [c003d524] (warn_slowpath_null+0x1c/0x24) [7.232038] [c003d524] (warn_slowpath_null) from [c012de64] (exit_mmap+0x1a8/0x21c) [7.240536] [c012de64] (exit_mmap) from [c003abb8] (mmput+0x44/0xec) [7.247612] [c003abb8] (mmput) from [c0151368] (flush_old_exec+0x300/0x5a4) [7.255357] [c0151368] (flush_old_exec) from [c0195c10] (load_elf_binary+0x2ec/0x1144) [7.264111] [c0195c10] (load_elf_binary) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.273311] [c0150ea0] (search_binary_handler) from [c019554c] (load_script+0x260/0x280) [7.282232] [c019554c] (load_script) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.291066] [c0150ea0] (search_binary_handler) from [c0151f0c] (do_execveat_common+0x538/0x6c4) [7.300628] [c0151f0c] (do_execveat_common) from [c01520c4] (do_execve+0x2c/0x34) [7.308881] [c01520c4] (do_execve) from [c000e5e0] (ret_fast_syscall+0x0/0x4c) [7.316881] ---[ end trace 3b8a46b1b280f423 ]--- seems like it's caused by: b316feb3c37ff19cddcaf1f6b5056c633193257d is the first bad commit Adding Kiryl to the loop. git bisect start # good: [ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc] Linux 3.19-rc5 git bisect good ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc # bad: [a0d4287f787889e59db0fd295853a0f1f55d0699] Add linux-next specific files for 20150119 git bisect bad a0d4287f787889e59db0fd295853a0f1f55d0699 # good: [1c2f70b77b8ca77f10c59d479d009e07359d00d2] Merge remote-tracking branch 'drm/drm-next' git bisect good 1c2f70b77b8ca77f10c59d479d009e07359d00d2 # good: [73c1390843223d8bfc85795c560c36b3d0ffee40] Merge remote-tracking branch 'leds/for-next' git bisect good 73c1390843223d8bfc85795c560c36b3d0ffee40 # good: [7bc6bef35d48e91ad796b6eead7304998842c782] Merge remote-tracking branch 'pinctrl/for-next' git bisect good 7bc6bef35d48e91ad796b6eead7304998842c782 # bad: [45e1eaa38732ffa3de0d18fe95d2d2b960a7c777] lib: bitmap: change bitmap_shift_right to take unsigned parameters git bisect bad 45e1eaa38732ffa3de0d18fe95d2d2b960a7c777 # good: [c82a73a0369a7dd6dcfaf9e6bd572a4e5deda223] mm, page_alloc: reduce number of alloc_pages* functions' parameters git bisect good c82a73a0369a7dd6dcfaf9e6bd572a4e5deda223 # bad: [0b1c810fbc4bbff7e314dd6ff91c2b4af499199d] mm: don't split THP page when syscall is called git bisect bad 0b1c810fbc4bbff7e314dd6ff91c2b4af499199d # good: [54faa439355a9ae476a446429967e9e38f04363e] oom, PM: make OOM detection in the freezer path raceless git bisect good 54faa439355a9ae476a446429967e9e38f04363e # bad: [b6c9f11c6b6993303067f7c04a73258226a6e77e] mm/compaction: add tracepoint to observe behaviour of compaction defer git bisect bad b6c9f11c6b6993303067f7c04a73258226a6e77e # good: [9ce5d3fb13a80f28db450de4ecf2727893e99c93] mm: pagemap_read: limit scan to virtual region being asked git bisect good 9ce5d3fb13a80f28db450de4ecf2727893e99c93 # bad: [1a7a376546ca56e7750987c15d0c7541c17a512c] mm/compaction: change tracepoint format from decimal to hexadecimal git bisect bad 1a7a376546ca56e7750987c15d0c7541c17a512c # bad: [4081187ff19cf2186010c003939c17d70d0bbb27] page_writeback: put account_page_redirty() after set_page_dirty() git bisect bad 4081187ff19cf2186010c003939c17d70d0bbb27 # bad: [b316feb3c37ff19cddcaf1f6b5056c633193257d] mm: account pmd page tables to the process git bisect bad b316feb3c37ff19cddcaf1f6b5056c633193257d # first bad commit: [b316feb3c37ff19cddcaf1f6b5056c633193257d] mm: account pmd page tables to the process I've added a dump_mm() call when the bug happens followed by a while (true) loop (to avoid constant reprinting of the same thing), here's what I get: [7.235903] [ cut here ] [7.240881] WARNING: CPU: 0 PID: 58 at mm/mmap.c:2859 exit_mmap+0x1b4/0x218() [7.248369] Modules linked in: ipv6 autofs4 [7.252792] CPU: 0 PID: 58 Comm: systemd Not tainted 3.19.0-rc5-next-20150119-dirty #888 [7.261274] Hardware name: Generic AM43 (Flattened Device Tree) [7.267512] [c0015afc] (unwind_backtrace) from [c001221c] (show_stack+0x10/0x14
[next-20150119]regression (mm)?
Hi, Most platforms seem broken intoday's next tag. https://github.com/nmenon/kernel-test-logs/tree/next-20150119 (defconfig: omap2plus_defconfig) [7.166600] [ cut here ] [7.171676] WARNING: CPU: 0 PID: 54 at mm/mmap.c:2859 exit_mmap+0x1a8/0x21c() [7.179194] Modules linked in: [7.182479] CPU: 0 PID: 54 Comm: init Not tainted 3.19.0-rc5-next-20150119-2-gfdefcded1272 #1 [7.191863] Hardware name: Generic AM33XX (Flattened Device Tree) [7.198318] [c00153f0] (unwind_backtrace) from [c0011a74] (show_stack+0x10/0x14) [7.206528] [c0011a74] (show_stack) from [c0580150] (dump_stack+0x78/0x94) [7.214191] [c0580150] (dump_stack) from [c003d4d0] (warn_slowpath_common+0x7c/0xb4) [7.222751] [c003d4d0] (warn_slowpath_common) from [c003d524] (warn_slowpath_null+0x1c/0x24) [7.232038] [c003d524] (warn_slowpath_null) from [c012de64] (exit_mmap+0x1a8/0x21c) [7.240536] [c012de64] (exit_mmap) from [c003abb8] (mmput+0x44/0xec) [7.247612] [c003abb8] (mmput) from [c0151368] (flush_old_exec+0x300/0x5a4) [7.255357] [c0151368] (flush_old_exec) from [c0195c10] (load_elf_binary+0x2ec/0x1144) [7.264111] [c0195c10] (load_elf_binary) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.273311] [c0150ea0] (search_binary_handler) from [c019554c] (load_script+0x260/0x280) [7.282232] [c019554c] (load_script) from [c0150ea0] (search_binary_handler+0x88/0x1ac) [7.291066] [c0150ea0] (search_binary_handler) from [c0151f0c] (do_execveat_common+0x538/0x6c4) [7.300628] [c0151f0c] (do_execveat_common) from [c01520c4] (do_execve+0x2c/0x34) [7.308881] [c01520c4] (do_execve) from [c000e5e0] (ret_fast_syscall+0x0/0x4c) [7.316881] ---[ end trace 3b8a46b1b280f423 ]--- -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/7] ARM: OMAP2+: Remove unused ti81xx platform init code
* Matthijs van Duin matthijsvand...@gmail.com [150118 12:35]:
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -82,16 +82,8 @@ void __init usb_musb_init(struct omap_musb_board_data
*musb_board_data)
musb_plat.mode = board_data-mode;
musb_plat.extvbus = board_data-extvbus;
- if (soc_is_am35xx()) {
Was it intentional that this patch also removed a test for am35xx
(rather than am335x) ?
Oops that was not intentional. However, with the pending patches to
make am3517 dt only, this won't hurt anything as the only legacy
platform then left are omap3430 to omap3730 which us the default
musb-omap2430.
Regards,
Tony
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[PATCH v9 2/3] clk: Make clk API return per-user struct clk instances
Moves clock state to struct clk_core, but takes care to change as little API as
possible.
struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.
The struct clk that clk_get_parent() returns isn't owned by the caller, but by
the clock implementation, so the former shouldn't call clk_put() on it.
Because some boards in mach-omap2 still register clocks statically, their clock
registration had to be updated to take into account that the clock information
is stored in struct clk_core now.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
v9: * Add missing NULL checks
* Remove __clk_prepare and __clk_unprepare as they are unused
now
v7: * Add stub for __of_clk_get_by_name to fix builds without OF
v6: * Guard against NULL pointer
v4: * Remove unused function __clk_core_to_clk
* Use core more often as the name for struct clk_core* variables
* Make sure we don't lose information about the caller in of_clk_get_*
v3: * Rebase on top of linux-next 20141009
v2: * Remove exported functions that aren't really used outside clk.c
* Rename new internal functions to clk_core_ prefix
* Remove redundant checks for error pointers in *_get_parent
* Change __clk_create_clk to take a struct clk_hw instead
* Match the original error behavior in clk_get_sys
---
arch/arm/mach-omap2/cclock3xxx_data.c | 108 --
arch/arm/mach-omap2/clock.h | 11 +-
arch/arm/mach-omap2/clock_common_data.c | 5 +-
drivers/clk/clk.c | 633
drivers/clk/clk.h | 5 +
drivers/clk/clkdev.c| 80 +++-
include/linux/clk-private.h | 35 +-
include/linux/clk-provider.h| 11 +-
8 files changed, 583 insertions(+), 305 deletions(-)
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c
b/arch/arm/mach-omap2/cclock3xxx_data.c
index 644ff32..4305105 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -82,7 +82,7 @@ DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
-DEFINE_CLK_DIVIDER(sys_ck, osc_sys_ck, osc_sys_ck, 0x0,
+DEFINE_CLK_DIVIDER(sys_ck, osc_sys_ck, osc_sys_ck_core, 0x0,
OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
@@ -132,7 +132,7 @@ static struct clk_hw_omap dpll3_ck_hw = {
DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
-DEFINE_CLK_DIVIDER(dpll3_m2_ck, dpll3_ck, dpll3_ck, 0x0,
+DEFINE_CLK_DIVIDER(dpll3_m2_ck, dpll3_ck, dpll3_ck_core, 0x0,
OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
@@ -149,12 +149,12 @@ static const struct clk_ops core_ck_ops = {};
DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
-DEFINE_CLK_DIVIDER(l3_ick, core_ck, core_ck, 0x0,
+DEFINE_CLK_DIVIDER(l3_ick, core_ck, core_ck_core, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
-DEFINE_CLK_DIVIDER(l4_ick, l3_ick, l3_ick, 0x0,
+DEFINE_CLK_DIVIDER(l4_ick, l3_ick, l3_ick_core, 0x0,
OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
@@ -275,9 +275,9 @@ static struct clk_hw_omap dpll1_ck_hw = {
DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
-DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, dpll1_ck, dpll1_ck, 0x0, 2, 1);
+DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, dpll1_ck, dpll1_ck_core, 0x0, 2, 1);
-DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, dpll1_x2_ck, dpll1_x2_ck, 0x0,
+DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, dpll1_x2_ck, dpll1_x2_ck_core, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
@@ -292,7 +292,7 @@ static const char *mpu_ck_parent_names[] = {
DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, mpu_clkdm);
DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
-DEFINE_CLK_DIVIDER(arm_fck, mpu_ck, mpu_ck, 0x0,
+DEFINE_CLK_DIVIDER(arm_fck, mpu_ck, mpu_ck_core, 0x0,
OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
0x0, NULL);
@@ -424,7 +424,7 @@ static const struct clk_div_table dpll4_mx_ck_div_table[] =
{
{ .div = 0 },
};
-DEFINE_CLK_DIVIDER(dpll4_m5_ck, dpll4_ck, dpll4_ck, 0x0,
[PATCH v9 3/3] clk: Add floor and ceiling constraints to clock rates
Adds a way for clock consumers to set maximum and minimum rates. This can be
used for thermal drivers to set ceiling rates, or by misc. drivers to set
floor rates to assure a minimum performance level.
Changes the signature of the determine_rate callback by adding the
parameters floor_rate and ceiling_rate.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
v9: * s/floor/min and s/ceiling/max
* Add a bunch of NULL checks
* Propagate our rate range when querying our parent for the rate
* Take constraints into account in clk_round_rate
* Add __clk_determine_rate() for clk providers to ask their
parents for a rate within their range
* Make sure that what ops-round_rate returns when changing
rates is within the range
v7: * Update a few more instances in new code
v6: * Take the prepare lock before removing a per-user clk
* Init per-user clks list before adding the first clk
* Pass the constraints to determine_rate and let clk
implementations deal with constraints
* Add clk_set_rate_range
v5: * Initialize clk.ceiling_constraint to ULONG_MAX
* Warn about inconsistent constraints
v4: * Copy function docs from header
* Move WARN out of critical section
* Refresh rate after removing a per-user clk
* Rename clk_core.per_user_clks to clk_core.clks
* Store requested rate and re-apply it when constraints are updated
---
Documentation/clk.txt | 2 +
arch/arm/mach-omap2/dpll3xxx.c | 2 +
arch/arm/mach-omap2/dpll44xx.c | 2 +
arch/mips/alchemy/common/clock.c| 8 ++
drivers/clk/at91/clk-programmable.c | 2 +
drivers/clk/bcm/clk-kona.c | 2 +
drivers/clk/clk-composite.c | 9 +-
drivers/clk/clk.c | 216 ++--
drivers/clk/hisilicon/clk-hi3620.c | 2 +
drivers/clk/mmp/clk-mix.c | 2 +
drivers/clk/qcom/clk-pll.c | 1 +
drivers/clk/qcom/clk-rcg.c | 10 +-
drivers/clk/qcom/clk-rcg2.c | 6 +
drivers/clk/sunxi/clk-factors.c | 2 +
drivers/clk/sunxi/clk-sun6i-ar100.c | 2 +
include/linux/clk-private.h | 6 +
include/linux/clk-provider.h| 15 ++-
include/linux/clk.h | 28 +
include/linux/clk/ti.h | 4 +
19 files changed, 281 insertions(+), 40 deletions(-)
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 4ff8462..0e4f90a 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -73,6 +73,8 @@ the operations defined in clk.h:
unsigned long *parent_rate);
long(*determine_rate)(struct clk_hw *hw,
unsigned long rate,
+ unsigned long min_rate,
+ unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw
**best_parent_clk);
int (*set_parent)(struct clk_hw *hw, u8 index);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index c2da2a0..ac3fb11 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
* in failure.
*/
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long min_rate,
+ unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk)
{
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 0e58e5a..acacb90 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -222,6 +222,8 @@ out:
* in failure.
*/
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long min_rate,
+ unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk)
{
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc..4e65404 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -373,6 +373,8 @@ static long alchemy_calc_div(unsigned long rate, unsigned
long prate,
}
static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
+ unsigned long min_rate,
+ unsigned long max_rate,
unsigned long
Re: [patch-net-next v3 2/2] net: ethernet: cpsw: don't requests IRQs we don't use
From: Felipe Balbi ba...@ti.com Date: Mon, 19 Jan 2015 08:40:17 -0600 On Sun, Jan 18, 2015 at 01:07:50AM -0500, David Miller wrote: From: Felipe Balbi ba...@ti.com Date: Fri, 16 Jan 2015 10:11:12 -0600 CPSW never uses RX_THRESHOLD or MISC interrupts. In fact, they are always kept masked in their appropriate IRQ Enable register. Instead of allocating an IRQ that never fires, it's best to remove that code altogether and let future patches implement it if anybody needs those. Signed-off-by: Felipe Balbi ba...@ti.com Applied. looks like randconfig caught a build break. Do you want an incremental patch or this patch again with the fix in it ? Always incremental patches. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] ARM: dts: dra72-evm: Add extcon nodes for USB
On this EVM, the USB cable state has to be determined via the
ID pin tied to a GPIO line. We use the gpio-usb-extcon driver
to read the ID pin and the extcon framework to forward
the USB cable state information to the USB driver so the
controller can be configured in the right mode (host/peripheral).
Gets USB peripheral mode to work on this EVM.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d0..d93a98f 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include dra72x.dtsi
+#include dt-bindings/gpio/gpio.h
/ {
model = TI DRA722;
@@ -24,6 +25,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
};
+
+ extcon_usb1: extcon_usb1 {
+ compatible = linux,extcon-usb;
+ id-gpio = pcf_gpio_21 1 GPIO_ACTIVE_HIGH;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = linux,extcon-usb;
+ id-gpio = pcf_gpio_21 2 GPIO_ACTIVE_HIGH;
+ };
};
dra7_pmx_core {
@@ -243,6 +254,18 @@
ti,palmas-long-press-seconds = 6;
};
};
+
+ pcf_gpio_21: gpio@21 {
+ compatible = ti,pcf8575;
+ reg = 0x21;
+ lines-initial-states = 0x1408;
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupt-parent = gpio6;
+ interrupts = 11 IRQ_TYPE_EDGE_FALLING;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
};
uart1 {
@@ -345,6 +368,14 @@
phy-supply = ldo4_reg;
};
+omap_dwc3_1 {
+ extcon = extcon_usb1;
+};
+
+omap_dwc3_2 {
+ extcon = extcon_usb2;
+};
+
usb1 {
dr_mode = peripheral;
pinctrl-names = default;
--
2.1.0
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[PATCH 0/5] extcon: usb: Introduce USB GPIO extcon driver. Fix DRA7 USB.
Hi, On DRA7 EVMs the USB ID pin is connected to a GPIO line. The USB drivers (dwc3 + dwc3-omap) depend on extcon framework to get the USB cable state (USB or USB-Host) to put the controller in the right mode. There were earlier attempts [1] to get this working by trying to patch up the existing GPIO extcon driver. This series attemts to take a different approach by introducing a new USB specific extcon driver to handle the USB ID GPIO pin and interpret a right USB cable state. The reasoning to introduce this new driver is: 1) The existing GPIO extcon driver doesn't understand USB cable states and it can't handle more than one cable per instance. For the USB case we need to handle at least 2 cable states. a) USB (attach/detach) b) USB-Host (attach/detach) and could possible include more states like c) Fast-charger (attach/detach) d) Slow-charger (attach/detach) 2) This USB specific driver can be easily updated in the future to handle VBUS events, or charger detect events, in case it happens to be available on GPIO for any platform. 3) The DT implementation is very easy. You just need one extcon node per USB instead of one extcon node per cable state as in case of [1]. 4) The cable state string doesn't need to be encoded in the device tree as in case of [1]. 5) With only ID event available, you can simulate a USB-peripheral attach when USB-Host is detacted instead of hacking the USB driver to do the same. Tested on DRA7-evm and DRA72-evm. cheers, -roger [1] - https://lkml.org/lkml/2014/11/3/513 Roger Quadros (5): extcon: gpio-usb: Introduce gpio usb extcon driver usb: extcon: Fix USB-Host cable name ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: omap2plus_defconfig: Enable PCF857X and EXTCON_GPIO_USB .../devicetree/bindings/extcon/extcon-usb.txt | 20 ++ arch/arm/boot/dts/dra7-evm.dts | 31 +++ arch/arm/boot/dts/dra72-evm.dts| 31 +++ arch/arm/configs/omap2plus_defconfig | 2 + drivers/extcon/Kconfig | 7 + drivers/extcon/Makefile| 1 + drivers/extcon/extcon-gpio-usb.c | 225 + drivers/extcon/extcon-palmas.c | 18 +- drivers/usb/dwc3/dwc3-omap.c | 6 +- drivers/usb/phy/phy-omap-otg.c | 4 +- drivers/usb/phy/phy-tahvo.c| 8 +- 11 files changed, 335 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/extcon/extcon-usb.txt create mode 100644 drivers/extcon/extcon-gpio-usb.c -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: OMAP2+: Add clock domain support for dm816x
* Tony Lindgren t...@atomide.com [150113 15:29]:
From: Aida Mynzhasova aida.mynzhas...@skitlab.ru
This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init() was substituted by
new ti81xx_clockdomains_init() while early initialization of
TI81XX platform.
Looks like this can cause make randconfnig build errors, we need
to have the mach-omap2/io.c code in a separate CONFIG_SOC_TI81XX
block. Updated patch below.
Regards,
Tony
8 ---
From: Aida Mynzhasova aida.mynzhas...@skitlab.ru
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add clock domain support for dm816x
This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init() was substituted by
new ti81xx_clockdomains_init() while early initialization of
TI81XX platform.
Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX
block instead inside the ifdef block for omap3 to avoid make
randconfig build errors.
This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches
published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Brian Hutchinson b.hutch...@gmail.com
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Aida Mynzhasova aida.mynzhas...@skitlab.ru
[t...@atomide.com: updated to apply, renamed to clockdomains81xx.c
fixed to use am33xx_clkdm_operations]
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -171,6 +171,8 @@ obj-$(CONFIG_ARCH_OMAP4)+= $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_TI81XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_TI81XX) += clockdomains81xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
obj-$(CONFIG_SOC_OMAP5)+= $(clockdomain-common)
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
+extern void __init ti81xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -0,0 +1,191 @@
+/*
+ * TI81XX Clock Domain data.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
+
+#include linux/kernel.h
+#include linux/io.h
+
+#include clockdomain.h
+
+#include cm81xx.h
+
+/*
+ * - Add other domains as required
+ * - Fill up associated powerdomans (especially ALWON powerdomains are NULL at
+ * the moment
+ * - Consider dependencies across domains (probably not applicable till now)
+ */
+
+/* Common TI81XX */
+static struct clockdomain alwon_l3_slow_81xx_clkdm = {
+ .name = l3s_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= TI81XX_CM_ALWON_MOD,
+ .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_med_81xx_clkdm = {
+ .name = alwon_l3_med_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= TI81XX_CM_ALWON_MOD,
+ .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_l3_fast_81xx_clkdm = {
+ .name = alwon_l3_fast_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= TI81XX_CM_ALWON_MOD,
+ .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain alwon_ethernet_81xx_clkdm = {
+ .name = alwon_ethernet_clkdm,
+ .pwrdm = { .name = alwon_pwrdm },
+ .cm_inst= TI81XX_CM_ALWON_MOD,
+
Re: [PATCH 1/4] ARM: OMAP2+: Add board-generic.c entry for ti81xx
* Tony Lindgren t...@atomide.com [150114 16:14]:
* Sergei Shtylyov sergei.shtyl...@cogentembedded.com [150114 05:54]:
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
Heh thanks will updated to:
This allows booting ti81xx boards when a .dts file
is in place.
This too needs to be in a separate ifdef CONFIG_SOC_TI81XX block
to avoid make randconfig build errors. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -142,6 +142,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517 (Flattened
Device Tree))
.dt_compat = am3517_boards_compat,
.restart= omap3xxx_restart,
MACHINE_END
+
+static const char *const ti814x_boards_compat[] __initconst = {
+ ti,dm8148,
+ ti,dm814,
+ NULL,
+};
+#endif
+
+#ifdef CONFIG_SOC_TI81XX
+DT_MACHINE_START(TI81XX_DT, Generic ti814x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti814x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti814x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
+
+static const char *const ti816x_boards_compat[] __initconst = {
+ ti,dm8168,
+ ti,dm816,
+ NULL,
+};
+
+DT_MACHINE_START(TI816X_DT, Generic ti816x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti816x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti816x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
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Re: [PATCH 5/5] ARM: omap2plus_defconfig: Enable PCF857X and EXTCON_GPIO_USB
* Tony Lindgren t...@atomide.com [150119 10:52]: * Roger Quadros rog...@ti.com [150119 09:55]: Both are needed for USB cable type detection on dra7-evm. Signed-off-by: Roger Quadros rog...@ti.com --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..bc23b90 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -203,6 +203,7 @@ CONFIG_SPI_OMAP24XX=y CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TWL4030=y CONFIG_W1=y CONFIG_BATTERY_BQ27x00=m Looks like I have this too but as a loadable module :) So I'll keep that one. @@ -326,6 +327,7 @@ CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y CONFIG_EXTCON=y +CONFIG_EXTCON_GPIO_USB=y CONFIG_EXTCON_PALMAS=y CONFIG_PWM=y CONFIG_PWM_TIECAP=y I'll apply this part into omap-for-v3.20/defconfig but make it into =m instead of =y. Oh but this depends on the driver being added, so not applying. Can you please repost a patch adding CONFIG_EXTCON_GPIO_USB=m once the driver is merged? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] ARM: OMAP: hwmod fixes for v3.19-rc
* Paul Walmsley p...@pwsan.com [150104 15:38]: Hi Tony The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672: Linux 3.19-rc1 (2014-12-20 17:08:50 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git tags/for-v3.19-rc/omap-fixes-a for you to fetch changes up to 99d076b747455449b2eec9e37f3fb0bfdf51af32: MAINTAINERS: add maintainer for OMAP hwmod data (2015-01-02 16:24:27 -0700) For v3.19-rc, fix some hwmod structure details for the OMAP DSS modules for DRA7xx and AM43xx. Also update the MAINTAINERS file to encourage folks to cc me on hwmod data patches. Basic build, boot, and PM testlogs are available here: http://www.pwsan.com/omap/testlogs/omap-fixes-a-for-v3.19-rc/20150103144242/ Paul, got any updates on this? Anyways, I'll just untag this email as you asked me to wait on pulling this. Regards, Tony Paul Walmsley (1): MAINTAINERS: add maintainer for OMAP hwmod data Tomi Valkeinen (2): ARM: AM43xx: hwmod: set DSS submodule parent hwmods ARM: DRA7xx: hwmod: set DSS submodule parent hwmods MAINTAINERS| 6 ++ arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 2 ++ arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 ++ 3 files changed, 10 insertions(+) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 2/5] usb: dwc3: add revision number DWC3_REVISION_300A
-Original Message- From: Felipe Balbi [mailto:ba...@ti.com] Sent: Monday, January 19, 2015 6:47 AM looking at Synopsys Solvnet for this IP, it shows that current version is 2.90a. There's no 3.00a. Paul, John, is there a 3.00a version of the DWC USB3 IP ? Yes there is, but it has not been released yet, thus it's not in Solvnet. John -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [patch-net-next v3] net: ethernet: ti: cpsw: fix buld break when NET_POLL_CONTROLLER
From: Felipe Balbi ba...@ti.com Date: Mon, 19 Jan 2015 11:52:36 -0600 Commit c03abd84634d (net: ethernet: cpsw: don't requests IRQs we don't use) left one build breakage when NET_POLL_CONTROLLER is enabled. Fix this build break by referring to the correct irqs_table array. Fixes: c03abd84634d (net: ethernet: cpsw: don't requests IRQs we don't use) Reported-by: kbuild test robot fengguang...@intel.com Signed-off-by: Felipe Balbi ba...@ti.com Applied, thanks. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] ARM: dts: dra7-evm: Add extcon nodes for USB
On this EVM, the USB cable state has to be determined via the
ID pin tied to a GPIO line. We use the gpio-usb-extcon driver
to read the ID pin and the extcon framework to forward
the USB cable state information to the USB driver so the
controller can be configured in the right mode (host/peripheral).
Gets USB peripheral mode to work on this EVM.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c..47d9a06 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -26,6 +26,16 @@
regulator-max-microvolt = 330;
};
+ extcon_usb1: extcon_usb1 {
+ compatible = linux,extcon-usb;
+ id-gpio = pcf_gpio_21 1 GPIO_ACTIVE_HIGH;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = linux,extcon-usb;
+ id-gpio = pcf_gpio_21 2 GPIO_ACTIVE_HIGH;
+ };
+
vtt_fixed: fixedregulator-vtt {
compatible = regulator-fixed;
regulator-name = vtt_fixed;
@@ -391,6 +401,19 @@
};
};
};
+
+ pcf_gpio_21: gpio@21 {
+ compatible = ti,pcf8575;
+ reg = 0x21;
+ lines-initial-states = 0x1408;
+ gpio-controller;
+ #gpio-cells = 2;
+ interrupt-parent = gpio6;
+ interrupts = 11 IRQ_TYPE_EDGE_FALLING;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
};
i2c2 {
@@ -520,6 +543,14 @@
};
};
+omap_dwc3_1 {
+ extcon = extcon_usb1;
+};
+
+omap_dwc3_2 {
+ extcon = extcon_usb2;
+};
+
usb1 {
dr_mode = peripheral;
pinctrl-names = default;
--
2.1.0
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[PATCH 2/5] usb: extcon: Fix USB-Host cable name
The recommended name for USB-Host cable state is USB-Host and not
USB-HOST as per drivers/extcon/extcon-class.c extcon_cable_name.
Change all instances of USB-HOST to USB-Host.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/extcon/extcon-palmas.c | 18 +-
drivers/usb/dwc3/dwc3-omap.c | 6 +++---
drivers/usb/phy/phy-omap-otg.c | 4 ++--
drivers/usb/phy/phy-tahvo.c| 8
4 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c
index 11c6757..6d002c3 100644
--- a/drivers/extcon/extcon-palmas.c
+++ b/drivers/extcon/extcon-palmas.c
@@ -31,7 +31,7 @@
static const char *palmas_extcon_cable[] = {
[0] = USB,
- [1] = USB-HOST,
+ [1] = USB-Host,
NULL,
};
@@ -93,26 +93,26 @@ static irqreturn_t palmas_id_irq_handler(int irq, void
*_palmas_usb)
PALMAS_USB_ID_INT_LATCH_CLR,
PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND);
palmas_usb-linkstat = PALMAS_USB_STATE_ID;
- extcon_set_cable_state(palmas_usb-edev, USB-HOST, true);
- dev_info(palmas_usb-dev, USB-HOST cable is attached\n);
+ extcon_set_cable_state(palmas_usb-edev, USB-Host, true);
+ dev_info(palmas_usb-dev, USB-Host cable is attached\n);
} else if ((set PALMAS_USB_ID_INT_SRC_ID_FLOAT)
(id_src PALMAS_USB_ID_INT_SRC_ID_FLOAT)) {
palmas_write(palmas_usb-palmas, PALMAS_USB_OTG_BASE,
PALMAS_USB_ID_INT_LATCH_CLR,
PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT);
palmas_usb-linkstat = PALMAS_USB_STATE_DISCONNECT;
- extcon_set_cable_state(palmas_usb-edev, USB-HOST, false);
- dev_info(palmas_usb-dev, USB-HOST cable is detached\n);
+ extcon_set_cable_state(palmas_usb-edev, USB-Host, false);
+ dev_info(palmas_usb-dev, USB-Host cable is detached\n);
} else if ((palmas_usb-linkstat == PALMAS_USB_STATE_ID)
(!(set PALMAS_USB_ID_INT_SRC_ID_GND))) {
palmas_usb-linkstat = PALMAS_USB_STATE_DISCONNECT;
- extcon_set_cable_state(palmas_usb-edev, USB-HOST, false);
- dev_info(palmas_usb-dev, USB-HOST cable is detached\n);
+ extcon_set_cable_state(palmas_usb-edev, USB-Host, false);
+ dev_info(palmas_usb-dev, USB-Host cable is detached\n);
} else if ((palmas_usb-linkstat == PALMAS_USB_STATE_DISCONNECT)
(id_src PALMAS_USB_ID_INT_SRC_ID_GND)) {
palmas_usb-linkstat = PALMAS_USB_STATE_ID;
- extcon_set_cable_state(palmas_usb-edev, USB-HOST, true);
- dev_info(palmas_usb-dev, USB-HOST cable is attached\n);
+ extcon_set_cable_state(palmas_usb-edev, USB-Host, true);
+ dev_info(palmas_usb-dev, USB-Host cable is attached\n);
}
return IRQ_HANDLED;
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 172d64e..6713ad9 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -445,14 +445,14 @@ static int dwc3_omap_extcon_register(struct dwc3_omap
*omap)
omap-id_nb.notifier_call = dwc3_omap_id_notifier;
ret = extcon_register_interest(omap-extcon_id_dev,
- edev-name, USB-HOST,
+ edev-name, USB-Host,
omap-id_nb);
if (ret 0)
- dev_vdbg(omap-dev, failed to register notifier for
USB-HOST\n);
+ dev_vdbg(omap-dev, failed to register notifier for
USB-Host\n);
if (extcon_get_cable_state(edev, USB) == true)
dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
- if (extcon_get_cable_state(edev, USB-HOST) == true)
+ if (extcon_get_cable_state(edev, USB-Host) == true)
dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
}
diff --git a/drivers/usb/phy/phy-omap-otg.c b/drivers/usb/phy/phy-omap-otg.c
index 56ee760..53cba3f 100644
--- a/drivers/usb/phy/phy-omap-otg.c
+++ b/drivers/usb/phy/phy-omap-otg.c
@@ -119,7 +119,7 @@ static int omap_otg_probe(struct platform_device *pdev)
otg_dev-vbus_nb.notifier_call = omap_otg_vbus_notifier;
ret = extcon_register_interest(otg_dev-id_dev, config-extcon,
- USB-HOST, otg_dev-id_nb);
+ USB-Host, otg_dev-id_nb);
if (ret)
return ret;
@@ -130,7 +130,7 @@ static int omap_otg_probe(struct platform_device *pdev)
return ret;
}
- otg_dev-id = extcon_get_cable_state(extcon, USB-HOST);
+ otg_dev-id =
[PATCH 5/5] ARM: omap2plus_defconfig: Enable PCF857X and EXTCON_GPIO_USB
Both are needed for USB cable type detection on dra7-evm. Signed-off-by: Roger Quadros rog...@ti.com --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..bc23b90 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -203,6 +203,7 @@ CONFIG_SPI_OMAP24XX=y CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TWL4030=y CONFIG_W1=y CONFIG_BATTERY_BQ27x00=m @@ -326,6 +327,7 @@ CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y CONFIG_EXTCON=y +CONFIG_EXTCON_GPIO_USB=y CONFIG_EXTCON_PALMAS=y CONFIG_PWM=y CONFIG_PWM_TIECAP=y -- 2.1.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[patch-net-next v3] net: ethernet: ti: cpsw: fix buld break when NET_POLL_CONTROLLER
Commit c03abd84634d (net: ethernet: cpsw: don't requests IRQs we don't use) left one build breakage when NET_POLL_CONTROLLER is enabled. Fix this build break by referring to the correct irqs_table array. Fixes: c03abd84634d (net: ethernet: cpsw: don't requests IRQs we don't use) Reported-by: kbuild test robot fengguang...@intel.com Signed-off-by: Felipe Balbi ba...@ti.com --- drivers/net/ethernet/ti/cpsw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index ba09ff3c1695..a0e9a2b384f8 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1625,8 +1625,8 @@ static void cpsw_ndo_poll_controller(struct net_device *ndev) cpsw_intr_disable(priv); cpdma_ctlr_int_ctrl(priv-dma, false); - cpsw_rx_interrupt(priv-irq[0], priv); - cpsw_tx_interrupt(priv-irq[1], priv); + cpsw_rx_interrupt(priv-irqs_table[0], priv); + cpsw_tx_interrupt(priv-irqs_table[1], priv); cpdma_ctlr_int_ctrl(priv-dma, true); cpsw_intr_enable(priv); } -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND v8 1/2] clk: Make clk API return per-user struct clk instances
On 01/19/2015 01:55 AM, Tomeu Vizoso wrote:
On 17 January 2015 at 02:02, Stephen Boyd sb...@codeaurora.org wrote:
On 01/12, Tomeu Vizoso wrote:
+}
EXPORT_SYMBOL_GPL(__clk_get_rate);
@@ -630,7 +656,12 @@ out:
return !!ret;
}
-bool __clk_is_enabled(struct clk *clk)
+bool __clk_is_prepared(struct clk *clk)
+{
+ return clk_core_is_prepared(clk-core);
Oops. clk can be NULL here. Return false if so. Or drop the
function entirely? It looks like it may become unused.
Are you thinking of anything specific that the alchemy arch can do
instead of calling __clk_is_prepared?
Ah I missed that one. Bad grep.
+}
EXPORT_SYMBOL_GPL(__clk_is_enabled);
@@ -762,7 +805,12 @@ void __clk_unprepare(struct clk *clk)
if (clk-ops-unprepare)
clk-ops-unprepare(clk-hw);
- __clk_unprepare(clk-parent);
+ clk_core_unprepare(clk-parent);
+}
+
+void __clk_unprepare(struct clk *clk)
+{
+ clk_core_unprepare(clk-core);
OOps. clk can be NULL here. Bail early if so.
Actually, looks like nobody is using __clk_prepare nor __clk_unprepare
so I'm removing these.
Ok.
--
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Re: [PATCH 5/5] ARM: omap2plus_defconfig: Enable PCF857X and EXTCON_GPIO_USB
* Roger Quadros rog...@ti.com [150119 09:55]: Both are needed for USB cable type detection on dra7-evm. Signed-off-by: Roger Quadros rog...@ti.com --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..bc23b90 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -203,6 +203,7 @@ CONFIG_SPI_OMAP24XX=y CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TWL4030=y CONFIG_W1=y CONFIG_BATTERY_BQ27x00=m Looks like I have this too but as a loadable module :) So I'll keep that one. @@ -326,6 +327,7 @@ CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y CONFIG_EXTCON=y +CONFIG_EXTCON_GPIO_USB=y CONFIG_EXTCON_PALMAS=y CONFIG_PWM=y CONFIG_PWM_TIECAP=y I'll apply this part into omap-for-v3.20/defconfig but make it into =m instead of =y. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] gpio: omap: Fix bad device access with setup_irq()
On 1/16/15 5:00 PM, Tony Lindgren wrote: * santosh shilimkar santosh.shilim...@oracle.com [150116 16:23]: On 1/16/2015 2:50 PM, Tony Lindgren wrote: Similar to omap_gpio_irq_type() let's make sure that the GPIO is usable as an interrupt if the platform init code did not call gpio_request(). Otherwise we can get invalid device access after setup_irq(): I let Linus W comment on it but IIRC we chewed this issue last time and the conclusion was the gpio_request() must have to be called directly or indirectly in case of irq line. This is a corner case where the error is triggered by a wrong, non-GPIO IRQ so gpio_request() will never be called before setup_irq() unlike for any legacy platform code. The legacy and DT cases we're already handling in the gpio-omap.c driver a while back with: 2f56e0a57ff1 (gpio/omap: use gpiolib API to mark a GPIO used as an IRQ) fac7fa162a19 (gpio/omap: auto-setup a GPIO when used as an IRQ) fa365e4d7290 (gpio/omap: maintain GPIO and IRQ usage separately) And most of that the bank specific hacks we can get rid of by making the driver multple instances as that allows replacing BANK_USED with just runtime PM. Right. Thanks for expanding it. Regards, Santosh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] Few omap2plus_defconfig changes to make more boards usable
Hi, Let's add davinci_emac, and fix the NOR configuration. And let's also add pcf857x as a loadable module. Regards, Tony Tony Lindgren (3): ARM: omap2plus_defconfig: Enable support for davinci_emac ARM: omap2plus_defconfig: Enable pcf857x ARM: omap2plus_defconfig: Add NOR flash support arch/arm/configs/omap2plus_defconfig | 4 1 file changed, 4 insertions(+) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: omap2plus_defconfig: Enable support for davinci_emac
We have this on at least 3517-evm and dm8168-evm. Let's enable davinci_emac so those can be booted with NFSroot. Cc: Brian Hutchinson b.hutch...@gmail.com Signed-off-by: Tony Lindgren t...@atomide.com --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index b5ccb36..d6f84f2 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -145,6 +145,7 @@ CONFIG_KS8851_MLL=y CONFIG_SMC91X=y CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_TI_DAVINCI_EMAC=y CONFIG_TI_CPSW=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: omap2plus_defconfig: Add NOR flash support
Some omaps have NOR flash as the rootfs but we're missing physmap and physmap_of to properly support it. Signed-off-by: Tony Lindgren t...@atomide.com --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 3ac8269..6654b23 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -108,6 +108,8 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_OOPS=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC_BCH=y CONFIG_MTD_NAND_OMAP2=y -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: omap2plus_defconfig: Enable pcf857x
We have pcf857x at least several boards. Let's enable it as a loadable module. Cc: Brian Hutchinson b.hutch...@gmail.com Signed-off-by: Tony Lindgren t...@atomide.com --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index d6f84f2..3ac8269 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -205,6 +205,7 @@ CONFIG_SPI_TI_QSPI=m CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TWL4030=y CONFIG_W1=m CONFIG_HDQ_MASTER_OMAP=m -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] irqchip: omap-intc: fix legacy DMA regression
* Jason Cooper ja...@lakedaemon.net [150106 19:03]: On Tue, Jan 06, 2015 at 02:38:08PM -0600, Felipe Balbi wrote: commit 55601c9f2467 (arm: omap: intc: switch over to linear irq domain) introduced a regression with SDMA legacy driver because that driver strictly depends on INTC's IRQs starting at NR_IRQs. Aparently irq_domain_add_linear() won't guarantee that, since we see a 7 IRQs difference when booting with and without the commit cited above. Until arch/arm/plat-omap/dma.c is properly fixed, we must maintain OMAP2/3 using irq_domain_add_legacy(). A FIXME note was added so people know to delete that code once that legacy DMA driver is fixed up. Fixes: 55601c9f2467 (arm: omap: intc: switch over to linear irq domain) Cc: sta...@vger.kernel.org # v3.18 Tested-by: Aaro Koskinen aaro.koski...@iki.fi Tested-by: Tony Lindgren t...@atomide.com Signed-off-by: Felipe Balbi ba...@ti.com --- drivers/irqchip/irq-omap-intc.c | 26 +- 1 file changed, 21 insertions(+), 5 deletions(-) Applied to irqchip/urgent. Thanks for taking care of the Fixes and stable tags! Jason, I'm not seeing this merged into v3.19-rc5, seems to be in Linux next though. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/4] ARM: OMAP2+: Add board-generic.c entry for ti81xx
* Felipe Balbi ba...@ti.com [150119 12:46]:
On Mon, Jan 19, 2015 at 11:18:34AM -0800, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150114 16:14]:
* Sergei Shtylyov sergei.shtyl...@cogentembedded.com [150114 05:54]:
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
Heh thanks will updated to:
This allows booting ti81xx boards when a .dts file
is in place.
This too needs to be in a separate ifdef CONFIG_SOC_TI81XX block
to avoid make randconfig build errors. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -142,6 +142,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517 (Flattened
Device Tree))
.dt_compat = am3517_boards_compat,
.restart= omap3xxx_restart,
MACHINE_END
+
+static const char *const ti814x_boards_compat[] __initconst = {
should this definition be within that ifdef too ?
Oops yes totally thanks for catching that. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -144,6 +144,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517 (Flattened
Device Tree))
MACHINE_END
#endif
+#ifdef CONFIG_SOC_TI81XX
+static const char *const ti814x_boards_compat[] __initconst = {
+ ti,dm8148,
+ ti,dm814,
+ NULL,
+};
+
+DT_MACHINE_START(TI81XX_DT, Generic ti814x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti814x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti814x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
+
+static const char *const ti816x_boards_compat[] __initconst = {
+ ti,dm8168,
+ ti,dm816,
+ NULL,
+};
+
+DT_MACHINE_START(TI816X_DT, Generic ti816x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti816x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti816x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
+#endif
+
#ifdef CONFIG_SOC_AM33XX
static const char *const am33xx_boards_compat[] __initconst = {
ti,am33xx,
--
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Re: [PATCH 1/4] ARM: OMAP2+: Add board-generic.c entry for ti81xx
On Mon, Jan 19, 2015 at 01:05:45PM -0800, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [150119 12:46]:
On Mon, Jan 19, 2015 at 11:18:34AM -0800, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150114 16:14]:
* Sergei Shtylyov sergei.shtyl...@cogentembedded.com [150114 05:54]:
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
Heh thanks will updated to:
This allows booting ti81xx boards when a .dts file
is in place.
This too needs to be in a separate ifdef CONFIG_SOC_TI81XX block
to avoid make randconfig build errors. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -142,6 +142,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517
(Flattened Device Tree))
.dt_compat = am3517_boards_compat,
.restart= omap3xxx_restart,
MACHINE_END
+
+static const char *const ti814x_boards_compat[] __initconst = {
should this definition be within that ifdef too ?
Oops yes totally thanks for catching that. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -144,6 +144,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517 (Flattened
Device Tree))
MACHINE_END
#endif
+#ifdef CONFIG_SOC_TI81XX
+static const char *const ti814x_boards_compat[] __initconst = {
+ ti,dm8148,
+ ti,dm814,
+ NULL,
+};
+
+DT_MACHINE_START(TI81XX_DT, Generic ti814x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti814x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti814x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
+
+static const char *const ti816x_boards_compat[] __initconst = {
+ ti,dm8168,
+ ti,dm816,
+ NULL,
+};
+
+DT_MACHINE_START(TI816X_DT, Generic ti816x (Flattened Device Tree))
+ .reserve= omap_reserve,
+ .map_io = ti81xx_map_io,
+ .init_early = ti816x_init_early,
+ .init_machine = omap_generic_init,
+ .init_late = ti81xx_init_late,
+ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = ti816x_boards_compat,
+ .restart= ti81xx_restart,
+MACHINE_END
+#endif
+
#ifdef CONFIG_SOC_AM33XX
static const char *const am33xx_boards_compat[] __initconst = {
ti,am33xx,
--
balbi
signature.asc
Description: Digital signature
[PATCH v2] ASoC: OMAP: mcbsp: ensure that CLKX and CLKR are not used as ouput pins when they are used as input clock for the SRG.
This patch fixes faulty behaviour in a setup where the input clock for the SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must not be configured as output pin. Otherwise the input clock is messed up horribly. This patch makes it possible to use the CLKR/CLKX pin rather than CLKS to inject a reference clock in setups where McBSP is master and not both rx and tx are used. However for this to work it has to be ensured that set_dai_sysclk() is called after set_dai_fmt(). This was tested on a beagleboard-xm using McBSP1 to drive a i2s DAC through the tx lines (CLKX,FSX,DX). Using this patch the CLKR pin is used to inject an external reference clock. changes since v1: - added comments explaining the bit masking to disable output on CLKR/CLKX Signed-off-by: Thomas Niederprüm nied...@physik.uni-kl.de --- sound/soc/omap/omap-mcbsp.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index bd3ef2a..c37f606 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -530,8 +530,19 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, case OMAP_MCBSP_SYSCLK_CLKX_EXT: regs-srgr2 |= CLKSM; + regs-pcr0 |= SCLKME; + /* +* If McBSP is master but yet the CLKX/CLKR pin drives the SRG, +* disable output on those pins. This enables to inject the +* reference clock through CLKX/CLKR. For this to work +* set_dai_sysclk() _needs_ to be called after set_dai_fmt(). +*/ + regs-pcr0 = ~CLKXM; + break; case OMAP_MCBSP_SYSCLK_CLKR_EXT: regs-pcr0 |= SCLKME; + /* Disable ouput on CLKR pin in master mode */ + regs-pcr0 = ~CLKRM; break; default: err = -ENODEV; -- 2.1.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: OMAP: Work around hardcoded interrupts
* Tony Lindgren t...@atomide.com [150119 12:26]:
* Nishanth Menon n...@ti.com [150119 12:17]:
On 10:21-20150117, Marc Zyngier wrote:
Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
should have been
Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.
Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.
This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.
It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.
Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Other than that, This looks good to me.
Acked-by: Nishanth Menon n...@ti.com
OK thanks applying into omap-for-v3.19/fixes and will send out a
pull request later on today after some make randconfig builds.
Looks like we need to now have omap4_pmic_init() wrapped with
ifdef CONFIG_ARCH_OMAP4 to avoid make randconfig errors. I've also
added the missing commit quotes Nishanth mentioned.
Planning to apply the following after some more randconfig build
testing.
Regards,
Tony
8 -
From: Marc Zyngier marc.zyng...@arm.com
Date: Sat, 17 Jan 2015 10:21:08 +
Subject: [PATCH] ARM: OMAP: Work around hardcoded interrupts
Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.
Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.
This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.
It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.
Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Nishanth Menon n...@ti.com
[t...@atomide.com: updated to fix make randconfig issue]
Signed-off-by: Tony Lindgren t...@atomide.com
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index db57741..64e44d6 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
extern struct device *omap2_get_l3_device(void);
extern struct device *omap4_get_dsp_device(void);
+unsigned int omap4_xlate_irq(unsigned int hwirq);
void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
}
omap_early_initcall(omap4_sar_ram_init);
+static struct of_device_id gic_match[] = {
+ { .compatible = arm,cortex-a9-gic, },
+ { .compatible = arm,cortex-a15-gic, },
+ { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+ struct of_phandle_args irq_data;
+ unsigned int irq;
+
+ if (!gic_node)
+ gic_node = of_find_matching_node(NULL, gic_match);
+
+ if (WARN_ON(!gic_node))
+ return hwirq;
+
+ irq_data.np = gic_node;
+ irq_data.args_count = 3;
+ irq_data.args[0] = 0;
+ irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+ irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+ irq = irq_create_of_mapping(irq_data);
+ if (WARN_ON(!irq))
+ irq = hwirq;
+
+ return irq;
+}
+
void __init omap_gic_of_init(void)
{
struct device_node *np;
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh,
struct resource *res)
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i mpu_irqs_cnt; i++) {
+ unsigned int irq;
+
+ if (oh-xlate_irq)
+ irq = oh-xlate_irq((oh-mpu_irqs + i)-irq);
+ else
+ irq = (oh-mpu_irqs + i)-irq;
(res + r)-name = (oh-mpu_irqs + i)-name;
- (res + r)-start = (oh-mpu_irqs + i)-irq;
- (res + r)-end = (oh-mpu_irqs + i)-irq;
+ (res + r)-start = irq;
+ (res + r)-end = irq;
(res + r)-flags = IORESOURCE_IRQ;
r++;
}
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@
[PATCH v2] ARM: omap2plus_defconfig: Enable OHCI EHCI HCD support
Enable CONFIG_USB_EHCI_HCD and CONFIG_USB_OHCI_HCD to get USB supports with omap2plus_defconfig. Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk --- Changes in v2: Enable as modules rather then builtin arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..f4009a2 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -159,6 +159,8 @@ CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_EPSON2888=y +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_OHCI_HCD=m CONFIG_USB_KC2190=y CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] ARM: l2c: OMAP4/AM437x: Additional register programming support.
* Nishanth Menon n...@ti.com [150102 09:55]: On 01/02/2015 11:38 AM, Tony Lindgren wrote: * Nishanth Menon n...@ti.com [150102 09:20]: Hi, OMAP4 and AM437x ROM code provides services to program PL310's latency registers and AM437x provides service for programming Address filter registers. Provide support in the kernel for the same. This provides some support to the series: http://marc.info/?l=linux-arm-kernelm=141933190912495w=2 Are these to be applied before Thomasz's series as fixes? If we don't need these as fixes for the -rc, then probably makes sense for RMK to merge them all together for v3.20. These dont need to go in fixes. Can easily wait till 3.20. Thomaz series wont exercise these path by default until someone modifies the DT properties. Yes, will be nice to have them along with other changes in v3.20. just for the record, i made a couple of typos in v1 of this series and have updated a retested v2 of the series. Applying both int omap-for-v3.20/fixes thanks. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] bluetooth: Add hci_h4p driver
Hi Pavel,
Add HCI driver for H4 with Nokia extensions. This device is used on
Nokia N900 cell phone.
Older version of this driver lived in staging, before being reverted
in a4102f90e87cfaa3fdbed6fdf469b23f0eeb4bfd .
Signed-off-by: Pavel Machek pa...@ucw.cz
Thanks-to: Sebastian Reichel s...@debian.org
Thanks-to: Joe Perches j...@perches.com
---
Please apply,
Pavel
Kconfig | 10
Makefile |4
nokia_core.c | 1149
+++
nokia_fw.c | 99 +
nokia_h4p.h | 214 ++
nokia_uart.c | 171
7 files changed, 1667 insertions(+)
so when I run this through checkpatch --strict, then I get tons of warning that
we have DOS style ^M line breaks. There are also trailing whitespace that need
fixing. I can use cleanpatch to do this, but so can you.
Even after doing that there are still obvious plain coding style violation in
the patch. For example:
ERROR: space prohibited before that ',' (ctx:WxW)
#610: FILE: drivers/bluetooth/nokia_core.c:517:
+ __h4p_set_auto_ctsrts(info, 0 , UART_EFR_RTS);
^
CHECK: Alignment should match open parenthesis
#662: FILE: drivers/bluetooth/nokia_core.c:569:
+ h4p_outb(info, UART_OMAP_SCR,
+h4p_inb(info, UART_OMAP_SCR) |
CHECK: Blank lines aren't necessary before a close brace '}'
#692: FILE: drivers/bluetooth/nokia_core.c:599:
+
+}
These are only few. They are more and all these need fixing before I even
consider it.
Also this worries me:
WARNING: DT compatible string brcm,uart,bcm2048 appears un-documented --
check ./Documentation/devicetree/bindings/
#1222: FILE: drivers/bluetooth/nokia_core.c:1129:
+ { .compatible = brcm,uart,bcm2048 },
Regards
Marcel
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Re: [PATCH 0/2] ARM: l2c: OMAP4/AM437x: Additional register programming support.
* Tony Lindgren t...@atomide.com [150119 13:35]: * Nishanth Menon n...@ti.com [150102 09:55]: On 01/02/2015 11:38 AM, Tony Lindgren wrote: * Nishanth Menon n...@ti.com [150102 09:20]: Hi, OMAP4 and AM437x ROM code provides services to program PL310's latency registers and AM437x provides service for programming Address filter registers. Provide support in the kernel for the same. This provides some support to the series: http://marc.info/?l=linux-arm-kernelm=141933190912495w=2 Are these to be applied before Thomasz's series as fixes? If we don't need these as fixes for the -rc, then probably makes sense for RMK to merge them all together for v3.20. These dont need to go in fixes. Can easily wait till 3.20. Thomaz series wont exercise these path by default until someone modifies the DT properties. Yes, will be nice to have them along with other changes in v3.20. just for the record, i made a couple of typos in v1 of this series and have updated a retested v2 of the series. Applying both int omap-for-v3.20/fixes thanks. Oops actually not applying based on reading the comments in v2 of this series. Please repost if you still want to patch something. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: omap-intc: improve IRQ handler
* Felipe Balbi ba...@ti.com [150102 10:50]:
as it turns out the current IRQ number will
*always* be available from SIR register which
renders the reads of PENDING registers as plain
unnecessary overhead.
In order to catch any situation where SIR reads
as zero, we're adding a WARN() to turn it into
a very verbose error and users actually report
it.
With this patch average running time of
omap_intc_handle_irq() reduced from about 28.5us
to 19.8us as measured by the kernel function
profiler.
Tested with BeagleBoneBlack Rev A5C.
Signed-off-by: Felipe Balbi ba...@ti.com
Jason, looks like this is not showing up in Linux next. The
same for the changes I did for dm81xx.
Regards,
Tony
---
Before applying, it would be very nice to get reports
from other folks on different platforms, specially OMAP2/3
ones which I don't have (easy) access.
drivers/irqchip/irq-omap-intc.c | 35 +--
1 file changed, 5 insertions(+), 30 deletions(-)
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c
index 28718d3..a2da6d5 100644
--- a/drivers/irqchip/irq-omap-intc.c
+++ b/drivers/irqchip/irq-omap-intc.c
@@ -315,37 +315,12 @@ static int __init omap_init_irq(u32 base, struct
device_node *node)
static asmlinkage void __exception_irq_entry
omap_intc_handle_irq(struct pt_regs *regs)
{
- u32 irqnr = 0;
- int handled_irq = 0;
- int i;
-
- do {
- for (i = 0; i omap_nr_pending; i++) {
- irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
- if (irqnr)
- goto out;
- }
-
-out:
- if (!irqnr)
- break;
-
- irqnr = intc_readl(INTC_SIR);
- irqnr = ACTIVEIRQ_MASK;
+ u32 irqnr;
- if (irqnr) {
- handle_domain_irq(domain, irqnr, regs);
- handled_irq = 1;
- }
- } while (irqnr);
-
- /*
- * If an irq is masked or deasserted while active, we will
- * keep ending up here with no irq handled. So remove it from
- * the INTC with an ack.
- */
- if (!handled_irq)
- omap_ack_irq(NULL);
+ irqnr = intc_readl(INTC_SIR);
+ irqnr = ACTIVEIRQ_MASK;
+ WARN(!irqnr, Spuriour IRQ ?\n);
+ handle_domain_irq(domain, irqnr, regs);
}
void __init omap2_init_irq(void)
--
2.2.0
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Re: [PATCH 3.19-rc2 v15 5/8] arm: omap1: Migrate debug_ll macros to use 8250.S
* Daniel Thompson daniel.thomp...@linaro.org [150105 04:49]: The omap1's debug-macro.S is similar to the generic 8250 code. Compared to the 8520 code the omap1 macro automatically determines what UART to use based on breadcrumbs left by the bootloader and automatically copes with the eccentric register layout on OMAP7XX. This patch drops both these features and relies instead on the generic 8250 macros: 1. Dropping support for the bootloader breadcrumbs is identical to the way the migration was handled for OMAP2 (see 808b7e07464d...). 2. Support for OMAP7XX still exists but it must be configured by hand (DEBUG_OMAP7XXUART1/2/3) rather than handled at runtime. Signed-off-by: Daniel Thompson daniel.thomp...@linaro.org Cc: Russell King li...@arm.linux.org.uk Cc: Arnd Bergmann arnd.bergm...@linaro.org Cc: linux-omap@vger.kernel.org Tested-by: Aaro Koskinen aaro.koski...@iki.fi Acked-by: Tony Lindgren t...@atomide.com Daniel, I suggest you upload this patch into Russell's patch tracking system to get it merged. That at least shrinks down your patch series if the other patches need more work. Regards, Tony --- arch/arm/Kconfig.debug | 57 +- arch/arm/mach-omap1/include/mach/debug-macro.S | 101 - 2 files changed, 56 insertions(+), 102 deletions(-) delete mode 100644 arch/arm/mach-omap1/include/mach/debug-macro.S diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index eba36e35bad2..ec25d746b4dd 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -527,6 +527,30 @@ choice Say Y here if you want kernel low-level debugging support on TI-NSPIRE CX models. + config DEBUG_OMAP1UART1 + bool Kernel low-level debugging via OMAP1 UART1 + depends on ARCH_OMAP1 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP1 based platforms (except OMAP730) on the UART1. + + config DEBUG_OMAP1UART2 + bool Kernel low-level debugging via OMAP1 UART2 + depends on ARCH_OMAP1 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP1 based platforms (except OMAP730) on the UART2. + + config DEBUG_OMAP1UART3 + bool Kernel low-level debugging via OMAP1 UART3 + depends on ARCH_OMAP1 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP1 based platforms (except OMAP730) on the UART3. + config DEBUG_OMAP2UART1 bool OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards) depends on ARCH_OMAP2PLUS @@ -569,6 +593,30 @@ choice depends on ARCH_OMAP2PLUS select DEBUG_OMAP2PLUS_UART + config DEBUG_OMAP7XXUART1 + bool Kernel low-level debugging via OMAP730 UART1 + depends on ARCH_OMAP730 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP730 based platforms on the UART1. + + config DEBUG_OMAP7XXUART2 + bool Kernel low-level debugging via OMAP730 UART2 + depends on ARCH_OMAP730 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP730 based platforms on the UART2. + + config DEBUG_OMAP7XXUART3 + bool Kernel low-level debugging via OMAP730 UART3 + depends on ARCH_OMAP730 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on OMAP730 based platforms on the UART3. + config DEBUG_TI81XXUART1 bool Kernel low-level debugging messages via TI81XX UART1 (ti8148evm) depends on ARCH_OMAP2PLUS @@ -1308,6 +1356,9 @@ config DEBUG_UART_PHYS default 0xffe4 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 default 0xfff36000 if DEBUG_HIGHBANK_UART + default 0xfffb if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 + default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 + default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 default 0xfffe8600 if DEBUG_UART_BCM63XX default 0xf700 if ARCH_IOP33X depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ @@ -1390,6 +1441,9 @@ config DEBUG_UART_VIRT default 0xfef0 if ARCH_IXP4XX !CPU_BIG_ENDIAN default 0xfef3 if ARCH_IXP4XX CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART + default 0xfefb if DEBUG_OMAP1UART1
Re: [PATCH v2] ARM: omap2plus_defconfig: Enable OHCI EHCI HCD support
On Mon, Jan 19, 2015 at 10:28:36PM +0100, Sjoerd Simons wrote: Enable CONFIG_USB_EHCI_HCD and CONFIG_USB_OHCI_HCD to get USB supports with omap2plus_defconfig. Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Reviewed-by: Felipe Balbi ba...@ti.com --- Changes in v2: Enable as modules rather then builtin arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index c2c3a85..f4009a2 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -159,6 +159,8 @@ CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_EPSON2888=y +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_OHCI_HCD=m CONFIG_USB_KC2190=y CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m -- 2.1.4 -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 2/5] usb: dwc3: add revision number DWC3_REVISION_300A
On Mon, Jan 19, 2015 at 07:45:31PM +, John Youn wrote: -Original Message- From: Felipe Balbi [mailto:ba...@ti.com] Sent: Monday, January 19, 2015 6:47 AM looking at Synopsys Solvnet for this IP, it shows that current version is 2.90a. There's no 3.00a. Paul, John, is there a 3.00a version of the DWC USB3 IP ? Yes there is, but it has not been released yet, thus it's not in Solvnet. alright, in that case, Sneeker, can you update this patch to add 2.90a and 3.00a macros ? Thanks -- balbi signature.asc Description: Digital signature
Re: [PATCH 1/4] ARM: OMAP2+: Add board-generic.c entry for ti81xx
On Mon, Jan 19, 2015 at 11:18:34AM -0800, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150114 16:14]:
* Sergei Shtylyov sergei.shtyl...@cogentembedded.com [150114 05:54]:
Hello.
On 1/14/2015 2:37 AM, Tony Lindgren wrote:
This allows booting ti81xx boards with with when a .dts
So, with, with or when? :-)
Heh thanks will updated to:
This allows booting ti81xx boards when a .dts file
is in place.
This too needs to be in a separate ifdef CONFIG_SOC_TI81XX block
to avoid make randconfig build errors. Updated patch below.
Regards,
Tony
8 -
From: Tony Lindgren t...@atomide.com
Date: Mon, 19 Jan 2015 10:38:07 -0800
Subject: [PATCH] ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson b.hutch...@gmail.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -142,6 +142,42 @@ DT_MACHINE_START(AM3517_DT, Generic AM3517 (Flattened
Device Tree))
.dt_compat = am3517_boards_compat,
.restart= omap3xxx_restart,
MACHINE_END
+
+static const char *const ti814x_boards_compat[] __initconst = {
should this definition be within that ifdef too ?
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH v2] ARM: OMAP: Work around hardcoded interrupts
On 10:21-20150117, Marc Zyngier wrote:
Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
should have been
Commit 9a1091ef0017 (irqchip: gic: Support hierarchy irq domain)
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.
Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.
This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.
It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.
Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Other than that, This looks good to me.
Acked-by: Nishanth Menon n...@ti.com
---
From v1:
- OMAP4 can either get the PRM interrupt from hwmod or from device tree.
In the latter case, remove the xlate_irq method.
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/omap4-common.c | 32
++
arch/arm/mach-omap2/omap_hwmod.c | 10 --
arch/arm/mach-omap2/omap_hwmod.h | 1 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 5 +
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 1 +
arch/arm/mach-omap2/prcm-common.h | 1 +
arch/arm/mach-omap2/prm44xx.c | 5 -
arch/arm/mach-omap2/prm_common.c | 14 +++--
arch/arm/mach-omap2/twl-common.c | 5 -
10 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea8..b664494 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -211,6 +211,7 @@ extern struct device *omap2_get_iva_device(void);
extern struct device *omap2_get_l3_device(void);
extern struct device *omap4_get_dsp_device(void);
+unsigned int omap4_xlate_irq(unsigned int hwirq);
void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44a..cc30e49 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -256,6 +256,38 @@ static int __init omap4_sar_ram_init(void)
}
omap_early_initcall(omap4_sar_ram_init);
+static struct of_device_id gic_match[] = {
+ { .compatible = arm,cortex-a9-gic, },
+ { .compatible = arm,cortex-a15-gic, },
+ { },
+};
+
+static struct device_node *gic_node;
+
+unsigned int omap4_xlate_irq(unsigned int hwirq)
+{
+ struct of_phandle_args irq_data;
+ unsigned int irq;
+
+ if (!gic_node)
+ gic_node = of_find_matching_node(NULL, gic_match);
+
+ if (WARN_ON(!gic_node))
+ return hwirq;
+
+ irq_data.np = gic_node;
+ irq_data.args_count = 3;
+ irq_data.args[0] = 0;
+ irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
+ irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
+
+ irq = irq_create_of_mapping(irq_data);
+ if (WARN_ON(!irq))
+ irq = hwirq;
+
+ return irq;
+}
+
void __init omap_gic_of_init(void)
{
struct device_node *np;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
b/arch/arm/mach-omap2/omap_hwmod.c
index cbb908d..9025fff 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3534,9 +3534,15 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh,
struct resource *res)
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i mpu_irqs_cnt; i++) {
+ unsigned int irq;
+
+ if (oh-xlate_irq)
+ irq = oh-xlate_irq((oh-mpu_irqs + i)-irq);
+ else
+ irq = (oh-mpu_irqs + i)-irq;
(res + r)-name = (oh-mpu_irqs + i)-name;
- (res + r)-start = (oh-mpu_irqs + i)-irq;
- (res + r)-end = (oh-mpu_irqs + i)-irq;
+ (res + r)-start = irq;
+ (res + r)-end = irq;
(res + r)-flags = IORESOURCE_IRQ;
r++;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h
b/arch/arm/mach-omap2/omap_hwmod.h
index 35ca6ef..5b42faf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -676,6 +676,7 @@ struct omap_hwmod {
spinlock_t _lock;
struct list_headnode;
struct omap_hwmod_ocp_if*_mpu_port;
+ unsigned int(*xlate_irq)(unsigned int);
u16 flags;
u8 mpu_rt_idx;
u8 response_lat;
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
