Re: [RFC/PATCH-v4.2-rc6 2/5] arm: boot: dts: am4372: add ARM timers and SCU nodes
On Wed, Aug 12, 2015 at 12:28:16AM -0700, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [150810 14:44]: AM437x devices sport SCU, TWD and Global timers, let's add them to DTS so they have a chance to probe and be used by Linux. Is this one safe to apply already without the Kconfig change? Or will it cause multi_v7_defconfig with the timers selected to not boot properly? I'd have to try :-) But it should be safe, just the timers won't be chosen for anything :-) -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 2/6] rtc: omap: Add external clock enabling support
On Mon, 10 Aug 2015, Keerthy wrote: Switch to external clock source during suspend and switch back to internal source on resume. This helps rtc ticking across suspend. Doesn't this type of dynamic switching make it likely that ticks will be lost? If the external, optional source is present, isn't it best just to use the external source 100% of the time? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/6] ARM: AM43XX: HWMOD: Add rtc hwmod
On Mon, 10 Aug 2015, Keerthy wrote: The patch adds rtc hwmod. This is present on gp and sk evm and not on epos evm. Hence adding it selectively using a seprate list. Signed-off-by: Keerthy j-keer...@ti.com So just to confirm, the RTC IP block has been physically removed or permanently disabled on these new AM438x chips? So the registers are no longer accessible by the MPU? Is there a TRM available for these chips? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH-v4.2-rc6 4/5] arm: omap2: timer: simplify omap4_local_timer_init()
On Wed, Aug 12, 2015 at 12:14:24AM -0700, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [150810 14:44]: all users of omap4_local_timer_init() are already DT-only, so we can remove the check for having DTB or not. While at that, fix a typo in comment. We already have d1dabab2841d (ARM: OMAP2+: Clean up omap4_local_timer_init) in Linux next reviewed-by you :) hehe, I had forgotten about that sorry. I'll rebase this on today's next and resend the series. I'll also test $subject without the other patches. -- balbi signature.asc Description: Digital signature
Re: [PATCH v2 2/6] rtc: omap: Add external clock enabling support
Hi, On 13/08/2015 at 00:38:50 +0530, Keerthy wrote : The intent here is to switch to a higher precision clock which is the internal clock when available. Alexandre, Is dynamic switching preferred over sticking to external clock always if present? I'd say that I don't really care. I'd say the best would be to make a decision based on clock-accuracy but maybe that is an information you don't have yet. Anyway, this could be added at a later date. -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] clk: Convert __clk_get_name(hw-clk) to clk_hw_get_name(hw)
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
-__clk_get_name(E-clk)
+clk_hw_get_name(E)
Cc: Heiko Stuebner he...@sntech.de
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Cc: Prashant Gaikwad pgaik...@nvidia.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Thierry Reding thierry.red...@gmail.com
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Cc: Andrew Bresticker abres...@chromium.org
Cc: Ezequiel Garcia ezequiel.gar...@imgtec.com
Cc: Ralf Baechle r...@linux-mips.org
Cc: Kevin Cernekee cerne...@chromium.org
Cc: Geert Uytterhoeven geert+rene...@glider.be
Cc: Ulrich Hecht ulrich.hecht+rene...@gmail.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-rockc...@lists.infradead.org
Cc: linux-samsung-...@vger.kernel.org
Cc: linux-te...@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/clk/berlin/berlin2-pll.c | 4 ++--
drivers/clk/clk-xgene.c | 22 +++---
drivers/clk/pistachio/clk-pll.c | 4 ++--
drivers/clk/qcom/clk-branch.c| 2 +-
drivers/clk/rockchip/clk-inverter.c | 2 +-
drivers/clk/rockchip/clk-mmc-phase.c | 2 +-
drivers/clk/samsung/clk-pll.c| 18 +-
drivers/clk/shmobile/clk-div6.c | 2 +-
drivers/clk/st/clk-flexgen.c | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 18 +-
drivers/clk/st/clkgen-mux.c | 2 +-
drivers/clk/st/clkgen-pll.c | 8
drivers/clk/tegra/clk-pll.c | 8
drivers/clk/ti/apll.c| 4 ++--
drivers/clk/ti/clkt_dflt.c | 8
drivers/clk/ti/clockdomain.c | 14 +++---
drivers/clk/ux500/clk-prcmu.c| 16
drivers/clk/ux500/clk-sysctrl.c | 2 +-
18 files changed, 70 insertions(+), 70 deletions(-)
diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c
index f4b8d324b083..1c2294d3ba85 100644
--- a/drivers/clk/berlin/berlin2-pll.c
+++ b/drivers/clk/berlin/berlin2-pll.c
@@ -61,7 +61,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long
parent_rate)
fbdiv = (val map-fbdiv_shift) FBDIV_MASK;
rfdiv = (val map-rfdiv_shift) RFDIV_MASK;
if (rfdiv == 0) {
- pr_warn(%s has zero rfdiv\n, __clk_get_name(hw-clk));
+ pr_warn(%s has zero rfdiv\n, clk_hw_get_name(hw));
rfdiv = 1;
}
@@ -70,7 +70,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long
parent_rate)
vcodiv = map-vcodiv[vcodivsel];
if (vcodiv == 0) {
pr_warn(%s has zero vcodiv (index %d)\n,
- __clk_get_name(hw-clk), vcodivsel);
+ clk_hw_get_name(hw), vcodivsel);
vcodiv = 1;
}
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 4caee9356407..96a6190acac2 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -74,7 +74,7 @@ static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
u32 data;
data = xgene_clk_read(pllclk-reg + pllclk-pll_offset);
- pr_debug(%s pll %s\n, __clk_get_name(hw-clk),
+ pr_debug(%s pll %s\n, clk_hw_get_name(hw),
data REGSPEC_RESET_F1_MASK ? disabled : enabled);
return data REGSPEC_RESET_F1_MASK ? 0 : 1;
@@ -112,7 +112,7 @@ static unsigned long xgene_clk_pll_recalc_rate(struct
clk_hw *hw,
fref = parent_rate / nref;
fvco = fref * nfb;
}
- pr_debug(%s pll recalc rate %ld parent %ld\n, __clk_get_name(hw-clk),
+ pr_debug(%s pll recalc rate %ld parent %ld\n, clk_hw_get_name(hw),
fvco / nout, parent_rate);
return fvco / nout;
@@ -225,7 +225,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
spin_lock_irqsave(pclk-lock, flags);
if (pclk-param.csr_reg != NULL) {
- pr_debug(%s clock enabled\n, __clk_get_name(hw-clk));
+ pr_debug(%s clock enabled\n, clk_hw_get_name(hw));
reg = __pa(pclk-param.csr_reg);
/* First enable the clock */
data = xgene_clk_read(pclk-param.csr_reg +
@@ -234,7 +234,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
xgene_clk_write(data, pclk-param.csr_reg +
pclk-param.reg_clk_offset);
pr_debug(%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X
value 0x%08X\n,
- __clk_get_name(hw-clk), reg,
+ clk_hw_get_name(hw), reg,
pclk-param.reg_clk_offset,
Re: [RFC/PATCH-v4.2-rc6 1/5] Revert ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp
* Felipe Balbi ba...@ti.com [150810 14:45]: This reverts commit 904464b91eca8c665acea033489225af02eeb75a. The problem pointed out by commit 904464b91eca (ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp) doesn't exist anymore. We can safely boot with nosmp and the warning won't show up. The other side benefit of this patch is that TWD has a chance to probe on single-core A9 systems such as AM437x which sport TWD. Can you please upload this into Russell's patch tracking system if no comments? Please also feel free to add: Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH-v4.2-rc6 4/5] arm: omap2: timer: simplify omap4_local_timer_init()
* Felipe Balbi ba...@ti.com [150810 14:44]: all users of omap4_local_timer_init() are already DT-only, so we can remove the check for having DTB or not. While at that, fix a typo in comment. We already have d1dabab2841d (ARM: OMAP2+: Clean up omap4_local_timer_init) in Linux next reviewed-by you :) Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] omap clock dts changes for v4.3 merge window
* Tero Kristo t-kri...@ti.com [150806 04:10]: The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590: Linux 4.2-rc2 (2015-07-12 15:10:30 -0700) are available in the git repository at: https://github.com/t-kristo/linux-pm.git for-4.3/ti-clk-dt for you to fetch changes up to dff8a207815a605872dfc5bffc1bae1cad29d87c: ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock (2015-07-31 12:13:18 +0300) Keerthy (2): ARM: dts: AM437X: add dpll_clksel_mac_clk node ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock arch/arm/boot/dts/am4372.dtsi|7 +-- arch/arm/boot/dts/am43xx-clocks.dtsi |9 + drivers/clk/ti/clk-43xx.c|1 + 3 files changed, 15 insertions(+), 2 deletions(-) Pulling this into omap-for-v4.3/dt-v2 thanks. We're getting close to the merge window so guarantees it will get merged. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] memory: omap-gpmc: Don't try to save the GPMC context
* Javier Martinez Canillas jav...@dowhile0.org [150805 05:47]: Hello Tomeu, On Wed, Aug 5, 2015 at 2:24 PM, Tomeu Vizoso tomeu.viz...@collabora.com wrote: ...if there isn't one already. I think is better to instead splitting the subject line like this, to change it for something that fits like memory: omap-gpmc: Don't try to save uninitialized GPMC context or memory: omap-gpmc: Fix gpmc_base NULL pointer dereference I'll apply this into omap-for-v4.2/fixes-v2 with the description updated by adding word unitialized. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP3: clock: remove un-used core dpll re-program code
* Tero Kristo t-kri...@ti.com [150716 01:10]: Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. OK I'm applying this into omap-for-v4.3/soc. If we ever need the code it will be in the git history. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/6] ARM: AM43xx: Introduce a separate soc_is function for am438x series of SoCs
* Keerthy a0393...@ti.com [150811 10:57]: On Tuesday 11 August 2015 06:25 PM, Tony Lindgren wrote: * Keerthy j-keer...@ti.com [150810 02:31]: @@ -371,8 +372,10 @@ IS_OMAP_TYPE(3430, 0x3430) #ifdefCONFIG_SOC_AM43XX # undef soc_is_am43xx # undef soc_is_am437x -# define soc_is_am43xx() is_am43xx() -# define soc_is_am437x() is_am437x() +# undef soc_is_am438x +# define soc_is_am43xx() of_machine_is_compatible(ti,am43) +# define soc_is_am437x() of_machine_is_compatible(ti,am4372) +# define soc_is_am438x() of_machine_is_compatible(ti,am438x) #endif Hmm didn't I already comment on this change? I don't want to do it for one SoC. Please add the SoC detection the old way for am43xx, then do another series that changes all the DT only SoCs to use of_machine_is_compatible() after it's been properly tested so now regressions are caused for the early init code. Okay. I misinterpreted your earlier comment. Thanks for clarifying. I will re-do. Actually, can you please do the following patches first while at it: 1. Change dra7 SoC detection to intialize soc_name and soc_rev registers based on the of_machine_is_compatible so we don't do pointless string comparisons with the current code 2. Add am437x detection the same way 3. Change all the existing DT only SoCs to do the same (this can be done in a separate series) That should allow us to drop most of the SoC detection code. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH-v4.2-rc6 2/5] arm: boot: dts: am4372: add ARM timers and SCU nodes
* Felipe Balbi ba...@ti.com [150810 14:44]: AM437x devices sport SCU, TWD and Global timers, let's add them to DTS so they have a chance to probe and be used by Linux. Is this one safe to apply already without the Kconfig change? Or will it cause multi_v7_defconfig with the timers selected to not boot properly? Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: AM4372: Add the am4372-rtc compatible string
* Keerthy j-keer...@ti.com [150806 22:10]: am4372-rtc string was already part of dts, introduced to identify the rtc specific to am4372 family of SoCs. It was removed in one of the previous patches. Adding back the same with appropriate documentation. Applying into omap-for-v4.3/dt-v2 thanks. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[net-next PATCH 2/3] ARM: dts: dra7: update cpsw compatible
CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8f1e25b..b4fdd10 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1398,7 +1398,7 @@
};
mac: ethernet@4a10 {
- compatible = ti,cpsw;
+ compatible = ti,dra7-cpsw,ti,cpsw;
ti,hwmods = gmac;
clocks = dpll_gmac_ck, gmac_gmii_ref_clk_div;
clock-names = fck, cpts;
--
2.5.0.234.gefc8a62
--
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[net-next PATCH 1/3] drivers: net: cpsw: add am335x errata workarround for interrutps
As per Am335x Errata [1] Advisory 1.0.9, The CPSW C0_TX_PEND and
C0_RX_PEND interrupt outputs provide a single transmit interrupt
that combines transmit channel interrupts TXPEND[7:0] and a
single receive interrupt that combines receive channel interrupts
RXPEND[7:0]. The TXPEND[0] and RXPEND[0] interrupt outputs are
connected to the ARM Cortex-A8 interrupt controller (INTC) rather
than the C0_TX_PEND and C0_RX_PEND interrupt outputs. So even
though CPSW interrupt is cleared by writing appropriate values to
EOI register the interrupt is not cleared in IRQ controller. So
interrupt is still pending and CPU is struck in ISR, the
workaround is to disable the interrupts in ARM irq controller.
[1] http://www.ti.com/lit/er/sprz360f/sprz360f.pdf
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 83 +++---
1 file changed, 77 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 3b81b39..8fc90f1 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -387,6 +387,9 @@ struct cpsw_priv {
struct cpsw_ale *ale;
boolrx_pause;
booltx_pause;
+ boolquirk_irq;
+ boolrx_irq_disabled;
+ booltx_irq_disabled;
/* snapshot of IRQ numbers */
u32 irqs_table[4];
u32 num_irqs;
@@ -755,6 +758,11 @@ static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
writel(0, priv-wr_regs-tx_en);
cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_TX);
+ if (priv-quirk_irq) {
+ disable_irq_nosync(priv-irqs_table[1]);
+ priv-tx_irq_disabled = true;
+ }
+
napi_schedule(priv-napi_tx);
return IRQ_HANDLED;
}
@@ -766,6 +774,11 @@ static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
cpdma_ctlr_eoi(priv-dma, CPDMA_EOI_RX);
writel(0, priv-wr_regs-rx_en);
+ if (priv-quirk_irq) {
+ disable_irq_nosync(priv-irqs_table[0]);
+ priv-rx_irq_disabled = true;
+ }
+
napi_schedule(priv-napi_rx);
return IRQ_HANDLED;
}
@@ -779,6 +792,10 @@ static int cpsw_tx_poll(struct napi_struct *napi_tx, int
budget)
if (num_tx budget) {
napi_complete(napi_tx);
writel(0xff, priv-wr_regs-tx_en);
+ if (priv-quirk_irq priv-tx_irq_disabled) {
+ priv-tx_irq_disabled = false;
+ enable_irq(priv-irqs_table[1]);
+ }
}
if (num_tx)
@@ -796,6 +813,10 @@ static int cpsw_rx_poll(struct napi_struct *napi_rx, int
budget)
if (num_rx budget) {
napi_complete(napi_rx);
writel(0xff, priv-wr_regs-rx_en);
+ if (priv-quirk_irq priv-rx_irq_disabled) {
+ priv-rx_irq_disabled = false;
+ enable_irq(priv-irqs_table[0]);
+ }
}
if (num_rx)
@@ -1267,6 +1288,16 @@ static int cpsw_ndo_open(struct net_device *ndev)
napi_enable(priv_sl0-napi_rx);
napi_enable(priv_sl0-napi_tx);
+ if (priv_sl0-tx_irq_disabled) {
+ priv_sl0-tx_irq_disabled = false;
+ enable_irq(priv-irqs_table[1]);
+ }
+
+ if (priv_sl0-rx_irq_disabled) {
+ priv_sl0-rx_irq_disabled = false;
+ enable_irq(priv-irqs_table[0]);
+ }
+
if (WARN_ON(!priv-data.rx_descs))
priv-data.rx_descs = 128;
@@ -2128,6 +2159,44 @@ static int cpsw_probe_dual_emac(struct platform_device
*pdev,
return ret;
}
+#define CPSW_QUIRK_IRQ BIT(0)
+
+static struct platform_device_id cpsw_devtype[] = {
+ {
+ /* keep it for existing comaptibles */
+ .name = cpsw,
+ .driver_data = CPSW_QUIRK_IRQ,
+ }, {
+ .name = am335x-cpsw,
+ .driver_data = CPSW_QUIRK_IRQ,
+ }, {
+ .name = am4372-cpsw,
+ .driver_data = 0,
+ }, {
+ .name = dra7-cpsw,
+ .driver_data = 0,
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(platform, cpsw_devtype);
+
+enum ti_cpsw_type {
+ CPSW = 0,
+ AM335X_CPSW,
+ AM4372_CPSW,
+ DRA7_CPSW,
+};
+
+static const struct of_device_id cpsw_of_mtable[] = {
+ { .compatible = ti,cpsw, .data = cpsw_devtype[CPSW], },
+ { .compatible = ti,am335x-cpsw, .data = cpsw_devtype[AM335X_CPSW], },
+ { .compatible = ti,am4372-cpsw, .data = cpsw_devtype[AM4372_CPSW], },
+ { .compatible = ti,dra7-cpsw, .data = cpsw_devtype[DRA7_CPSW], },
+ { /* sentinel */
[net-next PATCH 3/3] ARM: dts: am33xx: update cpsw compatible
CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 21fcc44..8b59c86 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -700,7 +700,7 @@
};
mac: ethernet@4a10 {
- compatible = ti,cpsw;
+ compatible = ti,am335x-cpsw,ti,cpsw;
ti,hwmods = cpgmac0;
clocks = cpsw_125mhz_gclk, cpsw_cpts_rft_clk;
clock-names = fck, cpts;
--
2.5.0.234.gefc8a62
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[net-next PATCH 0/3] Add AM335x PG1.0 CPSW errata workaround
With commit 870915feabdc (drivers: net: cpsw: remove disable_irq/enable_irq as irq can be masked from cpsw itself), CPSW on AM335x beagle bone white is broken as there is a errata for AM335x PG1.0. This patch series implements the workaround by disabling the interrupts from ARM IRQ controller for AM335x SoC in addition to the masking of interrupts in CPSW. Mugunthan V N (3): drivers: net: cpsw: add am335x errata workarround for interrutps ARM: dts: dra7: update cpsw compatible ARM: dts: am33xx: update cpsw compatible arch/arm/boot/dts/am33xx.dtsi | 2 +- arch/arm/boot/dts/dra7.dtsi| 2 +- drivers/net/ethernet/ti/cpsw.c | 83 +++--- 3 files changed, 79 insertions(+), 8 deletions(-) -- 2.5.0.234.gefc8a62 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: OMAP3: clock: remove un-used core dpll re-program code
* Tony Lindgren t...@atomide.com [150812 00:29]: * Tero Kristo t-kri...@ti.com [150716 01:10]: Remove the OMAP3 core DPLL re-program code, and the associated SRAM code that does the low-level programming of the DPLL divider, idling of the SDRAM etc. This code was never fully implemented in the kernel; things missing were driver side handling of core clock changes (they need to account for their functional clock rate being changed on-the-fly), and the whole framework required for handling this. Thus, there is not much point to keep carrying the low-level support code either. OK I'm applying this into omap-for-v4.3/soc. If we ever need the code it will be in the git history. Actually I'll wait on this one and apply it later on as it currently adds merge conflicts into Linux next. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/5] spi: introduce flag for memory mapped read
On 08/07/2015 03:46 PM, Michal Suchanek wrote:
[snip]
On 7 August 2015 at 10:35, Vignesh R vigne...@ti.com wrote:
On 08/07/2015 01:08 PM, Michal Suchanek wrote:
Now since the description is clearer it's obvious that ti-qspi cannot
work fully mmapped as fsl-qspi does because the setup has to be done
over normal spi access and using non-m25p80 devices on the same bus is
a requirement.
The place where it is known if a transfer can use the mmap access is
m25p80.c
So my suggestion is
- add a new method for spi master that gets the read opcode, dummy
length, address, address length, buffer, buffer length and performs
read from the flash memory in a hardware-specific way
- add a check in m25p80.c that the master supports this feature and if
so use it (eg check that the method is non-null)
Presumably if some new SPI controllers with similar feature are
supported in the future they can use the same inteface because you
pass on everything the m25p80 read knows.
Ok... Do you mean something like this?
I will take m25p80 as example but can be expanded for any flash.
In include/linux/mtd.h:
struct spi_mtd_config_info {
struct spi_device *spi;
u32 page_size;
u8 addr_width;
u8 erase_opcode;
u8 read_opcode;
u8 read_dummy;
u8 program_opcode;
enum read_mode flash_read;
} /* subset of struct spi_nor */
I would just pass these as separate arguments to the function but whatver.
In m25p80.c:
static int m25p80_read(struct spi_nor *nor, loff_t from,
size_t len, size_t *retlen,
u_char *buf)
{
struct spi_mtd_config_info info;
struct spi_device *spi;
if (spi-master-spi_mtd_mmap_read) {
/* Populate spi_mtd_config_info */
spi-master-spi_mtd_mmap_read(info, from, len,
retlen, buf);
}
else {
/* no mtd specific acceleration supported try normal
* SPI way of communicating with flash
* continue with current code
* set up spi_message and call spi_sync()
*/
}
}
In spi-ti-qspi.c:
Implement spi_mtd_mmap_read while holding master-bus_lock mutex.
I will re-submit patches based on the above idea, if there are no
further comments..
--
Thanks
Vignesh
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OMAP baseline test results for v4.2-rc5
Here are some basic OMAP test results for Linux v4.2-rc5. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v4.2-rc5/20150809200304/ Test summary Build: uImage: Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only, omap1_defconfig_5912osk_only Build: uImage+dtb: Pass (13/13): omap2plus_defconfig_am33xx_only/am335x-bone, omap2plus_defconfig/omap4-panda, omap2plus_defconfig/omap4-panda-es, omap2plus_defconfig/omap4-var-stk-om44, omap2plus_defconfig/omap3-evm-37xx, omap2plus_defconfig_n800_only_a/omap2420-n800, omap2plus_defconfig/omap2430-sdp, omap2plus_defconfig/am3517-evm, omap2plus_defconfig/omap3-beagle, omap2plus_defconfig/omap3-beagle-xm, omap2plus_defconfig/omap3-sbc-t3517, omap2plus_defconfig/omap5-uevm, omap2plus_defconfig/omap5-sbc-t54 Build: zImage: Pass (17/17): omap2plus_defconfig, omap2plus_defconfig_am33xx_only, omap2plus_defconfig_n800_only_a, omap2plus_defconfig_n800_multi_omap2xxx, omap2plus_defconfig_2430sdp_only, omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, omap2plus_defconfig_omap2_4_only, omap2plus_defconfig_omap3_4_only, omap2plus_defconfig_omap5_only, omap2plus_defconfig_dra7xx_only, omap2plus_defconfig_am43xx_only, rmk_omap3430_ldp_oldconfig, rmk_omap3430_ldp_allnoconfig, rmk_omap4430_sdp_oldconfig, rmk_omap4430_sdp_allnoconfig, multi_v7_defconfig Build warnings from toolchain: uImage: (none) Build warnings from toolchain: uImage+dtb: (none) Build warnings from toolchain: zImage: FAIL (10/17): omap2plus_defconfig, omap2plus_defconfig_am33xx_only, omap2plus_defconfig_2430sdp_only, omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, omap2plus_defconfig_omap2_4_only, omap2plus_defconfig_omap3_4_only, omap2plus_defconfig_omap5_only, omap2plus_defconfig_dra7xx_only, omap2plus_defconfig_am43xx_only Boot to userspace: FAIL ( 1/17): 2430sdp skip ( 3/17): 5912osk, 3517evm, 5430es2sbct54 Pass (13/17): am335xbonelt, am335xbone, 4430es2panda, 4460pandaes, 4460varsomom, 37xxevm, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm, cmt3517, 5430es2uevm, 2420n800 Kernel warnings during boot to userspace: FAIL ( 2/17): 4430es2panda, cmt3517 PM: chip retention via suspend: FAIL ( 6/11): am335xbonelt, 4430es2panda, 4460varsomom, 37xxevm, 2430sdp, 5430es2uevm Pass ( 5/11): 4460pandaes, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm PM: chip retention via dynamic idle: FAIL ( 6/11): am335xbonelt, 4430es2panda, 4460varsomom, 37xxevm, 2430sdp, 5430es2uevm Pass ( 5/11): 4460pandaes, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm PM: chip off (except CORE, due to errata) via suspend: Pass ( 1/ 1): 3730beaglexm PM: chip off (except CORE, due to errata) via dynamic idle: Pass ( 1/ 1): 3730beaglexm PM: chip off via suspend: FAIL ( 1/ 4): 37xxevm Pass ( 3/ 4): 3530es3beagle, 3530es31beagle, 3730es12beaglexm PM: chip off via dynamic idle: FAIL ( 1/ 4): 37xxevm Pass ( 3/ 4): 3530es3beagle, 3530es31beagle, 3730es12beaglexm Kernel warnings during PM test: FAIL ( 1/17): 4430es2panda Obsolete Kconfig symbols: FAIL ( 1/20): multi_v7_defconfig vmlinux object size (delta in bytes from test_v4.2-rc5 (74d33293e467df61de1b1d8b2fbe29e550dec33b)): text data bsstotal kernel 0000 omap1_defconfig 0000 omap1_defconfig_1510innovator_only 0000 omap1_defconfig_5912osk_only 0000 multi_v7_defconfig 0000 omap2plus_defconfig 0000 omap2plus_defconfig_2430sdp_only 0000 omap2plus_defconfig_am33xx_only 0000 omap2plus_defconfig_am43xx_only 0000 omap2plus_defconfig_cpupm 0000 omap2plus_defconfig_dra7xx_only 0000 omap2plus_defconfig_n800_multi_omap2xxx 0000 omap2plus_defconfig_n800_only_a 0000 omap2plus_defconfig_no_pm 0000 omap2plus_defconfig_omap2_4_only 000
OMAP baseline test results for v4.2-rc6
Here are some basic OMAP test results for Linux v4.2-rc6. Logs and other details at: http://www.pwsan.com/omap/testlogs/test_v4.2-rc6/20150810114017/ Test summary Build: uImage: Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only, omap1_defconfig_5912osk_only Build: uImage+dtb: Pass (13/13): omap2plus_defconfig_am33xx_only/am335x-bone, omap2plus_defconfig/omap4-panda, omap2plus_defconfig/omap4-panda-es, omap2plus_defconfig/omap4-var-stk-om44, omap2plus_defconfig/omap3-evm-37xx, omap2plus_defconfig_n800_only_a/omap2420-n800, omap2plus_defconfig/omap2430-sdp, omap2plus_defconfig/am3517-evm, omap2plus_defconfig/omap3-beagle, omap2plus_defconfig/omap3-beagle-xm, omap2plus_defconfig/omap3-sbc-t3517, omap2plus_defconfig/omap5-uevm, omap2plus_defconfig/omap5-sbc-t54 Build: zImage: Pass (17/17): omap2plus_defconfig, omap2plus_defconfig_am33xx_only, omap2plus_defconfig_n800_only_a, omap2plus_defconfig_n800_multi_omap2xxx, omap2plus_defconfig_2430sdp_only, omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, omap2plus_defconfig_omap2_4_only, omap2plus_defconfig_omap3_4_only, omap2plus_defconfig_omap5_only, omap2plus_defconfig_dra7xx_only, omap2plus_defconfig_am43xx_only, rmk_omap3430_ldp_oldconfig, rmk_omap3430_ldp_allnoconfig, rmk_omap4430_sdp_oldconfig, rmk_omap4430_sdp_allnoconfig, multi_v7_defconfig Build warnings from toolchain: uImage: (none) Build warnings from toolchain: uImage+dtb: (none) Build warnings from toolchain: zImage: FAIL (10/17): omap2plus_defconfig, omap2plus_defconfig_am33xx_only, omap2plus_defconfig_2430sdp_only, omap2plus_defconfig_cpupm, omap2plus_defconfig_no_pm, omap2plus_defconfig_omap2_4_only, omap2plus_defconfig_omap3_4_only, omap2plus_defconfig_omap5_only, omap2plus_defconfig_dra7xx_only, omap2plus_defconfig_am43xx_only Boot to userspace: FAIL ( 1/17): 2430sdp skip ( 3/17): 5912osk, 3517evm, 5430es2sbct54 Pass (13/17): am335xbonelt, am335xbone, 4430es2panda, 4460pandaes, 4460varsomom, 37xxevm, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm, cmt3517, 5430es2uevm, 2420n800 Kernel warnings during boot to userspace: FAIL ( 2/17): 4430es2panda, cmt3517 PM: chip retention via suspend: FAIL ( 6/11): am335xbonelt, 4430es2panda, 4460varsomom, 37xxevm, 2430sdp, 5430es2uevm Pass ( 5/11): 4460pandaes, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm PM: chip retention via dynamic idle: FAIL ( 6/11): am335xbonelt, 4430es2panda, 4460varsomom, 37xxevm, 2430sdp, 5430es2uevm Pass ( 5/11): 4460pandaes, 3530es3beagle, 3530es31beagle, 3730beaglexm, 3730es12beaglexm PM: chip off (except CORE, due to errata) via suspend: Pass ( 1/ 1): 3730beaglexm PM: chip off (except CORE, due to errata) via dynamic idle: Pass ( 1/ 1): 3730beaglexm PM: chip off via suspend: FAIL ( 1/ 4): 37xxevm Pass ( 3/ 4): 3530es3beagle, 3530es31beagle, 3730es12beaglexm PM: chip off via dynamic idle: FAIL ( 1/ 4): 37xxevm Pass ( 3/ 4): 3530es3beagle, 3530es31beagle, 3730es12beaglexm Kernel warnings during PM test: FAIL ( 1/17): 4430es2panda Obsolete Kconfig symbols: FAIL ( 1/20): multi_v7_defconfig vmlinux object size (delta in bytes from test_v4.2-rc5 (74d33293e467df61de1b1d8b2fbe29e550dec33b)): text data bsstotal kernel +25100 +251 omap1_defconfig +25100 +251 omap1_defconfig_1510innovator_only +25100 +251 omap1_defconfig_5912osk_only +54000 +540 multi_v7_defconfig +444300+4443 omap2plus_defconfig +12700 +127 omap2plus_defconfig_2430sdp_only +34700 +347 omap2plus_defconfig_am33xx_only +34700 +347 omap2plus_defconfig_am43xx_only +34700 +347 omap2plus_defconfig_cpupm +34700 +347 omap2plus_defconfig_dra7xx_only +41500 +415 omap2plus_defconfig_n800_multi_omap2xxx +43500 +435 omap2plus_defconfig_n800_only_a +34700 +347 omap2plus_defconfig_no_pm +34700 +347 omap2plus_defconfig_omap2_4_only +41500
[PATCH v2 2/6] genirq: fix irqchip_set_wake_parent if IRQCHIP_SKIP_SET_WAKE
The irqchip_set_wake_parent should not fail if IRQ chip
specifies IRQCHIP_SKIP_SET_WAKE. Otherwise, IRQ wakeup
configuration can't be propagated properly through IRQ
domains hierarchy.
In case of TI OMAP DRA7 the issue reproduced with following
configuration:
ARM GIC-OMAP wakeupgen-TI CBAR-GPIO-GPIO pcf857x-gpio_key
gpio_key is wakeup source
Failure is reproduced during suspend/resume to RAM:
suspend:
- gpio_keys_suspend
enable_irq_wake
+ pcf857x_irq_set_wake
+ omap_gpio_wake_enable
+ TI CBAR irq_chip_set_wake_parent
+ OMAP wakeupgen has no .irq_set_wake()
and -ENOSYS will be returned
resume:
- gpio_keys_resume
+ disable_irq_wake
+ irq_set_irq_wake
+ WARN(1, Unbalanced IRQ %d wake disable\n, irq);
Fixes: 08b55e2a9208 ('genirq: Add irqchip_set_wake_parent')
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
kernel/irq/chip.c | 4
1 file changed, 4 insertions(+)
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6de638b..bdb1b9d 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -1024,6 +1024,10 @@ int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data, void *vcpu_info)
int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
{
data = data-parent_data;
+
+ if (irq_data_get_irq_chip(data)-flags IRQCHIP_SKIP_SET_WAKE)
+ return 0;
+
if (data-chip-irq_set_wake)
return data-chip-irq_set_wake(data, on);
--
2.5.0
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[PATCH v2 0/6] genirq: irqdomain_hierarchy: fixes
Hi All, I've had able to identify and reproduce four issues related to switching on using IRQ domain hierarchy on TI OMAP DRA7 (dra7-evm). Most of them were discovered during testing of Suspend to RAM and IRQ wakeup functionality. In my opinion, most of these issue could also affect on other ARM SoC if they are using IRQ domain hierarchy. In case of TI OMAP DRA7 the following IRQ hierarchy is defined: ARM GIC - OMAP wakeupgen - TI CBAR Issue 1 - patch 1(new): IRQ re-triggering is not working if IRQ domain hierarchy used in combination with ARM GIC and irq_chip_retrigger_hierarchy() is used by child IRQ domain. Issue 2 - patch 2(new): IRQ wakeup configuration is not propagated properly through IRQ domains hierarchy if irq_chip_set_wake_parent() is used and parent IRQ domain don't implement .irq_set_wake(), but has IRQCHIP_SKIP_SET_WAKE flag set. Issue 3 - patches 3-5: ARM GIC IRQ triggering type is not configured properly when IRQ is routed through IRQ domain hierarchy and system started using DT. As result, system will start using default ARM GIC configuration, ignore DT IRQ triggering configuration, and value of desc-irq_data.state_use_accessors = 0. / # cat /proc/interrupts -- before 230: 0 0 CBAR 30 Edge- 48051000.gpio 263: 0 0 CBAR 116 Edge- 48053000.gpio 296:246 0 CBAR 67 Edge- OMAP UART0 311:341 0 CBAR 51 Edge- 4807.i2c 312: 3 0 CBAR 52 Edge- 48072000.i2c 313: 0 0 CBAR 56 Edge- 4806.i2c 314:255 0 CBAR 78 Edge- mmc0 315: 40 0 CBAR 81 Edge- mmc1 316: 13 0 CBAR 91 Edge- mmc2 320: 0 0 CBAR 49 Edge- 4a14.sata 324: 0 0 CBAR 1 Edge- 48078000.elm 325: 0 0 CBAR 15 Edge- gpmc 333: 0 0 CBAR 335 Edge- 48484000.ethernet 334: 0 0 CBAR 336 Edge- 48484000.ethernet 415: 0 0 pcf857x 2 Edge- btnUser1 416: 0 0 pcf857x 3 Edge- btnUser2 445: 0 0 pinctrl 992 Edge-0001 4806a000.seria / # cat /proc/interrupts -- after 230: 0 0 CBAR 30 Level -2004 48051000.gpio 263: 0 0 CBAR 116 Level -2004 48053000.gpio 296:567 0 CBAR 67 Level -2004 OMAP UART0 311:363 0 CBAR 51 Level -2004 4807.i2c 312: 3 0 CBAR 52 Level -2004 48072000.i2c 313: 0 0 CBAR 56 Level -2004 4806.i2c 314:197 0 CBAR 78 Level -2004 mmc0 315: 40 0 CBAR 81 Level -2004 mmc1 316: 13 0 CBAR 91 Level -2004 mmc2 320: 0 0 CBAR 49 Level -2004 4a14.sata 324: 0 0 CBAR 1 Level -2004 48078000.elm 325: 0 0 CBAR 15 Level -2004 gpmc 333: 0 0 CBAR 335 Level -2004 48484000.ethernet 334: 0 0 CBAR 336 Level -2004 48484000.ethernet 415: 0 0 pcf857x 2 Edge- btnUser1 416: 4 2 pcf857x 3 Edge- btnUser2 445: 0 0 pinctrl 992 Edge-0001 4806a000.serial - are current values of desc-irq_data.state_use_accessors Issue 4 - patch 5(new): ARM GIC IRQs are not masked during suspend even if they are not wakeup source. This issue related to IRQCHIP MASK ON SUSPEND flag usage and, honestly, it's not clear how this flag has to be processed in case of IRQ domain hierarchy - previously there was one IRQ chip per IRQ desc and if it has IRQCHIP MASK ON SUSPEND flag set we had to mask IRQ. But now there are up to three (DRA7) IRQ chip per IRQ desc, and all of them could have different IRQCHIP MASK ON SUSPEND flag's configuration. Here, to fix an issue, I've just added IRQCHIP MASK ON SUSPEND flag to TI Crossbar which is the last IRQ domain in hierarchy. IRQ domain hierarchy code was merged in 4.1, so it seems these patches are material for stable 4.1+. Tested on: TI OMAP DRA7, dra7-evm Series based on: Linux 4.2-rc6 Changes in v2: - initial patch has been split on three; - added three more patechs. Link on v1: https://lkml.org/lkml/2015/8/11/179 Grygorii Strashko (6): genirq: fix irq_chip_retrigger_hierarchy genirq: fix irqchip_set_wake_parent if IRQCHIP_SKIP_SET_WAKE genirq: introduce irq_chip_set_type_parent() helper irqchip: crossbar: fix arm gic irq type configuration ARM: OMAP: wakeupgen: fix arm gic irq type
Re: [PATCH] ARM: OMAP: irqdomain_hierarchy: fix arm gic irq type configuration
Hi Marc,
On 08/11/2015 05:33 PM, Marc Zyngier wrote:
On Tue, 11 Aug 2015 13:16:13 +0100
Grygorii Strashko grygorii.stras...@ti.com wrote:
On 08/11/2015 02:24 PM, Marc Zyngier wrote:
On Tue, 11 Aug 2015 10:25:47 +0100
Grygorii Strashko grygorii.stras...@ti.com wrote:
It's observed that ARM GIC IRQ triggering type is not configured
properly when IRQ is routed through IRQ domains hierarchy and
system started using DT. As result, system will start using default
ARM GIC configuration, ignore DT IRQ type configuration,
and value of desc-irq_data.state_use_accessors = 0.
In case of TI OMAP the following IRQ hierarchy is defined:
ARM GIC - OMAP wakeupgen - TI CBAR
Failed call chain:
irq_create_of_mapping
irq_set_irq_type
__irq_set_trigger
if (!chip || !chip-irq_set_type) {
return 0; - return here
}
CBAR has no .irq_set_type() defined and, so, IRQ triggering
configuration will not be propagated to parent IRQ domain.
Hence, fix it by introducing irq_chip_set_type_parent(), in the
same manner as irq_chip_set_wake_parent(), and use it for IRQ
triggering type propagation to the parent IRQ domain in
irq-crossbar and omap-wakeupgen.
/ # cat /proc/interrupts -- before
230: 0 0 CBAR 30 Edge- 48051000.gpio
263: 0 0 CBAR 116 Edge- 48053000.gpio
296:246 0 CBAR 67 Edge- OMAP UART0
311:341 0 CBAR 51 Edge- 4807.i2c
312: 3 0 CBAR 52 Edge- 48072000.i2c
313: 0 0 CBAR 56 Edge- 4806.i2c
314:255 0 CBAR 78 Edge- mmc0
315: 40 0 CBAR 81 Edge- mmc1
316: 13 0 CBAR 91 Edge- mmc2
320: 0 0 CBAR 49 Edge- 4a14.sata
324: 0 0 CBAR 1 Edge- 48078000.elm
325: 0 0 CBAR 15 Edge- gpmc
333: 0 0 CBAR 335 Edge- 48484000.ethernet
334: 0 0 CBAR 336 Edge- 48484000.ethernet
415: 0 0 pcf857x 2 Edge- btnUser1
416: 0 0 pcf857x 3 Edge- btnUser2
445: 0 0 pinctrl 992 Edge-0001 4806a000.seria
/ # cat /proc/interrupts -- after
230: 0 0 CBAR 30 Level -2004 48051000.gpio
263: 0 0 CBAR 116 Level -2004 48053000.gpio
296:567 0 CBAR 67 Level -2004 OMAP UART0
311:363 0 CBAR 51 Level -2004 4807.i2c
312: 3 0 CBAR 52 Level -2004 48072000.i2c
313: 0 0 CBAR 56 Level -2004 4806.i2c
314:197 0 CBAR 78 Level -2004 mmc0
315: 40 0 CBAR 81 Level -2004 mmc1
316: 13 0 CBAR 91 Level -2004 mmc2
320: 0 0 CBAR 49 Level -2004 4a14.sata
324: 0 0 CBAR 1 Level -2004 48078000.elm
325: 0 0 CBAR 15 Level -2004 gpmc
333: 0 0 CBAR 335 Level -2004 48484000.ethernet
334: 0 0 CBAR 336 Level -2004 48484000.ethernet
415: 0 0 pcf857x 2 Edge- btnUser1
416: 4 2 pcf857x 3 Edge- btnUser2
445: 0 0 pinctrl 992 Edge-0001 4806a000.serial
Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar to stacked
domains')
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
Hi All,
I can split patch if required and overall solution acceptable.
This looks good to me. Please repost it after splitting it in two
patches.
just to clarify - Do you want to see two or three patches?
2) or 3) arch/arm/mach-omap2/omap-wakeupgen.c | 1 +
2) drivers/irqchip/irq-crossbar.c | 1 +
1) include/linux/irq.h | 1 +
1) kernel/irq/chip.c| 16
Ah, I forgot wakeupgen lived in the omap-specific directory.
Please cut it in 3 then (generic implementation, crossbar and
wakeupgen).
Sry for delay - found three more problems. Just posted patches.
--
regards,
-grygorii
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[PATCH v2 3/6] genirq: introduce irq_chip_set_type_parent() helper
It's expected to use this helper when the current
domain doesn't implement .irq_set_type(), but expect
the parent to do so.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 20
2 files changed, 21 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 92188b0..51744bc 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -484,6 +484,7 @@ extern int irq_chip_set_affinity_parent(struct irq_data
*data,
extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
void *vcpu_info);
+extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
#endif
/* Handling of unhandled and spurious interrupts: */
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index bdb1b9d..b48938b 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -985,6 +985,26 @@ int irq_chip_set_affinity_parent(struct irq_data *data,
}
/**
+ * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
+ * @data: Pointer to interrupt specific data
+ * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
+{
+ data = data-parent_data;
+
+ if (irq_data_get_irq_chip(data)-flags IRQCHIP_SKIP_SET_WAKE)
+ return 0;
+
+ if (data-chip-irq_set_type)
+ return data-chip-irq_set_type(data, type);
+
+ return -ENOSYS;
+}
+
+/**
* irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
* @data: Pointer to interrupt specific data
*
--
2.5.0
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[PATCH v2 5/6] ARM: OMAP: wakeupgen: fix arm gic irq type configuration
It's observed that ARM GIC IRQ triggering type is not configured
properly when IRQ is routed through IRQ domain hierarchy and
system started using DT. As result, system will start using default
ARM GIC configuration, ignore DT IRQ triggering configuration,
and value of desc-irq_data.state_use_accessors = 0.
In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
ARM GIC - OMAP wakeupgen - TI CBAR
Failed call chain:
irq_create_of_mapping
irq_set_irq_type
__irq_set_trigger
if (!chip || !chip-irq_set_type) {
return 0; - return here
}
OMAP wakeupgen has no .irq_set_type() defined and, so, IRQ triggering
configuration will not be propagated to parent IRQ domain.
Hence, fix it by using irq_chip_set_type_parent() for
propagation IRQ triggering type to parent IRQ domains.
Fixes: 7136d457f365 ('ARM: omap: convert wakeupgen to stacked domains')
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
arch/arm/mach-omap2/omap-wakeupgen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c
b/arch/arm/mach-omap2/omap-wakeupgen.c
index 8e52621..e1d2e99 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -392,6 +392,7 @@ static struct irq_chip wakeupgen_chip = {
.irq_mask = wakeupgen_mask,
.irq_unmask = wakeupgen_unmask,
.irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_set_type = irq_chip_set_type_parent,
.flags = IRQCHIP_SKIP_SET_WAKE |
IRQCHIP_MASK_ON_SUSPEND,
#ifdef CONFIG_SMP
.irq_set_affinity = irq_chip_set_affinity_parent,
--
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Re: [PATCH v2 2/6] rtc: omap: Add external clock enabling support
On Wednesday 12 August 2015 07:57 PM, Paul Walmsley wrote: On Mon, 10 Aug 2015, Keerthy wrote: Switch to external clock source during suspend and switch back to internal source on resume. This helps rtc ticking across suspend. Doesn't this type of dynamic switching make it likely that ticks will be lost? If the external, optional source is present, isn't it best just to use the external source 100% of the time? Paul, The intent here is to switch to a higher precision clock which is the internal clock when available. Alexandre, Is dynamic switching preferred over sticking to external clock always if present? Regards, Keerthy - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend
All ARM GIC IRQs have to masked during suspend if they are not
wakeup source. Now this is not happen, since switching to
use IRQ domain hierarchy, because suspend_device_irq() only checks flags
in the last IRQ chip in hierarchy for IRQCHIP_MASK_ON_SUSPEND
bit set. And in the case of TI OMAP DRA7 the last IRQ chip is TI Crossbar
which do not have this flag set.
In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
ARM GIC - OMAP wakeupgen - TI CBAR
ARM GIC - IRQCHIP_MASK_ON_SUSPEND=n
OMAP wakeupgen - IRQCHIP_MASK_ON_SUSPEND=y
TI CBAR - IRQCHIP_MASK_ON_SUSPEND=n
Hence, fix by adding IRQCHIP_MASK_ON_SUSPEND for
TI Crossbar IRQ chip.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/irqchip/irq-crossbar.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 3ba58e7..f5a72cc 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -70,6 +70,7 @@ static struct irq_chip crossbar_chip = {
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_wake = irq_chip_set_wake_parent,
.irq_set_type = irq_chip_set_type_parent,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
#ifdef CONFIG_SMP
.irq_set_affinity = irq_chip_set_affinity_parent,
#endif
--
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[PATCH v2 4/6] irqchip: crossbar: fix arm gic irq type configuration
It's observed that ARM GIC IRQ triggering type is not configured
properly when IRQ is routed through IRQ domain hierarchy and
system started using DT. As result, system will start using default
ARM GIC configuration, ignore DT IRQ triggering configuration,
and value of desc-irq_data.state_use_accessors = 0.
In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
ARM GIC - OMAP wakeupgen - TI CBAR
Failed call chain:
irq_create_of_mapping
irq_set_irq_type
__irq_set_trigger
if (!chip || !chip-irq_set_type) {
return 0; - return here
}
Crossbar has no .irq_set_type() defined and, so, IRQ triggering
configuration will not be propagated to parent IRQ domain.
Hence, fix it by using irq_chip_set_type_parent() for
propagation IRQ triggering type to parent IRQ domains.
Fixes: 783d31863fb8 ('irqchip: crossbar: Convert dra7 crossbar...')
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/irqchip/irq-crossbar.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 692fe2b..3ba58e7 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -69,6 +69,7 @@ static struct irq_chip crossbar_chip = {
.irq_unmask = irq_chip_unmask_parent,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_wake = irq_chip_set_wake_parent,
+ .irq_set_type = irq_chip_set_type_parent,
#ifdef CONFIG_SMP
.irq_set_affinity = irq_chip_set_affinity_parent,
#endif
--
2.5.0
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[PATCH v2 1/6] genirq: fix irq_chip_retrigger_hierarchy
Now irq_chip_retrigger_hierarchy() returns -ENOSYS if it
was not able to find at least one .irq_retrigger() callback
implemented in IRQ domain hierarchy. As result, IRQ
re-triggering is not working now on ARM (TI OMAP) where
ARM GIC is not implemented this callback.
The .irq_retrigger() is optional (see check_irq_resend())
and there are no reasons to fail if it was not found, hence
lets return 0 in this case.
In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
ARM GIC - OMAP wakeupgen - TI CBAR
Failure is reproduced during resume from suspend to RAM:
- wakeup by IRQx
- suspend_enter
+ arch_suspend_enable_irqs
+ handle_fasteoi_irq
+ irq_may_run
+ irq_pm_check_wakeup
+ irq_disable(IRQx)
+ dpm_resume_noirq()
+ resume_device_irqs
+ resume_irqs
+ resume_irq
+ __enable_irq == IRQx is not re-triggered
Fixes: 85f08c17de26 ('genirq: Introduce helper functions...')
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
kernel/irq/chip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 27f4332..6de638b 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -997,7 +997,7 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
if (data-chip data-chip-irq_retrigger)
return data-chip-irq_retrigger(data);
- return -ENOSYS;
+ return 0;
}
/**
--
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Re: [RFC/PATCH-v4.2-rc6 2/5] arm: boot: dts: am4372: add ARM timers and SCU nodes
Hi, On Wed, Aug 12, 2015 at 09:52:16AM -0500, Felipe Balbi wrote: On Wed, Aug 12, 2015 at 12:28:16AM -0700, Tony Lindgren wrote: * Felipe Balbi ba...@ti.com [150810 14:44]: AM437x devices sport SCU, TWD and Global timers, let's add them to DTS so they have a chance to probe and be used by Linux. Is this one safe to apply already without the Kconfig change? Or will it cause multi_v7_defconfig with the timers selected to not boot properly? I'd have to try :-) But it should be safe, just the timers won't be chosen for anything :-) Just booted with only $subject and patch 1/5, it works just fine. I'll resend the series (now, 4 patches only) and if RMK is fine with patch 1, then I'll add to his patch system. -- balbi signature.asc Description: Digital signature
[PATCH-next 0/4] arm: am437x: use TWD/Global timers
Hi, with these patches AM437x devices can use TWD/global timers. At least TWD is now used as sched_clock() which gives better latency as seen below. Keep in mind that while I ran cyclictest to have a feel for avg latency this test was not against an RT kernel, so results should be taken with a grain of salt. Also, I'm not 100% sure clock rate is correct. According to TRM, this timer should run as MPU_CLK/2 which would be 1GHz / 2 = 500MHz, but even though I'm using dpll_mpu_m2_ck clock, it still shows as 1000MHz. Are there any other tests I could/should run ? BTW, I boot-tested on AM4372 with and without 'nosmp' on cmdline. pre-patch: T: 0 ( 245) P:95 I:1000 C: 9995 Min: 24 Act: 31 Avg: 36 Max: 596 post-patch: T: 0 ( 253) P:95 I:1000 C: 9995 Min: 10 Act: 12 Avg: 14 Max: 68 Changes since v1: - Rebased on top of today's linux-next (c1a0c66f231d Add linux-next specific files for 20150812) Felipe Balbi (4): Revert ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp arm: boot: dts: am4372: add ARM timers and SCU nodes arm: omap2: Kconfig: select TWD and global timer on AM43xx devices arm: omap2: board-generic: use omap4_local_timer_init for AM437x arch/arm/boot/dts/am4372.dtsi | 21 + arch/arm/kernel/smp_twd.c | 4 arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-omap2/board-generic.c | 2 +- 4 files changed, 25 insertions(+), 5 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-next 2/4] arm: boot: dts: am4372: add ARM timers and SCU nodes
AM437x devices sport SCU, TWD and Global timers,
let's add them to DTS so they have a chance to
probe and be used by Linux.
Signed-off-by: Felipe Balbi ba...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 51feccfa0e0a..7dfc9d8bd003 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -64,6 +64,27 @@
interrupt-parent = gic;
};
+ scu: scu@4824 {
+ compatible = arm,cortex-a9-scu;
+ reg = 0x4824 0x100;
+ };
+
+ global_timer: timer@48240200 {
+ compatible = arm,cortex-a9-global-timer;
+ reg = 0x48240200 0x100;
+ interrupts = GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = gic;
+ clocks = dpll_mpu_m2_ck;
+ };
+
+ local_timer: timer@48240600 {
+ compatible = arm,cortex-a9-twd-timer;
+ reg = 0x48240600 0x100;
+ interrupts = GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = gic;
+ clocks = dpll_mpu_m2_ck;
+ };
+
l2-cache-controller@48242000 {
compatible = arm,pl310-cache;
reg = 0x48242000 0x1000;
--
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[PATCH-next 3/4] arm: omap2: Kconfig: select TWD and global timer on AM43xx devices
Make sure to tell the kernel that AM437x has TWD and global timers. Signed-off-by: Felipe Balbi ba...@ti.com --- arch/arm/mach-omap2/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 07d2e100caab..88ef10b2d415 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -63,6 +63,9 @@ config SOC_AM43XX select MACH_OMAP_GENERIC select MIGHT_HAVE_CACHE_L2X0 select HAVE_ARM_SCU + select HAVE_ARM_TWD + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK config SOC_DRA7XX bool TI DRA7XX -- 2.5.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-next 4/4] arm: omap2: board-generic: use omap4_local_timer_init for AM437x
AM437x-based boards, can use omap4_local_timer_init() just fine. Let's use that instead. Signed-off-by: Felipe Balbi ba...@ti.com --- arch/arm/mach-omap2/board-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 24c9afc9e8a7..89bf39663d61 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -279,7 +279,7 @@ DT_MACHINE_START(AM43_DT, Generic AM43 (Flattened Device Tree)) .init_late = am43xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, - .init_time = omap3_gptimer_timer_init, + .init_time = omap4_local_timer_init, .dt_compat = am43_boards_compat, .restart= omap44xx_restart, MACHINE_END -- 2.5.0 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH-next 1/4] Revert ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp
This reverts commit 904464b91eca8c665acea033489225af02eeb75a.
The problem pointed out by commit 904464b91eca (ARM: 7655/1:
smp_twd: make twd_local_timer_of_register() no-op for nosmp)
doesn't exist anymore.
We can safely boot with nosmp and the warning won't show up.
The other side benefit of this patch is that TWD has a chance
to probe on single-core A9 systems such as AM437x which sport
TWD.
Cc: Shawn Guo shawn@linaro.org
Cc: Dirk Behme dirk.be...@de.bosch.com
Cc: Russell King rmk+ker...@arm.linux.org.uk
Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Felipe Balbi ba...@ti.com
---
arch/arm/kernel/smp_twd.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index e9035cda1485..662ed88bc1f9 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -23,7 +23,6 @@
#include linux/of_irq.h
#include linux/of_address.h
-#include asm/smp_plat.h
#include asm/smp_twd.h
/* set up by the platform code */
@@ -392,9 +391,6 @@ static void __init twd_local_timer_of_register(struct
device_node *np)
{
int err;
- if (!is_smp() || !setup_max_cpus)
- return;
-
twd_ppi = irq_of_parse_and_map(np, 0);
if (!twd_ppi) {
err = -EINVAL;
--
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