RE: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hello Kishon,
-Original Message-
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Thursday, May 29, 2014 12:08 PM
To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-omap@vger.kernel.org; linux-
p...@vger.kernel.org; linux-ker...@vger.kernel.org
Cc: a...@arndb.de; t...@atomide.com; jg1@samsung.com;
kis...@ti.com; Jason Gunthorpe; Bjorn Helgaas; Mohit KUMAR DCG; Marek
Vasut
Subject: [PATCH v2 03/18] PCI: designware: Configuration space should be
specified in 'reg'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe jguntho...@obsidianresearch.com
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Mohit Kumar mohit.ku...@st.com
Cc: Jingoo Han jg1@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as samsung,exynos5440-pcie or fsl,imx6q-pcie.
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ The configuration address space should also be specified here.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
+#include linux/platform_device.h
#include linux/types.h
#include pcie-designware.h
@@ -392,11 +393,23 @@ static const struct irq_domain_ops
msi_domain_ops = { int __init dw_pcie_host_init(struct pcie_port *pp) {
struct device_node *np = pp-dev-of_node;
+ struct platform_device *pdev = to_platform_device(pp-dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+ struct resource *cfg_res;
u32 val;
int i;
+ cfg_res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, config);
+ if (cfg_res) {
+ pp-config.cfg0_size = resource_size(cfg_res)/2;
+ pp-config.cfg1_size = resource_size(cfg_res)/2;
+ pp-cfg0_base = cfg_res-start;
+ pp-cfg1_base = cfg_res-start + pp-config.cfg0_size;
+ } else {
+ dev_err(pp-dev, missing *config* reg space\n);
+ }
+
if (of_pci_range_parser_init(parser, np)) {
dev_err(pp-dev, missing ranges property\n);
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(range, np, pp-cfg);
pp-config.cfg0_size = resource_size(pp-cfg)/2;
pp-config.cfg1_size = resource_size(pp-cfg)/2;
+ pp-cfg0_base = pp-cfg.start;
+ pp-cfg1_base = pp-cfg.start + pp-
config.cfg0_size;
- As you are getting cfg address space as MEM resource, so remove above code
that
gets the configuration space from dt range. Also correct dt for pcie cfg space
for the platforms
based on this driver.
Otherwise looks fine to me.
Thanks
Mohit
}
}
@@ -441,8 +456,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp-cfg0_base = pp-cfg.start;
- pp-cfg1_base = pp-cfg.start + pp-config.cfg0_size;
pp-mem_base = pp-mem.start;
pp-va_cfg0_base = devm_ioremap(pp-dev, pp-cfg0_base,
--
1.7.9.5
--
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RE: [RFC PATCH 03/12] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hello Kishon,
-Original Message-
From: Jingoo Han [mailto:jg1@samsung.com]
Sent: Thursday, March 27, 2014 5:15 PM
To: 'Kishon Vijay Abraham I'; Mohit KUMAR DCG; Pratyush ANAND
Cc: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-
ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
o...@vger.kernel.org; linux-...@vger.kernel.org; bhelg...@google.com;
robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; r...@landley.net;
li...@arm.linux.org.uk; t...@atomide.com; rna...@ti.com;
p...@pwsan.com; 'Marek Vasut'; 'Richard Zhu'
Subject: Re: [RFC PATCH 03/12] pci: host: pcie-designware: Use *base-mask*
for configuring the iATU
On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller can see
only 28bit address. So whenever the cpu issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe
controller but the PCIe controller will see only (0x000_ -
0xFFF_FFF). So for programming the outbound translation window the
*base* should be programmed as 0x000_.
Whenever we try to write to say 0x2000_, it will be translated to
whatever we have programmed in the translation window with base as
0x000_.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
(+cc Pratyush Anand, Marek Vasut, Richard Zhu)
Acked-by: Jingoo Han jg1@samsung.com
Mohit Kumar, Pratyush Anand,
If you have other opinions, please let us know. :-) Thank you.
- Yes, looks more clean now.
Acked-by: Mohit Kumar mohit.ku...@st.com
Regards,
Mohit
Best regards,
Jingoo Han
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 39
++--
drivers/pci/host/pcie-designware.h |1 +
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..c574dd3 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -27,6 +27,7 @@ Optional properties for fsl,imx6q-pcie
- power-on-gpio: gpio pin number of power-enable signal
- wake-up-gpio: gpio pin number of incoming wakeup signal
- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable
signal
+- base-mask: address mask for the PCIe controller target port
Example:
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 17ce88f..98b661c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -464,6 +464,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
return -EINVAL;
}
+ if (of_property_read_u64(np, base-mask, pp-base_mask))
+ pp-base_mask = ~(0x0ULL);
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp-irq_domain = irq_domain_add_linear(pp-dev-
of_node,
MAX_MSI_IRQS, msi_domain_ops,
@@ -503,12 +506,15 @@ int __init dw_pcie_host_init(struct pcie_port
*pp)
static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32
busdev) {
+ u64 cfg0_base;
+
+ cfg0_base = pp-cfg0_base pp-base_mask;
/* Program viewport 0 : OUTBOUND : CFG0 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND |
PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, pp-cfg0_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp-cfg0_base 32),
PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp-cfg0_base + pp-config.cfg0_size - 1,
+ dw_pcie_writel_rc(pp, cfg0_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg0_base 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg0_base + pp-config.cfg0_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); @@ -518,14
+524,17
@@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32
busdev)
static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32
busdev) {
+ u64 cfg1_base;
+
+ cfg1_base = pp-cfg1_base pp-base_mask;
/* Program viewport 1 : OUTBOUND : CFG1 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND |
PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
- dw_pcie_writel_rc(pp, pp-cfg1_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp-cfg1_base 32),
PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp
