From: Mythri P K mythr...@ti.com
1.Add some H/w indexable registers missed in definition.
2.Remove usage of struct hdmi_reg and use u16 instead.
3.Move the avi_infoframe parameters comments above the field.
Signed-off-by: Mythri P K mythr...@ti.com
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 10 +-
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 296 ++---
2 files changed, 151 insertions(+), 155 deletions(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index da7fe50..5f22d2e 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -32,15 +32,15 @@
#include dss.h
static inline void hdmi_write_reg(void __iomem *base_addr,
- const struct hdmi_reg idx, u32 val)
+ const u16 idx, u32 val)
{
- __raw_writel(val, base_addr + idx.idx);
+ __raw_writel(val, base_addr + idx);
}
static inline u32 hdmi_read_reg(void __iomem *base_addr,
- const struct hdmi_reg idx)
+ const u16 idx)
{
- return __raw_readl(base_addr + idx.idx);
+ return __raw_readl(base_addr + idx);
}
static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
@@ -69,7 +69,7 @@ static inline void __iomem *hdmi_core_sys_base(struct
hdmi_ip_data *ip_data)
}
static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
- const struct hdmi_reg idx,
+ const u16 idx,
int b2, int b1, u32 val)
{
u32 t = 0;
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 929de88..2040956 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -30,142 +30,138 @@
#include sound/pcm_params.h
#endif
-struct hdmi_reg { u16 idx; };
-
-#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
-
/* HDMI Wrapper */
-#define HDMI_WP_REVISION HDMI_REG(0x0)
-#define HDMI_WP_SYSCONFIG HDMI_REG(0x10)
-#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24)
-#define HDMI_WP_IRQSTATUS HDMI_REG(0x28)
-#define HDMI_WP_PWR_CTRL HDMI_REG(0x40)
-#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C)
-#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50)
-#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60)
-#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68)
-#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C)
-#define HDMI_WP_WP_CLK HDMI_REG(0x70)
-#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80)
-#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84)
-#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88)
-#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C)
+#define HDMI_WP_REVISION 0x0
+#define HDMI_WP_SYSCONFIG 0x10
+#define HDMI_WP_IRQSTATUS_RAW 0x24
+#define HDMI_WP_IRQSTATUS 0x28
+#define HDMI_WP_PWR_CTRL 0x40
+#define HDMI_WP_IRQENABLE_SET 0x2C
+#define HDMI_WP_VIDEO_CFG 0x50
+#define HDMI_WP_VIDEO_SIZE 0x60
+#define HDMI_WP_VIDEO_TIMING_H 0x68
+#define HDMI_WP_VIDEO_TIMING_V 0x6C
+#define HDMI_WP_WP_CLK 0x70
+#define HDMI_WP_AUDIO_CFG 0x80
+#define HDMI_WP_AUDIO_CFG2 0x84
+#define HDMI_WP_AUDIO_CTRL 0x88
+#define HDMI_WP_AUDIO_DATA 0x8C
/* HDMI IP Core System */
-#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0)
-#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8)
-#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC)
-#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10)
-#define HDMI_CORE_SYS_SRST HDMI_REG(0x14)
-#define HDMI_CORE_CTRL1HDMI_REG(0x20)
-#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24)
-#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124)
-#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128)
-#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0)
-#define HDMI_CORE_SYS_INTR1HDMI_REG(0x1C4)
-#define HDMI_CORE_SYS_INTR2HDMI_REG(0x1C8)
-#define HDMI_CORE_SYS_INTR3HDMI_REG(0x1CC)
-#define HDMI_CORE_SYS_INTR4HDMI_REG(0x1D0)
-#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4)
-#define HDMI_CORE_SYS_TMDS_CTRLHDMI_REG(0x208)
-#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8)
-#define HDMI_CORE_SYS_DE_CTRL
