Re: [PATCH 07/15] OMAP: DSS2: VENC driver

[Tony Lindgren]

* Tomi Valkeinen  [090805 17:19]:

Please add a description and tell what VENC means. And check
the data tabbing here too. Other than that:

Acked-by: Tony Lindgren 

> Signed-off-by: Tomi Valkeinen 
> ---
>  drivers/video/omap2/dss/venc.c |  797 
> 
>  1 files changed, 797 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/omap2/dss/venc.c
> 


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[PATCH 07/15] OMAP: DSS2: VENC driver

[Tomi Valkeinen]

Signed-off-by: Tomi Valkeinen 
---
 drivers/video/omap2/dss/venc.c |  797 
 1 files changed, 797 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/omap2/dss/venc.c

diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
new file mode 100644
index 000..091ecc4
--- /dev/null
+++ b/drivers/video/omap2/dss/venc.c
@@ -0,0 +1,797 @@
+/*
+ * linux/drivers/video/omap2/dss/venc.c
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen 
+ *
+ * VENC settings from TI's DSS driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#define DSS_SUBSYS_NAME "VENC"
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "dss.h"
+
+#define VENC_BASE  0x48050C00
+
+/* Venc registers */
+#define VENC_REV_ID0x00
+#define VENC_STATUS0x04
+#define VENC_F_CONTROL 0x08
+#define VENC_VIDOUT_CTRL   0x10
+#define VENC_SYNC_CTRL 0x14
+#define VENC_LLEN  0x1C
+#define VENC_FLENS 0x20
+#define VENC_HFLTR_CTRL0x24
+#define VENC_CC_CARR_WSS_CARR  0x28
+#define VENC_C_PHASE   0x2C
+#define VENC_GAIN_U0x30
+#define VENC_GAIN_V0x34
+#define VENC_GAIN_Y0x38
+#define VENC_BLACK_LEVEL   0x3C
+#define VENC_BLANK_LEVEL   0x40
+#define VENC_X_COLOR   0x44
+#define VENC_M_CONTROL 0x48
+#define VENC_BSTAMP_WSS_DATA   0x4C
+#define VENC_S_CARR0x50
+#define VENC_LINE210x54
+#define VENC_LN_SEL0x58
+#define VENC_L21__WC_CTL   0x5C
+#define VENC_HTRIGGER_VTRIGGER 0x60
+#define VENC_SAVID__EAVID  0x64
+#define VENC_FLEN__FAL 0x68
+#define VENC_LAL__PHASE_RESET  0x6C
+#define VENC_HS_INT_START_STOP_X   0x70
+#define VENC_HS_EXT_START_STOP_X   0x74
+#define VENC_VS_INT_START_X0x78
+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
+#define VENC_VS_EXT_STOP_Y 0x88
+#define VENC_AVID_START_STOP_X 0x90
+#define VENC_AVID_START_STOP_Y 0x94
+#define VENC_FID_INT_START_X__FID_INT_START_Y  0xA0
+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
+#define VENC_TVDETGP_INT_START_STOP_X  0xB0
+#define VENC_TVDETGP_INT_START_STOP_Y  0xB4
+#define VENC_GEN_CTRL  0xB8
+#define VENC_OUTPUT_CONTROL0xC4
+#define VENC_OUTPUT_TEST   0xC8
+#define VENC_DAC_B__DAC_C  0xC8
+
+struct venc_config {
+   u32 f_control;
+   u32 vidout_ctrl;
+   u32 sync_ctrl;
+   u32 llen;
+   u32 flens;
+   u32 hfltr_ctrl;
+   u32 cc_carr_wss_carr;
+   u32 c_phase;
+   u32 gain_u;
+   u32 gain_v;
+   u32 gain_y;
+   u32 black_level;
+   u32 blank_level;
+   u32 x_color;
+   u32 m_control;
+   u32 bstamp_wss_data;
+   u32 s_carr;
+   u32 line21;
+   u32 ln_sel;
+   u32 l21__wc_ctl;
+   u32 htrigger_vtrigger;
+   u32 savid__eavid;
+   u32 flen__fal;
+   u32 lal__phase_reset;
+   u32 hs_int_start_stop_x;
+   u32 hs_ext_start_stop_x;
+   u32 vs_int_start_x;
+   u32 vs_int_stop_x__vs_int_start_y;
+   u32 vs_int_stop_y__vs_ext_start_x;
+   u32 vs_ext_stop_x__vs_ext_start_y;
+   u32 vs_ext_stop_y;
+   u32 avid_start_stop_x;
+   u32 avid_start_stop_y;
+   u32 fid_int_start_x__fid_int_start_y;
+   u32 fid_int_offset_y__fid_ext_start_x;
+   u32 fid_ext_start_y__fid_ext_offset_y;
+   u32 tvdetgp_int_start_stop_x;
+   u32 tvdetgp_int_start_stop_y;
+   u32 gen_ctrl;
+};
+
+/* from TRM */
+static const struct venc_config venc_config_pal_trm = {
+