RE: [PATCH 2/2 v2] OMAP3:PM:SR: SmartReflex Refactor Rev3.0
> -Original Message-
> From: Nishanth Menon [mailto:n...@ti.com]
> Sent: Friday, October 23, 2009 4:40 AM
> Imberton Guilhem-gimb01 had written, on 10/22/2009 04:04 PM,
> the following:
> > I have one small comment on the actual implementation
> >> + do {
> >> + value = prm_read_mod_reg(OMAP3430_GR_MOD,
> >> +
> OMAP3_PRM_VC_BYPASS_VAL_OFFSET)
> >> + & OMAP3430_VALID;
> >> + /* should i wait? */
> >> + if (value && (count % 50))
> >> + udelay(10);
> >> + count--;
> >> + *timeout_us -= 5;
> >> + } while (value && count);
> >
> > Why are you removing 5us every read ?
> Thanks for catching this. Yep, I have got my counters mixed
> up :(.. will
> add it as part of v2 for tomorrow evening with other
> potential comments
> if any.
>
> > If 50 iteration is 1us and we delay every loop by 10us we
> should remove 11us
> >
> > Shouldn't it be:
> >
> > + do {
> > + value = prm_read_mod_reg(OMAP3430_GR_MOD,
> > +
> OMAP3_PRM_VC_BYPASS_VAL_OFFSET)
> > + & OMAP3430_VALID;
> > + /* should i wait? */
> > + if (value && (count % 50)) {
> > + udelay(10);
> > + *timeout_us -= 11;
> > + }
> > + count--;
> > + } while (value && count);
> >
> here is a problem with the above logic:
> a) I dont know for sure if 50 iterations == 1 uSec.
> b) count = timeout*5
>==> if function is called with timeout = 10 uSec, count = 50, and
> udelay(10) will be called once. now *timeout -=11 will make it a
> negative value, which is not helpeful.
>
> so, the decrement has to be by 10 OR i can pad timeout_us ..
> not exactly
> useful either..
Your right negative value wont be good
Let's use 10uSec (50 registers reading remains realy small amount of time)
And it will anyway give us a good idea of the time spent here
> --
> Regards,
> Nishanth Menon
>
Regards,
Guilhem
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Re: [PATCH 2/2 v2] OMAP3:PM:SR: SmartReflex Refactor Rev3.0
Imberton Guilhem-gimb01 had written, on 10/22/2009 04:04 PM, the following:
I have one small comment on the actual implementation
+ do {
+ value = prm_read_mod_reg(OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET)
+ & OMAP3430_VALID;
+ /* should i wait? */
+ if (value && (count % 50))
+ udelay(10);
+ count--;
+ *timeout_us -= 5;
+ } while (value && count);
Why are you removing 5us every read ?
Thanks for catching this. Yep, I have got my counters mixed up :(.. will
add it as part of v2 for tomorrow evening with other potential comments
if any.
If 50 iteration is 1us and we delay every loop by 10us we should remove 11us
Shouldn't it be:
+ do {
+ value = prm_read_mod_reg(OMAP3430_GR_MOD,
+OMAP3_PRM_VC_BYPASS_VAL_OFFSET)
+ & OMAP3430_VALID;
+ /* should i wait? */
+ if (value && (count % 50)) {
+ udelay(10);
+ *timeout_us -= 11;
+ }
+ count--;
+ } while (value && count);
here is a problem with the above logic:
a) I dont know for sure if 50 iterations == 1 uSec.
b) count = timeout*5
==> if function is called with timeout = 10 uSec, count = 50, and
udelay(10) will be called once. now *timeout -=11 will make it a
negative value, which is not helpeful.
so, the decrement has to be by 10 OR i can pad timeout_us .. not exactly
useful either..
--
Regards,
Nishanth Menon
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[PATCH 2/2 v2] OMAP3:PM:SR: SmartReflex Refactor Rev3.0
**-- SNIP ME
V3 - Bunch of changes:
* Introduce debugfs entries for SR - since these
are variable updates, you can essentially do what we do
with test values, change things but without a rebuild!
* Removed the test values altogether
* srid is standardised to u8 and it is not a bit field
* Guilhem's changes for non-twl5030 PMIC incorporated
* uses ioremap
V2 - made possible to work with non twl5030 PMICs
V1 - original rewrite
**-- END OF SNIP ME
Refactor the smart reflex implementation.
Original implementation summary:
Eduardo Valentin (1):
OMAP3: PM: SmartReflex: Fix scheduled while atomic problem
Kalle Jokiniemi (1):
OMAP3: PM: SmartReflex driver integration
Kevin Hilman (1):
temp: SR: IO_ADDRESS conversion
Phil Carmody (2):
OMAP3: PM: Don't do unnecessary searches in omap_sr_vdd*_autocomp_store
OMAP3: PM: Early exit on invalid parameters
Rajendra Nayak (10):
OMAP3: SR: Fix init voltage on OPP change
OMAP3: SR: Update VDD1/2 voltages at boot
OMAP3: SR: Use sysclk for SR CLKLENGTH calc
OMAP3: SR: Reset voltage level on SR disable
OMAP3: SR: Replace printk's with pr_* calls
OMAP3: SR: Remove redundant defines
OMAP3: SR: Replace (0x1 << n) with BIT(n)
OMAP3: SR: Fix SR driver to check for omap-pm return values
OMAP3: PM: Put optimal SMPS stabilization delay
OMAP3: SR: Wait for VP idle before a VP disable
Roger Quadros (4):
OMAP3: PM: Fix Smartreflex when used with PM_NOOP layer
OMAP3: PM: Make Smartreflex driver independent of SRF
OMAP3: PM: Do not Enable SmartReflex if OPP tables not defined
OMAP3: PM: Smartreflex: Fix VDD2 OPP determining logic
Teerth Reddy (1):
OMAP3: SR: Replace SR_PASS/FAIL,SR_TRUE/FALSE
This patch introduces the following changes in addition to refactoring
the implementation:
a) changes the DVFS transition sequences from:
freq, voltage(SR+vp) and viceversa
TO:
disable_vp,SR; freq, voltage(SR+vp) and viceversa; enable_vp,SR
[NOTE: sequence change for disable path - was sr_dis,vp_dis]
This change prevents spikes and unexpected voltage changes
as a result of SR being left enabled at wrong times
b) Major rewrite of smartreflex.c to do the following:
1) Support VCbypass style of voltage configuration as optional
introduce and support forceupdate default as recommended by
OMAP3430 TRM.
2) Centralize operations to allow for simpler and predictable code
flows
3) Modification to SR configured values to be inline with
silicon characterization results
4) cleanup of header
5) Introduce a few omap_pmic weak functions which can be overridden
by platforms implementing PMICs which are different from TWL4030
derivatives
6) srid is standardised to u8 and it is not a bit field
c) Fix ERRCONFIG access to prevent unplanned cleanup of interrupt
status registers - this is done using a interrupt status mask
d) Test nvalues removed instead use debugfs entries to set any values
you like - no more Kconfig option either..
e) Setup h/w timeout based on cpu sysclk and not hardcoded values
g) finegrained with raw register values available over
debugfs in //
smartreflex/{srid}/
nvalue_opp[1-5] - nvalues for all 5 opps
following register tweakability:
VP register values:
vplimito_value
vpstepmax_value
vpstepmin_value
vpconfig_value
SR Register values:
sr_errconfig_value
sr_config_value
Advice: disable SR before hitting them, no checks at this point.
test value equivalent userspace bash script would be:
mount -t debugfs none /dbg
mount -t sysfs none /sys
#vdd1:
#0x00AAB48A - OPP3
echo -n "11187338" >/dbg/pm_debug/smartreflex/1/nvalue_opp3
#0x00ABA2E6 - OPP4
echo -n "11248358" >/dbg/pm_debug/smartreflex/1/nvalue_opp4
# 0x00AB90D3 - OPP5
echo -n "11243731" >/dbg/pm_debug/smartreflex/1/nvalue_opp5
#setup senn and senp value (essentially +120)
x=`cat /dbg/pm_debug/smartreflex/1/sr_config_value`
y=$((x + 120))
echo -n $y>/dbg/pm_debug/smartreflex/1/sr_config_value
#and enable it..
echo -n "1" >/sys/power/sr_vdd1_autocomp
#vdd2
#0x00AAC695 -OPP3
echo -n "11191957" > /dbg/pm_debug/smartreflex/2/nvalue_opp3
#setup senn and senp value (essentially +120)
x=`cat /dbg/pm_debug/smartreflex/2/sr_config_value`
y=$((x + 120))
echo -n $y>/dbg/pm_debug/smartreflex/2/sr_config_value
#and enable it..
echo -n "1" >/sys/power/sr_vdd2_autocomp
Tested on:
SDP3430 with test N values as above and with ES3.1 silicon
TODO:
a) Handle scenarios for multiple OMAP variants with differing
SR capabilities (e.g. varying OPP levels - e.g. 3630, 4430 etc..)
[IMMEDIATE I
