[PATCH V5 2/3] arm: dts: dra7: Replace peripheral interrupt numbers with crossbar inputs

2014-05-06 Thread Sricharan R 
Now with the crossbar IP in picture, the peripherals do not have the
fixed interrupt lines. Instead they rely on the crossbar irqchip to
allocate and map a free interrupt line to its crossbar input. So replacing
all the peripheral interrupt numbers with its fixed crossbar input lines.

Cc: Benoit Cousson bcous...@baylibre.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Sricharan R r.sricha...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
[V5] Rebased on 3.15-rc4 and replaced irqs numbers with crossbar
 numbers for new peripherals.

 arch/arm/boot/dts/dra7.dtsi |  100 +++
 1 file changed, 54 insertions(+), 46 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 0274a86..52e4bd0 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -106,8 +106,8 @@
ti,hwmods = l3_main_1, l3_main_2;
reg = 0x4400 0x2000,
  0x4480 0x3000;
-   interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH;
 
prm: prm@4ae06000 {
compatible = ti,dra7-prm;
@@ -182,10 +182,10 @@
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
-   interrupts = GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH,
-GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
#dma-cells = 1;
#dma-channels = 32;
#dma-requests = 127;
@@ -194,7 +194,7 @@
gpio1: gpio@4ae1 {
compatible = ti,omap4-gpio;
reg = 0x4ae1 0x200;
-   interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio1;
gpio-controller;
#gpio-cells = 2;
@@ -205,7 +205,7 @@
gpio2: gpio@48055000 {
compatible = ti,omap4-gpio;
reg = 0x48055000 0x200;
-   interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio2;
gpio-controller;
#gpio-cells = 2;
@@ -216,7 +216,7 @@
gpio3: gpio@48057000 {
compatible = ti,omap4-gpio;
reg = 0x48057000 0x200;
-   interrupts = GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio3;
gpio-controller;
#gpio-cells = 2;
@@ -227,7 +227,7 @@
gpio4: gpio@48059000 {
compatible = ti,omap4-gpio;
reg = 0x48059000 0x200;
-   interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio4;
gpio-controller;
#gpio-cells = 2;
@@ -238,7 +238,7 @@
gpio5: gpio@4805b000 {
compatible = ti,omap4-gpio;
reg = 0x4805b000 0x200;
-   interrupts = GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio5;
gpio-controller;
#gpio-cells = 2;
@@ -249,7 +249,7 @@
gpio6: gpio@4805d000 {
compatible = ti,omap4-gpio;
reg = 0x4805d000 0x200;
-   interrupts = GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH;
+   interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
ti,hwmods = gpio6;
gpio-controller;
#gpio-cells = 2;
@@ -260,7 +260,7 @@
gpio7: gpio@48051000 {
compatible = ti,omap4-gpio;
reg = 0x48051000 0x200;
-   interrupts =

Re: [PATCH V5 2/3] arm: dts: dra7: Replace peripheral interrupt numbers with crossbar inputs

2014-05-06 Thread Tony Lindgren 
* Sricharan R r.sricha...@ti.com [140506 06:58]:
 Now with the crossbar IP in picture, the peripherals do not have the
 fixed interrupt lines. Instead they rely on the crossbar irqchip to
 allocate and map a free interrupt line to its crossbar input. So replacing
 all the peripheral interrupt numbers with its fixed crossbar input lines.

Presumably this depends on the crossbar fixes?

Are you guys sure this is OK to apply now? Has it really been tested
for the devices to work with the mainline kernel?

I do not want to see constant patching of things over and over again
with this stuff, so I'd like to see at least two Tested-by's for this
series before applying.

Regards,

Tony
 
 Cc: Benoit Cousson bcous...@baylibre.com
 Cc: Santosh Shilimkar santosh.shilim...@ti.com
 Cc: Rajendra Nayak rna...@ti.com
 Cc: Tony Lindgren t...@atomide.com
 Signed-off-by: Sricharan R r.sricha...@ti.com
 Signed-off-by: Nishanth Menon n...@ti.com
 ---
 [V5] Rebased on 3.15-rc4 and replaced irqs numbers with crossbar
  numbers for new peripherals.
 
  arch/arm/boot/dts/dra7.dtsi |  100 
 +++
  1 file changed, 54 insertions(+), 46 deletions(-)
 
 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
 index 0274a86..52e4bd0 100644
 --- a/arch/arm/boot/dts/dra7.dtsi
 +++ b/arch/arm/boot/dts/dra7.dtsi
 @@ -106,8 +106,8 @@
   ti,hwmods = l3_main_1, l3_main_2;
   reg = 0x4400 0x2000,
 0x4480 0x3000;
 - interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
 -  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH,
 +  GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH;
  
   prm: prm@4ae06000 {
   compatible = ti,dra7-prm;
 @@ -182,10 +182,10 @@
   sdma: dma-controller@4a056000 {
   compatible = ti,omap4430-sdma;
   reg = 0x4a056000 0x1000;
 - interrupts = GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH,
 -  GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH,
 -  GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH,
 -  GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH,
 +  GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
 +  GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
 +  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
   #dma-cells = 1;
   #dma-channels = 32;
   #dma-requests = 127;
 @@ -194,7 +194,7 @@
   gpio1: gpio@4ae1 {
   compatible = ti,omap4-gpio;
   reg = 0x4ae1 0x200;
 - interrupts = GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
   ti,hwmods = gpio1;
   gpio-controller;
   #gpio-cells = 2;
 @@ -205,7 +205,7 @@
   gpio2: gpio@48055000 {
   compatible = ti,omap4-gpio;
   reg = 0x48055000 0x200;
 - interrupts = GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
   ti,hwmods = gpio2;
   gpio-controller;
   #gpio-cells = 2;
 @@ -216,7 +216,7 @@
   gpio3: gpio@48057000 {
   compatible = ti,omap4-gpio;
   reg = 0x48057000 0x200;
 - interrupts = GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH;
   ti,hwmods = gpio3;
   gpio-controller;
   #gpio-cells = 2;
 @@ -227,7 +227,7 @@
   gpio4: gpio@48059000 {
   compatible = ti,omap4-gpio;
   reg = 0x48059000 0x200;
 - interrupts = GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;
   ti,hwmods = gpio4;
   gpio-controller;
   #gpio-cells = 2;
 @@ -238,7 +238,7 @@
   gpio5: gpio@4805b000 {
   compatible = ti,omap4-gpio;
   reg = 0x4805b000 0x200;
 - interrupts = GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH;
 + interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
   ti,hwmods = gpio5;
   gpio-controller;
   #gpio-cells = 2;
 @@ -249,7 +249,7 @@
   gpio6: gpio@4805d000 {
   compatible = ti,omap4-gpio;
   reg = 0x4805d000 0x200;
 - interrupts = GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH;
 +