Re: [PATCH v9 6/9] MFD: TWL4030: workaround changes for TWL4030 Erratum 27
Hi Samuel, On Tue, Apr 26, 2011 at 3:43 PM, Samuel Ortiz sa...@linux.intel.com wrote: Hi Lesly, On Thu, Apr 14, 2011 at 05:57:54PM +0530, Lesly A M wrote: Workaround for TWL5030 Silicon Errata 27 28: 27 - VDD1, VDD2, may have glitches when their output value is updated. 28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock is switched from internal to external. Erratum 27: If the DCDC regulators is running on their internal oscillator, negative glitches may occur on VDD1, VDD2 output when voltage is changed. The OMAP device may reboot if the VDD1 or VDD2 go below the core minimum operating voltage. WORKAROUND Set up the TWL5030 DC-DC power supplies to use the HFCLKIN instead of the internal oscillator. Erratum 28: VDD1/VDD2 clock system may hang during switching the clock source from internal oscillator to external. VDD1/VDD2 output voltages may collapse if clock stops. WORKAROUND If HFCLK is disabled in OFFMODE, modify the sleep/wakeup sequence and setuptimes to make sure the switching will happen only when HFCLKIN is stable. Also use the TWL5030 watchdog to safeguard the first switching from internal oscillator to HFCLKIN during the TWL5030 init. IMPACT power sequence is changed. sleep/wakeup time values will be changed. The workaround changes are called from twl4030_power_init(), since we have to make some i2c_read calls to check the TWL4030 version the i2c will not be initialized in the early stage. This workaround is required for TWL5030 Silicon version less than ES1.2 The power script setup time changes are recommended by TI HW team. http://omapedia.org/wiki/TWL4030_power_scripts Changes taken from TWL4030 Erratum 27 workaround patch by Nishanth Menon. This patch and the following one depend on patch#4. Please re-send it once you agreed with Tony about where it should go. I will make the changes for Tony's comments and repost the patches. Thanks Regards, Lesly A M -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 6/9] MFD: TWL4030: workaround changes for TWL4030 Erratum 27
Hi Lesly, On Thu, Apr 14, 2011 at 05:57:54PM +0530, Lesly A M wrote: Workaround for TWL5030 Silicon Errata 27 28: 27 - VDD1, VDD2, may have glitches when their output value is updated. 28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock is switched from internal to external. Erratum 27: If the DCDC regulators is running on their internal oscillator, negative glitches may occur on VDD1, VDD2 output when voltage is changed. The OMAP device may reboot if the VDD1 or VDD2 go below the core minimum operating voltage. WORKAROUND Set up the TWL5030 DC-DC power supplies to use the HFCLKIN instead of the internal oscillator. Erratum 28: VDD1/VDD2 clock system may hang during switching the clock source from internal oscillator to external. VDD1/VDD2 output voltages may collapse if clock stops. WORKAROUND If HFCLK is disabled in OFFMODE, modify the sleep/wakeup sequence and setuptimes to make sure the switching will happen only when HFCLKIN is stable. Also use the TWL5030 watchdog to safeguard the first switching from internal oscillator to HFCLKIN during the TWL5030 init. IMPACT power sequence is changed. sleep/wakeup time values will be changed. The workaround changes are called from twl4030_power_init(), since we have to make some i2c_read calls to check the TWL4030 version the i2c will not be initialized in the early stage. This workaround is required for TWL5030 Silicon version less than ES1.2 The power script setup time changes are recommended by TI HW team. http://omapedia.org/wiki/TWL4030_power_scripts Changes taken from TWL4030 Erratum 27 workaround patch by Nishanth Menon. This patch and the following one depend on patch#4. Please re-send it once you agreed with Tony about where it should go. Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 6/9] MFD: TWL4030: workaround changes for TWL4030 Erratum 27
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
is switched from internal to external.
Erratum 27:
If the DCDC regulators is running on their internal oscillator,
negative glitches may occur on VDD1, VDD2 output when voltage is
changed.
The OMAP device may reboot if the VDD1 or VDD2 go below the
core minimum operating voltage.
WORKAROUND
Set up the TWL5030 DC-DC power supplies to use the HFCLKIN instead of
the internal oscillator.
Erratum 28:
VDD1/VDD2 clock system may hang during switching the clock source from
internal oscillator to external. VDD1/VDD2 output voltages may collapse
if clock stops.
WORKAROUND
If HFCLK is disabled in OFFMODE, modify the sleep/wakeup sequence and
setuptimes to make sure the switching will happen only when HFCLKIN is
stable.
Also use the TWL5030 watchdog to safeguard the first switching from
internal oscillator to HFCLKIN during the TWL5030 init.
IMPACT
power sequence is changed.
sleep/wakeup time values will be changed.
The workaround changes are called from twl4030_power_init(), since we have to
make some i2c_read calls to check the TWL4030 version the i2c will not be
initialized in the early stage.
This workaround is required for TWL5030 Silicon version less than ES1.2
The power script setup time changes are recommended by TI HW team.
http://omapedia.org/wiki/TWL4030_power_scripts
Changes taken from TWL4030 Erratum 27 workaround patch by Nishanth Menon.
Signed-off-by: Lesly A M lesl...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: David Derrick dderr...@ti.com
Cc: Samuel Ortiz sa...@linux.intel.com
---
arch/arm/mach-omap2/twl4030-script.c | 150 ++
drivers/mfd/twl4030-power.c | 78 ++
include/linux/i2c/twl.h |1 +
3 files changed, 229 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/twl4030-script.c
b/arch/arm/mach-omap2/twl4030-script.c
index aa5afbd..97cdaa3 100644
--- a/arch/arm/mach-omap2/twl4030-script.c
+++ b/arch/arm/mach-omap2/twl4030-script.c
@@ -324,8 +324,158 @@ static struct twl4030_resconfig twl4030_rconfig[] = {
{ 0, 0},
};
+/*
+ * Sleep and active sequences with changes for TWL5030 Erratum 27 workaround
+ *
+ * Sysoff (using sys_off signal):
+ * When SYS_CLKREQ goes low during retention no resources will be affected
+ * since no resources are assigned to P3 only.
+ *
+ * Since all resources are assigned to P1 and P3 then all resources
+ * will be affected on the falling edge of P3 (SYS_CLKREQ).
+ * When OMAP lower the SYS_CLKREQ signal PMIC will execute the
+ * A2S sequence in which HFCLKOUT is dissabled first and
+ * after 488.32 usec(PRM_VOLTOFFSET) resources assigned to P1 and P3
+ * and of TYPE2=1 are put to sleep
+ * (VDD1, VDD2, VPLL1, REGEN, NRESPWRON SYSEN).
+ * Again after a 61.04 usec resources assigned to P1 and P3
+ * and of TYPE2=2 are put to sleep
+ * (VINTANA1, VINTANA2, VINTDIG, VIO CLKEN).
+ *
+ * On wakeup event OMAP goes active and pulls the SYS_CLKREQ high,
+ * and will execute the S2A sequence which is same for P1_P2 P3.
+ * This will turn on all resources of TYPE2=2 to go to the active state.
+ * Three dummy broadcast messages are added to get a delay of ~10 ms
+ * before enabling the HFCLKOUT resource. And after a 30.52 usec
+ * all resources of TYPE2=1 are put to the active state.
+ *
+ * This 10ms delay can be reduced if the oscillator is having less
+ * stabilization time. A should be taken care if it needs more time
+ * for stabilization.
+ *
+ */
+
+/**
+ * DOC: Sleep to Active sequence for P1/P2/P3
+ *
+ * The wakeup sequence is adjusted to do the VDD1/VDD2 voltage ramp-up
+ * only after HFCLKIN is stabilized and the HFCLKOUT is enabled.
+ */
+static struct twl4030_ins wakeup_seq_erratum27[] __initdata = {
+ /*
+* Broadcast message to put res(TYPE2 = 2) to active.
+* Wait for ~10 mS (ramp-up time for OSC on the board)
+* after HFCLKIN is enabled
+*/
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 55},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 55},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 54},
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2,
+ RES_STATE_ACTIVE), 1},
+ /*
