Re: [PATCHv3 1/9] memory: emif: Move EMIF register defines to include/linux/
On Monday 12 August 2013 03:32 PM, Greg Kroah-Hartman wrote: > On Thu, Aug 08, 2013 at 09:35:46AM -0400, Santosh Shilimkar wrote: >> (You have not CC'ed Greg, Looping him) >> >> On Tuesday 06 August 2013 01:49 PM, Dave Gerlach wrote: >>> OMAP4 and AM33XX share the same EMIF controller IP. Although there >>> are significant differences in the IP integration due to which >>> AM33XX can't reuse the EMIF driver DVFS similar to OMAP4, >>> it can definitely benefit by reusing the EMIF related macros >>> defined in drivers/memory/emif.h. >>> >>> In the current OMAP PM framework the PM code resides under >>> arch/arm/mach-omap2/. To enable reuse of the register defines move >>> the register defines in the emif header file to include/linux so that >>> both the EMIF driver and the AM33XX PM code can benefit. >>> >>> Signed-off-by: Dave Gerlach >>> Cc: Santosh Shilimkar >>> Cc: Benoit Cousson >>> Cc: Aneesh V >>> --- >>> drivers/memory/emif.h | 543 >>> + >>> include/linux/ti_emif.h | 558 >>> +++ >>> 2 files changed, 559 insertions(+), 542 deletions(-) >>> create mode 100644 include/linux/ti_emif.h >>> >> For file movement or some part of file movement, while formating >> patch, use "git format-patch -C" so that only delta change will >> appear in the patch. >> >> The patch as such is fine by me. >> Acked-by: Santosh Shililmar >> >> Greg, >> Your ack is needed on this patch so that it can go >> along with the series. Subsequent patch from this series >> use the register defines from this patch. > > Acked-by: Greg Kroah-Hartman > Thanks !! -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 1/9] memory: emif: Move EMIF register defines to include/linux/
On Thu, Aug 08, 2013 at 09:35:46AM -0400, Santosh Shilimkar wrote: > (You have not CC'ed Greg, Looping him) > > On Tuesday 06 August 2013 01:49 PM, Dave Gerlach wrote: > > OMAP4 and AM33XX share the same EMIF controller IP. Although there > > are significant differences in the IP integration due to which > > AM33XX can't reuse the EMIF driver DVFS similar to OMAP4, > > it can definitely benefit by reusing the EMIF related macros > > defined in drivers/memory/emif.h. > > > > In the current OMAP PM framework the PM code resides under > > arch/arm/mach-omap2/. To enable reuse of the register defines move > > the register defines in the emif header file to include/linux so that > > both the EMIF driver and the AM33XX PM code can benefit. > > > > Signed-off-by: Dave Gerlach > > Cc: Santosh Shilimkar > > Cc: Benoit Cousson > > Cc: Aneesh V > > --- > > drivers/memory/emif.h | 543 > > + > > include/linux/ti_emif.h | 558 > > +++ > > 2 files changed, 559 insertions(+), 542 deletions(-) > > create mode 100644 include/linux/ti_emif.h > > > For file movement or some part of file movement, while formating > patch, use "git format-patch -C" so that only delta change will > appear in the patch. > > The patch as such is fine by me. > Acked-by: Santosh Shililmar > > Greg, > Your ack is needed on this patch so that it can go > along with the series. Subsequent patch from this series > use the register defines from this patch. Acked-by: Greg Kroah-Hartman -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv3 1/9] memory: emif: Move EMIF register defines to include/linux/
(You have not CC'ed Greg, Looping him) On Tuesday 06 August 2013 01:49 PM, Dave Gerlach wrote: > OMAP4 and AM33XX share the same EMIF controller IP. Although there > are significant differences in the IP integration due to which > AM33XX can't reuse the EMIF driver DVFS similar to OMAP4, > it can definitely benefit by reusing the EMIF related macros > defined in drivers/memory/emif.h. > > In the current OMAP PM framework the PM code resides under > arch/arm/mach-omap2/. To enable reuse of the register defines move > the register defines in the emif header file to include/linux so that > both the EMIF driver and the AM33XX PM code can benefit. > > Signed-off-by: Dave Gerlach > Cc: Santosh Shilimkar > Cc: Benoit Cousson > Cc: Aneesh V > --- > drivers/memory/emif.h | 543 + > include/linux/ti_emif.h | 558 > +++ > 2 files changed, 559 insertions(+), 542 deletions(-) > create mode 100644 include/linux/ti_emif.h > For file movement or some part of file movement, while formating patch, use "git format-patch -C" so that only delta change will appear in the patch. The patch as such is fine by me. Acked-by: Santosh Shililmar Greg, Your ack is needed on this patch so that it can go along with the series. Subsequent patch from this series use the register defines from this patch. > diff --git a/drivers/memory/emif.h b/drivers/memory/emif.h > index bfe08ba..8214f07 100644 > --- a/drivers/memory/emif.h > +++ b/drivers/memory/emif.h > @@ -12,548 +12,7 @@ > #ifndef __EMIF_H > #define __EMIF_H > > -/* > - * Maximum number of different frequencies supported by EMIF driver > - * Determines the number of entries in the pointer array for register > - * cache > - */ > -#define EMIF_MAX_NUM_FREQUENCIES 6 > - > -/* State of the core voltage */ > -#define DDR_VOLTAGE_STABLE 0 > -#define DDR_VOLTAGE_RAMPING 1 > - > -/* Defines for timing De-rating */ > -#define EMIF_NORMAL_TIMINGS 0 > -#define EMIF_DERATED_TIMINGS 1 > - > -/* Length of the forced read idle period in terms of cycles */ > -#define EMIF_READ_IDLE_LEN_VAL 5 > - > -/* > - * forced read idle interval to be used when voltage > - * is changed as part of DVFS/DPS - 1ms > - */ > -#define READ_IDLE_INTERVAL_DVFS (1*100) > - > -/* > - * Forced read idle interval to be used when voltage is stable > - * 50us - or maximum value will do > - */ > -#define READ_IDLE_INTERVAL_NORMAL(50*100) > - > -/* DLL calibration interval when voltage is NOT stable - 1us */ > -#define DLL_CALIB_INTERVAL_DVFS (1*100) > - > -#define DLL_CALIB_ACK_WAIT_VAL 5 > - > -/* Interval between ZQCS commands - hw team recommended value */ > -#define EMIF_ZQCS_INTERVAL_US(50*1000) > -/* Enable ZQ Calibration on exiting Self-refresh */ > -#define ZQ_SFEXITEN_ENABLE 1 > -/* > - * ZQ Calibration simultaneously on both chip-selects: > - * Needs one calibration resistor per CS > - */ > -#define ZQ_DUALCALEN_DISABLE0 > -#define ZQ_DUALCALEN_ENABLE 1 > - > -#define T_ZQCS_DEFAULT_NS90 > -#define T_ZQCL_DEFAULT_NS360 > -#define T_ZQINIT_DEFAULT_NS 1000 > - > -/* DPD_EN */ > -#define DPD_DISABLE 0 > -#define DPD_ENABLE 1 > - > -/* > - * Default values for the low-power entry to be used if not provided by user. > - * OMAP4/5 has a hw bug(i735) due to which this value can not be less than > 512 > - * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz > - */ > -#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048 > -#define EMIF_LP_MODE_TIMEOUT_POWER 512 > -#define EMIF_LP_MODE_FREQ_THRESHOLD 4 > - > -/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */ > -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000 > -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY0x41 > -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY0x80 > -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF > - > -/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */ > -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200 > -#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS1 > - > -/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */ > -#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360 > - > -#define EMIF_T_CSTA 3 > -#define EMIF_T_PDLL_UL 128 > - > -/* External PHY control re
[PATCHv3 1/9] memory: emif: Move EMIF register defines to include/linux/
OMAP4 and AM33XX share the same EMIF controller IP. Although there are significant differences in the IP integration due to which AM33XX can't reuse the EMIF driver DVFS similar to OMAP4, it can definitely benefit by reusing the EMIF related macros defined in drivers/memory/emif.h. In the current OMAP PM framework the PM code resides under arch/arm/mach-omap2/. To enable reuse of the register defines move the register defines in the emif header file to include/linux so that both the EMIF driver and the AM33XX PM code can benefit. Signed-off-by: Dave Gerlach Cc: Santosh Shilimkar Cc: Benoit Cousson Cc: Aneesh V --- drivers/memory/emif.h | 543 + include/linux/ti_emif.h | 558 +++ 2 files changed, 559 insertions(+), 542 deletions(-) create mode 100644 include/linux/ti_emif.h diff --git a/drivers/memory/emif.h b/drivers/memory/emif.h index bfe08ba..8214f07 100644 --- a/drivers/memory/emif.h +++ b/drivers/memory/emif.h @@ -12,548 +12,7 @@ #ifndef __EMIF_H #define __EMIF_H -/* - * Maximum number of different frequencies supported by EMIF driver - * Determines the number of entries in the pointer array for register - * cache - */ -#define EMIF_MAX_NUM_FREQUENCIES 6 - -/* State of the core voltage */ -#define DDR_VOLTAGE_STABLE 0 -#define DDR_VOLTAGE_RAMPING1 - -/* Defines for timing De-rating */ -#define EMIF_NORMAL_TIMINGS0 -#define EMIF_DERATED_TIMINGS 1 - -/* Length of the forced read idle period in terms of cycles */ -#define EMIF_READ_IDLE_LEN_VAL 5 - -/* - * forced read idle interval to be used when voltage - * is changed as part of DVFS/DPS - 1ms - */ -#define READ_IDLE_INTERVAL_DVFS(1*100) - -/* - * Forced read idle interval to be used when voltage is stable - * 50us - or maximum value will do - */ -#define READ_IDLE_INTERVAL_NORMAL (50*100) - -/* DLL calibration interval when voltage is NOT stable - 1us */ -#define DLL_CALIB_INTERVAL_DVFS(1*100) - -#define DLL_CALIB_ACK_WAIT_VAL 5 - -/* Interval between ZQCS commands - hw team recommended value */ -#define EMIF_ZQCS_INTERVAL_US (50*1000) -/* Enable ZQ Calibration on exiting Self-refresh */ -#define ZQ_SFEXITEN_ENABLE 1 -/* - * ZQ Calibration simultaneously on both chip-selects: - * Needs one calibration resistor per CS - */ -#defineZQ_DUALCALEN_DISABLE0 -#defineZQ_DUALCALEN_ENABLE 1 - -#define T_ZQCS_DEFAULT_NS 90 -#define T_ZQCL_DEFAULT_NS 360 -#define T_ZQINIT_DEFAULT_NS1000 - -/* DPD_EN */ -#define DPD_DISABLE0 -#define DPD_ENABLE 1 - -/* - * Default values for the low-power entry to be used if not provided by user. - * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512 - * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz - */ -#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048 -#define EMIF_LP_MODE_TIMEOUT_POWER 512 -#define EMIF_LP_MODE_FREQ_THRESHOLD4 - -/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */ -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000 -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41 -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80 -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF - -/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */ -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY0x0E084200 -#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 1 - -/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */ -#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS360 - -#define EMIF_T_CSTA3 -#define EMIF_T_PDLL_UL 128 - -/* External PHY control registers magic values */ -#define EMIF_EXT_PHY_CTRL_1_VAL0x04020080 -#define EMIF_EXT_PHY_CTRL_5_VAL0x04010040 -#define EMIF_EXT_PHY_CTRL_6_VAL0x01004010 -#define EMIF_EXT_PHY_CTRL_7_VAL0x1004 -#define EMIF_EXT_PHY_CTRL_8_VAL0x04010040 -#define EMIF_EXT_PHY_CTRL_9_VAL0x01004010 -#define EMIF_EXT_PHY_CTRL_10_VAL 0x1004 -#define EMIF_EXT_PHY_CTRL_11_VAL 0x -#define EMIF_EXT_PHY_CTRL_12_VAL 0x0
