RE: [RFC] [PATCH] OMAP3630 PM: Correct width for CLKSEL Fields

2009-11-10 Thread Sripathy, Vishwanath 
Alex,
On Wed, Nov 04, 2009 at 04:58:40 +0530, Sripathy, Vishwanath wrote:
  @@ -134,13 +135,13 @@ static struct omap_clk omap34xx_clks[] = {
  CLK(NULL,   omap_12m_fck, omap_12m_fck,  CK_343X),
  CLK(NULL,   dpll4_m2_ck,  dpll4_m2_ck,   CK_343X),
  CLK(NULL,   dpll4_m2x2_ck, dpll4_m2x2_ck, CK_343X),
  -   CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X),
  +   CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X | CK_363X),
  CLK(NULL,   dpll4_m3x2_ck, dpll4_m3x2_ck, CK_343X),
  -   CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X),
  +   CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X | CK_363X),
  CLK(NULL,   dpll4_m4x2_ck, dpll4_m4x2_ck, CK_343X),
  -   CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X),
  +   CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X | CK_363X),
  CLK(NULL,   dpll4_m5x2_ck, dpll4_m5x2_ck, CK_343X),
  -   CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X),
  +   CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X | CK_363X),
  CLK(NULL,   dpll4_m6x2_ck, dpll4_m6x2_ck, CK_343X),
  CLK(NULL,   emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
  CLK(NULL,   dpll5_ck, dpll5_ck,  CK_3430ES2),
 
 Doesn't it make more sense to have separate dpll4_*_ck's for 363X so as to 
 avoid the   clksel_mask_3630?
 

Then you will have to duplicate all the nodes in dpll4 clock tree which is 
redundant. There is no much difference in clock tree (between 3630 and 3430) 
except that clksel width is changed for 3630 which I feel does not justify 
adding a new clock tree. Updating the clksel mask is the simplest way to 
achieve it.

  @@ -1216,6 +1217,10 @@ int __init omap2_clk_init(void)
  cpu_mask |= RATE_IN_3430ES2;
  cpu_clkflg |= CK_3430ES2;
  }
  +   if (cpu_is_omap36xx()) {
  +   dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
  +   cpu_mask  |= RATE_IN_363X;
 
 Extra space before '|'.
 
  +   }
  }
 
 I think there's an indentation problem.
 
   
  clk_init(omap2_clk_functions);
  @@ -1225,6 +1230,11 @@ int __init omap2_clk_init(void)
   
  for (c = omap34xx_clks; c  omap34xx_clks + ARRAY_SIZE(omap34xx_clks); 
  c++)
  if (c-cpu  cpu_clkflg) {
  +   /* for 3630, change the mask value for clocks which are
  +   marked as CK_363X*/
  +   if (cpu_is_omap36xx())
  +   if (c-cpu   CK_363X)
 
 Extra space before ''.
 
  +   c-lk.clk-clksel_mask = 
  c-lk.clk-clksel_mask_3630;
 
 This looks longer than normally allowed.

What is longer? I did not get the comment.

 
 Regards,
 --
 Alex
 
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Re: [RFC] [PATCH] OMAP3630 PM: Correct width for CLKSEL Fields

2009-11-04 Thread Alexander Shishkin 
On Wed, Nov 04, 2009 at 04:58:40 +0530, Sripathy, Vishwanath wrote:
 @@ -134,13 +135,13 @@ static struct omap_clk omap34xx_clks[] = {
   CLK(NULL,   omap_12m_fck, omap_12m_fck,  CK_343X),
   CLK(NULL,   dpll4_m2_ck,  dpll4_m2_ck,   CK_343X),
   CLK(NULL,   dpll4_m2x2_ck, dpll4_m2x2_ck, CK_343X),
 - CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X),
 + CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X | CK_363X),
   CLK(NULL,   dpll4_m3x2_ck, dpll4_m3x2_ck, CK_343X),
 - CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X),
 + CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X | CK_363X),
   CLK(NULL,   dpll4_m4x2_ck, dpll4_m4x2_ck, CK_343X),
 - CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X),
 + CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X | CK_363X),
   CLK(NULL,   dpll4_m5x2_ck, dpll4_m5x2_ck, CK_343X),
 - CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X),
 + CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X | CK_363X),
   CLK(NULL,   dpll4_m6x2_ck, dpll4_m6x2_ck, CK_343X),
   CLK(NULL,   emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
   CLK(NULL,   dpll5_ck, dpll5_ck,  CK_3430ES2),

Doesn't it make more sense to have separate dpll4_*_ck's for 363X so as to
avoid the clksel_mask_3630?

 @@ -1216,6 +1217,10 @@ int __init omap2_clk_init(void)
   cpu_mask |= RATE_IN_3430ES2;
   cpu_clkflg |= CK_3430ES2;
   }
 + if (cpu_is_omap36xx()) {
 + dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
 + cpu_mask  |= RATE_IN_363X;

Extra space before '|'.

 + }
   }

I think there's an indentation problem.

  
   clk_init(omap2_clk_functions);
 @@ -1225,6 +1230,11 @@ int __init omap2_clk_init(void)
  
   for (c = omap34xx_clks; c  omap34xx_clks + ARRAY_SIZE(omap34xx_clks); 
 c++)
   if (c-cpu  cpu_clkflg) {
 + /* for 3630, change the mask value for clocks which are
 + marked as CK_363X*/
 + if (cpu_is_omap36xx())
 + if (c-cpu   CK_363X)

Extra space before ''.

 + c-lk.clk-clksel_mask = 
 c-lk.clk-clksel_mask_3630;

This looks longer than normally allowed.

Regards,
--
Alex
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[RFC] [PATCH] OMAP3630 PM: Correct width for CLKSEL Fields

2009-11-03 Thread Sripathy, Vishwanath 
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in 3630. 
This patch has changes to accommodate this in CM dynamically based on chip 
version. 
These changes are dependent on previous changes sent by 
Nishant/Richard under subject (OMAP3:clk - introduce DPLL4 jtype support)

Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 7844c04..f47a91a
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -97,6 +97,7 @@ struct omap_clk {
 #define CK_343X(1  0)
 #define CK_3430ES1 (1  1)
 #define CK_3430ES2 (1  2)
+#define CK_363X(1  3)
 
 static struct omap_clk omap34xx_clks[] = {
CLK(NULL,   omap_32k_fck, omap_32k_fck,  CK_343X),
@@ -134,13 +135,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL,   omap_12m_fck, omap_12m_fck,  CK_343X),
CLK(NULL,   dpll4_m2_ck,  dpll4_m2_ck,   CK_343X),
CLK(NULL,   dpll4_m2x2_ck, dpll4_m2x2_ck, CK_343X),
-   CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X),
+   CLK(NULL,   dpll4_m3_ck,  dpll4_m3_ck,   CK_343X | CK_363X),
CLK(NULL,   dpll4_m3x2_ck, dpll4_m3x2_ck, CK_343X),
-   CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X),
+   CLK(NULL,   dpll4_m4_ck,  dpll4_m4_ck,   CK_343X | CK_363X),
CLK(NULL,   dpll4_m4x2_ck, dpll4_m4x2_ck, CK_343X),
-   CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X),
+   CLK(NULL,   dpll4_m5_ck,  dpll4_m5_ck,   CK_343X | CK_363X),
CLK(NULL,   dpll4_m5x2_ck, dpll4_m5x2_ck, CK_343X),
-   CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X),
+   CLK(NULL,   dpll4_m6_ck,  dpll4_m6_ck,   CK_343X | CK_363X),
CLK(NULL,   dpll4_m6x2_ck, dpll4_m6x2_ck, CK_343X),
CLK(NULL,   emu_per_alwon_ck, emu_per_alwon_ck, CK_343X),
CLK(NULL,   dpll5_ck, dpll5_ck,  CK_3430ES2),
@@ -1216,6 +1217,10 @@ int __init omap2_clk_init(void)
cpu_mask |= RATE_IN_3430ES2;
cpu_clkflg |= CK_3430ES2;
}
+   if (cpu_is_omap36xx()) {
+   dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
+   cpu_mask  |= RATE_IN_363X;
+   }
}
 
clk_init(omap2_clk_functions);
@@ -1225,6 +1230,11 @@ int __init omap2_clk_init(void)
 
for (c = omap34xx_clks; c  omap34xx_clks + ARRAY_SIZE(omap34xx_clks); 
c++)
if (c-cpu  cpu_clkflg) {
+   /* for 3630, change the mask value for clocks which are
+   marked as CK_363X*/
+   if (cpu_is_omap36xx())
+   if (c-cpu   CK_363X)
+   c-lk.clk-clksel_mask = 
c-lk.clk-clksel_mask_3630;
clkdev_add(c-lk);
clk_register(c-lk.clk);
omap2_init_clk_clkdm(c-lk.clk);
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index a1b3de7..3e9420f
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -243,6 +243,43 @@ static const struct clksel_rate div16_dpll_rates[] = {
{ .div = 0 }
 };
 
+static const struct clksel_rate div32_dpll_rates[] = {
+   { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+   { .div = 2, .val = 2, .flags = RATE_IN_343X },
+   { .div = 3, .val = 3, .flags = RATE_IN_343X },
+   { .div = 4, .val = 4, .flags = RATE_IN_343X },
+   { .div = 5, .val = 5, .flags = RATE_IN_343X },
+   { .div = 6, .val = 6, .flags = RATE_IN_343X },
+   { .div = 7, .val = 7, .flags = RATE_IN_343X },
+   { .div = 8, .val = 8, .flags = RATE_IN_343X },
+   { .div = 9, .val = 9, .flags = RATE_IN_343X },
+   { .div = 10, .val = 10, .flags = RATE_IN_343X },
+   { .div = 11, .val = 11, .flags = RATE_IN_343X },
+   { .div = 12, .val = 12, .flags = RATE_IN_343X },
+   { .div = 13, .val = 13, .flags = RATE_IN_343X },
+   { .div = 14, .val = 14, .flags = RATE_IN_343X },
+   { .div = 15, .val = 15, .flags = RATE_IN_343X },
+   { .div = 16, .val = 16, .flags = RATE_IN_343X },
+   { .div = 17, .val = 17, .flags = RATE_IN_363X },
+   { .div = 18, .val = 18, .flags = RATE_IN_363X },
+   { .div = 19, .val = 19, .flags = RATE_IN_363X },
+   { .div = 20, .val = 20, .flags = RATE_IN_363X },
+   { .div = 21, .val = 21, .flags = RATE_IN_363X },
+   { .div = 22, .val = 22, .flags = RATE_IN_363X },
+   { .div = 23, .val = 23, .flags = RATE_IN_363X },
+   { .div = 24, .val = 24, .flags = RATE_IN_363X },
+   { .div = 25, .val = 25, .flags = RATE_IN_363X },
+   { .div = 26, .val = 26, .flags = RATE_IN_363X },
+   { .div = 27, .val = 27, .flags = RATE_IN_363X },
+   { .div = 28, .val = 28, .flags = RATE_IN_363X },
+   { .div = 29,