Re: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
Sripathy, Vishwanath wrote:
+ /* calculate the sram delay */
+ delay_sram = (((mpurate / gt_rate) * diff) / (loop * 2));
+
+ error_gain = mpurate / gt_rate;
+ delay_sram = delay_sram + error_gain;
Cosmetic changes:
error_gain = mpurate / gt_rate;
delay_sram = (error_gain * diff) / (loop);
delay_sram += error_gain;
Why *2 is missing in your code? 2 is needed since the loop takes 2 arm cycles.
its a typo, it should be (loop * 2).
BR,
Ambresh
Regards
Vishwa
Thanks,
Ambresh
+
+ return delay_sram;
+}
+#endif
+
int __init omap_sram_init(void)
{
omap_detect_sram();
omap_map_sram();
+#ifdef CONFIG_ARCH_OMAP3
+ _omap3_sram_delay = omap_sram_push(__sram_wait_delay,
+ __sram_wait_delay_sz);
+#endif
+
if (!(cpu_class_is_omap2()))
omap1_sram_init();
else if (cpu_is_omap242x())
--
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RE: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
-Original Message- From: K, Ambresh Sent: Thursday, March 18, 2010 12:46 PM To: Gurav , Pramod Cc: linux-omap@vger.kernel.org; Reddy, Teerth; Sripathy, Vishwanath Subject: Re: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS Gurav , Pramod wrote: From: Teerth Reddy tee...@ti.com The patch has the changes to calculate the dpll3 clock stabilization delay dynamically. The SRAM delay is calibrated during bootup using the gptimers and used while calculating the stabilization delay. By using the dynamic method the dependency on the type of cache being used is removed. The wait time for L3 clock stabilization is calculated using the formula = 4*REFCLK + 8*CLKOUTX2, which uses the M, N and M2 read from the registers. Since this gives slightly less value, 2us is added as buffer for safety. This works fine for omap3. Signed-off-by: Teerth Reddy tee...@ti.com Signed-off-by: Pramod Gurav pramod.gu...@ti.com Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 54 +++- arch/arm/mach-omap2/clock34xx.h|2 + arch/arm/mach-omap2/clock3xxx.c|2 +- arch/arm/mach-omap2/clock3xxx.h|1 + arch/arm/mach-omap2/clock3xxx_data.c | 13 arch/arm/mach-omap2/sram34xx.S |8 + arch/arm/plat-omap/include/plat/sram.h |4 ++ arch/arm/plat-omap/sram.c | 51 ++ 8 files changed, 126 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach- omap2/clkt34xx_dpll3m2.c index b2b1e37..29421b1 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -24,13 +24,21 @@ #include plat/clock.h #include plat/sram.h #include plat/sdrc.h +#include plat/prcm.h #include clock.h #include clock3xxx.h #include clock34xx.h #include sdrc.h -#define CYCLES_PER_MHZ 100 +#defineCYCLES_PER_MHZ 100 + +#defineDPLL_M_MASK 0x7ff +#defineDPLL_N_MASK 0x7f +#defineDPLL_M2_MASK0x1f +#defineSHIFT_DPLL_M16 +#defineSHIFT_DPLL_N8 +#defineSHIFT_DPLL_M2 27 /* * CORE DPLL (DPLL3) M2 divider rate programming functions @@ -56,6 +64,11 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + u32 clk_sel_regval; + u32 core_dpll_mul_m, core_dpll_div_n, core_dpll_clkoutdiv_m2; + u32 sys_clk_rate, sdrc_clk_stab; + u32 refclk, clkoutx2, switch_latency; + unsigned int delay_sram; if (!clk || !rate) return -EINVAL; @@ -79,16 +92,41 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } + clk_sel_regval = __raw_readl(clk-clksel_reg); + + /* Get the M, N and M2 values required for getting sdrc clk stab */ + core_dpll_mul_m = (clk_sel_regval SHIFT_DPLL_M) DPLL_M_MASK; + core_dpll_div_n = (clk_sel_regval SHIFT_DPLL_N) DPLL_N_MASK; + core_dpll_clkoutdiv_m2 = (clk_sel_regval SHIFT_DPLL_M2) + DPLL_M2_MASK; + sys_clk_rate = clk_get_rate(sys_ck_p); + + sys_clk_rate = sys_clk_rate / CYCLES_PER_MHZ; + + /* wait time for L3 clk stabilization = 4*REFCLK + 8*CLKOUTX2 */ + refclk = (4 * (core_dpll_div_n + 1)) / sys_clk_rate; + clkoutx2 = ((core_dpll_div_n + 1) * core_dpll_clkoutdiv_m2) / + (sys_clk_rate * core_dpll_mul_m * 2); + switch_latency = refclk + 8 * clkoutx2; + + /* Adding 2us to sdrc clk stab */ + sdrc_clk_stab = switch_latency + 2; + + delay_sram = delay_sram_val(); + /* -* XXX This only needs to be done when the CPU frequency changes +* Calculate the number of MPU cycles +* to wait for SDRC to stabilize */ + _mpurate = arm_fck_p-rate / CYCLES_PER_MHZ; - c = (_mpurate SDRC_MPURATE_SCALE) SDRC_MPURATE_BASE_SHIFT; - c += 1; /* for safety */ - c *= SDRC_MPURATE_LOOPS; - c = SDRC_MPURATE_SCALE; - if (c == 0) - c = 1; + + c = ((sdrc_clk_stab * _mpurate) / (delay_sram * 2)); + + pr_debug(m = %d, n = %d, m2 =%d\n, core_dpll_mul_m, core_dpll_div_n, + core_dpll_clkoutdiv_m2); + pr_debug(switch_latency = %d, sys_clk_rate = %d, cycles = %d\n, + switch_latency, sys_clk_rate, c); pr_debug(clock: changing CORE DPLL rate from %lu to %lu\n, clk-rate, validrate); diff --git a/arch/arm/mach-omap2
RE: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
-Original Message- From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of Gurav , Pramod Sent: Thursday, March 18, 2010 10:26 AM To: linux-omap@vger.kernel.org Cc: Reddy, Teerth; Gurav , Pramod; Sripathy, Vishwanath Subject: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS From: Teerth Reddy tee...@ti.com The patch has the changes to calculate the dpll3 clock stabilization delay dynamically. The SRAM delay is calibrated during bootup using the gptimers and used while calculating the stabilization delay. By using the dynamic method the dependency on the type of cache being used is removed. The wait time for L3 clock stabilization is calculated using the formula = 4*REFCLK + 8*CLKOUTX2, which uses the M, N and M2 read from the registers. Since this gives slightly less value, 2us is added as buffer for safety. This works fine for omap3. Signed-off-by: Teerth Reddy tee...@ti.com Signed-off-by: Pramod Gurav pramod.gu...@ti.com Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 54 +++- arch/arm/mach-omap2/clock34xx.h|2 + arch/arm/mach-omap2/clock3xxx.c|2 +- arch/arm/mach-omap2/clock3xxx.h|1 + arch/arm/mach-omap2/clock3xxx_data.c | 13 arch/arm/mach-omap2/sram34xx.S |8 + arch/arm/plat-omap/include/plat/sram.h |4 ++ arch/arm/plat-omap/sram.c | 51 ++ 8 files changed, 126 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37..29421b1 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -24,13 +24,21 @@ #include plat/clock.h #include plat/sram.h #include plat/sdrc.h +#include plat/prcm.h #include clock.h #include clock3xxx.h #include clock34xx.h #include sdrc.h -#define CYCLES_PER_MHZ 100 +#define CYCLES_PER_MHZ 100 + +#define DPLL_M_MASK 0x7ff +#define DPLL_N_MASK 0x7f Use one more tab +#define DPLL_M2_MASK0x1f +#define SHIFT_DPLL_M16 +#define SHIFT_DPLL_N8 +#define SHIFT_DPLL_M2 27 /* * CORE DPLL (DPLL3) M2 divider rate programming functions @@ -56,6 +64,11 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + u32 clk_sel_regval; + u32 core_dpll_mul_m, core_dpll_div_n, core_dpll_clkoutdiv_m2; + u32 sys_clk_rate, sdrc_clk_stab; + u32 refclk, clkoutx2, switch_latency; + unsigned int delay_sram; if (!clk || !rate) return -EINVAL; @@ -79,16 +92,41 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } + clk_sel_regval = __raw_readl(clk-clksel_reg); + + /* Get the M, N and M2 values required for getting sdrc clk stab */ + core_dpll_mul_m = (clk_sel_regval SHIFT_DPLL_M) DPLL_M_MASK; + core_dpll_div_n = (clk_sel_regval SHIFT_DPLL_N) DPLL_N_MASK; + core_dpll_clkoutdiv_m2 = (clk_sel_regval SHIFT_DPLL_M2) + DPLL_M2_MASK; + sys_clk_rate = clk_get_rate(sys_ck_p); + + sys_clk_rate = sys_clk_rate / CYCLES_PER_MHZ; + + /* wait time for L3 clk stabilization = 4*REFCLK + 8*CLKOUTX2 */ + refclk = (4 * (core_dpll_div_n + 1)) / sys_clk_rate; + clkoutx2 = ((core_dpll_div_n + 1) * core_dpll_clkoutdiv_m2) / + (sys_clk_rate * core_dpll_mul_m * 2); + switch_latency = refclk + 8 * clkoutx2; + + /* Adding 2us to sdrc clk stab */ + sdrc_clk_stab = switch_latency + 2; + + delay_sram = delay_sram_val(); + /* - * XXX This only needs to be done when the CPU frequency changes + * Calculate the number of MPU cycles + * to wait for SDRC to stabilize */ + _mpurate = arm_fck_p-rate / CYCLES_PER_MHZ; - c = (_mpurate SDRC_MPURATE_SCALE) SDRC_MPURATE_BASE_SHIFT; - c += 1; /* for safety */ - c *= SDRC_MPURATE_LOOPS; - c = SDRC_MPURATE_SCALE; - if (c == 0) - c = 1; + + c = ((sdrc_clk_stab * _mpurate) / (delay_sram * 2)); + + pr_debug(m = %d, n = %d, m2 =%d\n, core_dpll_mul_m, core_dpll_div_n, + core_dpll_clkoutdiv_m2); + pr_debug(switch_latency = %d, sys_clk_rate = %d, cycles = %d\n, + switch_latency, sys_clk_rate, c); pr_debug(clock:
Re: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
Gurav , Pramod wrote: From: Teerth Reddy tee...@ti.com The patch has the changes to calculate the dpll3 clock stabilization delay dynamically. The SRAM delay is calibrated during bootup using the gptimers and used while calculating the stabilization delay. By using the dynamic method the dependency on the type of cache being used is removed. The wait time for L3 clock stabilization is calculated using the formula = 4*REFCLK + 8*CLKOUTX2, which uses the M, N and M2 read from the registers. Since this gives slightly less value, 2us is added as buffer for safety. This works fine for omap3. Signed-off-by: Teerth Reddy tee...@ti.com Signed-off-by: Pramod Gurav pramod.gu...@ti.com Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 54 +++- arch/arm/mach-omap2/clock34xx.h|2 + arch/arm/mach-omap2/clock3xxx.c|2 +- arch/arm/mach-omap2/clock3xxx.h|1 + arch/arm/mach-omap2/clock3xxx_data.c | 13 arch/arm/mach-omap2/sram34xx.S |8 + arch/arm/plat-omap/include/plat/sram.h |4 ++ arch/arm/plat-omap/sram.c | 51 ++ 8 files changed, 126 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37..29421b1 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -24,13 +24,21 @@ #include plat/clock.h #include plat/sram.h #include plat/sdrc.h +#include plat/prcm.h #include clock.h #include clock3xxx.h #include clock34xx.h #include sdrc.h -#define CYCLES_PER_MHZ 100 +#defineCYCLES_PER_MHZ 100 + +#defineDPLL_M_MASK 0x7ff +#defineDPLL_N_MASK 0x7f +#defineDPLL_M2_MASK0x1f +#defineSHIFT_DPLL_M16 +#defineSHIFT_DPLL_N8 +#defineSHIFT_DPLL_M2 27 /* * CORE DPLL (DPLL3) M2 divider rate programming functions @@ -56,6 +64,11 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + u32 clk_sel_regval; + u32 core_dpll_mul_m, core_dpll_div_n, core_dpll_clkoutdiv_m2; + u32 sys_clk_rate, sdrc_clk_stab; + u32 refclk, clkoutx2, switch_latency; + unsigned int delay_sram; if (!clk || !rate) return -EINVAL; @@ -79,16 +92,41 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } + clk_sel_regval = __raw_readl(clk-clksel_reg); + + /* Get the M, N and M2 values required for getting sdrc clk stab */ + core_dpll_mul_m = (clk_sel_regval SHIFT_DPLL_M) DPLL_M_MASK; + core_dpll_div_n = (clk_sel_regval SHIFT_DPLL_N) DPLL_N_MASK; + core_dpll_clkoutdiv_m2 = (clk_sel_regval SHIFT_DPLL_M2) + DPLL_M2_MASK; + sys_clk_rate = clk_get_rate(sys_ck_p); + + sys_clk_rate = sys_clk_rate / CYCLES_PER_MHZ; + + /* wait time for L3 clk stabilization = 4*REFCLK + 8*CLKOUTX2 */ + refclk = (4 * (core_dpll_div_n + 1)) / sys_clk_rate; + clkoutx2 = ((core_dpll_div_n + 1) * core_dpll_clkoutdiv_m2) / + (sys_clk_rate * core_dpll_mul_m * 2); + switch_latency = refclk + 8 * clkoutx2; + + /* Adding 2us to sdrc clk stab */ + sdrc_clk_stab = switch_latency + 2; + + delay_sram = delay_sram_val(); + /* -* XXX This only needs to be done when the CPU frequency changes +* Calculate the number of MPU cycles +* to wait for SDRC to stabilize */ + _mpurate = arm_fck_p-rate / CYCLES_PER_MHZ; - c = (_mpurate SDRC_MPURATE_SCALE) SDRC_MPURATE_BASE_SHIFT; - c += 1; /* for safety */ - c *= SDRC_MPURATE_LOOPS; - c = SDRC_MPURATE_SCALE; - if (c == 0) - c = 1; + + c = ((sdrc_clk_stab * _mpurate) / (delay_sram * 2)); + + pr_debug(m = %d, n = %d, m2 =%d\n, core_dpll_mul_m, core_dpll_div_n, + core_dpll_clkoutdiv_m2); + pr_debug(switch_latency = %d, sys_clk_rate = %d, cycles = %d\n, + switch_latency, sys_clk_rate, c); pr_debug(clock: changing CORE DPLL rate from %lu to %lu\n, clk-rate, validrate); diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 628e8de..a9f2204 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -12,4 +12,6 @@ extern const struct clkops clkops_omap3430es2_ssi_wait; extern const struct clkops clkops_omap3430es2_hsotgusb_wait; extern const struct clkops
Re: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
G, Manjunath Kondaiah manj...@ti.com writes:
+#ifdef CONFIG_ARCH_OMAP3
+void (*_omap3_sram_delay)(unsigned int);
+unsigned int measure_sram_delay(unsigned int loop)
+{
+static struct omap_dm_timer *gpt;
+unsigned long flags, diff = 0, gt_rate, mpurate;
+unsigned int delay_sram, error_gain;
+unsigned int start = 0, end = 0;
+
+omap_dm_timer_init();
+gpt = omap_dm_timer_request();
+if (!gpt) {
Request timer API returns NULL on failure.
Use BUG_ON(gpt == NULL);
No. BUG_ON() will panic the kernel and hang here. There is no need
to crash the kernel for that.
Current aproach is fine, or if a more verbose warning is desired,
you can use if (WARN_ON(!gpt)) ... and drop the pr_err()
Kevin
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Re: [PATCH v4 1/2] OMAP3: SDRC: Dynamic Calculation of SDRC stall latency during DVFS
Pramod Gurav pramod.gu...@ti.com writes: From: Teerth Reddy tee...@ti.com The patch has the changes to calculate the dpll3 clock stabilization delay dynamically. The SRAM delay is calibrated during bootup using the gptimers and used while calculating the stabilization delay. By using the dynamic method the dependency on the type of cache being used is removed. The wait time for L3 clock stabilization is calculated using the formula = 4*REFCLK + 8*CLKOUTX2, which uses the M, N and M2 read from the registers. Since this gives slightly less value, 2us is added as buffer for safety. This works fine for omap3. Signed-off-by: Teerth Reddy tee...@ti.com Signed-off-by: Pramod Gurav pramod.gu...@ti.com Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com OK, I'm now OK with the GP timer usage in this version. The rest will need to be reviewed/merged by Paul. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
