RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
Sergio,
-Original Message-
From: Aguirre, Sergio
Sent: Friday, November 20, 2009 9:28 PM
To: Sripathy, Vishwanath; linux-omap@vger.kernel.org
Subject: RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
Vishwa,
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of
Sripathy, Vishwanath
Sent: Friday, November 20, 2009 9:29 AM
To: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630.This patch has changes to accommodate this in CM
dynamically based on
chip version.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 18 --
arch/arm/mach-omap2/clock34xx.h | 53
--
arch/arm/mach-omap2/cm-regbits-34xx.h |7 +++-
arch/arm/plat-omap/include/plat/clock.h |4 +-
4 files changed, 71 insertions(+), 11 deletions(-)
mode change 100644 = 100755 arch/arm/mach-omap2/clock34xx.c
No file mode changes, please.
Ack
diff --git a/arch/arm/mach-omap2/clock34xx.c
b/arch/arm/mach-omap2/clock34xx.c
index 167f075..1e35f9a
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -43,6 +43,7 @@
#include prm-regbits-34xx.h
#include cm.h
#include cm-regbits-34xx.h
+#include plat/cpu.h
static const struct clkops clkops_noncore_dpll_ops;
@@ -97,6 +98,7 @@ struct omap_clk {
#define CK_3XXX(1 0)
#define CK_3430ES1 (1 1)
#define CK_3430ES2 (1 2)
+#define CK_363X(1 3)
static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_32k_fck, omap_32k_fck, CK_3XXX),
@@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_12m_fck, omap_12m_fck, CK_3XXX),
CLK(NULL, dpll4_m2_ck, dpll4_m2_ck, CK_3XXX),
CLK(NULL, dpll4_m2x2_ck, dpll4_m2x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_3XXX),
+ CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_3XXX
| CK_363X),
Shouldn't CK_363X replace CK_3XXX?
CK_363X is always inside the CK_3XXX scope, but not the other way around.
Not really. If you see the intention of adding CK_363X, it is to indicate that
this particular clock node has some changes specific to 3630 and it needs
special handling. So we cannot replace CK_363X with CK_3XXX
CLK(NULL, dpll4_m3x2_ck, dpll4_m3x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_3XXX),
+ CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m4x2_ck, dpll4_m4x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_3XXX),
+ CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_3XXX),
+ CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck, CK_3XXX),
CLK(NULL, emu_per_alwon_ck, emu_per_alwon_ck, CK_3XXX),
CLK(NULL, dpll5_ck, dpll5_ck, CK_3430ES2),
@@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
dpll4_ck.dpll_data-sd_div_mask =
OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
+ dpll4_dd.mult_mask =
OMAP3630_PERIPH_DPLL_MULT_MASK;
+ cpu_mask |= RATE_IN_363X;
}
}
@@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
for (c = omap34xx_clks; c omap34xx_clks +
ARRAY_SIZE(omap34xx_clks); c++)
if (c-cpu cpu_clkflg) {
+ /* for 3630, change the mask value for
clocks which are
+ marked as CK_363X*/
+ if (cpu_is_omap3630() (c-cpu CK_363X)) {
+ c-lk.clk-clksel_mask =
+
c-lk.clk-clksel_mask_3630;
+ }
clkdev_add(c-lk);
clk_register(c-lk.clk);
omap2_init_clk_clkdm(c-lk.clk);
diff --git a/arch/arm/mach-omap2/clock34xx.h
b/arch/arm/mach-omap2/clock34xx.h
index 813a83e..93c92e5 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -243,6 +243,42 @@ static const struct clksel_rate
div16_dpll_rates[] = {
{ .div = 0 }
};
+static const struct clksel_rate div32_dpll_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+ { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+ { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+ { .div = 5, .val = 5, .flags = RATE_IN_3XXX
RE: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
Vishwa,
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of
Sripathy, Vishwanath
Sent: Friday, November 20, 2009 9:29 AM
To: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630.This patch has changes to accommodate this in CM
dynamically based on
chip version.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 18 --
arch/arm/mach-omap2/clock34xx.h | 53
--
arch/arm/mach-omap2/cm-regbits-34xx.h |7 +++-
arch/arm/plat-omap/include/plat/clock.h |4 +-
4 files changed, 71 insertions(+), 11 deletions(-)
mode change 100644 = 100755 arch/arm/mach-omap2/clock34xx.c
No file mode changes, please.
diff --git a/arch/arm/mach-omap2/clock34xx.c
b/arch/arm/mach-omap2/clock34xx.c
index 167f075..1e35f9a
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -43,6 +43,7 @@
#include prm-regbits-34xx.h
#include cm.h
#include cm-regbits-34xx.h
+#include plat/cpu.h
static const struct clkops clkops_noncore_dpll_ops;
@@ -97,6 +98,7 @@ struct omap_clk {
#define CK_3XXX (1 0)
#define CK_3430ES1 (1 1)
#define CK_3430ES2 (1 2)
+#define CK_363X (1 3)
static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_32k_fck, omap_32k_fck, CK_3XXX),
@@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_12m_fck, omap_12m_fck, CK_3XXX),
CLK(NULL, dpll4_m2_ck, dpll4_m2_ck, CK_3XXX),
CLK(NULL, dpll4_m2x2_ck, dpll4_m2x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_3XXX),
+ CLK(NULL, dpll4_m3_ck, dpll4_m3_ck, CK_3XXX
| CK_363X),
Shouldn't CK_363X replace CK_3XXX?
CK_363X is always inside the CK_3XXX scope, but not the other way around.
CLK(NULL, dpll4_m3x2_ck, dpll4_m3x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_3XXX),
+ CLK(NULL, dpll4_m4_ck, dpll4_m4_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m4x2_ck, dpll4_m4x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_3XXX),
+ CLK(NULL, dpll4_m5_ck, dpll4_m5_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_3XXX),
+ CLK(NULL, dpll4_m6_ck, dpll4_m6_ck, CK_3XXX
| CK_363X),
CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck, CK_3XXX),
CLK(NULL, emu_per_alwon_ck, emu_per_alwon_ck, CK_3XXX),
CLK(NULL, dpll5_ck, dpll5_ck, CK_3430ES2),
@@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
dpll4_ck.dpll_data-sd_div_mask =
OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
+ dpll4_dd.mult_mask =
OMAP3630_PERIPH_DPLL_MULT_MASK;
+ cpu_mask |= RATE_IN_363X;
}
}
@@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
for (c = omap34xx_clks; c omap34xx_clks +
ARRAY_SIZE(omap34xx_clks); c++)
if (c-cpu cpu_clkflg) {
+ /* for 3630, change the mask value for
clocks which are
+ marked as CK_363X*/
+ if (cpu_is_omap3630() (c-cpu CK_363X)) {
+ c-lk.clk-clksel_mask =
+
c-lk.clk-clksel_mask_3630;
+ }
clkdev_add(c-lk);
clk_register(c-lk.clk);
omap2_init_clk_clkdm(c-lk.clk);
diff --git a/arch/arm/mach-omap2/clock34xx.h
b/arch/arm/mach-omap2/clock34xx.h
index 813a83e..93c92e5 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -243,6 +243,42 @@ static const struct clksel_rate
div16_dpll_rates[] = {
{ .div = 0 }
};
+static const struct clksel_rate div32_dpll_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+ { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+ { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+ { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
+ { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
+ { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
+ { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
+ { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
+ { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
+ { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
+ { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
+ { .div
Re: [PATCHV2 3/4] OMAP3: Correct width for CLKSEL Fields
Hi Vishwa,
Thanks for the patch, few comments follow:
Sripathy, Vishwanath had written, on 11/20/2009 09:28 AM, the following:
DPLL4 M, M3, M4, M5 and M6 field width has been increased by 1 bit in
3630.This patch has changes to accommodate this in CM dynamically based on
chip version.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock34xx.c | 18 --
arch/arm/mach-omap2/clock34xx.h | 53 --
arch/arm/mach-omap2/cm-regbits-34xx.h |7 +++-
arch/arm/plat-omap/include/plat/clock.h |4 +-
4 files changed, 71 insertions(+), 11 deletions(-)
mode change 100644 = 100755 arch/arm/mach-omap2/clock34xx.c
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 167f075..1e35f9a
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -43,6 +43,7 @@
#include prm-regbits-34xx.h
#include cm.h
#include cm-regbits-34xx.h
+#include plat/cpu.h
static const struct clkops clkops_noncore_dpll_ops;
@@ -97,6 +98,7 @@ struct omap_clk {
#define CK_3XXX(1 0)
#define CK_3430ES1 (1 1)
#define CK_3430ES2 (1 2)
+#define CK_363X(1 3)
The patch subject/commit msg and actual action here seem to differ
unfortunately - you are in reality introducing the CK_36XX deltas
here, you may want to fix the commit message OR split this patch into two:
a) introduce 36XX clocks - You may want to consider these in multiple
patches each introducing one specific change - clock wise perhaps.
b) introduce the DPLL4 Mx changes
this will allow:
1. Later traceability when we do a git bisect to know a specific change
if we are tracking a bug at a later date.
2. easier review for us as each would be one smaller chunk topic to review
static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_32k_fck, omap_32k_fck, CK_3XXX),
@@ -134,13 +136,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, omap_12m_fck, omap_12m_fck, CK_3XXX),
CLK(NULL, dpll4_m2_ck,dpll4_m2_ck, CK_3XXX),
CLK(NULL, dpll4_m2x2_ck, dpll4_m2x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m3_ck,dpll4_m3_ck, CK_3XXX),
+ CLK(NULL, dpll4_m3_ck,dpll4_m3_ck, CK_3XXX |
CK_363X),
CLK(NULL, dpll4_m3x2_ck, dpll4_m3x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m4_ck,dpll4_m4_ck, CK_3XXX),
+ CLK(NULL, dpll4_m4_ck,dpll4_m4_ck, CK_3XXX |
CK_363X),
CLK(NULL, dpll4_m4x2_ck, dpll4_m4x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m5_ck,dpll4_m5_ck, CK_3XXX),
+ CLK(NULL, dpll4_m5_ck,dpll4_m5_ck, CK_3XXX |
CK_363X),
CLK(NULL, dpll4_m5x2_ck, dpll4_m5x2_ck, CK_3XXX),
- CLK(NULL, dpll4_m6_ck,dpll4_m6_ck, CK_3XXX),
+ CLK(NULL, dpll4_m6_ck,dpll4_m6_ck, CK_3XXX |
CK_363X),
CLK(NULL, dpll4_m6x2_ck, dpll4_m6x2_ck, CK_3XXX),
CLK(NULL, emu_per_alwon_ck, emu_per_alwon_ck, CK_3XXX),
CLK(NULL, dpll5_ck, dpll5_ck, CK_3430ES2),
@@ -1222,6 +1224,8 @@ int __init omap2_clk_init(void)
OMAP3630_PERIPH_DPLL_DCO_SEL_MASK;
dpll4_ck.dpll_data-sd_div_mask =
OMAP3630_PERIPH_DPLL_SD_DIV_MASK;
+ dpll4_dd.mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK;
+ cpu_mask |= RATE_IN_363X;
these two things probably are different actions..
}
}
@@ -1232,6 +1236,12 @@ int __init omap2_clk_init(void)
for (c = omap34xx_clks; c omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
if (c-cpu cpu_clkflg) {
+ /* for 3630, change the mask value for clocks which are
+ marked as CK_363X*/
+ if (cpu_is_omap3630() (c-cpu CK_363X)) {
+ c-lk.clk-clksel_mask =
+ c-lk.clk-clksel_mask_3630;
+ }
clkdev_add(c-lk);
clk_register(c-lk.clk);
omap2_init_clk_clkdm(c-lk.clk);
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 813a83e..93c92e5 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -243,6 +243,42 @@ static const struct clksel_rate div16_dpll_rates[] = {
{ .div = 0 }
};
+static const struct clksel_rate div32_dpll_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_3XXX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
+ { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
+ { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
+ { .div = 5, .val = 5, .flags =
