RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message- From: Sripathy, Vishwanath Sent: Tuesday, April 06, 2010 6:45 PM To: Premi, Sanjeev; Paul Walmsley Cc: linux-omap@vger.kernel.org Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider [snip]--[snip] I have been trying to find a good place for the same myself. Though, my reason is different. The default kernel boots with the OPP3 for OMAP34xx; but when mpurate is used to set 720; I feel sometimes the boot may fail if the voltage isn't right. I thought uboot would have set the right voltage while setting the MPU rate. Isn't that true? mpurate is argument passed to kernel. u-boot is not doing much with it. The voltage does stabilize when smartrelex reflex is initialized. Why do you have dependency on SR for voltage stabilization? You can set the right voltage even w/o SR (via VP). SR is only for optimizing Voltage for a given OPP. In the default flow, clock_arch_init() where mpurate is acted upon, I didn't want to start changing the VP. Else some part of the code in SR - related to VP - will be duplicated. OR needs to be exported. Still not made my mind; as I have been away from this problem for a while now :( ~sanjeev Regards Vishwa I was trying to move smartreflex above in the init sequence; after i2c has been initialized. Comments/ thoughts? Best regards, Sanjeev [snip]--[snip] -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: Premi, Sanjeev
Sent: Monday, April 05, 2010 6:39 PM
To: Sripathy, Vishwanath; Paul Walmsley
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of
Sripathy, Vishwanath
Sent: Monday, April 05, 2010 5:23 PM
To: Paul Walmsley
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
Sent: Monday, April 05, 2010 4:44 PM
To: Sripathy, Vishwanath
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass
Clock Divider
On Mon, 5 Apr 2010, Sripathy, Vishwanath wrote:
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
On Thu, 1 Apr 2010, Vishwanath BS wrote:
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-
omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
Code in resource34xx.c will be executed only when DVFS is
executed.
However above code makes sure that initial values of Bypass clock
dividers are good. This will ensure that even if DVFS is disabled,
IVA/MPU are never overclocked when they enter bypass mode.
My point is that you don't know how the bootloader has
configured the
system at the point when this code executes. You don't
know what voltage
level VDD1 and VDD2 are at; you don't know what state the
clock tree is
in. You only know this when you change OPPs. And the
selection of the
OPP at startup is use-case dependent.
May be I can move this code to init_opp?
I have been trying to find a good place for the same myself. Though,
my reason is different. The default kernel boots with the OPP3 for
OMAP34xx; but when mpurate is used to set 720; I feel sometimes the
boot may fail if the voltage isn't right.
I thought uboot would have set the right voltage while setting the MPU rate.
Isn't that true?
The voltage does stabilize when smartrelex reflex is initialized.
Why do you have dependency on SR for voltage stabilization? You can set the
right voltage even w/o SR (via VP). SR is only for optimizing Voltage for a
given OPP.
Regards
Vishwa
I was trying to move smartreflex above in the init sequence; after
i2c has been initialized.
Comments/ thoughts?
Best regards,
Sanjeev
So as far as I can tell, this code shouldn't be there. If
you want to do
something like this, then you should add some generic way
(e.g., a kernel
command line parameter) to set the VDD1 and VDD2 OPPs at boot.
- Paul
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linux-omap in
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RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
Sent: Thursday, April 01, 2010 2:57 PM
To: Sripathy, Vishwanath
Cc: linux-omap@vger.kernel.org
Subject: Re: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
On Thu, 1 Apr 2010, Vishwanath BS wrote:
DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM
UCs running DSP codec was earlier restricted as DSP crashed.
The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2.
The solution is to make sure DPLL1/DPLL2 bypass clock is always less
than maximum supported frequency for the specific OPP.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock3xxx_data.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
...
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
Code in resource34xx.c will be executed only when DVFS is executed. However
above code makes sure that initial values of Bypass clock dividers are good.
This will ensure that even if DVFS is disabled, IVA/MPU are never overclocked
when they enter bypass mode.
Regards
Vishwa
- Paul
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the body of a message to majord...@vger.kernel.org
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RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
On Mon, 5 Apr 2010, Sripathy, Vishwanath wrote:
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
On Thu, 1 Apr 2010, Vishwanath BS wrote:
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
Code in resource34xx.c will be executed only when DVFS is executed.
However above code makes sure that initial values of Bypass clock
dividers are good. This will ensure that even if DVFS is disabled,
IVA/MPU are never overclocked when they enter bypass mode.
My point is that you don't know how the bootloader has configured the
system at the point when this code executes. You don't know what voltage
level VDD1 and VDD2 are at; you don't know what state the clock tree is
in. You only know this when you change OPPs. And the selection of the
OPP at startup is use-case dependent.
So as far as I can tell, this code shouldn't be there. If you want to do
something like this, then you should add some generic way (e.g., a kernel
command line parameter) to set the VDD1 and VDD2 OPPs at boot.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
Sent: Monday, April 05, 2010 4:44 PM
To: Sripathy, Vishwanath
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
On Mon, 5 Apr 2010, Sripathy, Vishwanath wrote:
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
On Thu, 1 Apr 2010, Vishwanath BS wrote:
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-
omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
Code in resource34xx.c will be executed only when DVFS is executed.
However above code makes sure that initial values of Bypass clock
dividers are good. This will ensure that even if DVFS is disabled,
IVA/MPU are never overclocked when they enter bypass mode.
My point is that you don't know how the bootloader has configured the
system at the point when this code executes. You don't know what voltage
level VDD1 and VDD2 are at; you don't know what state the clock tree is
in. You only know this when you change OPPs. And the selection of the
OPP at startup is use-case dependent.
May be I can move this code to init_opp?
So as far as I can tell, this code shouldn't be there. If you want to do
something like this, then you should add some generic way (e.g., a kernel
command line parameter) to set the VDD1 and VDD2 OPPs at boot.
- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of
Sripathy, Vishwanath
Sent: Monday, April 05, 2010 5:23 PM
To: Paul Walmsley
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
Sent: Monday, April 05, 2010 4:44 PM
To: Sripathy, Vishwanath
Cc: linux-omap@vger.kernel.org
Subject: RE: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass
Clock Divider
On Mon, 5 Apr 2010, Sripathy, Vishwanath wrote:
-Original Message-
From: Paul Walmsley [mailto:p...@pwsan.com]
On Thu, 1 Apr 2010, Vishwanath BS wrote:
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-
omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
Code in resource34xx.c will be executed only when DVFS is
executed.
However above code makes sure that initial values of Bypass clock
dividers are good. This will ensure that even if DVFS is disabled,
IVA/MPU are never overclocked when they enter bypass mode.
My point is that you don't know how the bootloader has
configured the
system at the point when this code executes. You don't
know what voltage
level VDD1 and VDD2 are at; you don't know what state the
clock tree is
in. You only know this when you change OPPs. And the
selection of the
OPP at startup is use-case dependent.
May be I can move this code to init_opp?
I have been trying to find a good place for the same myself. Though,
my reason is different. The default kernel boots with the OPP3 for
OMAP34xx; but when mpurate is used to set 720; I feel sometimes the
boot may fail if the voltage isn't right.
The voltage does stabilize when smartrelex reflex is initialized.
I was trying to move smartreflex above in the init sequence; after
i2c has been initialized.
Comments/ thoughts?
Best regards,
Sanjeev
So as far as I can tell, this code shouldn't be there. If
you want to do
something like this, then you should add some generic way
(e.g., a kernel
command line parameter) to set the VDD1 and VDD2 OPPs at boot.
- Paul
--
To unsubscribe from this list: send the line unsubscribe
linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
--
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Re: [PATCHV3 1/2] OMAP3: Set MPU and IVA bypass Clock Divider
On Thu, 1 Apr 2010, Vishwanath BS wrote:
DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM
UCs running DSP codec was earlier restricted as DSP crashed.
The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2.
The solution is to make sure DPLL1/DPLL2 bypass clock is always less
than maximum supported frequency for the specific OPP.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
---
arch/arm/mach-omap2/clock3xxx_data.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index d5153b6..d8e57a6
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
...
@@ -3597,5 +3601,13 @@ int __init omap3xxx_clk_init(void)
sdrc_ick_p = clk_get(NULL, sdrc_ick);
arm_fck_p = clk_get(NULL, arm_fck);
+ /* Set the bypass clock dividers for DPLL1 and DPLL2 */
+ if (cpu_is_omap3630()) {
+ clk_set_rate(dpll1_fck, 4/2);
+ clk_set_rate(dpll2_fck, 4/2);
+ } else {
+ clk_set_rate(dpll1_fck, 33200/4);
+ clk_set_rate(dpll2_fck, 33200/4);
+ }
This code is highly OPP-specific. Why is this code needed here?
Shouldn't the code in resource34xx.c be sufficient?
- Paul
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
