[RFC] omap: mailbox: fix detection for previously supported chips
Fix the mailbox support detection for OMAP3630, 3530/25 and 2430.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
- Testing was made under 3630 and 3430 boards.
- Given that 2430 uses similar initialization than OMAP3, changes
to handle this case was added to the patch.
- HWMOD adaptation hopefully should solve this mess, but as of now
mailbox should work as before at least.
arch/arm/mach-omap2/mailbox.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 42dbfa4..26d6fb0 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -394,15 +394,19 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3430)
- else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+ else if (omap3_has_iva()) {
list = omap3_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
}
#endif
-#if defined(CONFIG_ARCH_OMAP2420)
- else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+ list[0]-irq = platform_get_irq_byname(pdev, dsp);
+ } else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
--
1.7.1
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[PATCH 2/2] omap: mailbox: fix detection for previously supported chips
Fix the mailbox detection for OMAP3630, 3530/25 and 2430.
Given that 2430 has an iva too include it, as the same steps
for omap3 apply.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Tony Lindgren t...@atomide.com
CC: Russell King li...@arm.linux.org.uk
CC: Hiroshi DOYU hiroshi.d...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
CC: Suman Anna s-a...@ti.com
CC: Kevin Hilman khil...@deeprootsystems.com
CC: linux-omap@vger.kernel.org
---
arch/arm/mach-omap2/mailbox.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 42dbfa4..26d6fb0 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -394,15 +394,19 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3430)
- else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+ else if (omap3_has_iva()) {
list = omap3_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
}
#endif
-#if defined(CONFIG_ARCH_OMAP2420)
- else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+ list[0]-irq = platform_get_irq_byname(pdev, dsp);
+ } else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
--
1.7.1
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Re: [PATCH 0/2] omap: dsp: make the driver actually work
On 10/5/2010 4:05 PM, Felipe Contreras wrote: On Tue, Oct 5, 2010 at 11:09 PM, Ramirez Luna, Omaromar.rami...@ti.com wrote: Felipe Contreras wrote: ... Hmmm, because my other option was to move the reserved memory outside the kernel, but that involves specifying bootargs again and using dma_alloc_coherent with their restrictions. Huh, if there's no contiguous memory region reserved, then the driver is doing dma_alloc_coherent already, but that fails (apparently 5M is too much). Plus I've read that dma_alloc_coherent is precious; shouldn't be used for that. Initially bridge was using the memory on the upper part of the RAM, specifying in bootargs mem=MAX-6MB, so reintroducing the parameter works fine; dma_alloc_coherent was also used when bridge was compiled as built-in the kernel but now it is not working either. So, first I wanted to try reserving some region with mem=X boot param, but that solution is ugly. If that worked, then I wanted ti see if flushing each time we access that shm memory block works, but in the process I wanted to reorganize the whole initialization code because right now it's very ugly and confusing. Yes, I can help with that, I'm sending a patch to reintroduce the parameter for phys_mempool_base, however we need to remove or disable the memblock functions related with dspbridge. I was thinking of a menuconfig parameter to specify mempool base for built-in compilation. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC] tidspbridge: use a parameter to allocate shared memory
tidspbridge driver uses a block of memory denominated SHared Memory
to store info communicate with DSP, this SHM needs to be physically
contiguous and non-cacheable, to achieve the latter the driver ioremaps
the memory reserved to be SHM, this will trigger a warning if the
memory is under kernel control (because it creates another set of
mapping attributes, for the same memory area).
For now this can be avoided if a portion of memory (6MB) is left out
of kernel control (using bootarg attribute mem=) where tidspbridge
driver can make use of the memory and ioremap it without above
restriction.
Parameter has precedence over memblock allocator for shared memory.
i.e.: on a system with 256MB
set 'bootargs mem=250M ...'
cat /proc/iomem
...
8000-8f9f : System RAM
So driver needs to be installed with:
insmod bridgedriver.ko phys_mempool_base=0x8FA0
Same rationale applies for the menuconfig option.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
Code to allocate dspbridge memblock needs to be disabled since
it will be wasting 6MB.
arch/arm/mach-omap2/dsp.c|2 +-
drivers/staging/tidspbridge/Kconfig | 10 ++
drivers/staging/tidspbridge/rmgr/drv_interface.c | 15 ++-
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 6feeeae..0a4ba2f 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -45,7 +45,7 @@ static int __init omap_dsp_init(void)
int err = -ENOMEM;
struct omap_dsp_platform_data *pdata = omap_dsp_pdata;
- pdata-phys_mempool_base = omap_dsp_get_mempool_base();
+ pdata-phys_mempool_base = CONFIG_TIDSPBRIDGE_MEMPOOL_BASE;
if (pdata-phys_mempool_base) {
pdata-phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
diff --git a/drivers/staging/tidspbridge/Kconfig
b/drivers/staging/tidspbridge/Kconfig
index 93de4f2..1214cbc 100644
--- a/drivers/staging/tidspbridge/Kconfig
+++ b/drivers/staging/tidspbridge/Kconfig
@@ -23,6 +23,16 @@ config TIDSPBRIDGE_DVFS
performance and power consumption to the current processing
requirements.
+config TIDSPBRIDGE_MEMPOOL_BASE
+ hex Physical memory pool base (Addr)
+ depends on TIDSPBRIDGE
+ default 0
+ help
+ Use this address as the start of the shared memory block, it is
assumed
+ that this address is outside kernel control and configured by tweaking
+ mem= in bootargs. BASE + SIZE should fit in the system RAM address
+ space.
+
config TIDSPBRIDGE_MEMPOOL_SIZE
hex Physical memory pool size (Byte)
depends on TIDSPBRIDGE
diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c
b/drivers/staging/tidspbridge/rmgr/drv_interface.c
index 1981e46..4533605 100644
--- a/drivers/staging/tidspbridge/rmgr/drv_interface.c
+++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c
@@ -86,6 +86,7 @@ static s32 driver_major;
static char *base_img;
char *iva_img;
static s32 shm_size = 0x50;/* 5 MB */
+static unsigned int phys_mempool_base;
static int tc_wordswapon; /* Default value is always false */
#ifdef CONFIG_TIDSPBRIDGE_RECOVERY
#define REC_TIMEOUT 5000 /*recovery timeout in msecs */
@@ -132,6 +133,9 @@ MODULE_PARM_DESC(shm_size, shm size, default = 4 MB,
minimum = 64 KB);
module_param(tc_wordswapon, int, 0);
MODULE_PARM_DESC(tc_wordswapon, TC Word Swap Option. default = 0);
+module_param(phys_mempool_base, uint, 0);
+MODULE_PARM_DESC(phys_mempool_base, Physical Address base for SHM);
+
MODULE_AUTHOR(Texas Instruments);
MODULE_LICENSE(GPL);
MODULE_VERSION(DSPBRIDGE_VERSION);
@@ -298,7 +302,16 @@ static int omap3_bridge_startup(struct platform_device
*pdev)
}
dev_dbg(bridge, %s: requested shm_size = 0x%x\n, __func__, shm_size);
- phys_membase = pdata-phys_mempool_base;
+ if (phys_mempool_base) {
+ /* Out of kernel SHM */
+ phys_membase = phys_mempool_base;
+ } else if (pdata-phys_mempool_base) {
+ /* Memblock allocator for SHM */
+ phys_membase = pdata-phys_mempool_base;
+ } else {
+ pr_err(%s: couldn't get SHM physical address\n, __func__);
+ goto err3;
+ }
phys_memsize = pdata-phys_mempool_size;
if (phys_membase 0 phys_memsize 0)
mem_ext_phys_pool_init(phys_membase, phys_memsize);
--
1.7.1
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Re: [RFC] tidspbridge: use a parameter to allocate shared memory
On 10/7/2010 2:40 AM, Laurent Pinchart wrote: Hi Omar, On Thursday 07 October 2010 07:45:36 Omar Ramirez Luna wrote: tidspbridge driver uses a block of memory denominated SHared Memory to store info communicate with DSP, this SHM needs to be physically contiguous and non-cacheable, There are non-cacheable mappings, but there's no such thing as non-cacheable memory. Does the MPU mapping for that SHM block really needs to be non- cacheable, yes your could you instead flush the cache after writing to it (performance issues might be involved, I don't know the details about that SHM usage) ? You can do that too, but it will involve more changes to dsp side, and yes performance might be an issue too. The so called shared memory is used between arm tidspbridge and the DSP, they exchange communication structures/streams/messages/parameters needed on both sides for its correct functionality (this is an eagle-eye view of the SHM, for more info if interested check page 32 of the overview pdf[1]). tidspbridge could have the changes made for flushing the SHM every time it writes into it, a flag could be used to prevent both of them (ARM DSP) flushing at the same time if needed, but I don't know how feasible would be making those changes in the dsp code. Regards, Omar --- [1] https://gforge.ti.com/gf/download/docmanfileversion/17/674/OMAP3430_Bridge_overview.pdf -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] tidspbridge: use a parameter to allocate shared memory
On 10/7/2010 9:01 AM, Laurent Pinchart wrote: On Thursday 07 October 2010 10:32:42 Russell King - ARM Linux wrote: ARMv6 and above don't like having multiple mappings with different memory type/shareability/cache attributes. It's architecturally forbidden. So if you want non-cacheable memory and you want to be architecturally compliant, you have to exclude it from the kernel's direct-mapped memory mapping. That's why Omar's patch uses 'mem=' to exclude system memory from the kernel mappings. That's not ideal though, as that memory will be wasted forever, hence my comments regarding whether a non-cacheable mapping was really required. it is not ideal to waste that memory, but strictly speaking old bootmem does the same, as no one will be touching that memory. i.e. you compile bridge as a module but you never insmod it, the reserved bootmem space is there for bridge anyway; same for bootargs tweaking, if you need dspbridge and are going to use it then you set aside some memory for it. What might be a pain for end-user, is to have drivers that need to do tweaking to bootargs to work; but right now that is a requirement, until a better solution is found/created. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] tidspbridge: use a parameter to allocate shared memory
On 10/7/2010 1:22 PM, Felipe Contreras wrote: ... Note that the shared memory described in the document you share has nothing to do with the SHM pool. AFAIK that memory is used for other things, like MMU PTEs, and storing the base image and socket-nodes, thus it needs to be contiguous. hmmm, no. it is the same memory. i.e.: we propagate the current opp through the shared memory so the dsp can read it if it went to sleep, with the proper offset you can read that variable starting from the mempool base address. storing the base image and socket-nodes symbols is also donde in the shared memory but this is done in different sections of the SHM. Right now allocating contiguous memory can only be done with memblock (bootmem), but in the future it could be done with CMA/VCMM. But the cacheability is a separate issue. yes I don't see any problem flushing the SHM area when needed, which probably has performance implications when mmaping/unmapping buffers, at which point you need to flush bigger memory areas anyway, so that's not an issue. well, you would have to flush when loading the base image, or allocating a socket node, but also minor flushes for opp propagation, SHM messages to DSP, chnl params, those are the ones I can quickly think of. Anyway, we will not know for sure until we try... Right? yes we can try, at least we now for sure arm side can be done. Regards, omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] tidspbridge: use a parameter to allocate shared memory
On 10/8/2010 3:18 AM, Felipe Contreras wrote: On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Lunaomar.rami...@ti.com wrote: On 10/7/2010 1:22 PM, Felipe Contreras wrote: ... Note that the shared memory described in the document you share has nothing to do with the SHM pool. AFAIK that memory is used for other things, like MMU PTEs, and storing the base image and socket-nodes, thus it needs to be contiguous. hmmm, no. it is the same memory. i.e.: we propagate the current opp through the shared memory so the dsp can read it if it went to sleep, with the proper offset you can read that variable starting from the mempool base address. The document mentions shared memory for buffer passing, normal memory is used for that, scattered, even user-space memory, not the SHM contiguous area. streaming (meaning dsp stream) buffers are passed through the SHM (check page 9). The regular big buffers are passed through old DMM (page 14) which is exactly as you describe it; but that SHM portion is referring to stream buffers. I don't see any problem flushing the SHM area when needed, which probably has performance implications when mmaping/unmapping buffers, at which point you need to flush bigger memory areas anyway, so that's not an issue. well, you would have to flush when loading the base image, or allocating a socket node, but also minor flushes for opp propagation, SHM messages to DSP, chnl params, those are the ones I can quickly think of. All those happen when you send buffers to the DSP, and when you do that you need to flush the buffer memory area, which is a much heavier operation. Except maybe the opp propagation, but that would require at most one page to be flushed, not a big deal I think, besides, it would be better if that specific area is handled differently than the rest of the SHM, so that we can allocate it with dma_alloc_coherent(). Yes, on top of the regular buffer flush, you need to flush the specific parts of the shared memory that the dsp is going to read, meaning: you send a buffer to the dsp, then send the MBX interrupt, to let it know there is a SHM message, DSP is going to read that SHM message from the SHM memory. You also need to invalidate if the dsp is going to write, so the next time you read there is no mismatch in the data, meaning: DSP sends a SHM message to slot 1, but you already read slot 1 from a previous transaction so contents might be still in cache, so you need to invalidate that memory and read again the new SHM message. Now to know when to read/write you need to have 2 flags per operation, one to know if you have new messages and other to know if you are reading/writing any message (all in SHM), which are there right now for this specific case; but if flushing the SHM, now you will need flags for knowing if the first two have been already flushed... and then 2 for these two... and so on. So in the end a better locking mechanism would be needed for both ARM and DSP which is not based on memory which may or may not have the latest contents (going the cacheable route). As I have been saying, we can try this changes in the ARM tidspbridge because we _freely_ see what is going on, but in the DSP we can't. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC] tidspbridge: use a parameter to allocate shared memory
On 10/8/2010 3:20 AM, Felipe Contreras wrote: On Thu, Oct 7, 2010 at 10:16 PM, Omar Ramirez Lunaomar.rami...@ti.com wrote: On 10/7/2010 1:22 PM, Felipe Contreras wrote: Anyway, we will not know for sure until we try... Right? yes we can try, at least we now for sure arm side can be done. The only thing that changes is the cacheability of the ARM side memory, so of course only the ARM side matters. The DSP side will continue to do what it's doing and would not notice any difference if the memory is flushed, or is non-cacheable. Please find my reply for the previous mail: http://marc.info/?l=linux-omapm=128655845213913w=2 Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] OMAP: control: add functions for DSP boot address/mode control
On 10/11/2010 4:35 PM, Paul Walmsley wrote: On Mon, 11 Oct 2010, Tony Lindgren wrote: Would be nice to get the dspbridge into working shape. Sounds we still need the following: - memblock fixes - this series to fix the control module related issues - platform data for the boards Is that all, or are we also missing something else? A few other things should be done also. 1. Most of the code in drivers/staging/tidspbridge/code/tiomap3430.c in the bridge_brd_monitor(), bridge_brd_start(), and bridge_brd_stop() should be moved into a file in arch/arm/mach-omap2. The DSPBridge driver should call those functions (to reset the DSP, start it, etc.) through platform_data function pointers. Once that happens, patch 3 of the control module-related series would not be needed, since that code would be in arch/arm/mach-omap2 anyway. 2. The direct CM/PRM/RM register access should be removed from that arch/arm/mach-omap2 code. That should be handled directly by the clock/hwmod/whatever code. 3. DSPBridge should be converted to use PM runtime, and the arch/arm/mach-omap2 portion should use omap_device, omap_hwmod, etc. I was working on the 3rd point, but wanted to populate hmods for iommu and reuse the patches for hwmod mailbox too, before sending. Also some stuff needed: - iommu patches[2], this is under discussion, to get iommu + tidspbridge working. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] OMAP: control: add functions for DSP boot address/mode control
On 10/11/2010 5:16 PM, Paul Walmsley wrote: 4. If the DSP uses a peripheral, such as a GPTIMER or a McBSP, DSPBridge needs to reserve that device with the rest of Linux so some other Linux code isn't using it or doesn't try to use it, causing conflicts with DSPBridge. I guess the list that we need to worry about is in _tiomap.h as l4_peripheral_table[]. this is done by using dmtimer fwk, mcbsp are also requested using mcbsp code (however I think functions to enable/disable mcbsp clocks should be added to mcbsp fwk)... There is no code (that I'm aware of) to control wdt3 nor ssi so this is still there. I still have to review the code to find any place were the registers are written directly though. The other peripherals, at the moment, doesn't have a direct interaction with bridge, although they might be interconnected to iva. I guess we can remove some of the mapped peripherals (like dsi, gpio, uart) and add them back on request and by implementing the code to request them on arm side. - omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] OMAP: control: add functions for DSP boot address/mode control
From: Paul Walmsley p...@pwsan.com
Add two functions for OMAP2430/OMAP3 IVA2 DSP boot control. These
registers wound up in the System Control Module. Other kernel code
that wishes to control the DSP's boot process should now use these
functions to do so; subsequent patches implement this in the two
in-tree users of these functions.
Signed-off-by: Paul Walmsley p...@pwsan.com
---
Updated description, removed:
This patch is functionally untested; that is for the DSP/Bridge
programmers to do.
Tested on OMAP3430 and 3630.
arch/arm/mach-omap2/control.c | 51 +
arch/arm/mach-omap2/control.h | 16 ---
arch/arm/plat-omap/include/plat/iva2_dsp.h | 56
3 files changed, 116 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/iva2_dsp.h
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..90fae36 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -209,6 +209,57 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset)
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
+/*
+ * OMAP3 DSP control functions
+ */
+
+/**
+ * omap2430_ctrl_set_dsp_bootaddr - set the DSP's boot address
+ * @pa: DSP boot address (in physical memory)
+ *
+ * Set the DSP's boot address. This is an address in physical memory.
+ * No return value. XXX The TRM claims that this is an index to a
+ * 4kByte page. If so, why is the bitfield 21 bits wide, rather than
+ * 20?
+ */
+void omap2430_ctrl_set_dsp_bootaddr(u32 pa)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, control: %s: not supported on this SoC\n, __func__);
+ return;
+ }
+
+ WARN(pa ~OMAP_CTRL_DSP_BOOTADDR_MASK,
+control: %s: invalid DSP boot address %08x\n, __func__, pa);
+
+ omap_ctrl_writel(pa, OMAP243X_CONTROL_IVA2_BOOTADDR);
+}
+
+/**
+ * omap2430_ctrl_set_dsp_bootmode - set the DSP's boot mode
+ * @mode: DSP boot mode (described below)
+ *
+ * Sets the DSP boot mode - see OMAP3 TRM revision ZH section 7.4.7.4
+ * IVA2.2 Boot Registers. Known values of @mode include 0, to boot
+ * directly to the address supplied by omap2_ctrl_set_dsp_bootaddr();
+ * 1, to boot to the DSP's ROM code and idle, waiting for interrupts;
+ * 2, to boot to the DSP's ROM code and spin in an idle loop; 3, to
+ * copy the user's bootstrap code from the DSP's internal memory and
+ * execute it (XXX how does the DSP know where to copy from?); and 4,
+ * to execute the DSP ROM code's context restore code. No return
+ * value.
+ */
+void omap2430_ctrl_set_dsp_bootmode(u8 mode)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, control: %s: not supported on this SoC\n, __func__);
+ return;
+ }
+
+ omap_ctrl_writel(mode, OMAP243X_CONTROL_IVA2_BOOTMOD);
+}
+
+
#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ac14e0a 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -258,11 +258,6 @@
/* CONTROL_PROG_IO1 bits */
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 20)
-/* CONTROL_IVA2_BOOTMOD bits */
-#define OMAP3_IVA2_BOOTMOD_SHIFT 0
-#define OMAP3_IVA2_BOOTMOD_MASK(0xf 0)
-#define OMAP3_IVA2_BOOTMOD_IDLE(0x1 0)
-
/* CONTROL_PADCONF_X bits */
#define OMAP3_PADCONF_WAKEUPEVENT0 (1 15)
#define OMAP3_PADCONF_WAKEUPENABLE0(1 14)
@@ -280,7 +275,7 @@
#define AM35XX_CPGMAC_FCLK_SHIFT9
#define AM35XX_VPFE_FCLK_SHIFT 10
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
#define AM35XX_CPGMAC_C0_MISC_PULSE_CLRBIT(0)
#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@@ -290,7 +285,7 @@
#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
-/*AM35XX CONTROL_IP_SW_RESET bits*/
+/* AM35XX CONTROL_IP_SW_RESET bits */
#define AM35XX_USBOTGSS_SW_RST BIT(0)
#define AM35XX_CPGMACSS_SW_RST BIT(1)
#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
@@ -330,6 +325,10 @@
#defineFEAT_NEON 0
#defineFEAT_NEON_NONE 1
+/*
+ * DSP booting-related constants
+ */
+#define OMAP_CTRL_DSP_BOOTADDR_MASK0xfc00
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -351,6 +350,9 @@ extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
+extern void omap2430_ctrl_set_dsp_bootaddr(u32 pa);
+extern void omap2430_ctrl_set_dsp_bootmode(u8 mode);
+
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git
[PATCH 2/3] OMAP3: PM: update DSP reset code to use new SCM DSP boot control functions
From: Paul Walmsley p...@pwsan.com
Update the DSP reset code in pm34xx.c to use one of the new SCM DSP
boot control functions, omap2430_ctrl_set_dsp_bootmode().
This reset code should be moved out to a separate function to be
called by the hwmod reset process at some point. Also, 2430
should be initializing the DSP in a similar fashion.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/pm34xx.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8c8f1ac..b90b1fb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -37,6 +37,7 @@
#include plat/prcm.h
#include plat/gpmc.h
#include plat/dma.h
+#include plat/iva2_dsp.h
#include asm/tlbflush.h
@@ -614,6 +615,7 @@ static struct platform_suspend_ops omap_pm_ops = {
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*
+ * XXX This should be handled by the hwmod.
**/
static void __init omap3_iva_idle(void)
{
@@ -635,9 +637,7 @@ static void __init omap3_iva_idle(void)
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
OMAP3430_IVA2_MOD, CM_FCLKEN);
- /* Set IVA2 boot mode to 'idle' */
- omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
-OMAP343X_CONTROL_IVA2_BOOTMOD);
+ omap2430_ctrl_set_dsp_bootmode(OMAP_IVA2_DSP_BOOTMODE_IDLE);
/* Un-reset IVA2 */
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
--
1.7.1
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[PATCH 3/3] tidspbridge: convert OMAP3430 adaptation layer to use new SCM DSP boot control fns
From: Paul Walmsley p...@pwsan.com
DSPBridge currently tries to __raw_writel() to the System Control
Module to control the DSP boot process. This is a layering violation;
this is SoC-specific code, and belongs in a file in
arch/arm/mach-omap2/*. None of those CM and PRM register accesses
through struct platform_data belong under drivers/. (Nor would they
belong in DSP platform init code in arch/arm/mach-omap2/* - such code
must use the clock, clockdomain, powerdomain, omap_device, and
omap_hwmod layers that are provided for this purpose.)
The immediate problem, however, is that after commit
346a5c890a55495c718394b74214be1de9303cf6, this code can no longer compile.
So to fix this immediate problem, convert the DSP boot control code to
use platform_data function pointers.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: fernando.l...@ti.com
---
Updated description by removing last paragraph and adding missing lines:
The DSPBridge-on-OMAP3 people also need to implement a file in
arch/arm/mach-omap2/ to populate the platform_data function pointers.
Such a file does not yet exist in the mainline tree, so it's unlikely
that DSPBridge is usable in the mainline until this is done.
arch/arm/mach-omap2/dsp.c |4
arch/arm/plat-omap/include/plat/dsp.h |4
drivers/staging/tidspbridge/core/tiomap3430.c | 13 ++---
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 6feeeae..307f67a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -12,6 +12,7 @@
*/
#include linux/platform_device.h
+#include control.h
#include prm.h
#include cm.h
#ifdef CONFIG_BRIDGE_DVFS
@@ -31,6 +32,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata
__initdata = {
.cpu_set_freq = omap_pm_cpu_set_freq,
.cpu_get_freq = omap_pm_cpu_get_freq,
#endif
+ .set_dsp_bootaddr = omap2430_ctrl_set_dsp_bootaddr,
+ .set_dsp_bootmode = omap2430_ctrl_set_dsp_bootmode,
+
.dsp_prm_read = prm_read_mod_reg,
.dsp_prm_write = prm_write_mod_reg,
.dsp_prm_rmw_bits = prm_rmw_mod_reg_bits,
diff --git a/arch/arm/plat-omap/include/plat/dsp.h
b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b3..34e2bd8 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -10,7 +10,11 @@ struct omap_dsp_platform_data {
unsigned long (*cpu_get_freq) (void);
unsigned long mpu_speed[6];
+ void (*set_dsp_bootaddr)(u32 pa);
+ void (*set_dsp_bootmode)(u8 mode);
+
/* functions to write and read PRCM registers */
+ /* XXX None of this should be here */
void (*dsp_prm_write)(u32, s16 , u16);
u32 (*dsp_prm_read)(s16 , u16);
u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c
b/drivers/staging/tidspbridge/core/tiomap3430.c
index f22bc12..b91d911 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -23,7 +23,7 @@
#include dspbridge/host_os.h
#include linux/mm.h
#include linux/mmzone.h
-#include plat/control.h
+#include plat/iva2_dsp.h
/* --- DSP/BIOS Bridge */
#include dspbridge/dbdefs.h
@@ -293,6 +293,7 @@ static int bridge_brd_start(struct bridge_dev_context
*dev_ctxt,
u32 clk_cmd;
struct io_mgr *hio_mgr;
u32 ul_load_monitor_timer;
+ u8 bootmode;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev-dev.platform_data;
@@ -334,15 +335,13 @@ static int bridge_brd_start(struct bridge_dev_context
*dev_ctxt,
OMAP3430_RST1_IVA2_MASK,
OMAP3430_IVA2_MOD,
OMAP2_RM_RSTCTRL);
/* Mask address with 1K for compatibility */
- __raw_writel(dsp_addr OMAP3_IVA2_BOOTADDR_MASK,
- OMAP343X_CTRL_REGADDR(
- OMAP343X_CONTROL_IVA2_BOOTADDR));
+ dsp_addr = OMAP3_IVA2_BOOTADDR_MASK;
+ (*pdata-set_dsp_bootaddr)(dsp_addr);
/*
* Set bootmode to self loop if dsp_debug flag is true
*/
- __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
- OMAP343X_CTRL_REGADDR(
- OMAP343X_CONTROL_IVA2_BOOTMOD));
+ bootmode = dsp_debug ? OMAP_IVA2_DSP_BOOTMODE_IDLE : 0;
+ (*pdata-set_dsp_bootmode)(bootmode);
}
}
--
1.7.1
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[PATCH] omap: mailbox: remove unreachable return
Remove unreachable return statement. Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/mailbox.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index a0af532..7dc9fa6 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -437,8 +437,6 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) return ret; } return 0; - - return ret; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] tidspbridge: convert OMAP3430 adaptation layer to use new SCM DSP boot control fns
On Tue, Oct 26, 2010 at 12:43 AM, Paul Walmsley p...@pwsan.com wrote: arch/arm/mach-omap2/dsp.c | 4 arch/arm/plat-omap/include/plat/dsp.h | 4 drivers/staging/tidspbridge/core/tiomap3430.c | 13 ++--- Could you please split the tiomap3430.c change into a separate patch? That should go in via the staging tree once this series is accepted. No problem. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/8] staging: tidspbridge - misc fixes
On Tue, Oct 26, 2010 at 9:43 AM, Felipe Contreras felipe.contre...@nokia.com wrote: gre...@suse.de wrote: On Mon, Oct 25, 2010 at 07:51:38PM -0500, Fernando Guzman Lugo wrote: This set of patches fix some issues found in lastest tree. Fernando Guzman Lugo (8): staging: tidspbridge - remove req_addr from proc_map staging: tidspbridge - add kconfig parameter for DMM size staging: tidspbridge - change mmufault tasklet to a workqueue staging: tidspbridge - fix timeout in dsp_gpt_wait_overflow staging: tidspbridge - use GTP7 for DSP stack dump staging: tidspbridge - remove disabling twl when printing DSP stack staging: tidspbridge - fix some issues after iommu patches staging: tidspbridge - make sync_wait_on_event interruptible Are any of these really applicable for .37 after .37-rc1? Or can they wait for .38? As of right now the dspbridge doesn't work, and there's a mess of dependencies to get it working. Just to note that there will be one more dependency for SCM changes[1] that will fix compilation, as these need to climb from linux-omap (if accepted) before applying tidspbridge chunks. Regards, Omar --- [1] http://marc.info/?l=linux-omapm=128779652429922w=2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/4] staging: tidspbridge: use new SCM DSP boot control fns
From: Paul Walmsley p...@pwsan.com Use the new functions from SCM layer instead of handling registers directly with __raw_writel, as explained in: http://marc.info/?l=linux-omapm=128779652429922w=2 Signed-off-by: Paul Walmsley p...@pwsan.com Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- drivers/staging/tidspbridge/core/tiomap3430.c | 13 ++--- 1 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index f22bc12..b91d911 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -23,7 +23,7 @@ #include dspbridge/host_os.h #include linux/mm.h #include linux/mmzone.h -#include plat/control.h +#include plat/iva2_dsp.h /* --- DSP/BIOS Bridge */ #include dspbridge/dbdefs.h @@ -293,6 +293,7 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, u32 clk_cmd; struct io_mgr *hio_mgr; u32 ul_load_monitor_timer; + u8 bootmode; struct omap_dsp_platform_data *pdata = omap_dspbridge_dev-dev.platform_data; @@ -334,15 +335,13 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Mask address with 1K for compatibility */ - __raw_writel(dsp_addr OMAP3_IVA2_BOOTADDR_MASK, - OMAP343X_CTRL_REGADDR( - OMAP343X_CONTROL_IVA2_BOOTADDR)); + dsp_addr = OMAP3_IVA2_BOOTADDR_MASK; + (*pdata-set_dsp_bootaddr)(dsp_addr); /* * Set bootmode to self loop if dsp_debug flag is true */ - __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0, - OMAP343X_CTRL_REGADDR( - OMAP343X_CONTROL_IVA2_BOOTMOD)); + bootmode = dsp_debug ? OMAP_IVA2_DSP_BOOTMODE_IDLE : 0; + (*pdata-set_dsp_bootmode)(bootmode); } } -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/4] OMAP3: PM: update DSP reset code to use new SCM DSP boot control functions
From: Paul Walmsley p...@pwsan.com
Update the DSP reset code in pm34xx.c to use one of the new SCM DSP
boot control functions, omap2430_ctrl_set_dsp_bootmode().
This reset code should be moved out to a separate function to be
called by the hwmod reset process at some point. Also, 2430
should be initializing the DSP in a similar fashion.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
arch/arm/mach-omap2/pm34xx.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8c8f1ac..b90b1fb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -37,6 +37,7 @@
#include plat/prcm.h
#include plat/gpmc.h
#include plat/dma.h
+#include plat/iva2_dsp.h
#include asm/tlbflush.h
@@ -614,6 +615,7 @@ static struct platform_suspend_ops omap_pm_ops = {
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*
+ * XXX This should be handled by the hwmod.
**/
static void __init omap3_iva_idle(void)
{
@@ -635,9 +637,7 @@ static void __init omap3_iva_idle(void)
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
OMAP3430_IVA2_MOD, CM_FCLKEN);
- /* Set IVA2 boot mode to 'idle' */
- omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
-OMAP343X_CONTROL_IVA2_BOOTMOD);
+ omap2430_ctrl_set_dsp_bootmode(OMAP_IVA2_DSP_BOOTMODE_IDLE);
/* Un-reset IVA2 */
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
--
1.7.1
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[PATCH v3 3/4] OMAP: dsp: convert OMAP3430 adaptation layer to use new SCM DSP boot control fns
From: Paul Walmsley p...@pwsan.com
DSPBridge currently tries to __raw_writel() to the System Control
Module to control the DSP boot process. This is a layering violation;
this is SoC-specific code, and belongs in a file in
arch/arm/mach-omap2/*. None of those CM and PRM register accesses
through struct platform_data belong under drivers/. (Nor would they
belong in DSP platform init code in arch/arm/mach-omap2/* - such code
must use the clock, clockdomain, powerdomain, omap_device, and
omap_hwmod layers that are provided for this purpose.)
The immediate problem, however, is that after commit
346a5c890a55495c718394b74214be1de9303cf6, this code can no longer compile.
So to fix this immediate problem, convert the DSP boot control code to
use platform_data function pointers.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: fernando.l...@ti.com
---
arch/arm/mach-omap2/dsp.c |4
arch/arm/plat-omap/include/plat/dsp.h |4
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 6feeeae..307f67a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -12,6 +12,7 @@
*/
#include linux/platform_device.h
+#include control.h
#include prm.h
#include cm.h
#ifdef CONFIG_BRIDGE_DVFS
@@ -31,6 +32,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata
__initdata = {
.cpu_set_freq = omap_pm_cpu_set_freq,
.cpu_get_freq = omap_pm_cpu_get_freq,
#endif
+ .set_dsp_bootaddr = omap2430_ctrl_set_dsp_bootaddr,
+ .set_dsp_bootmode = omap2430_ctrl_set_dsp_bootmode,
+
.dsp_prm_read = prm_read_mod_reg,
.dsp_prm_write = prm_write_mod_reg,
.dsp_prm_rmw_bits = prm_rmw_mod_reg_bits,
diff --git a/arch/arm/plat-omap/include/plat/dsp.h
b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b3..34e2bd8 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -10,7 +10,11 @@ struct omap_dsp_platform_data {
unsigned long (*cpu_get_freq) (void);
unsigned long mpu_speed[6];
+ void (*set_dsp_bootaddr)(u32 pa);
+ void (*set_dsp_bootmode)(u8 mode);
+
/* functions to write and read PRCM registers */
+ /* XXX None of this should be here */
void (*dsp_prm_write)(u32, s16 , u16);
u32 (*dsp_prm_read)(s16 , u16);
u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
--
1.7.1
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[PATCH v2 0/4] tidspbridge: SCM layer violation fixes
This is the patch series shared by Paul, for a short term fix to a compile break due SCM layer layer violations from tidspbridge driver, where the latter is used to write directly into registers and use SCM layer macros, among other layer bypassing. patch: staging: tidspbridge: use new SCM DSP boot control fns was split from its original version, it is meant to be on hold until the rest of the series gets upstreamed and can be found in the staging tree (unless best advice is given). Paul Walmsley (4): OMAP: control: add functions for DSP boot address/mode control OMAP3: PM: update DSP reset code to use new SCM DSP boot control functions OMAP: dsp: convert OMAP3430 adaptation layer to use new SCM DSP boot control fns staging: tidspbridge: use new SCM DSP boot control fns arch/arm/mach-omap2/control.c | 51 ++ arch/arm/mach-omap2/control.h | 16 --- arch/arm/mach-omap2/dsp.c |4 ++ arch/arm/mach-omap2/pm34xx.c |6 +- arch/arm/plat-omap/include/plat/dsp.h |4 ++ arch/arm/plat-omap/include/plat/iva2_dsp.h| 56 + drivers/staging/tidspbridge/core/tiomap3430.c | 13 +++--- 7 files changed, 133 insertions(+), 17 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/iva2_dsp.h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/4] OMAP: control: add functions for DSP boot address/mode control
From: Paul Walmsley p...@pwsan.com
Add two functions for OMAP2430/OMAP3 IVA2 DSP boot control. These
registers wound up in the System Control Module. Other kernel code
that wishes to control the DSP's boot process should now use these
functions to do so; subsequent patches implement this in the two
in-tree users of these functions.
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/control.c | 51 +
arch/arm/mach-omap2/control.h | 16 ---
arch/arm/plat-omap/include/plat/iva2_dsp.h | 56
3 files changed, 116 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/iva2_dsp.h
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..90fae36 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -209,6 +209,57 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset)
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
+/*
+ * OMAP3 DSP control functions
+ */
+
+/**
+ * omap2430_ctrl_set_dsp_bootaddr - set the DSP's boot address
+ * @pa: DSP boot address (in physical memory)
+ *
+ * Set the DSP's boot address. This is an address in physical memory.
+ * No return value. XXX The TRM claims that this is an index to a
+ * 4kByte page. If so, why is the bitfield 21 bits wide, rather than
+ * 20?
+ */
+void omap2430_ctrl_set_dsp_bootaddr(u32 pa)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, control: %s: not supported on this SoC\n, __func__);
+ return;
+ }
+
+ WARN(pa ~OMAP_CTRL_DSP_BOOTADDR_MASK,
+control: %s: invalid DSP boot address %08x\n, __func__, pa);
+
+ omap_ctrl_writel(pa, OMAP243X_CONTROL_IVA2_BOOTADDR);
+}
+
+/**
+ * omap2430_ctrl_set_dsp_bootmode - set the DSP's boot mode
+ * @mode: DSP boot mode (described below)
+ *
+ * Sets the DSP boot mode - see OMAP3 TRM revision ZH section 7.4.7.4
+ * IVA2.2 Boot Registers. Known values of @mode include 0, to boot
+ * directly to the address supplied by omap2_ctrl_set_dsp_bootaddr();
+ * 1, to boot to the DSP's ROM code and idle, waiting for interrupts;
+ * 2, to boot to the DSP's ROM code and spin in an idle loop; 3, to
+ * copy the user's bootstrap code from the DSP's internal memory and
+ * execute it (XXX how does the DSP know where to copy from?); and 4,
+ * to execute the DSP ROM code's context restore code. No return
+ * value.
+ */
+void omap2430_ctrl_set_dsp_bootmode(u8 mode)
+{
+ if (!(cpu_is_omap2430() || cpu_is_omap34xx())) {
+ WARN(1, control: %s: not supported on this SoC\n, __func__);
+ return;
+ }
+
+ omap_ctrl_writel(mode, OMAP243X_CONTROL_IVA2_BOOTMOD);
+}
+
+
#if defined(CONFIG_ARCH_OMAP3) defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ac14e0a 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -258,11 +258,6 @@
/* CONTROL_PROG_IO1 bits */
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 20)
-/* CONTROL_IVA2_BOOTMOD bits */
-#define OMAP3_IVA2_BOOTMOD_SHIFT 0
-#define OMAP3_IVA2_BOOTMOD_MASK(0xf 0)
-#define OMAP3_IVA2_BOOTMOD_IDLE(0x1 0)
-
/* CONTROL_PADCONF_X bits */
#define OMAP3_PADCONF_WAKEUPEVENT0 (1 15)
#define OMAP3_PADCONF_WAKEUPENABLE0(1 14)
@@ -280,7 +275,7 @@
#define AM35XX_CPGMAC_FCLK_SHIFT9
#define AM35XX_VPFE_FCLK_SHIFT 10
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
#define AM35XX_CPGMAC_C0_MISC_PULSE_CLRBIT(0)
#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@@ -290,7 +285,7 @@
#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
-/*AM35XX CONTROL_IP_SW_RESET bits*/
+/* AM35XX CONTROL_IP_SW_RESET bits */
#define AM35XX_USBOTGSS_SW_RST BIT(0)
#define AM35XX_CPGMACSS_SW_RST BIT(1)
#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
@@ -330,6 +325,10 @@
#defineFEAT_NEON 0
#defineFEAT_NEON_NONE 1
+/*
+ * DSP booting-related constants
+ */
+#define OMAP_CTRL_DSP_BOOTADDR_MASK0xfc00
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -351,6 +350,9 @@ extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
+extern void omap2430_ctrl_set_dsp_bootaddr(u32 pa);
+extern void omap2430_ctrl_set_dsp_bootmode(u8 mode);
+
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/plat-omap/include/plat/iva2_dsp.h
b/arch/arm/plat-omap/include/plat/iva2_dsp.h
new file mode 100644
index 000..495c6a9
--- /dev/null
+++
Re: [PATCH v2 0/4] tidspbridge: SCM layer violation fixes
On Tue, Oct 26, 2010 at 12:13 PM, Felipe Contreras felipe.contre...@gmail.com wrote: arch/arm/plat-omap/include/plat/iva2_dsp.h | 56 + Why not use the already existing dsp.h? Good point, I guess when the patch was made dsp.h didn't exist, but since the user of those defines is pm34xx.c too, including it in dsp.h would include the declaration of everything inside dsp.h; however I don't see that as an impediment for dma.h or gpmc.h to be included. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] omap: mailbox: initial hwmod support for omap3
From: Felipe Contreras felipe.contre...@gmail.com
HWMOD support for omap3.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 100 ---
arch/arm/mach-omap2/mailbox.c |1 +
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 54 +++
3 files changed, 70 insertions(+), 85 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index eaf3799..d977572 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -141,95 +141,25 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = iva,
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end= OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = mbox,
- },
-};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz0
-#endif
-
-static struct platform_device mbox_device = {
- .name = omap-mailbox,
- .id = -1,
-};
-
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err(%s: platform not supported\n, __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup(mailbox);
+ if (!oh) {
+ pr_err(%s: unable to find hwmod\n, __func__);
+ return;
+ }
+
+ od = omap_device_build(omap-mailbox, -1, oh,
+ NULL, 0,
+ NULL, 0,
+ 0);
+ if (!od) {
+ pr_err(%s: could not build device\n, __func__);
return;
}
- platform_device_register(mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 40ddeca..1ddb82d 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -15,6 +15,7 @@
#include linux/platform_device.h
#include linux/io.h
#include plat/mailbox.h
+#include plat/omap_hwmod.h
#include mach/irqs.h
#define MAILBOX_REVISION 0x000
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ed6bf4a..9e9e843 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -45,6 +45,7 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
static struct
[PATCH 4/5] omap: mailbox: fix detection for previously supported chips
Fix the mailbox detection for OMAP3630 and 2430, also minor
cleanup on conditional ifdef's that could affect it.
Given that 2430 has an iva too include it, as the same steps
for omap3 apply.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 61f2149..b8fd120 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -277,7 +277,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
/* FIXME: the following structs should be filled automatically by the user id
*/
-#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
@@ -302,7 +302,7 @@ struct omap_mbox mbox_dsp_info = {
};
#endif
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { mbox_dsp_info, NULL };
#endif
@@ -390,15 +390,19 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3430)
- else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+ else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
}
#endif
-#if defined(CONFIG_ARCH_OMAP2420)
- else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+ list[0]-irq = platform_get_irq_byname(pdev, dsp);
+ } else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
--
1.7.1
--
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[PATCH 3/5] omap: mailbox: add omap_device latency information
From: Felipe Contreras felipe.contre...@gmail.com
So that we can enable the main clock.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 19 +--
arch/arm/mach-omap2/mailbox.c | 21 +
arch/arm/plat-omap/include/plat/mailbox.h |6 ++
3 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d977572..337fd7a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -29,6 +29,7 @@
#include plat/dma.h
#include plat/omap_hwmod.h
#include plat/omap_device.h
+#include plat/mailbox.h
#include mux.h
#include control.h
@@ -141,10 +142,20 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_clocks,
+ .activate_lat = 5, /* FIXME random value */
+ .deactivate_func = omap_device_enable_clocks,
+ .deactivate_lat = 5, /* FIXME random value */
+ },
+};
+
static inline void omap_init_mbox(void)
{
struct omap_hwmod *oh;
struct omap_device *od;
+ struct omap_mbox_platform_data pdata;
oh = omap_hwmod_lookup(mailbox);
if (!oh) {
@@ -152,10 +163,14 @@ static inline void omap_init_mbox(void)
return;
}
+ pdata.device_enable = omap_device_enable;
+ pdata.device_disable = omap_device_idle;
+
od = omap_device_build(omap-mailbox, -1, oh,
- NULL, 0,
- NULL, 0,
+ pdata, sizeof(pdata),
+ mbox_latencies, ARRAY_SIZE(mbox_latencies),
0);
+
if (!od) {
pr_err(%s: could not build device\n, __func__);
return;
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 1ddb82d..61f2149 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -53,6 +53,7 @@
#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
static void __iomem *mbox_base;
+static struct platform_device *mbox_pdev;
struct omap_mbox2_fifo {
unsigned long msg;
@@ -71,8 +72,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -91,14 +90,10 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
{
u32 l;
unsigned long timeout;
+ struct omap_mbox_platform_data *pdata = mbox_pdev-dev.platform_data;
- mbox_ick_handle = clk_get(NULL, mailboxes_ick);
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR Could not get mailboxes_ick: %ld\n,
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
+ if (pdata-device_enable)
+ pdata-device_enable(mbox_pdev);
if (cpu_is_omap44xx()) {
mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
@@ -144,9 +139,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ struct omap_mbox_platform_data *pdata = mbox_pdev-dev.platform_data;
+ if (pdata-device_disable)
+ pdata-device_disable(mbox_pdev);
}
/* Mailbox FIFO handle functions */
@@ -428,6 +423,8 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (!mbox_base)
return -ENOMEM;
+ mbox_pdev = pdev;
+
ret = omap_mbox_register(pdev-dev, list);
if (ret) {
iounmap(mbox_base);
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h
b/arch/arm/plat-omap/include/plat/mailbox.h
index 9976565..59443b1 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -11,6 +11,7 @@
typedef u32 mbox_msg_t;
struct omap_mbox;
+struct platform_device;
typedef int __bitwise omap_mbox_irq_t;
#define IRQ_TX ((__force omap_mbox_irq_t) 1)
@@ -59,6 +60,11 @@ struct omap_mbox {
void*priv;
};
+struct omap_mbox_platform_data {
+ int (*device_enable)(struct platform_device *pdev);
+ int (*device_disable)(struct platform_device *pdev);
+};
+
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
void omap_mbox_init_seq(struct omap_mbox *);
--
1.7.1
--
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[PATCH 2/5] omap: mailbox: initial hwmod support for omap2
HWMOD support for omap2430 and 2420.
Compiled tested only.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 55
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 54 +++
2 files changed, 109 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a1a3dd6..e417fb4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -81,6 +81,7 @@ static struct omap_hwmod omap2420_uart2_hwmod;
static struct omap_hwmod omap2420_uart3_hwmod;
static struct omap_hwmod omap2420_i2c1_hwmod;
static struct omap_hwmod omap2420_i2c2_hwmod;
+static struct omap_hwmod omap2420_mailbox_hwmod;
/* L4_CORE - L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -557,6 +558,59 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.flags = HWMOD_16BIT_REG,
};
+/* Mailbox */
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = mailbox,
+};
+
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = dsp, .irq = INT_24XX_MAIL_U0_MPU },
+ { .name = iva, .irq = INT_24XX_MAIL_U3_MPU },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP24XX_MAILBOX_BASE,
+ .pa_end = OMAP24XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* L4_CORE - Mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_mailbox_hwmod,
+ .addr = omap2420_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap2420_mailbox_hwmod_class,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .main_clk = mailboxes_ick,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_l3_main_hwmod,
omap2420_l4_core_hwmod,
@@ -569,6 +623,7 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_uart3_hwmod,
omap2420_i2c1_hwmod,
omap2420_i2c2_hwmod,
+ omap2420_mailbox_hwmod,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 7cf0d3a..1a7d2d9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -81,6 +81,7 @@ static struct omap_hwmod omap2430_uart2_hwmod;
static struct omap_hwmod omap2430_uart3_hwmod;
static struct omap_hwmod omap2430_i2c1_hwmod;
static struct omap_hwmod omap2430_i2c2_hwmod;
+static struct omap_hwmod omap2430_mailbox_hwmod;
/* I2C IP block address space length (in bytes) */
#define OMAP2_I2C_AS_LEN 128
@@ -569,6 +570,58 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
+/* Mailbox */
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = mailbox,
+};
+
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .name = dsp, .irq = INT_24XX_MAIL_U0_MPU },
+};
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP24XX_MAILBOX_BASE,
+ .pa_end = OMAP24XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* L4_CORE - Mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = omap2430_l4_core_hwmod,
+ .slave = omap2430_mailbox_hwmod,
+ .addr = omap2430_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+ omap2430_l4_core__mailbox,
+};
+
+static struct
[PATCH 5/5] omap: mailbox: remove unreachable return
Remove unreachable return statement. Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/mailbox.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index b8fd120..2dd0e07 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -435,8 +435,6 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) return ret; } return 0; - - return ret; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] omap: mailbox: initial hwmod support for omap3
On Wed, Oct 27, 2010 at 12:07 AM, Varadarajan, Charulatha ch...@ti.com wrote: HWMOD support for omap3. Use hwmod. ok ... This patch series breaks OMAP4 support. indeed, I'll try to exercise a sanity use case with omap4 and its hwmod data OMAP2 support is broken with this patch and the same is fixed in the next patch. Hence patch 2 should be ordered before patch 1. Agree --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -15,6 +15,7 @@ #include linux/platform_device.h #include linux/io.h #include plat/mailbox.h +#include plat/omap_hwmod.h Is this required? I do not see this file using any hwmod info. might have been kept with the rebase, I'll check again Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/7] omap:mailbox-add notification support for multiple readers
Hi,
On 10/14/2010 9:13 PM, Hari Kanigeri wrote:
@@ -252,41 +253,39 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
...
+ if (!mbox-use_count++) {
+ ret = request_irq(mbox-irq, mbox_interrupt, IRQF_SHARED,
+ mbox-name, mbox);
...
@@ -296,29 +295,36 @@ fail_alloc_txq:
...
static void omap_mbox_fini(struct omap_mbox *mbox)
{
+ if (!--mbox-use_count) {
+ tasklet_kill(mbox-txq-tasklet);
+ flush_work(mbox-rxq-work);
+ mbox_queue_free(mbox-txq);
+ mbox_queue_free(mbox-rxq);
+ }
+
+ if (likely(mbox-ops-shutdown)) {
+ if (!--mbox_configured) {
+ free_irq(mbox-irq, mbox);
Above hunks will create an imbalance of free_irq, as request_irq can be
called per registered mailbox and free_irq is only done for the last
caller releasing the mailbox handle.
e.g.: mbox-1, mbox-N will request a shared irq on the same interrupt
line, but only the last caller of omap_mbox_put will free its irq,
leaving the other one there.
This can be fixed if the free is moved to be executed within the
following block:
if (!--mbox-use_count) {
...
free_irq(mbox-irq, mbox);
}
Regards,
Omar
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Re: [PATCH 5/7] omap:mailbox-resolve multiple receiver problem
On 10/14/2010 9:13 PM, Kanigeri, Hari wrote: OMAP4 shares one interrupt line for all the mailbox instances. The ISR is handling only the mailbox instance that was registered last. This shouldn't be needed, request_irq is being called with IRQF_SHARED flag and different device ids, so if a message arrives it fires an interrupt handler for each of the callers to request_irq and since the device id is actually a pointer to a mbox struct, the different users can be detected and signaled without looping through the mboxes list. Also using mboxes list, will try to check for all registered mailboxes during probe, which might not be the same as the actual users (the ones that have called omap_mbox_get) and then unnecesary check their irq statuses if an interrupt arrives. I think this patch can be dropped. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/4] tidspbridge: SCM layer violation fixes
On 10/26/2010 11:15 AM, Ramirez Luna, Omar wrote: This is the patch series shared by Paul, for a short term fix to a compile break due SCM layer layer violations from tidspbridge driver, where the latter is used to write directly into registers and use SCM layer macros, among other layer bypassing. patch: staging: tidspbridge: use new SCM DSP boot control fns was split from its original version, it is meant to be on hold until the rest of the series gets upstreamed and can be found in the staging tree (unless best advice is given). Paul Walmsley (4): OMAP: control: add functions for DSP boot address/mode control OMAP3: PM: update DSP reset code to use new SCM DSP boot control functions OMAP: dsp: convert OMAP3430 adaptation layer to use new SCM DSP boot control fns staging: tidspbridge: use new SCM DSP boot control fns arch/arm/mach-omap2/control.c | 51 ++ arch/arm/mach-omap2/control.h | 16 --- arch/arm/mach-omap2/dsp.c |4 ++ arch/arm/mach-omap2/pm34xx.c |6 +- arch/arm/plat-omap/include/plat/dsp.h |4 ++ arch/arm/plat-omap/include/plat/iva2_dsp.h| 56 + drivers/staging/tidspbridge/core/tiomap3430.c | 13 +++--- 7 files changed, 133 insertions(+), 17 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/iva2_dsp.h This series was tested on OMAP 3430 (zoom2) and 3630 (zoom3) boards. Regards, Omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 7/7] omap: mailbox: remove unreachable return
Remove unreachable return statement. Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/mailbox.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 5e9ea0f..335eb2b 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -434,8 +434,6 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) return ret; } return 0; - - return ret; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/7] omap: mailbox: add omap_device latency information
From: Felipe Contreras felipe.contre...@gmail.com
So that we can enable the main clock.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 18 --
arch/arm/mach-omap2/mailbox.c | 21 +
arch/arm/plat-omap/include/plat/mailbox.h |6 ++
3 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d977572..dafc23a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -29,6 +29,7 @@
#include plat/dma.h
#include plat/omap_hwmod.h
#include plat/omap_device.h
+#include plat/mailbox.h
#include mux.h
#include control.h
@@ -141,10 +142,19 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_clocks,
+ .deactivate_func = omap_device_enable_clocks,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+};
+
static inline void omap_init_mbox(void)
{
struct omap_hwmod *oh;
struct omap_device *od;
+ struct omap_mbox_platform_data pdata;
oh = omap_hwmod_lookup(mailbox);
if (!oh) {
@@ -152,10 +162,14 @@ static inline void omap_init_mbox(void)
return;
}
+ pdata.device_enable = omap_device_enable;
+ pdata.device_disable = omap_device_idle;
+
od = omap_device_build(omap-mailbox, -1, oh,
- NULL, 0,
- NULL, 0,
+ pdata, sizeof(pdata),
+ mbox_latencies, ARRAY_SIZE(mbox_latencies),
0);
+
if (!od) {
pr_err(%s: could not build device\n, __func__);
return;
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 40ddeca..bf598a3 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -52,6 +52,7 @@
#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
static void __iomem *mbox_base;
+static struct platform_device *mbox_pdev;
struct omap_mbox2_fifo {
unsigned long msg;
@@ -70,8 +71,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -90,14 +89,10 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
{
u32 l;
unsigned long timeout;
+ struct omap_mbox_platform_data *pdata = mbox_pdev-dev.platform_data;
- mbox_ick_handle = clk_get(NULL, mailboxes_ick);
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR Could not get mailboxes_ick: %ld\n,
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
+ if (pdata-device_enable)
+ pdata-device_enable(mbox_pdev);
if (cpu_is_omap44xx()) {
mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
@@ -143,9 +138,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ struct omap_mbox_platform_data *pdata = mbox_pdev-dev.platform_data;
+ if (pdata-device_disable)
+ pdata-device_disable(mbox_pdev);
}
/* Mailbox FIFO handle functions */
@@ -427,6 +422,8 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (!mbox_base)
return -ENOMEM;
+ mbox_pdev = pdev;
+
ret = omap_mbox_register(pdev-dev, list);
if (ret) {
iounmap(mbox_base);
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h
b/arch/arm/plat-omap/include/plat/mailbox.h
index 9976565..59443b1 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -11,6 +11,7 @@
typedef u32 mbox_msg_t;
struct omap_mbox;
+struct platform_device;
typedef int __bitwise omap_mbox_irq_t;
#define IRQ_TX ((__force omap_mbox_irq_t) 1)
@@ -59,6 +60,11 @@ struct omap_mbox {
void*priv;
};
+struct omap_mbox_platform_data {
+ int (*device_enable)(struct platform_device *pdev);
+ int (*device_disable)(struct platform_device *pdev);
+};
+
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
void omap_mbox_init_seq(struct omap_mbox *);
--
1.7.1
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[PATCH v2 6/7] omap: mailbox: fix detection for previously supported chips
Fix the mailbox detection for OMAP3630 and 2430, also minor
cleanup on conditional ifdef's that could affect it.
Given that 2430 has an iva too include it, as the same steps
for omap3 apply.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index bf598a3..5e9ea0f 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -276,7 +276,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
/* FIXME: the following structs should be filled automatically by the user id
*/
-#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
@@ -301,7 +301,7 @@ struct omap_mbox mbox_dsp_info = {
};
#endif
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { mbox_dsp_info, NULL };
#endif
@@ -389,15 +389,19 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (false)
;
-#if defined(CONFIG_ARCH_OMAP3430)
- else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+ else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
}
#endif
-#if defined(CONFIG_ARCH_OMAP2420)
- else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+ list[0]-irq = platform_get_irq_byname(pdev, dsp);
+ } else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]-irq = platform_get_irq_byname(pdev, dsp);
--
1.7.1
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[PATCH v2 0/7] omap: mailbox: hwmod support and dependent cleanup patches
hwmod support for omap2 and omap3 chips, plus cleanups. Tested on 3430 and 3630 ** v2 ** - Added omap4 hwmod support. - Moved mailbox_ick from hwmod to hwmod_if (omap 2/3) - Declared sysc classes for omap 2/3 ** v1 ** 1. omap: mailbox: initial hwmod support for omap3 Changes were made to: - Rebase to latest code. - Detect the hwmod by filling prcm union for omap2, without this it was unable to build the hwmod at runtime. - Replace magic number for defines. - Use ioremap again instead of relying on the one made by hwmod, as noted in http://patchwork.kernel.org/patch/101661/ 2. omap: mailbox: initial hwmod support for omap2 Was only compiled tested!! Unfortunately I don't have the HW for it. 4. omap: mailbox: fix detection for previously supported chips Original patch was using features framework, but when compiled as a module it was breaking, this patch uses cpu_is_omap34xx macro instead. This is meant as a short term solution until proper cleanup is done, as suggested in: http://marc.info/?l=linux-arm-kernelm=128534253231481w=2 Benoit Cousson (1): OMAP4: hwmod data: add mailbox data Felipe Contreras (3): OMAP3: hwmod data: add mailbox data omap: mailbox: initial hwmod support omap: mailbox: add omap_device latency information Omar Ramirez Luna (3): OMAP2: hwmod data: add mailbox data omap: mailbox: fix detection for previously supported chips omap: mailbox: remove unreachable return arch/arm/mach-omap2/devices.c | 104 +++- arch/arm/mach-omap2/mailbox.c | 39 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 67 ++ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 66 ++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 66 ++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 63 + arch/arm/plat-omap/include/plat/mailbox.h |6 ++ 7 files changed, 311 insertions(+), 100 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/7] OMAP2: hwmod data: add mailbox data
hwmod data for omap2430 and 2420.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 67
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 66 +++
2 files changed, 133 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a1a3dd6..76ad991 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -557,6 +557,72 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.flags = HWMOD_16BIT_REG,
};
+/* mailbox */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2420_mailbox_sysc,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod;
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP24XX_MAILBOX_BASE,
+ .pa_end = OMAP24XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_mailbox_hwmod,
+ .addr = omap2420_mailbox_addrs,
+ .clk= mailboxes_ick,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = dsp, .irq = INT_24XX_MAIL_U0_MPU, },
+ { .name = iva, .irq = INT_24XX_MAIL_U3_MPU, },
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap2420_mailbox_hwmod_class,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_l3_main_hwmod,
omap2420_l4_core_hwmod,
@@ -569,6 +635,7 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_uart3_hwmod,
omap2420_i2c1_hwmod,
omap2420_i2c2_hwmod,
+ omap2420_mailbox_hwmod,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 7cf0d3a..991bd5b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -569,6 +569,71 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
+/* mailbox */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2430_mailbox_sysc,
+};
+
+static struct omap_hwmod omap2430_mailbox_hwmod;
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP24XX_MAILBOX_BASE,
+ .pa_end = OMAP24XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+ .master = omap2430_l4_core_hwmod,
+ .slave = omap2430_mailbox_hwmod,
+ .addr = omap2430_mailbox_addrs,
+ .clk= mailboxes_ick,
+ .addr_cnt = ARRAY_SIZE
[PATCH v2 2/7] OMAP3: hwmod data: add mailbox data
From: Felipe Contreras felipe.contre...@gmail.com
hwmod data for omap3 mailbox.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 66
1 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ed6bf4a..60d977e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -736,6 +736,71 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
+/* mailbox */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP34XX_MAILBOX_BASE,
+ .pa_end = OMAP34XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap3xxx_mailbox_hwmod,
+ .addr = omap3xxx_mailbox_addrs,
+ .clk= mailboxes_ick,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+ omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .name = dsp, .irq = INT_24XX_MAIL_U0_MPU, },
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap3xxx_mailbox_hwmod_class,
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .slaves = omap3xxx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_l3_main_hwmod,
omap3xxx_l4_core_hwmod,
@@ -751,6 +816,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_i2c1_hwmod,
omap3xxx_i2c2_hwmod,
omap3xxx_i2c3_hwmod,
+ omap3xxx_mailbox_hwmod,
NULL,
};
--
1.7.1
--
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[PATCH v2 4/7] omap: mailbox: initial hwmod support
From: Felipe Contreras felipe.contre...@gmail.com
hwmod support for omap mailbox module.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 100 ++--
1 files changed, 15 insertions(+), 85 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index eaf3799..d977572 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -141,95 +141,25 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = iva,
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end= OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = mbox,
- },
-};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz0
-#endif
-
-static struct platform_device mbox_device = {
- .name = omap-mailbox,
- .id = -1,
-};
-
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err(%s: platform not supported\n, __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup(mailbox);
+ if (!oh) {
+ pr_err(%s: unable to find hwmod\n, __func__);
+ return;
+ }
+
+ od = omap_device_build(omap-mailbox, -1, oh,
+ NULL, 0,
+ NULL, 0,
+ 0);
+ if (!od) {
+ pr_err(%s: could not build device\n, __func__);
return;
}
- platform_device_register(mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
--
1.7.1
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[PATCH v2 3/7] OMAP4: hwmod data: add mailbox data
From: Benoit Cousson b-cous...@ti.com
hwmod data for omap4 mailbox.
Signed-off-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 63
1 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d5c6eb..f7525e3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1043,6 +1043,66 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/* mailbox */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap44xx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = OMAP44XX_MAILBOX_BASE,
+ .pa_end = OMAP44XX_MAILBOX_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_cfg - mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_mailbox_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .name = mbox, .irq = 26 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap44xx_mailbox_hwmod_class,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+ },
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .slaves = omap44xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
omap44xx_dmm_hwmod,
@@ -1077,6 +1137,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
omap44xx_uart2_hwmod,
omap44xx_uart3_hwmod,
omap44xx_uart4_hwmod,
+
+ /* mailbox */
+ omap44xx_mailbox_hwmod,
NULL,
};
--
1.7.1
--
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[PATCH 3/6] OMAP4: hwmod data: add mmu hwmod for ducati and tesla
Add mmu hwmod data for ducati and tesla.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 105
1 files changed, 105 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f7525e3..1d5eace 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,7 @@
#include plat/omap_hwmod.h
#include plat/cpu.h
+#include plat/iommu.h
#include omap_hwmod_common_data.h
@@ -1103,6 +1104,106 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/* mmu */
+
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+ .name = mmu,
+};
+
+/* ducati mmu */
+
+static struct omap_hwmod omap44xx_ducati_mmu_hwmod;
+
+static struct omap_hwmod_addr_space omap44xx_ducati_mmu_addrs[] = {
+ {
+ .pa_start = OMAP4_MMU1_BASE,
+ .pa_end = OMAP4_MMU1_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main_1 - ducati mmu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__ducati_mmu = {
+ .master = omap44xx_l3_main_1_hwmod,
+ .slave = omap44xx_ducati_mmu_hwmod,
+ .addr = omap44xx_ducati_mmu_addrs,
+ .clk= dpll_mpu_m2_ck,
+ .addr_cnt = ARRAY_SIZE(omap44xx_ducati_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ducati mmu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_ducati_mmu_slaves[] = {
+ omap44xx_l3_main_1__ducati_mmu,
+};
+
+static struct omap_hwmod_irq_info omap44xx_ducati_mmu_irqs[] = {
+ { .name = ducati, .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_mmu_dev_attr ducati_mmu_dev_attr = {
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_ducati_mmu_hwmod = {
+ .name = ducati,
+ .class = omap44xx_mmu_hwmod_class,
+ .mpu_irqs = omap44xx_ducati_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ducati_mmu_irqs),
+ .slaves = omap44xx_ducati_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_ducati_mmu_slaves),
+ .dev_attr = ducati_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* tesla mmu */
+
+static struct omap_hwmod omap44xx_tesla_mmu_hwmod;
+
+static struct omap_hwmod_addr_space omap44xx_tesla_mmu_addrs[] = {
+ {
+ .pa_start = OMAP4_MMU2_BASE,
+ .pa_end = OMAP4_MMU2_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main_1 - tesla mmu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__tesla_mmu = {
+ .master = omap44xx_l3_main_1_hwmod,
+ .slave = omap44xx_tesla_mmu_hwmod,
+ .addr = omap44xx_tesla_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_tesla_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* tesla mmu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_tesla_mmu_slaves[] = {
+ omap44xx_l3_main_1__tesla_mmu,
+};
+
+static struct omap_hwmod_irq_info omap44xx_tesla_mmu_irqs[] = {
+ { .name = tesla, .irq = 28 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_mmu_dev_attr tesla_mmu_dev_attr = {
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_tesla_mmu_hwmod = {
+ .name = tesla,
+ .class = omap44xx_mmu_hwmod_class,
+ .mpu_irqs = omap44xx_tesla_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_tesla_mmu_irqs),
+ .main_clk = dsp_fck,
+ .slaves = omap44xx_tesla_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_tesla_mmu_slaves),
+ .dev_attr = tesla_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .flags = HWMOD_NO_IDLEST,
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
omap44xx_dmm_hwmod,
@@ -1140,6 +1241,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] =
{
/* mailbox */
omap44xx_mailbox_hwmod,
+
+ /* mmu */
+ omap44xx_ducati_mmu_hwmod,
+ omap44xx_tesla_mmu_hwmod,
NULL,
};
--
1.7.1
--
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[PATCH 2/6] OMAP3: hwmod data: Add mmu for iva2 and isp
Add mmu hwmod data for iva2 and isp.
Plus a define for the iva2 base register.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 103
arch/arm/plat-omap/include/plat/iommu.h|8 ++
arch/arm/plat-omap/include/plat/omap34xx.h |2 +
3 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 60d977e..ff80efc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -21,6 +21,7 @@
#include plat/l4_3xxx.h
#include plat/i2c.h
#include plat/omap34xx.h
+#include plat/iommu.h
#include omap_hwmod_common_data.h
@@ -801,6 +802,106 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
+/* mmu */
+
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+ .name = mmu,
+};
+
+/* isp mmu */
+
+static struct omap_hwmod omap3xxx_isp_mmu_hwmod;
+
+static struct omap_hwmod_addr_space omap3xxx_isp_mmu_addrs[] = {
+ {
+ .pa_start = OMAP3430_ISP_MMU_BASE,
+ .pa_end = OMAP3430_ISP_MMU_BASE + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - isp mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__isp_mmu = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap3xxx_isp_mmu_hwmod,
+ .addr = omap3xxx_isp_mmu_addrs,
+ .clk= cam_ick,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* isp mmu slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_isp_mmu_slaves[] = {
+ omap3xxx_l4_core__isp_mmu,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_isp_mmu_irqs[] = {
+ { .name = isp, .irq = INT_24XX_CAM_IRQ, },
+};
+
+static struct omap_mmu_dev_attr isp_mmu_dev_attr = {
+ .nr_tlb_entries = 8,
+};
+
+static struct omap_hwmod omap3xxx_isp_mmu_hwmod = {
+ .name = isp,
+ .class = omap3xxx_mmu_hwmod_class,
+ .mpu_irqs = omap3xxx_isp_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_irqs),
+ .slaves = omap3xxx_isp_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_isp_mmu_slaves),
+ .dev_attr = isp_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .flags = HWMOD_NO_IDLEST,
+};
+
+/* iva2 mmu */
+
+static struct omap_hwmod omap3xxx_iva2_mmu_hwmod;
+
+static struct omap_hwmod_addr_space omap3xxx_iva2_mmu_addrs[] = {
+ {
+ .pa_start = OMAP34XX_IVA2_MMU_BASE,
+ .pa_end = OMAP34XX_IVA2_MMU_BASE + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l3_main - iva2 mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__iva2_mmu = {
+ .master = omap3xxx_l3_main_hwmod,
+ .slave = omap3xxx_iva2_mmu_hwmod,
+ .addr = omap3xxx_iva2_mmu_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_iva2_mmu_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva2 mmu slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_iva2_mmu_slaves[] = {
+ omap3xxx_l3_main__iva2_mmu,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_iva2_mmu_irqs[] = {
+ { .name = iva2, .irq = INT_24XX_DSP_MMU, },
+};
+
+static struct omap_mmu_dev_attr iva2_mmu_dev_attr = {
+ .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap3xxx_iva2_mmu_hwmod = {
+ .name = iva2,
+ .class = omap3xxx_mmu_hwmod_class,
+ .mpu_irqs = omap3xxx_iva2_mmu_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_iva2_mmu_irqs),
+ .main_clk = iva2_ck,
+ .slaves = omap3xxx_iva2_mmu_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_iva2_mmu_slaves),
+ .dev_attr = iva2_mmu_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .flags = HWMOD_NO_IDLEST,
+};
+
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_l3_main_hwmod,
omap3xxx_l4_core_hwmod,
@@ -817,6 +918,8 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_i2c2_hwmod,
omap3xxx_i2c3_hwmod,
omap3xxx_mailbox_hwmod,
+ omap3xxx_isp_mmu_hwmod,
+ omap3xxx_iva2_mmu_hwmod,
NULL,
};
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index 33c7d41..91a75a5 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -99,6 +99,14 @@ struct iommu_functions {
ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
};
+/* omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
[PATCH 1/6] omap: iommu: remove redundant clock usage
iommu driver is meant to provide control of mmu hardware blocks
its current users (MMUs) are part of larger subsystems and do not
have a dedicated clock as the one they use is shared with the
entire subsystem, it doesn't make sense to enable/disable on each
register read/write operation as the driver using its interface
should also be handling the same clock.
iommu should only enable/disable the clock on mmu request/free from
the driver wanting to use it.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/iommu.c | 38 +-
1 files changed, 5 insertions(+), 33 deletions(-)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 6cd151b..de992c8 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -108,7 +108,6 @@ static int iommu_enable(struct iommu *obj)
err = arch_iommu-enable(obj);
- clk_disable(obj-clk);
return err;
}
@@ -117,8 +116,6 @@ static void iommu_disable(struct iommu *obj)
if (!obj)
return;
- clk_enable(obj-clk);
-
arch_iommu-disable(obj);
clk_disable(obj-clk);
@@ -237,20 +234,16 @@ static struct cr_regs __iotlb_read_cr(struct iommu *obj,
int n)
**/
int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
{
- int err = 0;
struct iotlb_lock l;
struct cr_regs *cr;
if (!obj || !obj-nr_tlb_entries || !e)
return -EINVAL;
- clk_enable(obj-clk);
-
iotlb_lock_get(obj, l);
if (l.base == obj-nr_tlb_entries) {
dev_warn(obj-dev, %s: preserve entries full\n, __func__);
- err = -EBUSY;
- goto out;
+ return -EBUSY;
}
if (!e-prsvd) {
int i;
@@ -262,8 +255,7 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry
*e)
if (i == obj-nr_tlb_entries) {
dev_dbg(obj-dev, %s: full: no entry\n, __func__);
- err = -EBUSY;
- goto out;
+ return -EBUSY;
}
iotlb_lock_get(obj, l);
@@ -273,10 +265,8 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry
*e)
}
cr = iotlb_alloc_cr(obj, e);
- if (IS_ERR(cr)) {
- clk_disable(obj-clk);
+ if (IS_ERR(cr))
return PTR_ERR(cr);
- }
iotlb_load_cr(obj, cr);
kfree(cr);
@@ -287,9 +277,8 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry
*e)
if (++l.vict == obj-nr_tlb_entries)
l.vict = l.base;
iotlb_lock_set(obj, l);
-out:
- clk_disable(obj-clk);
- return err;
+
+ return 0;
}
EXPORT_SYMBOL_GPL(load_iotlb_entry);
@@ -305,8 +294,6 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
int i;
struct cr_regs cr;
- clk_enable(obj-clk);
-
for_each_iotlb_cr(obj, obj-nr_tlb_entries, i, cr) {
u32 start;
size_t bytes;
@@ -324,7 +311,6 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
}
}
- clk_disable(obj-clk);
if (i == obj-nr_tlb_entries)
dev_dbg(obj-dev, %s: no page for %08x\n, __func__, da);
@@ -359,15 +345,11 @@ void flush_iotlb_all(struct iommu *obj)
{
struct iotlb_lock l;
- clk_enable(obj-clk);
-
l.base = 0;
l.vict = 0;
iotlb_lock_set(obj, l);
iommu_write_reg(obj, 1, MMU_GFLUSH);
-
- clk_disable(obj-clk);
}
EXPORT_SYMBOL_GPL(flush_iotlb_all);
@@ -382,9 +364,7 @@ EXPORT_SYMBOL_GPL(flush_iotlb_all);
*/
void iommu_set_twl(struct iommu *obj, bool on)
{
- clk_enable(obj-clk);
arch_iommu-set_twl(obj, on);
- clk_disable(obj-clk);
}
EXPORT_SYMBOL_GPL(iommu_set_twl);
@@ -395,12 +375,8 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf,
ssize_t bytes)
if (!obj || !buf)
return -EINVAL;
- clk_enable(obj-clk);
-
bytes = arch_iommu-dump_ctx(obj, buf, bytes);
- clk_disable(obj-clk);
-
return bytes;
}
EXPORT_SYMBOL_GPL(iommu_dump_ctx);
@@ -412,7 +388,6 @@ static int __dump_tlb_entries(struct iommu *obj, struct
cr_regs *crs, int num)
struct cr_regs tmp;
struct cr_regs *p = crs;
- clk_enable(obj-clk);
iotlb_lock_get(obj, saved);
for_each_iotlb_cr(obj, num, i, tmp) {
@@ -422,7 +397,6 @@ static int __dump_tlb_entries(struct iommu *obj, struct
cr_regs *crs, int num)
}
iotlb_lock_set(obj, saved);
- clk_disable(obj-clk);
return p - crs;
}
@@ -795,9 +769,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
if (!err)
return IRQ_HANDLED;
- clk_enable(obj-clk);
stat = iommu_report_fault(obj, da
[PATCH 4/6] omap: iommu: intial hwmod support
Use the defined hwmod data according to the devices
present on omap3 and omap4.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap-iommu.c| 77 ---
arch/arm/plat-omap/include/plat/iommu.h |2 +-
arch/arm/plat-omap/iommu.c |2 +-
3 files changed, 21 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index f5a1aad..65460ef 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -14,12 +14,11 @@
#include plat/iommu.h
#include plat/irqs.h
+#include plat/omap_hwmod.h
+#include plat/omap_device.h
struct iommu_device {
- resource_size_t base;
- int irq;
struct iommu_platform_data pdata;
- struct resource res[2];
};
static struct iommu_device *devices;
static int num_iommu_devices;
@@ -27,128 +26,90 @@ static int num_iommu_devices;
#ifdef CONFIG_ARCH_OMAP3
static struct iommu_device omap3_devices[] = {
{
- .base = 0x480bd400,
- .irq = 24,
.pdata = {
.name = isp,
- .nr_tlb_entries = 8,
.clk_name = cam_ick,
},
},
#if defined(CONFIG_MPU_BRIDGE_IOMMU)
{
- .base = 0x5d00,
- .irq = 28,
.pdata = {
.name = iva2,
- .nr_tlb_entries = 32,
.clk_name = iva2_ck,
},
},
#endif
};
#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
-static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
#else
#define omap3_devices NULL
#define NR_OMAP3_IOMMU_DEVICES 0
-#define omap3_iommu_pdev NULL
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct iommu_device omap4_devices[] = {
{
- .base = OMAP4_MMU1_BASE,
- .irq = OMAP44XX_IRQ_DUCATI_MMU,
.pdata = {
.name = ducati,
- .nr_tlb_entries = 32,
.clk_name = ducati_ick,
},
},
#if defined(CONFIG_MPU_TESLA_IOMMU)
{
- .base = OMAP4_MMU2_BASE,
- .irq = INT_44XX_DSP_MMU,
.pdata = {
.name = tesla,
- .nr_tlb_entries = 32,
.clk_name = tesla_ick,
},
},
#endif
};
#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
-static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
#else
#define omap4_devices NULL
#define NR_OMAP4_IOMMU_DEVICES 0
-#define omap4_iommu_pdev NULL
#endif
-static struct platform_device **omap_iommu_pdev;
-
static int __init omap_iommu_init(void)
{
- int i, err;
- struct resource res[] = {
- { .flags = IORESOURCE_MEM },
- { .flags = IORESOURCE_IRQ },
- };
+ int i;
if (cpu_is_omap34xx()) {
devices = omap3_devices;
- omap_iommu_pdev = omap3_iommu_pdev;
num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
} else if (cpu_is_omap44xx()) {
devices = omap4_devices;
- omap_iommu_pdev = omap4_iommu_pdev;
num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
} else
return -ENODEV;
for (i = 0; i num_iommu_devices; i++) {
- struct platform_device *pdev;
- const struct iommu_device *d = devices[i];
+ struct omap_hwmod *oh;
+ struct omap_device *od;
- pdev = platform_device_alloc(omap-iommu, i);
- if (!pdev) {
- err = -ENOMEM;
- goto err_out;
+ oh = omap_hwmod_lookup(devices[i].pdata.name);
+ if (!oh) {
+ pr_err(%s: hwmod not found\n, __func__);
+ return -ENODEV;
}
- res[0].start = d-base;
- res[0].end = d-base + MMU_REG_SIZE - 1;
- res[1].start = res[1].end = d-irq;
+ devices[i].pdata.mmu_attr =
+ (struct omap_mmu_dev_attr *)oh-dev_attr;
- err = platform_device_add_resources(pdev, res,
- ARRAY_SIZE(res));
- if (err)
- goto err_out;
- err = platform_device_add_data(pdev, d-pdata,
- sizeof(d-pdata));
- if (err)
- goto err_out;
- err = platform_device_add(pdev);
- if (err)
- goto err_out;
- omap_iommu_pdev[i] = pdev;
+ od = omap_device_build(omap-iommu, i, oh
[PATCH 5/6] omap: iommu: hwmod device enable/disable routines
Use omap device enable/disable routines.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap-iommu.c| 16 +++-
arch/arm/plat-omap/include/plat/iommu.h |7 +--
arch/arm/plat-omap/iommu.c | 24 +++-
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 65460ef..0a76bce 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -28,14 +28,12 @@ static struct iommu_device omap3_devices[] = {
{
.pdata = {
.name = isp,
- .clk_name = cam_ick,
},
},
#if defined(CONFIG_MPU_BRIDGE_IOMMU)
{
.pdata = {
.name = iva2,
- .clk_name = iva2_ck,
},
},
#endif
@@ -51,14 +49,12 @@ static struct iommu_device omap4_devices[] = {
{
.pdata = {
.name = ducati,
- .clk_name = ducati_ick,
},
},
#if defined(CONFIG_MPU_TESLA_IOMMU)
{
.pdata = {
.name = tesla,
- .clk_name = tesla_ick,
},
},
#endif
@@ -69,6 +65,14 @@ static struct iommu_device omap4_devices[] = {
#define NR_OMAP4_IOMMU_DEVICES 0
#endif
+static struct omap_device_pm_latency iommu_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_clocks,
+ .deactivate_func = omap_device_enable_clocks,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
+ },
+};
+
static int __init omap_iommu_init(void)
{
int i;
@@ -94,10 +98,12 @@ static int __init omap_iommu_init(void)
devices[i].pdata.mmu_attr =
(struct omap_mmu_dev_attr *)oh-dev_attr;
+ devices[i].pdata.device_enable = omap_device_enable;
+ devices[i].pdata.device_disable = omap_device_idle;
od = omap_device_build(omap-iommu, i, oh,
devices[i].pdata, sizeof(devices[i].pdata),
- NULL, 0,
+ iommu_latencies, ARRAY_SIZE(iommu_latencies),
0);
if (!od) {
pr_err(%s: error device build failed\n, __func__);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index 9650309..fd8ffeb 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -13,6 +13,8 @@
#ifndef __MACH_IOMMU_H
#define __MACH_IOMMU_H
+struct platform_device;
+
struct iotlb_entry {
u32 da;
u32 pa;
@@ -28,7 +30,6 @@ struct iotlb_entry {
struct iommu {
const char *name;
struct module *owner;
- struct clk *clk;
void __iomem*regbase;
struct device *dev;
@@ -109,8 +110,10 @@ struct omap_mmu_dev_attr {
struct iommu_platform_data {
const char *name;
- const char *clk_name;
struct omap_mmu_dev_attr *mmu_attr;
+
+ int (*device_enable)(struct platform_device *pdev);
+ int (*device_disable)(struct platform_device *pdev);
};
#if defined(CONFIG_ARCH_OMAP1)
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 0fc9d90..36b1b63 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -100,11 +100,17 @@ EXPORT_SYMBOL_GPL(iommu_arch_version);
static int iommu_enable(struct iommu *obj)
{
int err;
+ struct iommu_platform_data *pdata;
+ struct platform_device *pdev;
if (!obj)
return -EINVAL;
- clk_enable(obj-clk);
+ pdev = container_of(obj-dev, struct platform_device, dev);
+ pdata = obj-dev-platform_data;
+
+ if (pdata-device_enable)
+ pdata-device_enable(pdev);
err = arch_iommu-enable(obj);
@@ -113,12 +119,19 @@ static int iommu_enable(struct iommu *obj)
static void iommu_disable(struct iommu *obj)
{
+ struct iommu_platform_data *pdata;
+ struct platform_device *pdev;
+
if (!obj)
return;
arch_iommu-disable(obj);
- clk_disable(obj-clk);
+ pdev = container_of(obj-dev, struct platform_device, dev);
+ pdata = obj-dev-platform_data;
+
+ if (pdata-device_enable)
+ pdata-device_disable(pdev);
}
/*
@@ -886,10 +899,6 @@ static int __devinit omap_iommu_probe(struct
platform_device *pdev)
if (!obj)
return -ENOMEM;
- obj-clk = clk_get(pdev-dev, pdata-clk_name);
- if (IS_ERR(obj-clk))
- goto err_clk;
-
obj-nr_tlb_entries = pdata-mmu_attr-nr_tlb_entries;
obj-name = pdata-name;
obj-dev = pdev-dev
[PATCH 0/6] omap: iommu: hwmod support and code reorganization
Boot tested on omap 3430 and 3630, functionality on iva2 only. Introduced hwmod data and support for omap3 (iva2 mmu isp mmu) and omap4 (ducati mmu tesla mmu). Minor cleanup due to this changes. There is an issue (present without patches too): Doing a cycle of insmod-rmmod to iommu module and then full insmod of bridgedriver (with all dependencies) causes the next read of iommu registers to dump an unhandled fault log; this, because when rmmod of iommu is called it tries to clean the iommu tables and flush any old entry prior to removing the driver, however these reads/writes are attempted while the MMU is under reset and will timeout on the L3 IVA target agent, which will leave MMU unusable until the proper restore sequence to clear this L3 error is executed. Fix would be to move page table allocation to iommu get and its correspondent free to iommu put, however it will fall entirely under iommu user responsibility, as it needs to clear the mmu reset bit, before calling iommu functions that read/write into mmu registers (which should apply only for first boot or on baseimage reload); trading this restriction in order to keep the same generic iommu code for all omap iommu devices. This issue has been seen on omap3 iva2 mmu, same restriction should apply for tesla mmu. For discussion: should iommu handle mmu reset source directly? This register is grouped into an IVA PRM register which handles sequencer, iva2 mmu and dsp resets. As mentioned iommu handles cam, iva2 mmu (OMAP3) and tesla, ducati mmu (OMAP4), only tesla and iva2 should suffer from this restriction and according changes should be needed to handle both cases on mach-omap2 code. This also affects hwmod, since, if defined, it tries to read SYSC registers at boot time when registering the hwmod and causing the same issue. Omar Ramirez Luna (6): omap: iommu: remove redundant clock usage OMAP3: hwmod data: Add mmu for iva2 and isp OMAP4: hwmod data: add mmu hwmod for ducati and tesla omap: iommu: intial hwmod support omap: iommu: hwmod device enable/disable routines omap: iommu: code reorganization and cleanup arch/arm/mach-omap2/omap-iommu.c | 168 +--- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 103 + arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 105 + arch/arm/plat-omap/include/plat/iommu.h| 19 +++- arch/arm/plat-omap/include/plat/omap34xx.h |2 + arch/arm/plat-omap/iommu.c | 64 --- 6 files changed, 299 insertions(+), 162 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/6] omap: iommu: code reorganization and cleanup
Since omap-iommu is now using hwmod, there are structures and
arrays that can be cleaned up to increase the readability of
the code.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap-iommu.c| 95 +++
arch/arm/plat-omap/include/plat/iommu.h |2 +-
2 files changed, 34 insertions(+), 63 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 0a76bce..135474b 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -17,53 +17,17 @@
#include plat/omap_hwmod.h
#include plat/omap_device.h
-struct iommu_device {
- struct iommu_platform_data pdata;
+static char *omap3_devices[] = {
+ isp,
+ iva2,
+ NULL,
};
-static struct iommu_device *devices;
-static int num_iommu_devices;
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct iommu_device omap3_devices[] = {
- {
- .pdata = {
- .name = isp,
- },
- },
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
- {
- .pdata = {
- .name = iva2,
- },
- },
-#endif
-};
-#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
-#else
-#define omap3_devices NULL
-#define NR_OMAP3_IOMMU_DEVICES 0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-static struct iommu_device omap4_devices[] = {
- {
- .pdata = {
- .name = ducati,
- },
- },
-#if defined(CONFIG_MPU_TESLA_IOMMU)
- {
- .pdata = {
- .name = tesla,
- },
- },
-#endif
+
+static char *omap4_devices[] = {
+ ducati,
+ tesla,
+ NULL,
};
-#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
-#else
-#define omap4_devices NULL
-#define NR_OMAP4_IOMMU_DEVICES 0
-#endif
static struct omap_device_pm_latency iommu_latencies[] = {
[0] = {
@@ -73,36 +37,28 @@ static struct omap_device_pm_latency iommu_latencies[] = {
},
};
-static int __init omap_iommu_init(void)
+static int __init omap_iommu_add(char **devices)
{
int i;
- if (cpu_is_omap34xx()) {
- devices = omap3_devices;
- num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
- } else if (cpu_is_omap44xx()) {
- devices = omap4_devices;
- num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
- } else
- return -ENODEV;
-
- for (i = 0; i num_iommu_devices; i++) {
+ for (i = 0; devices[i]; i++) {
struct omap_hwmod *oh;
struct omap_device *od;
+ struct iommu_platform_data pdata;
- oh = omap_hwmod_lookup(devices[i].pdata.name);
+ oh = omap_hwmod_lookup(devices[i]);
if (!oh) {
pr_err(%s: hwmod not found\n, __func__);
return -ENODEV;
}
- devices[i].pdata.mmu_attr =
- (struct omap_mmu_dev_attr *)oh-dev_attr;
- devices[i].pdata.device_enable = omap_device_enable;
- devices[i].pdata.device_disable = omap_device_idle;
+ pdata.name = devices[i];
+ pdata.mmu_attr = (struct omap_mmu_dev_attr *)oh-dev_attr;
+ pdata.device_enable = omap_device_enable;
+ pdata.device_disable = omap_device_idle;
od = omap_device_build(omap-iommu, i, oh,
- devices[i].pdata, sizeof(devices[i].pdata),
+ pdata, sizeof(pdata),
iommu_latencies, ARRAY_SIZE(iommu_latencies),
0);
if (!od) {
@@ -110,8 +66,23 @@ static int __init omap_iommu_init(void)
return -EPERM;
}
}
+
return 0;
}
+
+static int __init omap_iommu_init(void)
+{
+ int err;
+
+ if (cpu_is_omap34xx())
+ err = omap_iommu_add(omap3_devices);
+ else if (cpu_is_omap44xx())
+ err = omap_iommu_add(omap4_devices);
+ else
+ return -ENODEV;
+
+ return err;
+}
module_init(omap_iommu_init);
static void __exit omap_iommu_exit(void)
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index fd8ffeb..2205c3c 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -109,7 +109,7 @@ struct omap_mmu_dev_attr {
};
struct iommu_platform_data {
- const char *name;
+ char *name;
struct omap_mmu_dev_attr *mmu_attr;
int (*device_enable)(struct platform_device *pdev);
--
1.7.1
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[PATCH 01/02] omap: dsp: remove shm from normal memory
From: Felipe Contreras felipe.contre...@gmail.com
Also, don't be picky about the location, which incidentally fixes the
build since MEMBLOCK_REAL_LIMIT is gone on 2.6.37.
arch/arm/plat-omap/devices.c: In function 'omap_dsp_reserve_sdram_memblock':
arch/arm/plat-omap/devices.c:287: error: 'MEMBLOCK_REAL_LIMIT'
undeclared (first use in this function)
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/devices.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 6f42a18..fc81912 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -284,12 +284,14 @@ void __init omap_dsp_reserve_sdram_memblock(void)
if (!size)
return;
- paddr = __memblock_alloc_base(size, SZ_1M, MEMBLOCK_REAL_LIMIT);
+ paddr = memblock_alloc(size, SZ_1M);
if (!paddr) {
pr_err(%s: failed to reserve %x bytes\n,
__func__, size);
return;
}
+ memblock_free(paddr, size);
+ memblock_remove(paddr, size);
omap_dsp_phys_mempool_base = paddr;
}
--
1.7.1
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[PATCH 00/02] staging: tidspbridge: 2.6.37-rcX fixes
Hi Greg, Please consider the following patch set for tidspbridge driver in staging tree, the following has been tested on an omap3430 based board + gst-dsp environment. Many thanks to Felipe Contreras for piling this up, as I'm just propagating his patches. First two patches: 1. omap: dsp: remove shm from normal memory 2. staging: tidspbridge: hardcode SCM macros while fix is upstreamed Resolve a couple of build breaks due to adaptations for memblock and SCM layer. (2) Is meant as a temporary fix, until the patches to fix this (currently in review) are upstreamed. [1] The rest of the series, is the revert of iommu migration changes. These are needed because, without modifications made to iommu module, they do not work; these modifications (on iommu code) didn't make it for the previous merge window either. I will avoid posting the reverts (unless required), they can be found (along with the two patches of this series) at: git://dev.omapzoom.org/pub/scm/tidspbridge/kernel-dspbridge.git tidspbridge-2.6.37-rc1 Felipe Contreras (14): omap: dsp: remove shm from normal memory staging: tidspbridge: hardcode SCM macros while fix is upstreamed Revert staging: tidspbridge - update Kconfig to select IOMMU module Revert staging: tidspbridge - remove dmm custom module Revert staging: tidspbridge - deprecate reserve/unreserve_memory funtions Revert staging: tidspbridge - remove reserved memory clean up Revert staging: tidspbridge: remove dw_dmmu_base from cfg_hostres struct Revert staging: tidspbridge - move all iommu related code to a new file Revert staging: tidspbridge - remove hw directory Revert staging: tidspbridge - fix mmufault support Revert staging: tidspbridge - remove custom mmu code from tiomap3430.c Revert staging: tidspbridge - rename bridge_brd_mem_map/unmap to a proper name Revert staging: tidspbridge - move shared memory iommu maps to tiomap3430.c Revert staging: tidspbridge: replace iommu custom for opensource implementation arch/arm/plat-omap/devices.c |4 +- drivers/staging/tidspbridge/Kconfig|1 - drivers/staging/tidspbridge/Makefile |7 +- drivers/staging/tidspbridge/core/_deh.h|5 +- drivers/staging/tidspbridge/core/_tiomap.h | 19 +- drivers/staging/tidspbridge/core/dsp-mmu.c | 317 -- drivers/staging/tidspbridge/core/io_sm.c | 180 +++- drivers/staging/tidspbridge/core/tiomap3430.c | 1083 ++-- drivers/staging/tidspbridge/core/tiomap3430_pwr.c |4 + drivers/staging/tidspbridge/core/tiomap_io.c | 17 +- drivers/staging/tidspbridge/core/ue_deh.c | 115 ++- drivers/staging/tidspbridge/hw/EasiGlobal.h| 41 + drivers/staging/tidspbridge/hw/MMUAccInt.h | 76 ++ drivers/staging/tidspbridge/hw/MMURegAcM.h | 225 drivers/staging/tidspbridge/hw/hw_defs.h | 58 ++ drivers/staging/tidspbridge/hw/hw_mmu.c| 562 ++ drivers/staging/tidspbridge/hw/hw_mmu.h| 163 +++ .../tidspbridge/include/dspbridge/cfgdefs.h|1 + .../staging/tidspbridge/include/dspbridge/dev.h| 24 + .../staging/tidspbridge/include/dspbridge/dmm.h| 75 ++ .../staging/tidspbridge/include/dspbridge/drv.h| 10 + .../tidspbridge/include/dspbridge/dsp-mmu.h| 67 -- .../tidspbridge/include/dspbridge/dspdefs.h| 44 + .../tidspbridge/include/dspbridge/dspioctl.h |7 + .../staging/tidspbridge/include/dspbridge/proc.h | 46 + drivers/staging/tidspbridge/pmgr/dev.c | 63 ++- drivers/staging/tidspbridge/pmgr/dmm.c | 533 ++ drivers/staging/tidspbridge/pmgr/dspapi.c | 34 +- drivers/staging/tidspbridge/rmgr/drv.c | 15 + drivers/staging/tidspbridge/rmgr/drv_interface.c |2 + drivers/staging/tidspbridge/rmgr/node.c| 48 +- drivers/staging/tidspbridge/rmgr/proc.c| 197 - 32 files changed, 3471 insertions(+), 572 deletions(-) delete mode 100644 drivers/staging/tidspbridge/core/dsp-mmu.c create mode 100644 drivers/staging/tidspbridge/hw/EasiGlobal.h create mode 100644 drivers/staging/tidspbridge/hw/MMUAccInt.h create mode 100644 drivers/staging/tidspbridge/hw/MMURegAcM.h create mode 100644 drivers/staging/tidspbridge/hw/hw_defs.h create mode 100644 drivers/staging/tidspbridge/hw/hw_mmu.c create mode 100644 drivers/staging/tidspbridge/hw/hw_mmu.h create mode 100644 drivers/staging/tidspbridge/include/dspbridge/dmm.h delete mode 100644 drivers/staging/tidspbridge/include/dspbridge/dsp-mmu.h create mode 100644 drivers/staging/tidspbridge/pmgr/dmm.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 02/02] staging: tidspbridge: hardcode SCM macros while fix is upstreamed
From: Felipe Contreras felipe.contre...@gmail.com On 2.6.37-rc1, omap platform internals for SCM have changed, so the build is broken again. drivers/staging/tidspbridge/core/tiomap3430.c:26: fatal error: plat/control.h: No such file or directory This is a totally ugly layer violation, but needed until omap_ctrl_set_dsp_boot*() are provided. Signed-off-by: Felipe Contreras felipe.contre...@gmail.com Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- drivers/staging/tidspbridge/core/tiomap3430.c | 14 +- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index f22bc12..d302e30 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -23,7 +23,6 @@ #include dspbridge/host_os.h #include linux/mm.h #include linux/mmzone.h -#include plat/control.h /* --- DSP/BIOS Bridge */ #include dspbridge/dbdefs.h @@ -68,6 +67,19 @@ #define OMAP3_IVA2_BOOTADDR_MASK 0xFC00 #define PAGES_II_LVL_TABLE 512 +/* + * This is a totally ugly layer violation, but needed until + * omap_ctrl_set_dsp_boot*() are provided. + */ +#define OMAP3_IVA2_BOOTMOD_IDLE 1 +#define OMAP2_CONTROL_GENERAL 0x270 +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) + +#define OMAP343X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) + + /* Forward Declarations: */ static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt); static int bridge_brd_read(struct bridge_dev_context *dev_ctxt, -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] OMAP: ZOOM2: Change GPIO to enable LCD NEC NL8048HL11-01B on OMAP34x-II MDP
From: Yanick Saugy yanick.sa...@heig-vd.ch
The PIN which controls LCD's reset signal (VGA_nRESET/h_GPIO_96) was not
configured as a GPIO. We had to modify the OMAP MUX, and select this PIN
(CAM_XCLKA) as an output GPIO (OMAP_MUX_MODE4). (kernel 2.6.35)
Be aware of changing this PIN will probably disable the camera, because
it was previously configured as a camera clock.
Signed-off-by: Yanick Saugy yanick.sa...@heig-vd.ch
Acked-by: Tony Lindgren t...@atomide.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
I'm not sure if this patch was forgotten, hence resending. Without
it, a blanks screen is seen on zoom2 board.
Original patch:
http://patchwork.kernel.org/patch/196922/
arch/arm/mach-omap2/board-zoom2.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-zoom2.c
b/arch/arm/mach-omap2/board-zoom2.c
index 1cd6414..8fe578c 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -51,6 +51,8 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+ /* LCD Panel reset (PROD) - GPIO 96 */
+ OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
--
1.7.1
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[PATCH] staging: tidspbridge: remove file handling functions for loader
Instead use request_firmware and friends to get a valid firmware
image.
Right now the image is supplied dynamically through udev and the
following rule:
KERNEL==omap-dsp, SUBSYSTEM==firmware, ACTION==add, \
RUN+=/bin/sh -c 'echo 1 /sys/$DEVPATH/loading; \
cat $FIRMWARE /sys/$DEVPATH/data; \
echo 0 /sys/$DEVPATH/loading'
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
.../tidspbridge/include/dspbridge/dbldefs.h| 10 --
.../staging/tidspbridge/include/dspbridge/dbll.h |7 ++
.../tidspbridge/include/dspbridge/dblldefs.h | 35 --
drivers/staging/tidspbridge/pmgr/cod.c | 100 -
drivers/staging/tidspbridge/pmgr/dbll.c| 114 +++
5 files changed, 73 insertions(+), 193 deletions(-)
diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbldefs.h
b/drivers/staging/tidspbridge/include/dspbridge/dbldefs.h
index bf4fb99..c74321b 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/dbldefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/dbldefs.h
@@ -126,16 +126,6 @@ struct dbl_attrs {
dbl_sym_lookup sym_lookup;
void *sym_handle;
void *sym_arg;
-
- /*
-* These file manipulation functions should be compatible with the
-* C run time library functions of the same name.
-*/
-s32(*fread) (void *, size_t, size_t, void *);
-s32(*fseek) (void *, long, int);
-s32(*ftell) (void *);
-s32(*fclose) (void *);
- void *(*fopen) (const char *, const char *);
};
#endif /* DBLDEFS_ */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbll.h
b/drivers/staging/tidspbridge/include/dspbridge/dbll.h
index b018676..ad081e0 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/dbll.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/dbll.h
@@ -20,9 +20,16 @@
#ifndef DBLL_
#define DBLL_
+#include linux/firmware.h
#include dspbridge/dbdefs.h
#include dspbridge/dblldefs.h
+struct dsp_fw {
+ const struct firmware *img;
+ const char *name;
+ const u8 *pos;
+};
+
extern bool symbols_reloaded;
extern void dbll_close(struct dbll_library_obj *zl_lib);
diff --git a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h
b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h
index d2b4fda..f353a14 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/dblldefs.h
@@ -79,11 +79,6 @@ typedef s32(*dbll_alloc_fxn) (void *hdl, s32 space, u32
size, u32 align,
bool reserved);
/*
- * dbll_close_fxn
- */
-typedef s32(*dbll_f_close_fxn) (void *);
-
-/*
* dbll_free_fxn
* Free memory function. Free, or unreserve (if reserved == TRUE) size
* bytes of memory from segment space
@@ -92,11 +87,6 @@ typedef bool(*dbll_free_fxn) (void *hdl, u32 addr, s32
space, u32 size,
bool reserved);
/*
- * dbll_f_open_fxn
- */
-typedef void *(*dbll_f_open_fxn) (const char *, const char *);
-
-/*
* dbll_log_write_fxn
* Function to call when writing data from a section, to log the info.
* Can be NULL if no logging is required.
@@ -106,16 +96,6 @@ typedef int(*dbll_log_write_fxn) (void *handle,
u32 bytes);
/*
- * dbll_read_fxn
- */
-typedef s32(*dbll_read_fxn) (void *, size_t, size_t, void *);
-
-/*
- * dbll_seek_fxn
- */
-typedef s32(*dbll_seek_fxn) (void *, long, int);
-
-/*
* dbll_sym_lookup
* Symbol lookup function - Find the symbol name and return its value.
*
@@ -133,11 +113,6 @@ typedef bool(*dbll_sym_lookup) (void *handle, void *parg,
void *rmm_handle,
const char *name, struct dbll_sym_val ** sym);
/*
- * dbll_tell_fxn
- */
-typedef s32(*dbll_tell_fxn) (void *);
-
-/*
* dbll_write_fxn
* Write memory function. Write n HOST bytes of memory to segment mtype
* starting at address dsp_address from the buffer buf. The buffer is
@@ -163,16 +138,6 @@ struct dbll_attrs {
dbll_sym_lookup sym_lookup;
void *sym_handle;
void *sym_arg;
-
- /*
-* These file manipulation functions should be compatible with the
-* C run time library functions of the same name.
-*/
-s32(*fread) (void *, size_t, size_t, void *);
-s32(*fseek) (void *, long, int);
-s32(*ftell) (void *);
-s32(*fclose) (void *);
- void *(*fopen) (const char *, const char *);
};
/*
diff --git a/drivers/staging/tidspbridge/pmgr/cod.c
b/drivers/staging/tidspbridge/pmgr/cod.c
index 52989ab..31cfa9b 100644
--- a/drivers/staging/tidspbridge/pmgr/cod.c
+++ b/drivers/staging/tidspbridge/pmgr/cod.c
@@ -89,101
[PATCH] staging: tidspbridge: use the right type for list_is_last
Removes the following warning: CC [M] drivers/staging/tidspbridge/rmgr/rmm.o drivers/staging/tidspbridge/rmgr/rmm.c: In function 'rmm_alloc': drivers/staging/tidspbridge/rmgr/rmm.c:147: warning: passing argument 1 of 'list_is_last' from incompatible pointer type include/linux/list.h:170: note: expected 'const struct list_head *' but argument is of type 'struct rmm_ovly_sect *' Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- drivers/staging/tidspbridge/rmgr/rmm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/staging/tidspbridge/rmgr/rmm.c b/drivers/staging/tidspbridge/rmgr/rmm.c index aae8657..5a3f09c 100644 --- a/drivers/staging/tidspbridge/rmgr/rmm.c +++ b/drivers/staging/tidspbridge/rmgr/rmm.c @@ -144,7 +144,7 @@ int rmm_alloc(struct rmm_target_obj *target, u32 segid, u32 size, new_sect-addr = addr; new_sect-size = size; new_sect-page = segid; - if (list_is_last(sect, target-ovly_list)) + if (list_is_last(sect-list_elem, target-ovly_list)) /* Put new section at the end of the list */ list_add_tail(new_sect-list_elem, target-ovly_list); -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] OMAP: device: make rt_va easily avaialable to drivers
Patch OMAP: hwmod/device: add omap_{device, hwmod}_get_mpu_rt_va[1],
introduces omap_device_get_rt_va which is meant to be called
by drivers to retrieve the _mpu_rt_va, however this function
receives a pointer to an omap_device; since there is no
practical way for a driver to get this parameter without
fiddling with pdev and container_of macro, and omap_device code
already does this, it is better for it to handle this case.
Also moved header declaration to appear in the set of
functions to be used by drivers, as per the comment there.
[1] http://marc.info/?l=linux-omapm=127808467703366w=2
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/include/plat/omap_device.h |3 +--
arch/arm/plat-omap/omap_device.c |8 ++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h
b/arch/arm/plat-omap/include/plat/omap_device.h
index 28e2d1a..1877c1a 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -80,6 +80,7 @@ struct omap_device {
int omap_device_enable(struct platform_device *pdev);
int omap_device_idle(struct platform_device *pdev);
int omap_device_shutdown(struct platform_device *pdev);
+void __iomem *omap_device_get_rt_va(struct platform_device *pdev);
/* Core code interface */
@@ -101,8 +102,6 @@ struct omap_device *omap_device_build_ss(const char
*pdev_name, int pdev_id,
int omap_device_register(struct omap_device *od);
int omap_early_device_register(struct omap_device *od);
-void __iomem *omap_device_get_rt_va(struct omap_device *od);
-
/* OMAP PM interface */
int omap_device_align_pm_lat(struct platform_device *pdev,
u32 new_wakeup_lat_limit);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index abe933c..9d11195 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -681,7 +681,7 @@ struct powerdomain *omap_device_get_pwrdm(struct
omap_device *od)
/**
* omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
- * @od: struct omap_device *
+ * @pdev: struct platform_device *
*
* Return the MPU's virtual address for the base of the hwmod, from
* the ioremap() that the hwmod code does. Only valid if there is one
@@ -690,8 +690,12 @@ struct powerdomain *omap_device_get_pwrdm(struct
omap_device *od)
* otherwise, passes along the return value from
* omap_hwmod_get_mpu_rt_va().
*/
-void __iomem *omap_device_get_rt_va(struct omap_device *od)
+void __iomem *omap_device_get_rt_va(struct platform_device *pdev)
{
+ struct omap_device *od;
+
+ od = _find_by_pdev(pdev);
+
if (od-hwmods_cnt != 1)
return NULL;
--
1.7.1
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[PATCH] OMAP: device: make rt_va easily avaialable to drivers
Patch OMAP: hwmod/device: add omap_{device, hwmod}_get_mpu_rt_va[1],
introduces omap_device_get_rt_va which is meant to be called
by drivers to retrieve the _mpu_rt_va, however this function
receives a pointer to an omap_device; since there is no
practical way for a driver to get this parameter without
fiddling with pdev and container_of macro, and omap_device code
already does this, it is better for it to handle this case.
Also moved header declaration to appear in the set of
functions to be used by drivers, as per the comment there.
[1] http://marc.info/?l=linux-omapm=127808467703366w=2
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/include/plat/omap_device.h |3 +--
arch/arm/plat-omap/omap_device.c |8 ++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h
b/arch/arm/plat-omap/include/plat/omap_device.h
index 28e2d1a..1877c1a 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -80,6 +80,7 @@ struct omap_device {
int omap_device_enable(struct platform_device *pdev);
int omap_device_idle(struct platform_device *pdev);
int omap_device_shutdown(struct platform_device *pdev);
+void __iomem *omap_device_get_rt_va(struct platform_device *pdev);
/* Core code interface */
@@ -101,8 +102,6 @@ struct omap_device *omap_device_build_ss(const char
*pdev_name, int pdev_id,
int omap_device_register(struct omap_device *od);
int omap_early_device_register(struct omap_device *od);
-void __iomem *omap_device_get_rt_va(struct omap_device *od);
-
/* OMAP PM interface */
int omap_device_align_pm_lat(struct platform_device *pdev,
u32 new_wakeup_lat_limit);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index abe933c..9d11195 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -681,7 +681,7 @@ struct powerdomain *omap_device_get_pwrdm(struct
omap_device *od)
/**
* omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
- * @od: struct omap_device *
+ * @pdev: struct platform_device *
*
* Return the MPU's virtual address for the base of the hwmod, from
* the ioremap() that the hwmod code does. Only valid if there is one
@@ -690,8 +690,12 @@ struct powerdomain *omap_device_get_pwrdm(struct
omap_device *od)
* otherwise, passes along the return value from
* omap_hwmod_get_mpu_rt_va().
*/
-void __iomem *omap_device_get_rt_va(struct omap_device *od)
+void __iomem *omap_device_get_rt_va(struct platform_device *pdev)
{
+ struct omap_device *od;
+
+ od = _find_by_pdev(pdev);
+
if (od-hwmods_cnt != 1)
return NULL;
--
1.7.1
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[PATCH v3 2/5] OMAP3: hwmod data: add mailbox data
From: Felipe Contreras felipe.contre...@gmail.com
Mailbox hwmod data for omap3.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8eb81b4..9ce347e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1089,6 +1089,74 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
.class = omap3xxx_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap3xxx_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap3xxx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+ omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -1115,6 +1183,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_gpio4_hwmod,
omap3xxx_gpio5_hwmod,
omap3xxx_gpio6_hwmod,
+
+ /* mailbox class */
+ omap3xxx_mailbox_hwmod,
NULL,
};
--
1.7.1
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[PATCH v3 1/5] OMAP2: hwmod data: add mailbox data
Mailbox hwmod data for omap2430 and 2420.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++
2 files changed, 145 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index ce5d890..64f8f8b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -778,6 +778,76 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
.class = omap242x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+ { .name = iva, .irq = 34, },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap2420_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap2420_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -799,6 +869,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_gpio2_hwmod,
omap2420_gpio3_hwmod,
omap2420_gpio4_hwmod,
+
+ /* mailbox class */
+ omap2420_mailbox_hwmod,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 0f87736..939af19 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -839,6 +839,75 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
.class = omap243x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+};
+
+static
[PATCH v3 0/5] omap: mailbox: hwmod support
Tested on 3430, based of pm-core branch. It may require rebase once the mailbox git pull is made. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg39719.html ** v3 ** - Taken mailbox hwmod as is from Benoit original branch. - Put back numbers for irq, addresses instead of considering them as magic numbers. - Follow the declaration layout for omap4 hwmods. - Using pm_runtime to enable the clocks. TBD: Cleanup, once omap_device_get_rt_va can be called by drivers using pdev and the proper omap_device_reset API is submitted. ** v2 ** - Added omap4 hwmod support. - Moved mailbox_ick from hwmod to hwmod_if (omap 2/3) - Declared sysc classes for omap 2/3 ** v1 ** 1. omap: mailbox: initial hwmod support for omap3 Changes were made to: - Rebase to latest code. - Detect the hwmod by filling prcm union for omap2, without this it was unable to build the hwmod at runtime. - Replace magic number for defines. - Use ioremap again instead of relying on the one made by hwmod, as noted in http://patchwork.kernel.org/patch/101661/ 2. omap: mailbox: initial hwmod support for omap2 Was only compiled tested!! Unfortunately I don't have the HW for it. Benoit Cousson (1): OMAP4: hwmod data: add mailbox data Felipe Contreras (3): OMAP3: hwmod data: add mailbox data OMAP: mailbox: build device using omap_device/omap_hwmod OMAP: mailbox: add omap_device latency information omar ramirez (1): OMAP2: hwmod data: add mailbox data arch/arm/mach-omap2/devices.c | 102 ++-- arch/arm/mach-omap2/mailbox.c | 18 ++--- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 +++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 68 ++ 6 files changed, 310 insertions(+), 94 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/5] OMAP4: hwmod data: add mailbox data
From: Benoit Cousson b-cous...@ti.com
Mailbox hwmod data for omap4.
Signed-off-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 68
1 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ae14bd5..9c6db0e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1380,6 +1380,71 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .name = mbox, .irq = 26 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_cfg - mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_mailbox_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
omap44xx_dmm_hwmod,
@@ -1422,6 +1487,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
omap44xx_uart2_hwmod,
omap44xx_uart3_hwmod,
omap44xx_uart4_hwmod,
+
+ /* mailbox class */
+ omap44xx_mailbox_hwmod,
NULL,
};
--
1.7.1
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[PATCH v3 5/5] OMAP: mailbox: add omap_device latency information
From: Felipe Contreras felipe.contre...@gmail.com
So that we can enable the main clock.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 10 +-
arch/arm/mach-omap2/mailbox.c | 18 ++
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 3bb7724..9478cb3 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -142,6 +142,14 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_clocks,
+ .deactivate_func = omap_device_enable_clocks,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+};
+
static inline void omap_init_mbox(void)
{
struct omap_hwmod *oh;
@@ -155,7 +163,7 @@ static inline void omap_init_mbox(void)
od = omap_device_build(omap-mailbox, -1, oh,
NULL, 0,
- NULL, 0,
+ mbox_latencies, ARRAY_SIZE(mbox_latencies),
0);
if (!od) {
pr_err(%s: could not build device\n, __func__);
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 40ddeca..6dd59b3 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,6 +14,7 @@
#include linux/err.h
#include linux/platform_device.h
#include linux/io.h
+#include linux/pm_runtime.h
#include plat/mailbox.h
#include mach/irqs.h
@@ -52,6 +53,7 @@
#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
static void __iomem *mbox_base;
+static struct platform_device *mbox_pdev;
struct omap_mbox2_fifo {
unsigned long msg;
@@ -70,8 +72,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -91,13 +91,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
u32 l;
unsigned long timeout;
- mbox_ick_handle = clk_get(NULL, mailboxes_ick);
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR Could not get mailboxes_ick: %ld\n,
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
+ pm_runtime_get_sync(mbox_pdev-dev);
if (cpu_is_omap44xx()) {
mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
@@ -143,9 +137,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ pm_runtime_put_sync(mbox_pdev-dev);
}
/* Mailbox FIFO handle functions */
@@ -427,6 +419,8 @@ static int __devinit omap2_mbox_probe(struct
platform_device *pdev)
if (!mbox_base)
return -ENOMEM;
+ mbox_pdev = pdev;
+
ret = omap_mbox_register(pdev-dev, list);
if (ret) {
iounmap(mbox_base);
--
1.7.1
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[PATCH v3 4/5] OMAP: mailbox: build device using omap_device/omap_hwmod
From: Felipe Contreras felipe.contre...@gmail.com
Remove static platform_device and resource data within
omap mailbox driver; use the one defined in the hwmod
database along with omap_device framework for device
build and registration.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 100 ++--
1 files changed, 15 insertions(+), 85 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b5cafd3..3bb7724 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -142,95 +142,25 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = iva,
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end= OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = mbox,
- },
-};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz0
-#endif
-
-static struct platform_device mbox_device = {
- .name = omap-mailbox,
- .id = -1,
-};
-
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err(%s: platform not supported\n, __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup(mailbox);
+ if (!oh) {
+ pr_err(%s: unable to find hwmod\n, __func__);
+ return;
+ }
+
+ od = omap_device_build(omap-mailbox, -1, oh,
+ NULL, 0,
+ NULL, 0,
+ 0);
+ if (!od) {
+ pr_err(%s: could not build device\n, __func__);
return;
}
- platform_device_register(mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
--
1.7.1
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[PATCH v4 5/5] OMAP: mailbox: use runtime pm for clk and sysc handling
Use runtime pm APIs to enable/disable mailbox clocks and
to configure SYSC register.
Based on the patch sent by Felipe Contreras:
https://patchwork.kernel.org/patch/101662/
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 27 +--
1 files changed, 5 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 40ddeca..f5f72ba 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,6 +14,7 @@
#include linux/err.h
#include linux/platform_device.h
#include linux/io.h
+#include linux/pm_runtime.h
#include plat/mailbox.h
#include mach/irqs.h
@@ -34,12 +35,8 @@
#define MAILBOX_IRQ_NOTFULL(m) (1 (2 * (m) + 1))
/* SYSCONFIG: register bit definition */
-#define AUTOIDLE (1 0)
#define SOFTRESET (1 1)
-#define SMARTIDLE (2 3)
#define OMAP4_SOFTRESET(1 0)
-#define OMAP4_NOIDLE (1 2)
-#define OMAP4_SMARTIDLE(2 2)
/* SYSSTATUS: register bit definition */
#define RESETDONE (1 0)
@@ -70,8 +67,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -91,13 +86,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
u32 l;
unsigned long timeout;
- mbox_ick_handle = clk_get(NULL, mailboxes_ick);
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR Could not get mailboxes_ick: %ld\n,
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
+ pm_runtime_enable(mbox-dev-parent);
+ pm_runtime_get_sync(mbox-dev-parent);
if (cpu_is_omap44xx()) {
mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
@@ -130,12 +120,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
l = mbox_read_reg(MAILBOX_REVISION);
pr_debug(omap mailbox rev %d.%d\n, (l 0xf0) 4, (l 0x0f));
- if (cpu_is_omap44xx())
- l = OMAP4_SMARTIDLE;
- else
- l = SMARTIDLE | AUTOIDLE;
- mbox_write_reg(l, MAILBOX_SYSCONFIG);
-
omap2_mbox_enable_irq(mbox, IRQ_RX);
return 0;
@@ -143,9 +127,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ pm_runtime_put_sync(mbox-dev-parent);
+ pm_runtime_disable(mbox-dev-parent);
}
/* Mailbox FIFO handle functions */
--
1.7.1
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[PATCH v4 4/5] OMAP: mailbox: build device using omap_device/omap_hwmod
From: Felipe Contreras felipe.contre...@gmail.com
Remove static platform_device and resource data within
omap mailbox driver; use the one defined in the hwmod
database along with omap_device framework for device
build and registration.
Add device latency functions to be used, so clock can be
enabled and sysconfig is configured.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 102 -
1 files changed, 20 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b5cafd3..7493c30 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -142,95 +142,33 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = iva,
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end= OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = mbox,
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_hwmods,
+ .deactivate_func = omap_device_idle_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz0
-#endif
-
-static struct platform_device mbox_device = {
- .name = omap-mailbox,
- .id = -1,
-};
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err(%s: platform not supported\n, __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup(mailbox);
+ if (!oh) {
+ pr_err(%s: unable to find hwmod\n, __func__);
+ return;
+ }
+
+ od = omap_device_build(omap-mailbox, -1, oh,
+ NULL, 0,
+ mbox_latencies, ARRAY_SIZE(mbox_latencies),
+ 0);
+ if (!od) {
+ pr_err(%s: could not build device\n, __func__);
return;
}
- platform_device_register(mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
--
1.7.1
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[PATCH v4 2/5] OMAP3: hwmod data: add mailbox data
From: Felipe Contreras felipe.contre...@gmail.com
Mailbox hwmod data for omap3.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8eb81b4..9ce347e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1089,6 +1089,74 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
.class = omap3xxx_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap3xxx_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap3xxx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+ omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -1115,6 +1183,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
omap3xxx_gpio4_hwmod,
omap3xxx_gpio5_hwmod,
omap3xxx_gpio6_hwmod,
+
+ /* mailbox class */
+ omap3xxx_mailbox_hwmod,
NULL,
};
--
1.7.1
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[PATCH v4 1/5] OMAP2: hwmod data: add mailbox data
From: omar ramirez omar.rami...@ti.com
Mailbox hwmod data for omap2430 and 2420.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++
2 files changed, 145 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index ce5d890..64f8f8b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -778,6 +778,76 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
.class = omap242x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+ { .name = iva, .irq = 34, },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap2420_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap2420_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -799,6 +869,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
omap2420_gpio2_hwmod,
omap2420_gpio3_hwmod,
omap2420_gpio4_hwmod,
+
+ /* mailbox class */
+ omap2420_mailbox_hwmod,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 0f87736..939af19 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -839,6 +839,75 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
.class = omap243x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs
[PATCH v4 3/5] OMAP4: hwmod data: add mailbox data
From: Benoit Cousson b-cous...@ti.com
Mailbox hwmod data for omap4.
Signed-off-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 67
1 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7367648..f14b01c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1740,6 +1740,70 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .name = mbox, .irq = 26 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_cfg - mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_mailbox_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
omap44xx_dmm_hwmod,
@@ -1798,6 +1862,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
omap44xx_wd_timer2_hwmod,
omap44xx_wd_timer3_hwmod,
+ /* mailbox class */
+ omap44xx_mailbox_hwmod,
+
NULL,
};
--
1.7.1
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[PATCH v4 0/5] omap: mailbox: hwmod support
Tested on 3430, based of pm-core branch. Patches affecting mailbox code may require rebase once the mailbox git pull is made. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg39719.html ** v4 ** - Merged device latency info with previous patch in series. - Removed usage of omap_device_enable_clocks and replaced for omap_device_[enable|disable]_hwmods to handle sysc setup and clocks. - Fixed pm_runtime usage by adding its enable/disable functions, and now handling sysc register with it, because of changes in device latency functions. - For pm_runtime, instead of adding a global variable to make use of pdev-dev, use 'parent' inside of 'dev' returned by device_create and which is stored inside omap_mbox struct, in future cleanup consider cleaning omap_mbox struct. ** v3 ** - Taken mailbox hwmod as is from Benoit original branch. - Put back numbers for irq, addresses instead of considering them as magic numbers. - Follow the declaration layout for omap4 hwmods. - Using pm_runtime to enable the clocks. ** v2 ** - Added omap4 hwmod support. - Moved mailbox_ick from hwmod to hwmod_if (omap 2/3) - Declared sysc classes for omap 2/3 ** v1 ** 1. omap: mailbox: initial hwmod support for omap3 Changes were made to: - Rebase to latest code. - Detect the hwmod by filling prcm union for omap2, without this it was unable to build the hwmod at runtime. - Replace magic number for defines. - Use ioremap again instead of relying on the one made by hwmod, as noted in http://patchwork.kernel.org/patch/101661/ 2. omap: mailbox: initial hwmod support for omap2 Was only compiled tested!! Unfortunately I don't have the HW for it. Benoit Cousson (1): OMAP4: hwmod data: add mailbox data Felipe Contreras (2): OMAP3: hwmod data: add mailbox data OMAP: mailbox: build device using omap_device/omap_hwmod Omar Ramirez Luna (1): OMAP: mailbox: use runtime pm for clk and sysc handling omar ramirez (1): OMAP2: hwmod data: add mailbox data arch/arm/mach-omap2/devices.c | 102 ++-- arch/arm/mach-omap2/mailbox.c | 27 ++-- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 +++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 67 ++ 6 files changed, 308 insertions(+), 104 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] OMAP: RM-680: fix omap2_init_common_hw compile break
This solves the following: arch/arm/mach-omap2/board-rm680.c: In function 'rm680_init_irq': arch/arm/mach-omap2/board-rm680.c:149: error: implicit declaration of function 'omap2_init_common_hw' And another occurence of the same functions in am3517crane board file. Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/board-am3517crane.c |3 ++- arch/arm/mach-omap2/board-rm680.c |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 8ba4047..781ed25 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -47,7 +47,8 @@ static void __init am3517_crane_init_irq(void) omap_board_config = am3517_crane_config; omap_board_config_size = ARRAY_SIZE(am3517_crane_config); - omap2_init_common_hw(NULL, NULL); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); omap_init_irq(); } diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 8da65bd..e51e737 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -146,7 +146,8 @@ static void __init rm680_init_irq(void) struct omap_sdrc_params *sdrc_params; sdrc_params = nokia_get_sdram_timings(); - omap2_init_common_hw(sdrc_params, sdrc_params); + omap2_init_common_infrastructure(); + omap2_init_common_devices(sdrc_params, sdrc_params); omap_init_irq(); } -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/5] OMAP4: hwmod data: add mailbox data
From: Benoit Cousson b-cous...@ti.com
Mailbox hwmod data for omap4.
Signed-off-by: Benoit Cousson b-cous...@ti.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 67
1 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c2806bd..c495669 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2001,6 +2001,70 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap44xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap44xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
+ { .name = mbox, .irq = 26 + OMAP44XX_IRQ_GIC_START, },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_cfg - mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+ .master = omap44xx_l4_cfg_hwmod,
+ .slave = omap44xx_mailbox_hwmod,
+ .clk= l4_div_ck,
+ .addr = omap44xx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
+ omap44xx_l4_cfg__mailbox,
+};
+
+static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap44xx_mailbox_hwmod_class,
+ .mpu_irqs = omap44xx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ },
+ },
+ .slaves = omap44xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
@@ -2068,6 +2132,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
omap44xx_wd_timer2_hwmod,
omap44xx_wd_timer3_hwmod,
+ /* mailbox class */
+ omap44xx_mailbox_hwmod,
+
NULL,
};
--
1.7.1
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[PATCH v5 4/5] OMAP: mailbox: build device using omap_device/omap_hwmod
From: Felipe Contreras felipe.contre...@gmail.com
Remove static platform_device and resource data within
omap mailbox driver; use the one defined in the hwmod
database along with omap_device framework for device
build and registration.
Add device latency functions to be used, so clock can be
enabled and sysconfig is configured.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/devices.c | 98 +++--
1 files changed, 16 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2c9c912..826bea0 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -142,95 +142,29 @@ static inline void omap_init_camera(void)
#endif
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE 0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
- {
- .start = OMAP24XX_MAILBOX_BASE,
- .end= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
- {
- .start = INT_24XX_MAIL_U3_MPU,
- .flags = IORESOURCE_IRQ,
- .name = iva,
- },
-};
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources NULL
-#define omap2_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
- {
- .start = OMAP34XX_MAILBOX_BASE,
- .end= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_24XX_MAIL_U0_MPU,
- .flags = IORESOURCE_IRQ,
- .name = dsp,
- },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources NULL
-#define omap3_mbox_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-
-#define OMAP4_MBOX_REG_SIZE0x130
-static struct resource omap4_mbox_resources[] = {
- {
- .start = OMAP44XX_MAILBOX_BASE,
- .end= OMAP44XX_MAILBOX_BASE +
- OMAP4_MBOX_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = OMAP44XX_IRQ_MAIL_U0,
- .flags = IORESOURCE_IRQ,
- .name = mbox,
+static struct omap_device_pm_latency mbox_latencies[] = {
+ [0] = {
+ .activate_func = omap_device_enable_hwmods,
+ .deactivate_func = omap_device_idle_hwmods,
+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources NULL
-#define omap4_mbox_resources_sz0
-#endif
-
-static struct platform_device mbox_device = {
- .name = omap-mailbox,
- .id = -1,
-};
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap24xx()) {
- mbox_device.resource = omap2_mbox_resources;
- mbox_device.num_resources = omap2_mbox_resources_sz;
- } else if (cpu_is_omap34xx()) {
- mbox_device.resource = omap3_mbox_resources;
- mbox_device.num_resources = omap3_mbox_resources_sz;
- } else if (cpu_is_omap44xx()) {
- mbox_device.resource = omap4_mbox_resources;
- mbox_device.num_resources = omap4_mbox_resources_sz;
- } else {
- pr_err(%s: platform not supported\n, __func__);
+ struct omap_hwmod *oh;
+ struct omap_device *od;
+
+ oh = omap_hwmod_lookup(mailbox);
+ if (!oh) {
+ pr_err(%s: unable to find hwmod\n, __func__);
return;
}
- platform_device_register(mbox_device);
+
+ od = omap_device_build(omap-mailbox, -1, oh, NULL, 0,
+ mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
+ WARN(IS_ERR(od), %s: could not build device, err %ld\n,
+ __func__, PTR_ERR(od));
}
#else
static inline void omap_init_mbox(void) { }
--
1.7.1
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[PATCH v5 0/5] omap: mailbox: hwmod support
Mailbox hwmod support for OMAP 2,3,4. This was tested on OMAP3 (3430, 3630), minor testing was made on OMAP4. No testing on OMAP2 since I don't have the hardware. Highlights from v5 include the comments received from previous version v4[1]. Benoit Cousson (1): OMAP4: hwmod data: add mailbox data Felipe Contreras (2): OMAP3: hwmod data: add mailbox data OMAP: mailbox: build device using omap_device/omap_hwmod Omar Ramirez Luna (1): OMAP: mailbox: use runtime pm for clk and sysc handling omar ramirez (1): OMAP2: hwmod data: add mailbox data arch/arm/mach-omap2/devices.c | 98 +--- arch/arm/mach-omap2/mailbox.c | 67 ++- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 74 + arch/arm/mach-omap2/omap_hwmod_2430_data.c | 73 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 72 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 67 +++ 6 files changed, 308 insertions(+), 143 deletions(-) --- [1] http://bit.ly/gfLaIs -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/5] OMAP2: hwmod data: add mailbox data
From: omar ramirez omar.rami...@ti.com
Mailbox hwmod data for omap2430 and 2420.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 74
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 73 +++
2 files changed, 147 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b85c630..3f54c20 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -779,6 +779,76 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
.class = omap242x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+ { .name = iva, .irq = 34, },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+ .master = omap2420_l4_core_hwmod,
+ .slave = omap2420_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap2420_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+ omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap2420_mailbox_hwmod_class,
+ .mpu_irqs = omap2420_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap2420_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -885,6 +955,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
/* dma_system class*/
omap2420_dma_system_hwmod,
+
+ /* mailbox class */
+ omap2420_mailbox_hwmod,
+
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8ecfbcd..d591aaf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -834,6 +834,75 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
.class = omap243x_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26
[PATCH v5 5/5] OMAP: mailbox: use runtime pm for clk and sysc handling
Use runtime pm APIs to enable/disable mailbox clocks and
to configure SYSC register.
Based on the patch sent by Felipe Contreras:
https://patchwork.kernel.org/patch/101662/
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 67 -
1 files changed, 6 insertions(+), 61 deletions(-)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 394413d..4a387e2 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
#include linux/err.h
#include linux/platform_device.h
#include linux/io.h
+#include linux/pm_runtime.h
#include plat/mailbox.h
#include mach/irqs.h
#define MAILBOX_REVISION 0x000
-#define MAILBOX_SYSCONFIG 0x010
-#define MAILBOX_SYSSTATUS 0x014
#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
#define MAILBOX_IRQ_NEWMSG(m) (1 (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m) (1 (2 * (m) + 1))
-/* SYSCONFIG: register bit definition */
-#define AUTOIDLE (1 0)
-#define SOFTRESET (1 1)
-#define SMARTIDLE (2 3)
-#define OMAP4_SOFTRESET(1 0)
-#define OMAP4_NOIDLE (1 2)
-#define OMAP4_SMARTIDLE(2 2)
-
-/* SYSSTATUS: register bit definition */
-#define RESETDONE (1 0)
-
#define MBOX_REG_SIZE 0x120
#define OMAP4_MBOX_REG_SIZE0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
unsigned long irqdisable;
};
-static struct clk *mbox_ick_handle;
-
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
u32 l;
- unsigned long timeout;
- mbox_ick_handle = clk_get(NULL, mailboxes_ick);
- if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR Could not get mailboxes_ick: %ld\n,
- PTR_ERR(mbox_ick_handle));
- return PTR_ERR(mbox_ick_handle);
- }
- clk_enable(mbox_ick_handle);
-
- if (cpu_is_omap44xx()) {
- mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = mbox_read_reg(MAILBOX_SYSCONFIG);
- if (!(l OMAP4_SOFTRESET))
- break;
- } while (!time_after(jiffies, timeout));
-
- if (l OMAP4_SOFTRESET) {
- pr_err(Can't take mailbox out of reset\n);
- return -ENODEV;
- }
- } else {
- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = mbox_read_reg(MAILBOX_SYSSTATUS);
- if (l RESETDONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (!(l RESETDONE)) {
- pr_err(Can't take mailbox out of reset\n);
- return -ENODEV;
- }
- }
+ pm_runtime_enable(mbox-dev-parent);
+ pm_runtime_get_sync(mbox-dev-parent);
l = mbox_read_reg(MAILBOX_REVISION);
pr_debug(omap mailbox rev %d.%d\n, (l 0xf0) 4, (l 0x0f));
- if (cpu_is_omap44xx())
- l = OMAP4_SMARTIDLE;
- else
- l = SMARTIDLE | AUTOIDLE;
- mbox_write_reg(l, MAILBOX_SYSCONFIG);
-
omap2_mbox_enable_irq(mbox, IRQ_RX);
return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
- clk_disable(mbox_ick_handle);
- clk_put(mbox_ick_handle);
- mbox_ick_handle = NULL;
+ pm_runtime_put_sync(mbox-dev-parent);
+ pm_runtime_disable(mbox-dev-parent);
}
/* Mailbox FIFO handle functions */
--
1.7.1
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[PATCH v5 2/5] OMAP3: hwmod data: add mailbox data
From: Felipe Contreras felipe.contre...@gmail.com
Mailbox hwmod data for omap3.
Signed-off-by: Felipe Contreras felipe.contre...@gmail.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 72
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d81813..5960d5e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1132,6 +1132,74 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
.class = omap3xxx_gpio_hwmod_class,
.dev_attr = gpio_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+ .name = mailbox,
+ .sysc = omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+ { .name = dsp, .irq = 26, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x480941ff,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
+/* l4_core - mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+ .master = omap3xxx_l4_core_hwmod,
+ .slave = omap3xxx_mailbox_hwmod,
+ .clk= mailboxes_ick,
+ .addr = omap3xxx_mailbox_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+ omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+ .name = mailbox,
+ .class = omap3xxx_mailbox_hwmod_class,
+ .mpu_irqs = omap3xxx_mailbox_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+ .prcm = {
+ .omap2 = {
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+ },
+ },
+ .slaves = omap3xxx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -1387,6 +1455,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] =
{
/* dma_system class*/
omap3xxx_dma_system_hwmod,
+
+ /* mailbox class */
+ omap3xxx_mailbox_hwmod,
+
NULL,
};
--
1.7.1
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[PATCH 0/8] misc patches
Next set of patches to be applied on top of sync point. Highlights: *** Ioctl numbers has changed, this will require an update on libbridge and clients accesing directly to the driver *** - IO_ADDRESS is replaced for ioremap. - DMM table is increased to hold up to 256 MB (in pages). Fernando Guzman Lugo (1): DSPBRIDGE: change to cpufreq_register_notifier for OPP changes Hari Kanigeri (1): DSPBRIDGE: Increased DMM size to 256MB Omar Ramirez Luna (6): DSPBRIDGE: Cleanup SSI handling - remove IO_ADDRESS DSPBRIDGE: sysfs entry for global driver state DSPBRIDGE: Remove unused hDrvObject in bridge_[open|release] DSPBRIDGE: Use dspbridge to initialize platform data DSPBRIDGE: Fix header locations mach to plat DSPBRIDGE: Use _IOxx macro to define ioctls arch/arm/mach-omap2/Makefile|4 +- arch/arm/mach-omap2/dspbridge.c |2 +- arch/arm/plat-omap/include/dspbridge/dmm.h |2 +- arch/arm/plat-omap/include/dspbridge/drv.h |7 + arch/arm/plat-omap/include/dspbridge/host_os.h |2 +- arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 144 ++- drivers/dsp/bridge/Kconfig |2 +- drivers/dsp/bridge/pmgr/dmm.c |8 +- drivers/dsp/bridge/pmgr/wcd.c | 128 ++-- drivers/dsp/bridge/rmgr/drv_interface.c | 137 +- drivers/dsp/bridge/services/clk.c | 30 +++--- drivers/dsp/bridge/wmd/tiomap3430.c |2 +- 12 files changed, 271 insertions(+), 197 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/8] DSPBRIDGE: Cleanup SSI handling - remove IO_ADDRESS
This patch cleans SSI clock preparation and also removes
the dependency on IO_ADDRESS variants for easier maintenance.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/include/dspbridge/drv.h |7 ++
drivers/dsp/bridge/services/clk.c | 30 ++-
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/drv.h
b/arch/arm/plat-omap/include/dspbridge/drv.h
index d14613f..59c26fc 100644
--- a/arch/arm/plat-omap/include/dspbridge/drv.h
+++ b/arch/arm/plat-omap/include/dspbridge/drv.h
@@ -115,6 +115,13 @@
#define OMAP_DMMU_BASE 0x5D00
#define OMAP_DMMU_SIZE 0x1000
+#define OMAP_SSI_BASE 0x48058000
+#define OMAP_SSI_SIZE 0x1000
+
+#define SSI_AUTOIDLE (1 0)
+#define SSI_SIDLE_SMARTIDLE(2 3)
+#define SSI_MIDLE_NOIDLE (1 12)
+
#define OMAP_PRCM_VDD1_DOMAIN 1
#define OMAP_PRCM_VDD2_DOMAIN 2
diff --git a/drivers/dsp/bridge/services/clk.c
b/drivers/dsp/bridge/services/clk.c
index d1c68fc..dbe3988 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -39,6 +39,7 @@
#include dspbridge/std.h
#include dspbridge/dbdefs.h
#include dspbridge/errbase.h
+#include dspbridge/drv.h
/* --- Trace Debug */
#include dspbridge/dbc.h
@@ -54,11 +55,6 @@
typedef volatile unsigned long REG_UWORD32;
-#define SSI_Base0x48058000
-
-#define SSI_BASE IO_ADDRESS(SSI_Base)
-
-
struct SERVICES_Clk_t {
struct clk *clk_handle;
const char *clk_name;
@@ -354,19 +350,25 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id)
void SSI_Clk_Prepare(bool FLAG)
{
- u32 ssi_sysconfig;
- ssi_sysconfig = __raw_readl((SSI_BASE) + 0x10);
+ void __iomem *ssi_base;
+ unsigned int value;
+
+ ssi_base = ioremap(OMAP_SSI_BASE, OMAP_SSI_SIZE);
if (FLAG) {
- /* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
-* no idle
+ /*
+* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
+* no idle.
*/
- ssi_sysconfig = 0x1011;
+ value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
} else {
- /* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
-* forced idle
+ /*
+* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
+* forced idle.
*/
- ssi_sysconfig = 0x1;
+ value = SSI_AUTOIDLE;
}
- __raw_writel((u32)ssi_sysconfig, SSI_BASE + 0x10);
+
+ __raw_writel(value, ssi_base + 0x10);
+ iounmap(ssi_base);
}
--
1.6.2.4
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[PATCH 2/8] DSPBRIDGE: sysfs entry for global driver state
This patch creates a new sysfs entry to query the driver
state without making any bridge direct call, this is
useful to monitor driver state without creating any handle
to bridge driver.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
drivers/dsp/bridge/rmgr/drv_interface.c | 87 +++
1 files changed, 87 insertions(+), 0 deletions(-)
diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c
b/drivers/dsp/bridge/rmgr/drv_interface.c
index c853854..3a4d058 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -58,11 +58,13 @@
#include linux/init.h
#include linux/moduleparam.h
#include linux/cdev.h
+#include linux/kobject.h
/* --- DSP/BIOS Bridge */
#include dspbridge/std.h
#include dspbridge/dbdefs.h
#include dspbridge/errbase.h
+#include _tiomap.h
/* --- Trace Debug */
#include dspbridge/gt.h
@@ -148,6 +150,10 @@ static int omap34xxbridge_suspend_lockout(
}
#endif
+/* Sysfs interface */
+static void bridge_create_sysfs(struct platform_device *pdev);
+static void bridge_destroy_sysfs(struct platform_device *pdev);
+
#ifdef DEBUG
module_param(GT_str, charp, 0);
MODULE_PARM_DESC(GT_str, GT string, default = NULL);
@@ -297,6 +303,9 @@ static int __devinit omap34xx_bridge_probe(struct
platform_device *pdev)
device_create(bridge_class, NULL, MKDEV(driver_major, driver_minor),
NULL, DspBridge);
+ /* Create sysfs interface */
+ bridge_create_sysfs(pdev);
+
GT_init();
GT_create(driverTrace, LD);
@@ -454,6 +463,9 @@ func_cont:
SERVICES_Exit();
GT_exit();
+ /* Remove driver sysfs entries */
+ bridge_destroy_sysfs(pdev);
+
devno = MKDEV(driver_major, driver_minor);
if (bridge_device) {
cdev_del(bridge_device-cdev);
@@ -677,6 +689,81 @@ DSP_STATUS DRV_RemoveAllResources(HANDLE hPCtxt)
}
#endif
+/*
+ * Sysfs
+ */
+static ssize_t drv_state_show(struct device *dev, struct device_attribute
*attr,
+ char *buf)
+{
+ struct WMD_DEV_CONTEXT *dev_ctxt;
+ struct DEV_OBJECT *dev_obj = NULL;
+ char *drv_state = unknown;
+
+ dev_obj = (struct DEV_OBJECT *)DRV_GetFirstDevObject();
+ DEV_GetWMDContext(dev_obj, dev_ctxt);
+
+ if (!dev_ctxt)
+ goto err;
+
+ switch (dev_ctxt-dwBrdState) {
+ case BRD_STOPPED:
+ drv_state = stopped;
+ break;
+ case BRD_IDLE:
+ drv_state = idle;
+ break;
+ case BRD_RUNNING:
+ drv_state = running;
+ break;
+ case BRD_LOADED:
+ drv_state = loaded;
+ break;
+ case BRD_SLEEP_TRANSITION:
+ drv_state = sleep transition;
+ break;
+ case BRD_HIBERNATION:
+ drv_state = hibernation;
+ break;
+ case BRD_RETENTION:
+ drv_state = retention;
+ break;
+ case BRD_DSP_HIBERNATION:
+ drv_state = self initiated hibernation;
+ break;
+ case BRD_ERROR:
+ drv_state = error;
+ break;
+ }
+
+err:
+ return sprintf(buf, %s\n, drv_state);
+}
+static DEVICE_ATTR(drv_state, S_IRUGO, drv_state_show, NULL);
+
+static struct attribute *attrs[] = {
+ dev_attr_drv_state.attr,
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = attrs,
+};
+
+static void bridge_create_sysfs(struct platform_device *pdev)
+{
+ int error;
+
+ error = sysfs_create_group(pdev-dev.kobj, attr_group);
+
+ if (error)
+ kobject_put(pdev-dev.kobj);
+}
+
+static void bridge_destroy_sysfs(struct platform_device *pdev)
+{
+ sysfs_remove_group(pdev-dev.kobj, attr_group);
+}
+
/* Bridge driver initialization and de-initialization functions */
module_init(bridge_init);
module_exit(bridge_exit);
--
1.6.2.4
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[PATCH 3/8] DSPBRIDGE: Increased DMM size to 256MB
From: Hari Kanigeri h-kanige...@ti.com
This patch increases the DMM from 64MB to 256MB.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
Signed-off-by: Leed Aguilar leed.agui...@ti.com
---
arch/arm/plat-omap/include/dspbridge/dmm.h |2 +-
drivers/dsp/bridge/pmgr/dmm.c |8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/dmm.h
b/arch/arm/plat-omap/include/dspbridge/dmm.h
index 335edf8..af0c35a 100644
--- a/arch/arm/plat-omap/include/dspbridge/dmm.h
+++ b/arch/arm/plat-omap/include/dspbridge/dmm.h
@@ -41,7 +41,7 @@
u32 reserved;
} ;
-#define DMMPOOLSIZE 0x400
+#define DMMPOOLSIZE 0x1000
/*
* DMM_GetHandle
diff --git a/drivers/dsp/bridge/pmgr/dmm.c b/drivers/dsp/bridge/pmgr/dmm.c
index 46c05c6..f878855 100644
--- a/drivers/dsp/bridge/pmgr/dmm.c
+++ b/drivers/dsp/bridge/pmgr/dmm.c
@@ -103,10 +103,10 @@ static struct GT_Mask DMM_debugMask = { NULL, NULL };
/* GT trace variable */
static u32 cRefs; /* module reference count */
struct MapPage {
- u32 RegionSize:15;
- u32 MappedSize:15;
- u32 bReserved:1;
- u32 bMapped:1;
+ u64 RegionSize:31;
+ u64 MappedSize:31;
+ u64 bReserved:1;
+ u64 bMapped:1;
};
/* Create the free list */
--
1.6.2.4
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[PATCH 4/8] DSPBRIDGE: Remove unused hDrvObject in bridge_[open|release]
This patch removes an unused variable in bridge_open
and bridge_release functions, which reduces indentation.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
drivers/dsp/bridge/rmgr/drv_interface.c | 25 +
1 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c
b/drivers/dsp/bridge/rmgr/drv_interface.c
index 3a4d058..e551840 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -540,18 +540,10 @@ static void __exit bridge_exit(void)
static int bridge_open(struct inode *ip, struct file *filp)
{
int status = 0;
- DSP_STATUS dsp_status;
- HANDLE hDrvObject;
struct PROCESS_CONTEXT *pr_ctxt = NULL;
GT_0trace(driverTrace, GT_ENTER, - bridge_open\n);
- dsp_status = CFG_GetObject((u32 *)hDrvObject, REG_DRV_OBJECT);
- if (DSP_FAILED(dsp_status)) {
- status = -EIO;
- goto err;
- }
-
/*
* Allocate a new process context and insert it into global
* process context list.
@@ -564,7 +556,6 @@ static int bridge_open(struct inode *ip, struct file *filp)
filp-private_data = pr_ctxt;
-err:
GT_0trace(driverTrace, GT_ENTER, - bridge_open\n);
return status;
}
@@ -576,8 +567,6 @@ err:
static int bridge_release(struct inode *ip, struct file *filp)
{
int status = 0;
- DSP_STATUS dsp_status;
- HANDLE hDrvObject;
struct PROCESS_CONTEXT *pr_ctxt;
GT_0trace(driverTrace, GT_ENTER, - bridge_release\n);
@@ -588,15 +577,11 @@ static int bridge_release(struct inode *ip, struct file
*filp)
}
pr_ctxt = filp-private_data;
- dsp_status = CFG_GetObject((u32 *)hDrvObject, REG_DRV_OBJECT);
- if (DSP_SUCCEEDED(dsp_status)) {
- flush_signals(current);
- DRV_RemoveAllResources(pr_ctxt);
- PROC_Detach(pr_ctxt);
- MEM_Free(pr_ctxt);
- } else {
- status = -EIO;
- }
+ flush_signals(current);
+ DRV_RemoveAllResources(pr_ctxt);
+ PROC_Detach(pr_ctxt);
+ MEM_Free(pr_ctxt);
+
filp-private_data = NULL;
err:
--
1.6.2.4
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[PATCH 5/8] DSPBRIDGE: change to cpufreq_register_notifier for OPP changes
From: Fernando Guzman Lugo x0095...@ti.com
This patch changes clk_notifier_unregister with
cpufreq_unregister_notifier, which is used for OPP change
notifications
Signed-off-by: Fernando Guzman Lugo x0095...@ti.com
---
drivers/dsp/bridge/Kconfig |2 +-
drivers/dsp/bridge/rmgr/drv_interface.c | 25 +++--
2 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig
index e494f02..ea639e3 100644
--- a/drivers/dsp/bridge/Kconfig
+++ b/drivers/dsp/bridge/Kconfig
@@ -13,7 +13,7 @@ menuconfig MPU_BRIDGE
config BRIDGE_DVFS
bool Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)
- depends on MPU_BRIDGE OMAP_PM_SRF
+ depends on MPU_BRIDGE OMAP_PM_SRF CPU_FREQ
default n
help
DVFS allows DSP Bridge to initiate the operating point change to
diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c
b/drivers/dsp/bridge/rmgr/drv_interface.c
index e551840..d7aa8e0 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -240,15 +240,18 @@ u32 vdd1_dsp_freq[6][4] = {
};
#ifdef CONFIG_BRIDGE_DVFS
-static int dspbridge_post_scale(struct notifier_block *op, unsigned long level,
- void *ptr)
+static int dspbridge_scale_notification(struct notifier_block *op,
+ unsigned long val, void *ptr)
{
- PWR_PM_PostScale(PRCM_VDD1, level);
+ struct dspbridge_platform_data *pdata =
+ omap_dspbridge_dev-dev.platform_data;
+ if (CPUFREQ_POSTCHANGE == val pdata-dsp_get_opp)
+ PWR_PM_PostScale(PRCM_VDD1, pdata-dsp_get_opp());
return 0;
}
static struct notifier_block iva_clk_notifier = {
- .notifier_call = dspbridge_post_scale,
+ .notifier_call = dspbridge_scale_notification,
NULL,
};
#endif
@@ -387,12 +390,13 @@ static int __devinit omap34xx_bridge_probe(struct
platform_device *pdev)
GT_0trace(driverTrace, GT_7CLASS,
clk_get PASS to get iva2_ck \n);
}
- if (!clk_notifier_register(clk_handle, iva_clk_notifier)) {
+ if (!cpufreq_register_notifier(iva_clk_notifier,
+ CPUFREQ_TRANSITION_NOTIFIER)) {
GT_0trace(driverTrace, GT_7CLASS,
- clk_notifier_register PASS for iva2_ck \n);
+ cpufreq_register_notifier PASS for iva2_ck \n);
} else {
GT_0trace(driverTrace, GT_7CLASS,
- clk_notifier_register FAIL for iva2_ck \n);
+ cpufreq_register_notifier FAIL for iva2_ck \n);
}
#endif
driverContext = DSP_Init(initStatus);
@@ -436,12 +440,13 @@ static int __devexit omap34xx_bridge_remove(struct
platform_device *pdev)
goto func_cont;
#ifdef CONFIG_BRIDGE_DVFS
- if (!clk_notifier_unregister(clk_handle, iva_clk_notifier)) {
+ if (!cpufreq_unregister_notifier(iva_clk_notifier,
+ CPUFREQ_TRANSITION_NOTIFIER)) {
GT_0trace(driverTrace, GT_7CLASS,
- clk_notifier_unregister PASS for iva2_ck \n);
+ cpufreq_unregister_notifier PASS for iva2_ck \n);
} else {
GT_0trace(driverTrace, GT_7CLASS,
- clk_notifier_unregister FAILED for iva2_ck \n);
+ cpufreq_unregister_notifier FAILED for iva2_ck \n);
}
#endif /* #ifdef CONFIG_BRIDGE_DVFS */
--
1.6.2.4
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[PATCH 6/8] DSPBRIDGE: Use dspbridge to initialize platform data
Include dspbridge compilation whenever bridge driver is selected to be compiled, either as a module or part of the kernel. This will initialize platform data specific PM functions. Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/Makefile |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d1cf986..0881470 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -75,7 +75,9 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # Debobs obj-$(CONFIG_OMAP3_DEBOBS) += debobs.o -obj-$(CONFIG_MPU_BRIDGE) += dspbridge.o +ifneq ($(CONFIG_MPU_BRIDGE),) +obj-y += dspbridge.o +endif # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC)+= board-generic.o -- 1.6.2.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/8] DSPBRIDGE: Fix header locations mach to plat
Fix header locations, replaced mach to plat Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- arch/arm/mach-omap2/dspbridge.c|2 +- arch/arm/plat-omap/include/dspbridge/host_os.h |2 +- drivers/dsp/bridge/wmd/tiomap3430.c|2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/dspbridge.c b/arch/arm/mach-omap2/dspbridge.c index ea109a3..4150896 100644 --- a/arch/arm/mach-omap2/dspbridge.c +++ b/arch/arm/mach-omap2/dspbridge.c @@ -14,7 +14,7 @@ #include linux/platform_device.h #ifdef CONFIG_BRIDGE_DVFS -#include mach/omap-pm.h +#include plat/omap-pm.h #endif #include dspbridge/host_os.h diff --git a/arch/arm/plat-omap/include/dspbridge/host_os.h b/arch/arm/plat-omap/include/dspbridge/host_os.h index 6fe1462..74cf6d4 100644 --- a/arch/arm/plat-omap/include/dspbridge/host_os.h +++ b/arch/arm/plat-omap/include/dspbridge/host_os.h @@ -54,7 +54,7 @@ #include linux/ioport.h #include linux/platform_device.h #include dspbridge/dbtype.h -#include mach/clock.h +#include plat/clock.h #include linux/clk.h #include linux/pagemap.h #include asm/cacheflush.h diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c index 7138396..b123707 100644 --- a/drivers/dsp/bridge/wmd/tiomap3430.c +++ b/drivers/dsp/bridge/wmd/tiomap3430.c @@ -34,7 +34,7 @@ #include mach-omap2/cm.h #include mach-omap2/prm-regbits-34xx.h #include mach-omap2/cm-regbits-34xx.h -#include mach/control.h +#include plat/control.h /* --- DSP/BIOS Bridge */ #include dspbridge/std.h -- 1.6.2.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/8] DSPBRIDGE: Use _IOxx macro to define ioctls
- Use standard convention to define ioctls.
- Removed runtime check for ioctl matching table number.
- Added __deprectaed marker to functions that are not used anymore.
Currently 'DB' is used as identifier for dspbridge.
Added TODOs for removing the function table and, deprecated
and not implemented ioctls, this can be done when all the ioctls
are accessed through a switch instead of a pointer to function.
*** NOTE: An update in api ioctl definitions is required. ***
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
---
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 144 ++-
drivers/dsp/bridge/pmgr/wcd.c | 128 ++--
2 files changed, 129 insertions(+), 143 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
index 04b13ab..e7601c3 100644
--- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
+++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
@@ -437,83 +437,69 @@ union Trapped_Args {
} ARGS_UTIL_TESTDLL;
} ;
-#define CMD_BASE 1
-
-/* MGR module offsets */
-#define CMD_MGR_BASE_OFFSET CMD_BASE
-#define CMD_MGR_ENUMNODE_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 0)
-#define CMD_MGR_ENUMPROC_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 1)
-#define CMD_MGR_REGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 2)
-#define CMD_MGR_UNREGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 3)
-#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4)
-
-#ifndef RES_CLEANUP_DISABLE
-#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)
-#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET
-#else
-#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET
-#endif
-
-#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1)
-#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0)
-#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1)
-#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2)
-#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3)
-#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4)
-#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5)
-#define CMD_PROC_GETTRACE_OFFSET (CMD_PROC_BASE_OFFSET + 6)
-#define CMD_PROC_LOAD_OFFSET (CMD_PROC_BASE_OFFSET + 7)
-#define CMD_PROC_REGISTERNOTIFY_OFFSET (CMD_PROC_BASE_OFFSET + 8)
-#define CMD_PROC_START_OFFSET (CMD_PROC_BASE_OFFSET + 9)
-#define CMD_PROC_RSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 10)
-#define CMD_PROC_UNRSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 11)
-#define CMD_PROC_MAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 12)
-#define CMD_PROC_UNMAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 13)
-#define CMD_PROC_FLUSHMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 14)
-#define CMD_PROC_STOP_OFFSET (CMD_PROC_BASE_OFFSET + 15)
-#define CMD_PROC_INVALIDATEMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 16)
-#define CMD_PROC_END_OFFSET CMD_PROC_INVALIDATEMEMORY_OFFSET
-
-
-#define CMD_NODE_BASE_OFFSET (CMD_PROC_END_OFFSET + 1)
-#define CMD_NODE_ALLOCATE_OFFSET (CMD_NODE_BASE_OFFSET + 0)
-#define CMD_NODE_ALLOCMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 1)
-#define CMD_NODE_CHANGEPRIORITY_OFFSET (CMD_NODE_BASE_OFFSET + 2)
-#define CMD_NODE_CONNECT_OFFSET (CMD_NODE_BASE_OFFSET + 3)
-#define CMD_NODE_CREATE_OFFSET (CMD_NODE_BASE_OFFSET + 4)
-#define CMD_NODE_DELETE_OFFSET (CMD_NODE_BASE_OFFSET + 5)
-#define CMD_NODE_FREEMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 6)
-#define CMD_NODE_GETATTR_OFFSET (CMD_NODE_BASE_OFFSET + 7)
-#define CMD_NODE_GETMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 8)
-#define CMD_NODE_PAUSE_OFFSET (CMD_NODE_BASE_OFFSET + 9)
-#define CMD_NODE_PUTMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 10)
-#define CMD_NODE_REGISTERNOTIFY_OFFSET (CMD_NODE_BASE_OFFSET + 11)
-#define CMD_NODE_RUN_OFFSET (CMD_NODE_BASE_OFFSET + 12)
-#define CMD_NODE_TERMINATE_OFFSET (CMD_NODE_BASE_OFFSET + 13)
-#define CMD_NODE_GETUUIDPROPS_OFFSET(CMD_NODE_BASE_OFFSET + 14)
-#define CMD_NODE_END_OFFSET CMD_NODE_GETUUIDPROPS_OFFSET
-
-#define CMD_STRM_BASE_OFFSET (CMD_NODE_END_OFFSET + 1)
-#define CMD_STRM_ALLOCATEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 0)
-#define CMD_STRM_CLOSE_OFFSET (CMD_STRM_BASE_OFFSET + 1)
-#define CMD_STRM_FREEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 2)
-#define CMD_STRM_GETEVENTHANDLE_OFFSET (CMD_STRM_BASE_OFFSET + 3)
-#define CMD_STRM_GETINFO_OFFSET (CMD_STRM_BASE_OFFSET + 4)
-#define CMD_STRM_IDLE_OFFSET (CMD_STRM_BASE_OFFSET + 5)
-#define CMD_STRM_ISSUE_OFFSET (CMD_STRM_BASE_OFFSET + 6)
-#define CMD_STRM_OPEN_OFFSET (CMD_STRM_BASE_OFFSET + 7)
-#define CMD_STRM_RECLAIM_OFFSET (CMD_STRM_BASE_OFFSET + 8)
-#define CMD_STRM_REGISTERNOTIFY_OFFSET (CMD_STRM_BASE_OFFSET + 9)
-#define CMD_STRM_SELECT_OFFSET (CMD_STRM_BASE_OFFSET + 10)
-#define CMD_STRM_END_OFFSET CMD_STRM_SELECT_OFFSET
-
-/* Communication Memory
[PATCH] driver version 0.1
Given the on going efforts to review bridge patches, a branch has been published with all of the comments received a few weeks ago, the current dspbridge which is meant to be 0.1 can be found at: Branch: dspbridge @ http://dev.omapzoom.org/?p=tidspbridge/kernel-dspbridge.git;a=shortlog;h=refs/heads/dspbridge Special thanks to: - Felipe Contreras: for his comments and time during this sync up. - Hiroshi Doyu and Ameya Palande for their time reviewing patches. - And all who also have provided their comments. Omar Ramirez Luna (1): DSPBRIDGE: driver version 0.1 drivers/dsp/bridge/rmgr/drv_interface.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) CC: Felipe Contreras felipe.contre...@nokia.com CC: Hiroshi Doyu hiroshi.d...@nokia.com CC: Ameya Palande ameya.pala...@nokia.com CC: Nishant Menon n...@ti.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] DSPBRIDGE: driver version 0.1
This is the official 0.1 dspbridge version. CC: Felipe Contreras felipe.contre...@nokia.com CC: Hiroshi Doyu hiroshi.d...@nokia.com CC: Ameya Palande ameya.pala...@nokia.com CC: Nishant Menon n...@ti.com Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com --- drivers/dsp/bridge/rmgr/drv_interface.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c index c853854..efce35d 100644 --- a/drivers/dsp/bridge/rmgr/drv_interface.c +++ b/drivers/dsp/bridge/rmgr/drv_interface.c @@ -101,6 +101,7 @@ #define BRIDGE_NAME C6410 /* --- Globals */ #define DRIVER_NAME DspBridge +#define DSPBRIDGE_VERSION 0.1 s32 dsp_debug; struct platform_device *omap_dspbridge_dev; @@ -177,6 +178,7 @@ MODULE_PARM_DESC(tc_wordswapon, TC Word Swap Option. default = 0); MODULE_AUTHOR(Texas Instruments); MODULE_LICENSE(GPL); +MODULE_VERSION(DSPBRIDGE_VERSION); static char *driver_name = DRIVER_NAME; -- 1.6.2.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] DSPBRIDGE: Mark unused ioctls as deprecated
Mark unused ioctls as deprecated for future removal.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 11 --
drivers/dsp/bridge/pmgr/wcd.c | 38 +--
2 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
index 04b13ab..4b9dd0a 100644
--- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
+++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
@@ -439,6 +439,8 @@ union Trapped_Args {
#define CMD_BASE 1
+/* TODO: Remove deprecated and not implemented */
+
/* MGR module offsets */
#define CMD_MGR_BASE_OFFSET CMD_BASE
#define CMD_MGR_ENUMNODE_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 0)
@@ -448,7 +450,7 @@ union Trapped_Args {
#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4)
#ifndef RES_CLEANUP_DISABLE
-#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)
+#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)/*
Deprecated */
#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET
#else
#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET
@@ -457,7 +459,7 @@ union Trapped_Args {
#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1)
#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0)
#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1)
-#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2)
+#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2) /* Deprecated */
#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3)
#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4)
#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5)
@@ -497,6 +499,7 @@ union Trapped_Args {
#define CMD_STRM_ALLOCATEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 0)
#define CMD_STRM_CLOSE_OFFSET (CMD_STRM_BASE_OFFSET + 1)
#define CMD_STRM_FREEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 2)
+/* Not Impl'd */
#define CMD_STRM_GETEVENTHANDLE_OFFSET (CMD_STRM_BASE_OFFSET + 3)
#define CMD_STRM_GETINFO_OFFSET (CMD_STRM_BASE_OFFSET + 4)
#define CMD_STRM_IDLE_OFFSET (CMD_STRM_BASE_OFFSET + 5)
@@ -509,8 +512,8 @@ union Trapped_Args {
/* Communication Memory Manager (UCMM) */
#define CMD_CMM_BASE_OFFSET (CMD_STRM_END_OFFSET + 1)
-#define CMD_CMM_ALLOCBUF_OFFSET (CMD_CMM_BASE_OFFSET + 0)
-#define CMD_CMM_FREEBUF_OFFSET (CMD_CMM_BASE_OFFSET + 1)
+#define CMD_CMM_ALLOCBUF_OFFSET (CMD_CMM_BASE_OFFSET + 0)/* Not
Impl'd */
+#define CMD_CMM_FREEBUF_OFFSET (CMD_CMM_BASE_OFFSET + 1) /* Not Impl'd */
#define CMD_CMM_GETHANDLE_OFFSET (CMD_CMM_BASE_OFFSET + 2)
#define CMD_CMM_GETINFO_OFFSET (CMD_CMM_BASE_OFFSET + 3)
#define CMD_CMM_END_OFFSET CMD_CMM_GETINFO_OFFSET
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index 7226b5a..f95980b 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -456,6 +456,8 @@ DSP_STATUS WCD_InitComplete2(void)
return status;
}
+/* TODO: Remove deprecated and not implemented ioctl wrappers */
+
/*
* MGRWRAP_EnumNode_Info
*/
@@ -634,21 +636,11 @@ u32 MGRWRAP_WaitForBridgeEvents(union Trapped_Args *args,
void *pr_ctxt)
/*
* MGRWRAP_GetProcessResourceInfo
*/
-u32 MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args, void *pr_ctxt)
+u32 __deprecated MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args,
+ void *pr_ctxt)
{
-DSP_STATUS status = DSP_SOK;
-u32 uSize = 0;
-u8 *pBuf = MEM_Alloc(8092, MEM_NONPAGED);
-GT_1trace(WCD_debugMask, GT_ENTER,
-MGRWRAP_GetProcessResourcesInfo:uSize=%d :\n, uSize);
-cp_to_usr(args-ARGS_PROC_GETTRACE.pBuf, pBuf, status, uSize);
-GT_0trace(WCD_debugMask, GT_ENTER, \n***
-123MGRWRAP_GetProcessResourcesInfo:**\n);
-GT_0trace(WCD_debugMask, GT_ENTER, \n***
-456MGRWRAP_GetProcessResourcesInfo:**\n);
-cp_to_usr(args-ARGS_PROC_GETTRACE.pSize, uSize, status, 1);
-MEM_Free(pBuf);
-return status;
+ pr_err(%s: deprecated dspbridge ioctl\n, __func__);
+ return DSP_SOK;
}
#endif
@@ -732,14 +724,10 @@ func_end:
/*
* PROCWRAP_Detach
*/
-u32 PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt)
+u32 __deprecated PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt)
{
- GT_1trace(WCD_debugMask, GT_ENTER,
-PROCWRAP_Detach: entered args\n0x%x
-hProceesor \n, args-ARGS_PROC_DETACH.hProcessor);
-
/* PROC_Detach called at bridge_release only */
-
+ pr_err(%s: deprecated dspbridge ioctl\n, __func__);
return DSP_SOK
[PATCH 5/6] DSPBRIDGE: Rename pResult to result for WCD_CallDevIOCtl
Trivial cleanup, rename pResult to result for WCD_CallDevIOCtl
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
---
drivers/dsp/bridge/pmgr/wcd.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index 960b3cb..02def74 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -271,11 +271,11 @@ static inline void __cp_to_usr(void __user *to, const
void *from,
* Call the (wrapper) function for the corresponding WCD IOCTL.
*/
inline DSP_STATUS WCD_CallDevIOCtl(u32 cmd, union Trapped_Args *args,
- u32 *pResult, void *pr_ctxt)
+ u32 *result, void *pr_ctxt)
{
if (cmd ARRAY_SIZE(WCD_cmdTable)) {
/* make the fxn call via the cmd table */
- *pResult = (*WCD_cmdTable[cmd].fxn) (args, pr_ctxt);
+ *result = (*WCD_cmdTable[cmd].fxn) (args, pr_ctxt);
return DSP_SOK;
}
--
1.6.2.4
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[PATCH 4/6] DSPBRIDGE: remove ioctl runtime check
This patch removes the runtime check of device
ioctl array.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/pmgr/wcd.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index f95980b..960b3cb 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -321,13 +321,7 @@ bool WCD_Init(void)
bool fInit = true;
bool fDRV, fDEV, fCOD, fSERVICES, fCHNL, fMSG, fIO;
bool fMGR, fPROC, fNODE, fDISP, fNTFY, fSTRM, fRMM;
-#ifdef DEBUG
- /* runtime check of Device IOCtl array. */
- u32 i;
- for (i = 1; i ARRAY_SIZE(WCD_cmdTable); i++)
- DBC_Assert(WCD_cmdTable[i - 1].dwIndex == i);
-#endif
if (WCD_cRefs == 0) {
/* initialize all SERVICES modules */
fSERVICES = SERVICES_Init();
--
1.6.2.4
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[PATCH v2 0/6] misc patches
Ioctl numbers has changed, this will require an update on libbridge and clients accesing directly to the driver - IO_ADDRESS is replaced for ioremap. *v2 - dropped from the series: DSPBRIDGE: Increased DMM size to 256MB DSPBRIDGE: sysfs entry for global driver state - will be kept in bridge-pm DSPBRIDGE: Use dspbridge to initialize platform data DSPBRIDGE: change to cpufreq_register_notifier for OPP changes DSPBRIDGE: Fix header locations mach to plat - previously acked DSPBRIDGE: Remove unused hDrvObject in bridge_[open|release] Omar Ramirez Luna (6): DSPBRIDGE: replace IO_ADDRESS with ioremap DSPBRIDGE: Replace magic numbers in SSI configuration DSPBRIDGE: Mark unused ioctls as deprecated DSPBRIDGE: remove ioctl runtime check DSPBRIDGE: Rename pResult to result for WCD_CallDevIOCtl DSPBRIDGE: Use _IOxx macro to define ioctls arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 167 + drivers/dsp/bridge/pmgr/wcd.c | 228 +-- drivers/dsp/bridge/rmgr/drv_interface.c |3 - drivers/dsp/bridge/services/clk.c | 23 ++- 4 files changed, 234 insertions(+), 187 deletions(-) CC: Nishant Menon n...@ti.com CC: Hiroshi Doyu hiroshi.d...@nokia.com CC: Ameya Palande ameya.pala...@nokia.com CC: Felipe Contreras felipe.contre...@gmail.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] DSPBRIDGE: replace IO_ADDRESS with ioremap
Use ioremap() instead of using IO_ADDRESS macro to make it generic.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/services/clk.c | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/dsp/bridge/services/clk.c
b/drivers/dsp/bridge/services/clk.c
index d1c68fc..116e10e 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -54,10 +54,9 @@
typedef volatile unsigned long REG_UWORD32;
-#define SSI_Base0x48058000
-
-#define SSI_BASE IO_ADDRESS(SSI_Base)
-
+#define OMAP_SSI_OFFSET0x58000
+#define OMAP_SSI_SIZE 0x1000
+#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
struct SERVICES_Clk_t {
struct clk *clk_handle;
@@ -355,7 +354,9 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id)
void SSI_Clk_Prepare(bool FLAG)
{
u32 ssi_sysconfig;
- ssi_sysconfig = __raw_readl((SSI_BASE) + 0x10);
+ void __iomem *ssi_base;
+
+ ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
if (FLAG) {
/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
@@ -368,5 +369,7 @@ void SSI_Clk_Prepare(bool FLAG)
*/
ssi_sysconfig = 0x1;
}
- __raw_writel((u32)ssi_sysconfig, SSI_BASE + 0x10);
+
+ __raw_writel(ssi_sysconfig, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
+ iounmap(ssi_base);
}
--
1.6.2.4
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[PATCH 2/6] DSPBRIDGE: Replace magic numbers in SSI configuration
Rename ssi_sysconfig variable and replace the usage of magic
numbers while updating SSI configuration.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/services/clk.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/dsp/bridge/services/clk.c
b/drivers/dsp/bridge/services/clk.c
index 116e10e..0537487 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -58,6 +58,10 @@ typedef volatile unsigned long REG_UWORD32;
#define OMAP_SSI_SIZE 0x1000
#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
+#define SSI_AUTOIDLE (1 0)
+#define SSI_SIDLE_SMARTIDLE(2 3)
+#define SSI_MIDLE_NOIDLE (1 12)
+
struct SERVICES_Clk_t {
struct clk *clk_handle;
const char *clk_name;
@@ -353,8 +357,8 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id)
void SSI_Clk_Prepare(bool FLAG)
{
- u32 ssi_sysconfig;
void __iomem *ssi_base;
+ unsigned int value;
ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
@@ -362,14 +366,14 @@ void SSI_Clk_Prepare(bool FLAG)
/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
* no idle
*/
- ssi_sysconfig = 0x1011;
+ value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
} else {
/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
* forced idle
*/
- ssi_sysconfig = 0x1;
+ value = SSI_AUTOIDLE;
}
- __raw_writel(ssi_sysconfig, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
+ __raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
iounmap(ssi_base);
}
--
1.6.2.4
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[PATCH 6/6] DSPBRIDGE: Use _IOxx macro to define ioctls
- Use standard convention to define ioctls.
Currently 0xDB is used as identifier for dspbridge.
Discussion:
http://marc.info/?l=linux-omapm=126297631603035w=2
WARNING:
An update in api ioctl definitions is required, usually replacing
to a new libbridge (with ioctl patch) should be enough. Other
clients (not using libbridge) need to update their ioctl numbers
manually.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishant Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 164 +++--
drivers/dsp/bridge/pmgr/wcd.c | 182 ++-
drivers/dsp/bridge/rmgr/drv_interface.c |3 -
3 files changed, 200 insertions(+), 149 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
index 4b9dd0a..452be83 100644
--- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
+++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
@@ -437,86 +437,92 @@ union Trapped_Args {
} ARGS_UTIL_TESTDLL;
} ;
-#define CMD_BASE 1
+/* Ioctl driver name */
+#define DB 0xDB
+
+/* Ioctl module masks */
+#define DB_MGR 0x0
+#define DB_PROC0x20
+#define DB_NODE0x40
+#define DB_STRM0x60
+#define DB_CMM 0x80
+
+/*
+ * Following are used to distinguish between module ioctls, this is needed
+ * in case new ioctls are introduced.
+ */
+#define DB_MODULE_MASK 0xE0
+#define DB_IOC_MASK0x1F
+
+/* Macro used to calculate the ioctl per dspbridge module */
+#define DB_IOC(module, num) \
+ (((module) DB_MODULE_MASK) | ((num) DB_IOC_MASK))
/* TODO: Remove deprecated and not implemented */
-/* MGR module offsets */
-#define CMD_MGR_BASE_OFFSET CMD_BASE
-#define CMD_MGR_ENUMNODE_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 0)
-#define CMD_MGR_ENUMPROC_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 1)
-#define CMD_MGR_REGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 2)
-#define CMD_MGR_UNREGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 3)
-#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4)
-
-#ifndef RES_CLEANUP_DISABLE
-#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)/*
Deprecated */
-#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET
-#else
-#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET
-#endif
-
-#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1)
-#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0)
-#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1)
-#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2) /* Deprecated */
-#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3)
-#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4)
-#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5)
-#define CMD_PROC_GETTRACE_OFFSET (CMD_PROC_BASE_OFFSET + 6)
-#define CMD_PROC_LOAD_OFFSET (CMD_PROC_BASE_OFFSET + 7)
-#define CMD_PROC_REGISTERNOTIFY_OFFSET (CMD_PROC_BASE_OFFSET + 8)
-#define CMD_PROC_START_OFFSET (CMD_PROC_BASE_OFFSET + 9)
-#define CMD_PROC_RSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 10)
-#define CMD_PROC_UNRSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 11)
-#define CMD_PROC_MAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 12)
-#define CMD_PROC_UNMAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 13)
-#define CMD_PROC_FLUSHMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 14)
-#define CMD_PROC_STOP_OFFSET (CMD_PROC_BASE_OFFSET + 15)
-#define CMD_PROC_INVALIDATEMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 16)
-#define CMD_PROC_END_OFFSET CMD_PROC_INVALIDATEMEMORY_OFFSET
-
-
-#define CMD_NODE_BASE_OFFSET (CMD_PROC_END_OFFSET + 1)
-#define CMD_NODE_ALLOCATE_OFFSET (CMD_NODE_BASE_OFFSET + 0)
-#define CMD_NODE_ALLOCMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 1)
-#define CMD_NODE_CHANGEPRIORITY_OFFSET (CMD_NODE_BASE_OFFSET + 2)
-#define CMD_NODE_CONNECT_OFFSET (CMD_NODE_BASE_OFFSET + 3)
-#define CMD_NODE_CREATE_OFFSET (CMD_NODE_BASE_OFFSET + 4)
-#define CMD_NODE_DELETE_OFFSET (CMD_NODE_BASE_OFFSET + 5)
-#define CMD_NODE_FREEMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 6)
-#define CMD_NODE_GETATTR_OFFSET (CMD_NODE_BASE_OFFSET + 7)
-#define CMD_NODE_GETMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 8)
-#define CMD_NODE_PAUSE_OFFSET (CMD_NODE_BASE_OFFSET + 9)
-#define CMD_NODE_PUTMESSAGE_OFFSET (CMD_NODE_BASE_OFFSET + 10)
-#define CMD_NODE_REGISTERNOTIFY_OFFSET (CMD_NODE_BASE_OFFSET + 11)
-#define CMD_NODE_RUN_OFFSET (CMD_NODE_BASE_OFFSET + 12)
-#define CMD_NODE_TERMINATE_OFFSET (CMD_NODE_BASE_OFFSET + 13)
-#define CMD_NODE_GETUUIDPROPS_OFFSET(CMD_NODE_BASE_OFFSET + 14)
-#define CMD_NODE_END_OFFSET CMD_NODE_GETUUIDPROPS_OFFSET
-
-#define CMD_STRM_BASE_OFFSET
[PATCH v3 4/7] DSPBRIDGE: remove ioctl runtime check
This patch removes the runtime check of device
ioctl array.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/pmgr/wcd.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index f95980b..960b3cb 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -321,13 +321,7 @@ bool WCD_Init(void)
bool fInit = true;
bool fDRV, fDEV, fCOD, fSERVICES, fCHNL, fMSG, fIO;
bool fMGR, fPROC, fNODE, fDISP, fNTFY, fSTRM, fRMM;
-#ifdef DEBUG
- /* runtime check of Device IOCtl array. */
- u32 i;
- for (i = 1; i ARRAY_SIZE(WCD_cmdTable); i++)
- DBC_Assert(WCD_cmdTable[i - 1].dwIndex == i);
-#endif
if (WCD_cRefs == 0) {
/* initialize all SERVICES modules */
fSERVICES = SERVICES_Init();
--
1.6.2.4
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[PATCH v3 3/7] DSPBRIDGE: Mark unused ioctls as deprecated
Mark unused ioctls as deprecated for future removal
and print an error message whenever they are used.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 11 --
drivers/dsp/bridge/pmgr/wcd.c | 38 +--
2 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
index 04b13ab..4b9dd0a 100644
--- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
+++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
@@ -439,6 +439,8 @@ union Trapped_Args {
#define CMD_BASE 1
+/* TODO: Remove deprecated and not implemented */
+
/* MGR module offsets */
#define CMD_MGR_BASE_OFFSET CMD_BASE
#define CMD_MGR_ENUMNODE_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 0)
@@ -448,7 +450,7 @@ union Trapped_Args {
#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4)
#ifndef RES_CLEANUP_DISABLE
-#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)
+#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)/*
Deprecated */
#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET
#else
#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET
@@ -457,7 +459,7 @@ union Trapped_Args {
#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1)
#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0)
#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1)
-#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2)
+#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2) /* Deprecated */
#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3)
#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4)
#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5)
@@ -497,6 +499,7 @@ union Trapped_Args {
#define CMD_STRM_ALLOCATEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 0)
#define CMD_STRM_CLOSE_OFFSET (CMD_STRM_BASE_OFFSET + 1)
#define CMD_STRM_FREEBUFFER_OFFSET (CMD_STRM_BASE_OFFSET + 2)
+/* Not Impl'd */
#define CMD_STRM_GETEVENTHANDLE_OFFSET (CMD_STRM_BASE_OFFSET + 3)
#define CMD_STRM_GETINFO_OFFSET (CMD_STRM_BASE_OFFSET + 4)
#define CMD_STRM_IDLE_OFFSET (CMD_STRM_BASE_OFFSET + 5)
@@ -509,8 +512,8 @@ union Trapped_Args {
/* Communication Memory Manager (UCMM) */
#define CMD_CMM_BASE_OFFSET (CMD_STRM_END_OFFSET + 1)
-#define CMD_CMM_ALLOCBUF_OFFSET (CMD_CMM_BASE_OFFSET + 0)
-#define CMD_CMM_FREEBUF_OFFSET (CMD_CMM_BASE_OFFSET + 1)
+#define CMD_CMM_ALLOCBUF_OFFSET (CMD_CMM_BASE_OFFSET + 0)/* Not
Impl'd */
+#define CMD_CMM_FREEBUF_OFFSET (CMD_CMM_BASE_OFFSET + 1) /* Not Impl'd */
#define CMD_CMM_GETHANDLE_OFFSET (CMD_CMM_BASE_OFFSET + 2)
#define CMD_CMM_GETINFO_OFFSET (CMD_CMM_BASE_OFFSET + 3)
#define CMD_CMM_END_OFFSET CMD_CMM_GETINFO_OFFSET
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index 7226b5a..f95980b 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -456,6 +456,8 @@ DSP_STATUS WCD_InitComplete2(void)
return status;
}
+/* TODO: Remove deprecated and not implemented ioctl wrappers */
+
/*
* MGRWRAP_EnumNode_Info
*/
@@ -634,21 +636,11 @@ u32 MGRWRAP_WaitForBridgeEvents(union Trapped_Args *args,
void *pr_ctxt)
/*
* MGRWRAP_GetProcessResourceInfo
*/
-u32 MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args, void *pr_ctxt)
+u32 __deprecated MGRWRAP_GetProcessResourcesInfo(union Trapped_Args *args,
+ void *pr_ctxt)
{
-DSP_STATUS status = DSP_SOK;
-u32 uSize = 0;
-u8 *pBuf = MEM_Alloc(8092, MEM_NONPAGED);
-GT_1trace(WCD_debugMask, GT_ENTER,
-MGRWRAP_GetProcessResourcesInfo:uSize=%d :\n, uSize);
-cp_to_usr(args-ARGS_PROC_GETTRACE.pBuf, pBuf, status, uSize);
-GT_0trace(WCD_debugMask, GT_ENTER, \n***
-123MGRWRAP_GetProcessResourcesInfo:**\n);
-GT_0trace(WCD_debugMask, GT_ENTER, \n***
-456MGRWRAP_GetProcessResourcesInfo:**\n);
-cp_to_usr(args-ARGS_PROC_GETTRACE.pSize, uSize, status, 1);
-MEM_Free(pBuf);
-return status;
+ pr_err(%s: deprecated dspbridge ioctl\n, __func__);
+ return DSP_SOK;
}
#endif
@@ -732,14 +724,10 @@ func_end:
/*
* PROCWRAP_Detach
*/
-u32 PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt)
+u32 __deprecated PROCWRAP_Detach(union Trapped_Args *args, void *pr_ctxt)
{
- GT_1trace(WCD_debugMask, GT_ENTER,
-PROCWRAP_Detach: entered args\n0x%x
-hProceesor \n, args-ARGS_PROC_DETACH.hProcessor
[PATCH v3 1/7] DSPBRIDGE: replace IO_ADDRESS with ioremap
Use ioremap() instead of using IO_ADDRESS macro to make it generic.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Tony Lindgren t...@atomide.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/services/clk.c | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/dsp/bridge/services/clk.c
b/drivers/dsp/bridge/services/clk.c
index d1c68fc..21a61d8 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -54,10 +54,9 @@
typedef volatile unsigned long REG_UWORD32;
-#define SSI_Base0x48058000
-
-#define SSI_BASE IO_ADDRESS(SSI_Base)
-
+#define OMAP_SSI_OFFSET0x58000
+#define OMAP_SSI_SIZE 0x1000
+#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
struct SERVICES_Clk_t {
struct clk *clk_handle;
@@ -355,7 +354,13 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id)
void SSI_Clk_Prepare(bool FLAG)
{
u32 ssi_sysconfig;
- ssi_sysconfig = __raw_readl((SSI_BASE) + 0x10);
+ void __iomem *ssi_base;
+
+ ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
+ if (!ssi_base) {
+ pr_err(%s: error, SSI not configured\n, __func__);
+ return;
+ }
if (FLAG) {
/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
@@ -368,5 +373,7 @@ void SSI_Clk_Prepare(bool FLAG)
*/
ssi_sysconfig = 0x1;
}
- __raw_writel((u32)ssi_sysconfig, SSI_BASE + 0x10);
+
+ __raw_writel(ssi_sysconfig, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
+ iounmap(ssi_base);
}
--
1.6.2.4
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[PATCH v3 6/7] DSPBRIDGE: Use _IOxx macro to define ioctls
- Use standard convention to define ioctls.
Currently 0xDB is used as identifier for dspbridge.
Discussion:
http://marc.info/?l=linux-omapm=126297631603035w=2
WARNING:
An update in api ioctl definitions is required, usually replacing
to a new libbridge (with ioctl patch) should be enough. Other
clients (not using libbridge) need to update their ioctl numbers
manually.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
arch/arm/plat-omap/include/dspbridge/wcdioctl.h | 181 -
drivers/dsp/bridge/pmgr/wcd.c | 200 +++
drivers/dsp/bridge/rmgr/drv_interface.c |3 -
3 files changed, 237 insertions(+), 147 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
index 4b9dd0a..656d56b 100644
--- a/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
+++ b/arch/arm/plat-omap/include/dspbridge/wcdioctl.h
@@ -437,86 +437,109 @@ union Trapped_Args {
} ARGS_UTIL_TESTDLL;
} ;
-#define CMD_BASE 1
+/*
+ * Dspbridge Ioctl numbering scheme
+ *
+ *7 0
+ * -
+ * | Module | Ioctl Number|
+ * -
+ * | x | x | x | 0 | 0 | 0 | 0 | 0 |
+ * -
+ */
+
+/* Ioctl driver identifier */
+#define DB 0xDB
+
+/*
+ * Following are used to distinguish between module ioctls, this is needed
+ * in case new ioctls are introduced.
+ */
+#define DB_MODULE_MASK 0xE0
+#define DB_IOC_MASK0x1F
+
+/* Ioctl module masks */
+#define DB_MGR 0x0
+#define DB_PROC0x20
+#define DB_NODE0x40
+#define DB_STRM0x60
+#define DB_CMM 0x80
+
+#define DB_MODULE_SHIFT5
+
+/* Used to calculate the ioctl per dspbridge module */
+#define DB_IOC(module, num) \
+ (((module) DB_MODULE_MASK) | ((num) DB_IOC_MASK))
+/* Used to get dspbridge ioctl module */
+#define DB_GET_MODULE(cmd) ((cmd) DB_MODULE_MASK)
+/* Used to get dspbridge ioctl number */
+#define DB_GET_IOC(cmd)((cmd) DB_IOC_MASK)
/* TODO: Remove deprecated and not implemented */
-/* MGR module offsets */
-#define CMD_MGR_BASE_OFFSET CMD_BASE
-#define CMD_MGR_ENUMNODE_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 0)
-#define CMD_MGR_ENUMPROC_INFO_OFFSET(CMD_MGR_BASE_OFFSET + 1)
-#define CMD_MGR_REGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 2)
-#define CMD_MGR_UNREGISTEROBJECT_OFFSET (CMD_MGR_BASE_OFFSET + 3)
-#define CMD_MGR_WAIT_OFFSET (CMD_MGR_BASE_OFFSET + 4)
-
-#ifndef RES_CLEANUP_DISABLE
-#define CMD_MGR_RESOUCES_OFFSET (CMD_MGR_BASE_OFFSET + 5)/*
Deprecated */
-#define CMD_MGR_END_OFFSET CMD_MGR_RESOUCES_OFFSET
-#else
-#define CMD_MGR_END_OFFSET CMD_MGR_WAIT_OFFSET
-#endif
-
-#define CMD_PROC_BASE_OFFSET (CMD_MGR_END_OFFSET + 1)
-#define CMD_PROC_ATTACH_OFFSET (CMD_PROC_BASE_OFFSET + 0)
-#define CMD_PROC_CTRL_OFFSET (CMD_PROC_BASE_OFFSET + 1)
-#define CMD_PROC_DETACH_OFFSET (CMD_PROC_BASE_OFFSET + 2) /* Deprecated */
-#define CMD_PROC_ENUMNODE_OFFSET (CMD_PROC_BASE_OFFSET + 3)
-#define CMD_PROC_ENUMRESOURCES_OFFSET (CMD_PROC_BASE_OFFSET + 4)
-#define CMD_PROC_GETSTATE_OFFSET (CMD_PROC_BASE_OFFSET + 5)
-#define CMD_PROC_GETTRACE_OFFSET (CMD_PROC_BASE_OFFSET + 6)
-#define CMD_PROC_LOAD_OFFSET (CMD_PROC_BASE_OFFSET + 7)
-#define CMD_PROC_REGISTERNOTIFY_OFFSET (CMD_PROC_BASE_OFFSET + 8)
-#define CMD_PROC_START_OFFSET (CMD_PROC_BASE_OFFSET + 9)
-#define CMD_PROC_RSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 10)
-#define CMD_PROC_UNRSVMEM_OFFSET (CMD_PROC_BASE_OFFSET + 11)
-#define CMD_PROC_MAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 12)
-#define CMD_PROC_UNMAPMEM_OFFSET (CMD_PROC_BASE_OFFSET + 13)
-#define CMD_PROC_FLUSHMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 14)
-#define CMD_PROC_STOP_OFFSET (CMD_PROC_BASE_OFFSET + 15)
-#define CMD_PROC_INVALIDATEMEMORY_OFFSET (CMD_PROC_BASE_OFFSET + 16)
-#define CMD_PROC_END_OFFSET CMD_PROC_INVALIDATEMEMORY_OFFSET
-
-
-#define CMD_NODE_BASE_OFFSET (CMD_PROC_END_OFFSET + 1)
-#define CMD_NODE_ALLOCATE_OFFSET (CMD_NODE_BASE_OFFSET + 0)
-#define CMD_NODE_ALLOCMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 1)
-#define CMD_NODE_CHANGEPRIORITY_OFFSET (CMD_NODE_BASE_OFFSET + 2)
-#define CMD_NODE_CONNECT_OFFSET (CMD_NODE_BASE_OFFSET + 3)
-#define CMD_NODE_CREATE_OFFSET (CMD_NODE_BASE_OFFSET + 4)
-#define CMD_NODE_DELETE_OFFSET (CMD_NODE_BASE_OFFSET + 5)
-#define CMD_NODE_FREEMSGBUF_OFFSET (CMD_NODE_BASE_OFFSET + 6)
-#define CMD_NODE_GETATTR_OFFSET (CMD_NODE_BASE_OFFSET + 7)
-#define CMD_NODE_GETMESSAGE_OFFSET
[PATCH v3 7/7] DSPBRIDGE: remove WCD_Cmd structure
Remove WCD_Cmd structure given that only one member is being
used (fxn call), this structure is replaced for a definition
of an array of function pointers for each dspbridge ioctl
module.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/pmgr/wcd.c | 134 +++-
1 files changed, 64 insertions(+), 70 deletions(-)
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index 27e8e8e..37d1f8a 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -147,12 +147,6 @@
/* Used to get dspbridge ioctl table */
#define DB_GET_IOC_TABLE(cmd) (DB_GET_MODULE(cmd) DB_MODULE_SHIFT)
-/* Device IOCtl function pointer */
-struct WCD_Cmd {
- u32(*fxn)(union Trapped_Args *args, void *pr_ctxt);
- u32 dwIndex;
-} ;
-
/* --- Globals */
#if GT_TRACE
static struct GT_Mask WCD_debugMask = { NULL, NULL }; /* Core VxD Mask */
@@ -167,80 +161,80 @@ static u32 WCD_cRefs;
*/
/* MGR wrapper functions */
-static struct WCD_Cmd mgr_cmd[] = {
- {MGRWRAP_EnumNode_Info},/* MGR_ENUMNODE_INFO */
- {MGRWRAP_EnumProc_Info},/* MGR_ENUMPROC_INFO */
- {MGRWRAP_RegisterObject}, /* MGR_REGISTEROBJECT */
- {MGRWRAP_UnregisterObject}, /* MGR_UNREGISTEROBJECT */
- {MGRWRAP_WaitForBridgeEvents}, /* MGR_WAIT */
+static u32 (*mgr_cmd[])(union Trapped_Args *args, void *pr_ctxt) = {
+ MGRWRAP_EnumNode_Info, /* MGR_ENUMNODE_INFO */
+ MGRWRAP_EnumProc_Info, /* MGR_ENUMPROC_INFO */
+ MGRWRAP_RegisterObject, /* MGR_REGISTEROBJECT */
+ MGRWRAP_UnregisterObject, /* MGR_UNREGISTEROBJECT */
+ MGRWRAP_WaitForBridgeEvents,/* MGR_WAIT */
#ifndef RES_CLEANUP_DISABLE
- {MGRWRAP_GetProcessResourcesInfo}, /* MGR_GET_PROC_RES */
+ MGRWRAP_GetProcessResourcesInfo,/* MGR_GET_PROC_RES */
#else
- {NULL},
+ NULL,
#endif
};
/* PROC wrapper functions */
-static struct WCD_Cmd proc_cmd[] = {
- {PROCWRAP_Attach}, /* PROC_ATTACH */
- {PROCWRAP_Ctrl},/* PROC_CTRL */
- {PROCWRAP_Detach}, /* PROC_DETACH */
- {PROCWRAP_EnumNode_Info}, /* PROC_ENUMNODE */
- {PROCWRAP_EnumResources}, /* PROC_ENUMRESOURCES */
- {PROCWRAP_GetState},/* PROC_GET_STATE */
- {PROCWRAP_GetTrace},/* PROC_GET_TRACE */
- {PROCWRAP_Load},/* PROC_LOAD */
- {PROCWRAP_RegisterNotify}, /* PROC_REGISTERNOTIFY */
- {PROCWRAP_Start}, /* PROC_START */
- {PROCWRAP_ReserveMemory}, /* PROC_RSVMEM */
- {PROCWRAP_UnReserveMemory}, /* PROC_UNRSVMEM */
- {PROCWRAP_Map}, /* PROC_MAPMEM */
- {PROCWRAP_UnMap}, /* PROC_UNMAPMEM */
- {PROCWRAP_FlushMemory}, /* PROC_FLUSHMEMORY */
- {PROCWRAP_Stop},/* PROC_STOP */
- {PROCWRAP_InvalidateMemory},/* PROC_INVALIDATEMEMORY */
+static u32 (*proc_cmd[])(union Trapped_Args *args, void *pr_ctxt) = {
+ PROCWRAP_Attach,/* PROC_ATTACH */
+ PROCWRAP_Ctrl, /* PROC_CTRL */
+ PROCWRAP_Detach,/* PROC_DETACH */
+ PROCWRAP_EnumNode_Info, /* PROC_ENUMNODE */
+ PROCWRAP_EnumResources, /* PROC_ENUMRESOURCES */
+ PROCWRAP_GetState, /* PROC_GET_STATE */
+ PROCWRAP_GetTrace, /* PROC_GET_TRACE */
+ PROCWRAP_Load, /* PROC_LOAD */
+ PROCWRAP_RegisterNotify,/* PROC_REGISTERNOTIFY */
+ PROCWRAP_Start, /* PROC_START */
+ PROCWRAP_ReserveMemory, /* PROC_RSVMEM */
+ PROCWRAP_UnReserveMemory, /* PROC_UNRSVMEM */
+ PROCWRAP_Map, /* PROC_MAPMEM */
+ PROCWRAP_UnMap, /* PROC_UNMAPMEM */
+ PROCWRAP_FlushMemory, /* PROC_FLUSHMEMORY */
+ PROCWRAP_Stop, /* PROC_STOP */
+ PROCWRAP_InvalidateMemory, /* PROC_INVALIDATEMEMORY */
};
/* NODE wrapper functions */
-static struct WCD_Cmd node_cmd[] = {
- {NODEWRAP_Allocate},/* NODE_ALLOCATE */
- {NODEWRAP_AllocMsgBuf}, /* NODE_ALLOCMSGBUF */
- {NODEWRAP_ChangePriority}, /* NODE_CHANGEPRIORITY
[PATCH v3 5/7] DSPBRIDGE: Rename pResult to result for WCD_CallDevIOCtl
Trivial cleanup, rename pResult to result for WCD_CallDevIOCtl
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/pmgr/wcd.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c
index 960b3cb..02def74 100644
--- a/drivers/dsp/bridge/pmgr/wcd.c
+++ b/drivers/dsp/bridge/pmgr/wcd.c
@@ -271,11 +271,11 @@ static inline void __cp_to_usr(void __user *to, const
void *from,
* Call the (wrapper) function for the corresponding WCD IOCTL.
*/
inline DSP_STATUS WCD_CallDevIOCtl(u32 cmd, union Trapped_Args *args,
- u32 *pResult, void *pr_ctxt)
+ u32 *result, void *pr_ctxt)
{
if (cmd ARRAY_SIZE(WCD_cmdTable)) {
/* make the fxn call via the cmd table */
- *pResult = (*WCD_cmdTable[cmd].fxn) (args, pr_ctxt);
+ *result = (*WCD_cmdTable[cmd].fxn) (args, pr_ctxt);
return DSP_SOK;
}
--
1.6.2.4
--
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[PATCH v3 2/7] DSPBRIDGE: Replace magic numbers in SSI configuration
Rename ssi_sysconfig variable and replace the usage of magic
numbers while updating SSI configuration.
Signed-off-by: Omar Ramirez Luna omar.rami...@ti.com
CC: Nishanth Menon n...@ti.com
CC: Hiroshi Doyu hiroshi.d...@nokia.com
CC: Ameya Palande ameya.pala...@nokia.com
CC: Felipe Contreras felipe.contre...@gmail.com
---
drivers/dsp/bridge/services/clk.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/dsp/bridge/services/clk.c
b/drivers/dsp/bridge/services/clk.c
index 21a61d8..d6b2259 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -58,6 +58,10 @@ typedef volatile unsigned long REG_UWORD32;
#define OMAP_SSI_SIZE 0x1000
#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
+#define SSI_AUTOIDLE (1 0)
+#define SSI_SIDLE_SMARTIDLE(2 3)
+#define SSI_MIDLE_NOIDLE (1 12)
+
struct SERVICES_Clk_t {
struct clk *clk_handle;
const char *clk_name;
@@ -353,8 +357,8 @@ s32 CLK_Get_UseCnt(IN enum SERVICES_ClkId clk_id)
void SSI_Clk_Prepare(bool FLAG)
{
- u32 ssi_sysconfig;
void __iomem *ssi_base;
+ unsigned int value;
ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
if (!ssi_base) {
@@ -366,14 +370,14 @@ void SSI_Clk_Prepare(bool FLAG)
/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
* no idle
*/
- ssi_sysconfig = 0x1011;
+ value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
} else {
/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
* forced idle
*/
- ssi_sysconfig = 0x1;
+ value = SSI_AUTOIDLE;
}
- __raw_writel(ssi_sysconfig, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
+ __raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
iounmap(ssi_base);
}
--
1.6.2.4
--
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[PATCH 1/3] DSPBRIDGE: Interface tightening to check for invalid input parameters
From: Ernesto Ramos erne...@ti.com Add more error checking and range to address usecases accessing kernel APIs directly. Signed-off-by: Ernesto Ramos erne...@ti.com CC: Nishanth Menon n...@ti.com CC: Hiroshi Doyu hiroshi.d...@nokia.com CC: Ameya Palande ameya.pala...@nokia.com --- arch/arm/plat-omap/include/dspbridge/dbdefs.h |4 +- drivers/dsp/bridge/pmgr/wcd.c | 91 +++- drivers/dsp/bridge/services/mem.c |4 - 3 files changed, 75 insertions(+), 24 deletions(-) diff --git a/arch/arm/plat-omap/include/dspbridge/dbdefs.h b/arch/arm/plat-omap/include/dspbridge/dbdefs.h index acd291f..f77de39 100644 --- a/arch/arm/plat-omap/include/dspbridge/dbdefs.h +++ b/arch/arm/plat-omap/include/dspbridge/dbdefs.h @@ -217,7 +217,9 @@ DSP_DCDLIBRARYTYPE, DSP_DCDCREATELIBTYPE, DSP_DCDEXECUTELIBTYPE, - DSP_DCDDELETELIBTYPE + DSP_DCDDELETELIBTYPE, + /* DSP_DCDMAXOBJTYPE is meant to be the last DCD object type */ + DSP_DCDMAXOBJTYPE } ; /* Processor states */ diff --git a/drivers/dsp/bridge/pmgr/wcd.c b/drivers/dsp/bridge/pmgr/wcd.c index 39e3110..006ca63 100644 --- a/drivers/dsp/bridge/pmgr/wcd.c +++ b/drivers/dsp/bridge/pmgr/wcd.c @@ -539,6 +539,10 @@ u32 MGRWRAP_EnumNode_Info(union Trapped_Args *args, void *pr_ctxt) args-ARGS_MGR_ENUMNODE_INFO.pNDBProps, args-ARGS_MGR_ENUMNODE_INFO.uNDBPropsSize, args-ARGS_MGR_ENUMNODE_INFO.puNumNodes); + + if (size sizeof(struct DSP_NDBPROPS)) + return DSP_ESIZE; + pNDBProps = MEM_Alloc(size, MEM_NONPAGED); if (pNDBProps == NULL) status = DSP_EMEMORY; @@ -576,6 +580,10 @@ u32 MGRWRAP_EnumProc_Info(union Trapped_Args *args, void *pr_ctxt) args-ARGS_MGR_ENUMPROC_INFO.pProcessorInfo, args-ARGS_MGR_ENUMPROC_INFO.uProcessorInfoSize, args-ARGS_MGR_ENUMPROC_INFO.puNumProcs); + + if (size sizeof(struct DSP_PROCESSORINFO)) + return DSP_ESIZE; + pProcessorInfo = MEM_Alloc(size, MEM_NONPAGED); if (pProcessorInfo == NULL) status = DSP_EMEMORY; @@ -608,6 +616,11 @@ u32 MGRWRAP_RegisterObject(union Trapped_Args *args, void *pr_ctxt) char *pszPathName = NULL; DSP_STATUS status = DSP_SOK; + + GT_1trace(WCD_debugMask, GT_ENTER, +MGRWRAP_RegisterObject: entered +0x%x\n, args-ARGS_MGR_REGISTEROBJECT.pUuid); + cp_fm_usr(pUuid, args-ARGS_MGR_REGISTEROBJECT.pUuid, status, 1); if (DSP_FAILED(status)) goto func_end; @@ -625,9 +638,9 @@ u32 MGRWRAP_RegisterObject(union Trapped_Args *args, void *pr_ctxt) goto func_end; } - GT_1trace(WCD_debugMask, GT_ENTER, -MGRWRAP_RegisterObject: entered pg2hMsg -0x%x\n, args-ARGS_MGR_REGISTEROBJECT.pUuid); + if (args-ARGS_MGR_REGISTEROBJECT.objType = DSP_DCDMAXOBJTYPE) + return DSP_EINVALIDARG; + status = DCD_RegisterObject(pUuid, args-ARGS_MGR_REGISTEROBJECT.objType, (char *)pszPathName); @@ -814,7 +827,10 @@ u32 PROCWRAP_EnumNode_Info(union Trapped_Args *args, void *pr_ctxt) args-ARGS_PROC_ENUMNODE_INFO.uNodeTabSize, args-ARGS_PROC_ENUMNODE_INFO.puNumNodes, args-ARGS_PROC_ENUMNODE_INFO.puAllocated); - DBC_Require(args-ARGS_PROC_ENUMNODE_INFO.uNodeTabSize = MAX_NODES); + + if (!args-ARGS_PROC_ENUMNODE_INFO.uNodeTabSize) + return DSP_ESIZE; + status = PROC_EnumNodes(args-ARGS_PROC_ENUMNODE_INFO.hProcessor, aNodeTab, args-ARGS_PROC_ENUMNODE_INFO.uNodeTabSize, @@ -837,6 +853,10 @@ u32 PROCWRAP_FlushMemory(union Trapped_Args *args, void *pr_ctxt) GT_0trace(WCD_debugMask, GT_ENTER, PROCWRAP_FlushMemory: entered\n); + if (args-ARGS_PROC_FLUSHMEMORY.ulFlags +PROC_WRITEBACK_INVALIDATE_MEM) + return DSP_EINVALIDARG; + status = PROC_FlushMemory(args-ARGS_PROC_FLUSHMEMORY.hProcessor, args-ARGS_PROC_FLUSHMEMORY.pMpuAddr, args-ARGS_PROC_FLUSHMEMORY.ulSize, @@ -871,9 +891,6 @@ u32 PROCWRAP_EnumResources(union Trapped_Args *args, void *pr_ctxt) DSP_STATUS status = DSP_SOK; struct DSP_RESOURCEINFO pResourceInfo; - if (DSP_FAILED(status)) - goto func_end; - GT_4trace(WCD_debugMask, GT_ENTER, PROCWRAP_EnumResources: entered args:\n 0x%x hProcessor: 0x%x\tuResourceMask: 0x%x\tpResourceInfo @@ -882,15 +899,19 @@ u32 PROCWRAP_EnumResources(union Trapped_Args *args, void *pr_ctxt)
