[PATCH 2/4] arm: dts: rskrza1: Add Ethernet pin group

[Chris Brandt]

Add pin configuration for Ethernet.

Signed-off-by: Chris Brandt 
---
 arch/arm/boot/dts/r7s72100-rskrza1.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts 
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 5fac0f82d742..cedf887e809a 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -55,6 +55,29 @@
pinmux = ,/* TxD2 */
 ;/* RxD2 */
};
+
+   /* Ethernet */
+   ether_pins: ether {
+   /* Ethernet on Ports 1,2,3,5 */
+   pinmux = ,   /* ET_COL   */
+,/* ET_MDC   */
+,/* ET_MDIO  */
+,/* ET_RXCLK */
+,/* ET_RXER  */
+,/* ET_RXDV  */
+,/* ET_TXCLK */
+,/* ET_TXER  */
+,/* ET_TXEN  */
+,/* ET_CRS   */
+,/* ET_TXD0  */
+,/* ET_TXD1  */
+,/* ET_TXD2  */
+,/* ET_TXD3  */
+,/* ET_RXD0  */
+,/* ET_RXD1  */
+,   /* ET_RXD2  */
+;   /* ET_RXD3  */
+   };
 };
 
  {
@@ -62,6 +85,8 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <>;
-- 
2.13.0

[PATCH 0/4] dts: rskrza1: Add pin configurations

[Chris Brandt]

Now that the RZ/A1 pin control driver has appeared in 4.13-rc1, it
is safe to now add pin configurations for RZ/A1 boards.


Chris Brandt (4):
  arm: dts: rskrza1: Add SCIF2 pin group
  arm: dts: rskrza1: Add Ethernet pin group
  arm: dts: rskrza1: Add SDHI1 pin group
  arm: dts: rskrza1: Add LED0 pin support

 arch/arm/boot/dts/r7s72100-rskrza1.dts | 61 ++
 1 file changed, 61 insertions(+)

-- 
2.13.0

[PATCH 4/4] arm: dts: rskrza1: Add LED0 pin support

[Chris Brandt]

Add pin configuration for LED0 which is connected to a GPIO.

Signed-off-by: Chris Brandt 
---
 arch/arm/boot/dts/r7s72100-rskrza1.dts | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts 
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index f8285b951140..5dcaaf131d27 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -10,6 +10,7 @@
 
 /dts-v1/;
 #include "r7s72100.dtsi"
+#include 
 #include 
 
 / {
@@ -34,6 +35,15 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+   leds {
+   status = "okay";
+   compatible = "gpio-leds";
+
+   led0 {
+   gpios = < 1 GPIO_ACTIVE_LOW>;
+   };
+   };
 };
 
 _clk {
-- 
2.13.0

[PATCH 3/4] arm: dts: rskrza1: Add SDHI1 pin group

[Chris Brandt]

Add pin configuration for SDHI ch1.

Signed-off-by: Chris Brandt 
---
 arch/arm/boot/dts/r7s72100-rskrza1.dts | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts 
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index cedf887e809a..f8285b951140 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -78,6 +78,18 @@
 ,   /* ET_RXD2  */
 ;   /* ET_RXD3  */
};
+
+   /* SDHI ch1 on CN1 */
+   sdhi1_pins: sdhi1 {
+   pinmux = ,/* SD_CD_1 */
+,/* SD_WP_1 */
+,   /* SD_D1_1 */
+,   /* SD_D0_1 */
+,   /* SD_CLK_1 */
+,   /* SD_CMD_1 */
+,   /* SD_D3_1 */
+;   /* SD_D2_1 */
+   };
 };
 
  {
@@ -96,6 +108,8 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
bus-width = <4>;
status = "okay";
 };
-- 
2.13.0

[PATCH 1/4] arm: dts: rskrza1: Add SCIF2 pin group

[Chris Brandt]

Add pin configuration for SCIF2 serial console interface.

Signed-off-by: Chris Brandt 
---
 arch/arm/boot/dts/r7s72100-rskrza1.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts 
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 72df20a04320..5fac0f82d742 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -10,6 +10,7 @@
 
 /dts-v1/;
 #include "r7s72100.dtsi"
+#include 
 
 / {
model = "RSKRZA1";
@@ -47,6 +48,15 @@
clock-frequency = <32768>;
 };
 
+ {
+
+   /* Serial Console */
+   scif2_pins: serial2 {
+   pinmux = ,/* TxD2 */
+;/* RxD2 */
+   };
+};
+
  {
status = "okay";
 };
@@ -78,5 +88,7 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
status = "okay";
 };
-- 
2.13.0

Re: [PATCH v2 3/3] drm: rcar-du: Repair vblank for DRM page flips using the VSP

[Mauro Carvalho Chehab]

Em Wed, 12 Jul 2017 01:29:42 +0300
Laurent Pinchart  escreveu:

> From: Kieran Bingham 
> 
> The driver recently switched from handling page flip completion in the
> DU vertical blanking handler to the VSP frame end handler to fix a race
> condition. This unfortunately resulted in incorrect timestamps in the
> vertical blanking events sent to userspace as vertical blanking is now
> handled after sending the event.
> 
> To fix this we must reverse the order of the two operations. The easiest
> way is to handle vertical blanking in the VSP frame end handler before
> sending the event. The VSP frame end interrupt occurs approximately 50µs
> earlier than the DU frame end interrupt, but this should not cause any
> undue harm.
> 
> As we need to handle vertical blanking even when page flip completion is
> delayed, the VSP driver now needs to call the frame end completion
> callback unconditionally, with a new argument to report whether page
> flip has completed.
> 
> With this new scheme the DU vertical blanking interrupt isn't needed
> anymore, so we can stop enabling it.
> 
> Fixes: d503a43ac06a ("drm: rcar-du: Register a completion callback with VSP1")
> Signed-off-by: Kieran Bingham 
> Signed-off-by: Laurent Pinchart 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH] media: Convert to using %pOF instead of full_name

[Rob Herring]

On Thu, Jul 20, 2017 at 6:15 AM, Mauro Carvalho Chehab
 wrote:
> Em Wed, 19 Jul 2017 11:02:01 -0500
> Rob Herring  escreveu:
>
>> On Wed, Jul 19, 2017 at 4:41 AM, Sylwester Nawrocki
>>  wrote:
>> > On 07/18/2017 11:43 PM, Rob Herring wrote:
>> >> Now that we have a custom printf format specifier, convert users of
>> >> full_name to use %pOF instead. This is preparation to remove storing
>> >> of the full path string for each node.
>> >>
>> >> Signed-off-by: Rob Herring 
>> >
>> >> ---
>> >>   drivers/media/i2c/s5c73m3/s5c73m3-core.c   |  3 +-
>> >>   drivers/media/i2c/s5k5baf.c|  7 ++--
>> >>   drivers/media/platform/am437x/am437x-vpfe.c|  4 +-
>> >>   drivers/media/platform/atmel/atmel-isc.c   |  4 +-
>> >>   drivers/media/platform/davinci/vpif_capture.c  | 16 
>> >>   drivers/media/platform/exynos4-is/fimc-is.c|  8 ++--
>> >>   drivers/media/platform/exynos4-is/fimc-lite.c  |  3 +-
>> >>   drivers/media/platform/exynos4-is/media-dev.c  |  8 ++--
>> >>   drivers/media/platform/exynos4-is/mipi-csis.c  |  4 +-
>> >>   drivers/media/platform/mtk-mdp/mtk_mdp_comp.c  |  6 +--
>> >>   drivers/media/platform/mtk-mdp/mtk_mdp_core.c  |  8 ++--
>> >>   drivers/media/platform/omap3isp/isp.c  |  8 ++--
>> >>   drivers/media/platform/pxa_camera.c|  2 +-
>> >>   drivers/media/platform/rcar-vin/rcar-core.c|  4 +-
>> >>   drivers/media/platform/soc_camera/soc_camera.c |  6 +--
>> >>   drivers/media/platform/xilinx/xilinx-vipp.c| 52 
>> >> +-
>> >>   drivers/media/v4l2-core/v4l2-async.c   |  4 +-
>> >>   drivers/media/v4l2-core/v4l2-clk.c |  3 +-
>> >>   include/media/v4l2-clk.h   |  4 +-
>> >>   19 files changed, 71 insertions(+), 83 deletions(-)
>> >
>> >> diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c 
>> >> b/drivers/media/platform/xilinx/xilinx-vipp.c
>> >> index ac4704388920..9233ad0b1b6b 100644
>> >> --- a/drivers/media/platform/xilinx/xilinx-vipp.c
>> >> +++ b/drivers/media/platform/xilinx/xilinx-vipp.c
>> >
>> >> @@ -144,9 +144,8 @@ static int xvip_graph_build_one(struct 
>> >> xvip_composite_device *xdev,
>> >>   remote = ent->entity;
>> >>
>> >>   if (link.remote_port >= remote->num_pads) {
>> >> - dev_err(xdev->dev, "invalid port number %u on %s\n",
>> >> - link.remote_port,
>> >> - to_of_node(link.remote_node)->full_name);
>> >> + dev_err(xdev->dev, "invalid port number %u on 
>> >> %pOF\n",
>> >> + link.remote_port, link.remote_node);
>> >
>> > Shouldn't there be to_of_node(link.remote_node) instead of 
>> > link.remote_node ?
>>
>> Humm, yes. I thought I fixed that.
>
> After such fix, I'm OK with this patch.

I'll send a new version.

I think I'll send a revert of the referenced commit. It won't apply
cleanly, but at least it will capture the change in behavior and why
it was wrong.

> Are you planning to apply it on your tree, or via the media one?
>
> I guess it is probably better to apply via media, in order to avoid
> conflicts with other changes.

Yes, you can take it.

Rob

Re: [PATCH v2 11/14] v4l: vsp1: Add support for header display lists in continuous mode

[Mauro Carvalho Chehab]

Em Mon, 26 Jun 2017 21:12:23 +0300
Laurent Pinchart  escreveu:

> The VSP supports both header and headerless display lists. The latter is
> easier to use when the VSP feeds data directly to the DU in continuous
> mode, and the driver thus uses headerless display lists for DU operation
> and header display lists otherwise.
> 
> Headerless display lists are only available on WPF.0. This has never
> been an issue so far, as only WPF.0 is connected to the DU. However, on
> H3 ES2.0, the VSP-DL instance has both WPF.0 and WPF.1 connected to the
> DU. We thus can't use headerless display lists unconditionally for DU
> operation.
> 
> Implement support for continuous mode with header display lists, and use
> it for DU operation on WPF outputs that don't support headerless mode.
> 
> Signed-off-by: Laurent Pinchart 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 10/14] v4l: vsp1: Add support for multiple DRM pipelines

[Mauro Carvalho Chehab]

Em Mon, 26 Jun 2017 21:12:22 +0300
Laurent Pinchart  escreveu:

> The R-Car H3 ES2.0 VSP-DL instance has two LIF entities and can drive
> two display pipelines at the same time. Refactor the VSP DRM code to
> support that by introducing a vsp_drm_pipeline object that models one
> display pipeline.
> 
> Signed-off-by: Laurent Pinchart 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 09/14] v4l: vsp1: Add support for multiple LIF instances

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 18:57:40 +0100
Kieran Bingham  escreveu:

> Hi Laurent,
> 
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The VSP2-DL instance (present in the H3 ES2.0 and M3-N SoCs) has two LIF
> > instances. Adapt the driver infrastructure to support multiple LIFs.
> > Support for multiple display pipelines will be added separately.
> > 
> > The change to the entity routing table removes the ability to connect
> > the LIF output to the HGO or HGT histogram generators. This feature is
> > only available on Gen2 hardware, isn't supported by the rest of the
> > driver, and has no known use case, so this isn't an issue.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> This looks good.
> 
> Reviewed-by: Kieran Bingham 

Acked-by: Mauro Carvalho Chehab 


Thanks,
Mauro

Re: [PATCH v2.1 08/14] v4l: vsp1: Add support for new VSP2-BS, VSP2-DL and VSP2-D instances

[Mauro Carvalho Chehab]

Em Fri, 14 Jul 2017 03:35:57 +0300
Laurent Pinchart  escreveu:

> New Gen3 SoCs come with two new VSP2 variants names VSP2-BS and VSP2-DL,
> as well as a new VSP2-D variant on V3M and V3H SoCs. Add new entries for
> them in the VSP device info table.
> 
> Signed-off-by: Laurent Pinchart 
> Reviewed-by: Kieran Bingham 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 07/14] v4l: vsp1: Add support for the BRS entity

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 14:38:40 +0100
Kieran Bingham  escreveu:

> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The Blend/ROP Sub Unit (BRS) is a stripped-down version of the BRU found
> > in several VSP2 instances. Compared to a regular BRU, it supports two
> > inputs only, and thus has no ROP unit.
> > 
> > Add support for the BRS by modeling it as a new entity type, but reuse  
> 
> s/modeling/modelling/
> 
> 
> > the vsp1_bru object underneath. Chaining the BRU and BRS entities seems
> > to be supported by the hardware but isn't implemented yet as it isn't
> > the primary use case for the BRS.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> Reviewed-by: Kieran Bingham 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 06/14] v4l: vsp1: Add pipe index argument to the VSP-DU API

[Mauro Carvalho Chehab]

Em Fri, 14 Jul 2017 02:04:06 +0300
Laurent Pinchart  escreveu:

> On Thursday 13 Jul 2017 14:16:03 Kieran Bingham wrote:
> > On 26/06/17 19:12, Laurent Pinchart wrote:  
> > > In the H3 ES2.0 SoC the VSP2-DL instance has two connections to DU
> > > channels that need to be configured independently. Extend the VSP-DU API
> > > with a pipeline index to identify which pipeline the caller wants to
> > > operate on.
> > > 
> > > Signed-off-by: Laurent Pinchart
> > >   
> > 
> > A bit of comment merge between this and the next patch but it's minor and
> > not worth the effort to change that ... so I'll happily ignore it if you do
> > :)
> > 
> > Reviewed-by: Kieran Bingham 
> >   
> > > ---
> > > 
> > >  drivers/gpu/drm/rcar-du/rcar_du_vsp.c  | 12 ++--
> > >  drivers/media/platform/vsp1/vsp1_drm.c | 32 +++
> > >  include/media/vsp1.h   | 10 ++
> > >  3 files changed, 34 insertions(+), 20 deletions(-)  
> 
> [snip]
> 
> > > diff --git a/drivers/media/platform/vsp1/vsp1_drm.c
> > > b/drivers/media/platform/vsp1/vsp1_drm.c index c72d021ff820..daaafe7885fa
> > > 100644
> > > --- a/drivers/media/platform/vsp1/vsp1_drm.c
> > > +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> > > @@ -58,21 +58,26 @@ EXPORT_SYMBOL_GPL(vsp1_du_init);
> > >  /**
> > >   * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
> > >   * @dev: the VSP device
> > > + * @pipe_index: the DRM pipeline index
> > >   * @cfg: the LIF configuration
> > >   *
> > >   * Configure the output part of VSP DRM pipeline for the given frame
> > >   @cfg.width
> > > - * and @cfg.height. This sets up formats on the BRU source pad, the WPF0
> > > sink
> > > - * and source pads, and the LIF sink pad.
> > > + * and @cfg.height. This sets up formats on the blend unit (BRU or BRS)
> > > source
> > > + * pad, the WPF sink and source pads, and the LIF sink pad.
> > >   *
> > > - * As the media bus code on the BRU source pad is conditioned by the
> > > - * configuration of the BRU sink 0 pad, we also set up the formats on all
> > > BRU
> > > + * The @pipe_index argument selects which DRM pipeline to setup. The
> > > number of
> > > + * available pipelines depend on the VSP instance.
> > > + *
> > > + * As the media bus code on the blend unit source pad is conditioned by
> > > the
> > > + * configuration of its sink 0 pad, we also set up the formats on all
> > > blend unit
> > >   * sinks, even if the configuration will be overwritten later by
> > > - * vsp1_du_setup_rpf(). This ensures that the BRU configuration is set to
> > > a well
> > > - * defined state.
> > > + * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is
> > > set to
> > > + * a well defined state.  
> > 
> > I presume those comment updates for the BRU/ blend-unit configuration are
> > actually for the next patch - but I don't think it matters here - and isn't
> > worth the effort to move the hunks.  
> 
> Too late, I've fixed it already :-) Thanks for pointing it out.

Acked-by: Mauro Carvalho Chehab 


Thanks,
Mauro

Re: [PATCH v2 05/14] v4l: vsp1: Don't create links for DRM pipeline

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 14:06:04 +0100
Kieran Bingham  escreveu:

> On 26/06/17 19:12, Laurent Pinchart wrote:
> > When the VSP1 is used in a DRM pipeline the driver doesn't register the
> > media device. Links between entities are not exposed to userspace, but
> > are still used internally for the sole purpose of setting up internal
> > source to sink pointers through the link setup handler.
> > 
> > Instead of going through this complex procedure, remove link creation
> > and set the sink pointers directly.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> A whole function removed ... always love code removal...
> 
> Reviewed-by: Kieran Bingham 

Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH] gpu: Convert to using %pOF instead of full_name

[Sean Paul]

On Tue, Jul 18, 2017 at 04:43:04PM -0500, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
> 
> Signed-off-by: Rob Herring 

Hi Rob,
Thanks for sending this patch, and thanks to Laurent, Philipp, and Maxime for
reviews/acks.

I've applied it to drm-misc-next.

Sean


> Cc: Russell King 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Sean Paul 
> Cc: Inki Dae 
> Cc: Joonyoung Shim 
> Cc: Seung-Woo Kim 
> Cc: Kyungmin Park 
> Cc: Kukjin Kim 
> Cc: Krzysztof Kozlowski 
> Cc: Javier Martinez Canillas 
> Cc: Xinliang Liu 
> Cc: Rongrong Zou 
> Cc: Xinwei Kong 
> Cc: Chen Feng 
> Cc: CK Hu 
> Cc: Philipp Zabel 
> Cc: Matthias Brugger 
> Cc: Neil Armstrong 
> Cc: Carlo Caione 
> Cc: Kevin Hilman 
> Cc: Thierry Reding 
> Cc: Laurent Pinchart 
> Cc: Mark Yao 
> Cc: Heiko Stuebner 
> Cc: Maxime Ripard 
> Cc: Chen-Yu Tsai 
> Cc: Jyri Sarha 
> Cc: Tomi Valkeinen 
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-amlo...@lists.infradead.org
> Cc: linux-renesas-soc@vger.kernel.org
> Cc: linux-rockc...@lists.infradead.org
> ---
>  drivers/gpu/drm/armada/armada_crtc.c|  3 +--
>  drivers/gpu/drm/armada/armada_drv.c |  4 ++--
>  drivers/gpu/drm/drm_mipi_dsi.c  |  6 +++---
>  drivers/gpu/drm/drm_modes.c |  4 ++--
>  drivers/gpu/drm/drm_of.c|  4 ++--
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c |  3 +--
>  drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  3 +--
>  drivers/gpu/drm/mediatek/mtk_disp_color.c   |  4 ++--
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c |  4 ++--
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c|  4 ++--
>  drivers/gpu/drm/mediatek/mtk_dpi.c  |  6 +++---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  7 +++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  6 ++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 16 
>  drivers/gpu/drm/mediatek/mtk_dsi.c  |  4 ++--
>  drivers/gpu/drm/mediatek/mtk_hdmi.c |  8 
>  drivers/gpu/drm/meson/meson_drv.c   |  5 ++---
>  drivers/gpu/drm/panel/panel-lvds.c  | 16 
>  drivers/gpu/drm/rcar-du/rcar_du_encoder.c   |  4 ++--
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c   | 16 
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |  4 ++--
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  4 ++--
>  drivers/gpu/drm/stm/ltdc.c  |  3 +--
>  drivers/gpu/drm/sun4i/sun4i_drv.c   |  9 -
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c|  4 ++--
>  drivers/gpu/ipu-v3/ipu-common.c |  4 ++--
>  26 files changed, 73 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/gpu/drm/armada/armada_crtc.c 
> b/drivers/gpu/drm/armada/armada_crtc.c
> index 4fe19fde84f9..85977c08879e 100644
> --- a/drivers/gpu/drm/armada/armada_crtc.c
> +++ b/drivers/gpu/drm/armada/armada_crtc.c
> @@ -1329,8 +1329,7 @@ armada_lcd_bind(struct device *dev, struct device 
> *master, void *data)
>   port = of_get_child_by_name(parent, "port");
>   of_node_put(np);
>   if (!port) {
> - dev_err(dev, "no port node found in %s\n",
> - parent->full_name);
> + dev_err(dev, "no port node found in %pOF\n", parent);
>   return -ENXIO;
>   }
> 
> diff --git a/drivers/gpu/drm/armada/armada_drv.c 
> b/drivers/gpu/drm/armada/armada_drv.c
> index e618fab7f519..0b3227c039d7 100644
> --- a/drivers/gpu/drm/armada/armada_drv.c
> +++ b/drivers/gpu/drm/armada/armada_drv.c
> @@ -232,8 +232,8 @@ static void armada_add_endpoints(struct device *dev,
>   of_node_put(remote);
>   continue;
>   } else if (!of_device_is_available(remote->parent)) {
> - dev_warn(dev, "parent device of %s is not available\n",
> -

Re: [PATCH v2 04/14] v4l: vsp1: Store source and sink pointers as vsp1_entity

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 14:00:31 +0100
Kieran Bingham  escreveu:

> Hi Laurent,
> 
> This looks like a good simplification/removal of obfuscation to me!
> 
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The internal VSP entity source and sink pointers are stored as
> > media_entity pointers, which are then cast to a vsp1_entity. As all
> > sources and sinks are vsp1_entity instances, we can store the
> > vsp1_entity pointers directly.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> Reviewed-by: Kieran Bingham 
Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 03/14] v4l: vsp1: Don't set WPF sink pointer

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 13:50:20 +0100
Kieran Bingham  escreveu:

> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The sink pointer is used to configure routing inside the VSP, and as
> > such must point to the next VSP entity in the pipeline. The WPF being a
> > pipeline terminal sink, its output route can't be configured. The
> > routing configuration code already handles this correctly without
> > referring to the sink pointer, which thus doesn't need to be set.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> Reviewed-by: Kieran Bingham 

Acked-by: Mauro Carvalho Chehab 


Thanks,
Mauro

Re: [PATCH v2 02/14] v4l: vsp1: Don't recycle active list at display start

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 18:02:20 +0100
Kieran Bingham  escreveu:

> Hi Laurent,
> 
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > When the display start interrupt occurs, we know that the hardware has
> > finished loading the active display list. The driver then proceeds to
> > recycle the list, assuming it won't be needed anymore.
> > 
> > This assumption holds true for headerless display lists, as the VSP
> > doesn't reload the list for the next frame if it hasn't changed.
> > However, this isn't true anymore for header display lists, as they are
> > loaded at every frame start regardless of whether they have been
> > updated.
> > 
> > To prepare for header display lists usage in display pipelines, we need
> > to postpone recycling the list until it gets replaced by a new one
> > through a page flip. The driver already does so in the frame end
> > interrupt handler, so all we need is to skip list recycling in the
> > display start interrupt handler.
> > 
> > While the active list can be recycled at display start for headerless
> > display lists, there's no real harm in postponing that to the frame end
> > interrupt handler in all cases. This simplifies interrupt handling as we
> > don't need to process the display start interrupt anymore.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> Ok, I had skipped this one as I was concerned about its effects in relation to
> 11/14 but I see how that's working now.
> 
> Reviewed-by: Kieran Bingham 
Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH v2 01/14] v4l: vsp1: Fill display list headers without holding dlm spinlock

[Mauro Carvalho Chehab]

Em Thu, 13 Jul 2017 13:48:40 +0100
Kieran Bingham  escreveu:

> Hi Laurent,
> 
> Starts easy ... (I haven't gone through these in numerical order of course :D)
> 
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The display list headers are filled using information from the display
> > list only. Lower the display list manager spinlock contention by filling
> > the headers without holding the lock.
> > 
> > Signed-off-by: Laurent Pinchart  
> >  
> 
> Reviewed-by: Kieran Bingham 
Acked-by: Mauro Carvalho Chehab 

Thanks,
Mauro

Re: [PATCH 0/4] arm64: dts: renesas: Add Support for R-Car D3 and Draak

[Geert Uytterhoeven]

On Thu, Jul 20, 2017 at 2:54 PM, Geert Uytterhoeven
 wrote:
> This patch series adds minimal support for the R-Car D3 SoC and the
> Draak development board, allowing to boot from a ramdisk using a serial
> console.

>   arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions
>   arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr binding
   ^^^
   r8a77995

Bummer, these were the first (and definitely not the last :-( typos for R-Car
D3 part numbers...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 4/4] arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr binding definitions

[Geert Uytterhoeven]

Replace the hardcoded clock indices by R8A77995_CLK_* symbols.

Signed-off-by: Geert Uytterhoeven 
---
This depends on "clk: renesas: Add r8a77995 CPG Core Clock Definitions".
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index b984c174cf7edb70..74196882e555929d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -9,7 +9,7 @@
  * kind, whether express or implied.
  */
 
-#include 
+#include 
 #include 
 #include 
 
@@ -140,7 +140,7 @@
reg = <0 0xe6e88000 0 64>;
interrupts = ;
clocks = < CPG_MOD 310>,
-< CPG_CORE 16>,
+< CPG_CORE R8A77995_CLK_S3D1C>,
 <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = < R8A77995_PD_ALWAYS_ON>;
-- 
2.7.4

[PATCH 2/4] arm64: dts: renesas: Add Renesas Draak board support

[Geert Uytterhoeven]

Basic support for the Renesas Draak board based on R-Car D3:
  - Memory,
  - Main crystal,
  - Serial console,
  - Watchdog.

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm64/boot/dts/renesas/Makefile   |  1 +
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 46 ++
 2 files changed, 47 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77995-draak.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile 
b/arch/arm64/boot/dts/renesas/Makefile
index acc4bb30d485b6bc..381928bc1358fd9c 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb 
r8a7795-h3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
+dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
 
 always := $(dtb-y)
 clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
new file mode 100644
index ..d144370051d559fc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -0,0 +1,46 @@
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77995.dtsi"
+
+/ {
+   model = "Renesas Draak board based on r8a77995";
+   compatible = "renesas,draak", "renesas,r8a77995";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   bootargs = "ignore_loglevel";
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x1800>;
+   };
+};
+
+_clk {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   timeout-sec = <60>;
+   status = "okay";
+};
-- 
2.7.4

[PATCH 3/4] arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions

[Geert Uytterhoeven]

Replace the hardcoded power domain indices by R8A77995_PD_* symbols.

Signed-off-by: Geert Uytterhoeven 
---
This depends on "soc: renesas: rcar-sysc: Add support for R-Car D3 power
areas".
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 7c69b795cd3ebd82..b984c174cf7edb70 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 
 / {
compatible = "renesas,r8a77995";
@@ -30,14 +31,14 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
-   power-domains = < 5>;
+   power-domains = < R8A77995_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
};
 
L2_CA53: cache-controller-1 {
compatible = "cache";
-   power-domains = < 21>;
+   power-domains = < R8A77995_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -76,7 +77,7 @@
(GIC_CPU_MASK_SIMPLE(1) | 
IRQ_TYPE_LEVEL_HIGH)>;
clocks = < CPG_MOD 408>;
clock-names = "clk";
-   power-domains = < 32>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
resets = < 408>;
};
 
@@ -97,7 +98,7 @@
 "renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
clocks = < CPG_MOD 402>;
-   power-domains = < 32>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
resets = < 402>;
status = "disabled";
};
@@ -142,7 +143,7 @@
 < CPG_CORE 16>,
 <_clk>;
clock-names = "fck", "brg_int", "scif_clk";
-   power-domains = < 32>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
resets = < 310>;
status = "disabled";
};
-- 
2.7.4

[PATCH 0/4] arm64: dts: renesas: Add Support for R-Car D3 and Draak

[Geert Uytterhoeven]

Hi Simon, Magnus,

This patch series adds minimal support for the R-Car D3 SoC and the
Draak development board, allowing to boot from a ramdisk using a serial
console.

  - The first two patches add DT sources for R-Car D3 and Draak.
Due to the use of hardcoded constants, they have no further (build)
dependencies (obviously there is a runtime dependency).
  - The last two patches replace the hardcoded constants by symbols from
DT binding headers, and thus depend on those headers.  Hence it
should be postponed to v4.15.

For proper operation, this depends on the 3 series I have just sent:
  - [PATCH 0/3] arm64: renesas: Base R-Car D3 support,
  - [PATCH 0/4] soc: renesas: Add R-Car D3 support,
  - [PATCH 0/4] clk: renesas: Add R-Car D3 support.

For testing, an integration branch containing all dependencies (and a
few DT binding updates I do not want to send before "ARM: shmobile:
Document R-Car D3 SoC DT bindings" has been accepted) is available in
the topic/r8a77995-integration branch of the git repository at
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git.

Thanks for your comments!

Geert Uytterhoeven (4):
  arm64: dts: renesas: Add Renesas R8A77995 SoC support
  arm64: dts: renesas: Add Renesas Draak board support
  arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions
  arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr binding
definitions

 arch/arm64/boot/dts/renesas/Makefile   |   1 +
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts |  46 
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  | 151 +
 3 files changed, 198 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77995-draak.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77995.dtsi

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 1/4] arm64: dts: renesas: Add Renesas R8A77995 SoC support

[Geert Uytterhoeven]

Basic support for the R-Car D3 SoC:
  - PSCI,
  - CPU,
  - Cache controller,
  - Main clocks and controller,
  - Interrupt controller,
  - Timer,
  - Watchdog,
  - PMU,
  - Reset controller,
  - Product register,
  - System controller,
  - UART for console.

Signed-off-by: Geert Uytterhoeven 
---
To avoid dependencies on dt-binding headers going in through different
paths, clock and power domain indices use hardcoded numbers.
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 150 ++
 1 file changed, 150 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77995.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
new file mode 100644
index ..7c69b795cd3ebd82
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -0,0 +1,150 @@
+/*
+ * Device Tree Source for the r8a77995 SoC
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77995";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   psci {
+   compatible = "arm,psci-1.0", "arm,psci-0.2";
+   method = "smc";
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a53_0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0>;
+   device_type = "cpu";
+   power-domains = < 5>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller-1 {
+   compatible = "cache";
+   power-domains = < 21>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   gic: interrupt-controller@f101 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+   interrupt-controller;
+   reg = <0x0 0xf101 0 0x1000>,
+ <0x0 0xf102 0 0x2>,
+ <0x0 0xf104 0 0x2>,
+ <0x0 0xf106 0 0x2>;
+   interrupts = ;
+   clocks = < CPG_MOD 408>;
+   clock-names = "clk";
+   power-domains = < 32>;
+   resets = < 408>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   rwdt: watchdog@e602 {
+   compatible = "renesas,r8a77995-wdt",
+"renesas,rcar-gen3-wdt";
+   reg = <0 0xe602 0 0x0c>;
+   clocks = < CPG_MOD 402>;
+   power-domains = < 32>;
+   resets = < 402>;
+   status = "disabled";
+   };
+
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts = ;
+   };
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a77995-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>;
+   clock-names = "extal";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a77995-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
+   prr: chipid@fff00044 {
+   compatible = "renesas,prr";
+   reg 

[PATCH 0/4] clk: renesas: Add R-Car D3 support

[Geert Uytterhoeven]

Hi Mike, Stephen,

This patch series adds support for clocks on the R-Car D3 SoC.

As usual, this is meant to be queued up in clk-renesas-for-v4.14.

Thanks!

Geert Uytterhoeven (4):
  clk: renesas: Add r8a77995 CPG Core Clock Definitions
  clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
  clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
  clk: renesas: cpg-mssr: Add R8A77995 support

 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   3 +-
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a7795-cpg-mssr.c |  34 +--
 drivers/clk/renesas/r8a7796-cpg-mssr.c |  34 +--
 drivers/clk/renesas/r8a77995-cpg-mssr.c| 236 +
 drivers/clk/renesas/rcar-gen3-cpg.c|  22 +-
 drivers/clk/renesas/rcar-gen3-cpg.h|  15 +-
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 include/dt-bindings/clock/r8a77995-cpg-mssr.h  |  57 +
 11 files changed, 375 insertions(+), 39 deletions(-)
 create mode 100644 drivers/clk/renesas/r8a77995-cpg-mssr.c
 create mode 100644 include/dt-bindings/clock/r8a77995-cpg-mssr.h

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 1/4] clk: renesas: Add r8a77995 CPG Core Clock Definitions

[Geert Uytterhoeven]

Add all R-Car D3 Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2f ("List of Clocks [R-Car D3]") of the R-Car Series, 3rd
Generation Hardware User's Manual (Rev. 0.55, Jun. 30, 2017).

Note that internal CPG clocks (S0, S1, S2, S3, S1C, S3C, SDSRC, and
SSPSRC) are not included, as they are used as internal clock sources
only, and never referenced from DT.

Signed-off-by: Geert Uytterhoeven 
Cc: devicet...@vger.kernel.org
---
 include/dt-bindings/clock/r8a77995-cpg-mssr.h | 57 +++
 1 file changed, 57 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a77995-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h 
b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index ..4e8ae3dee5901b01
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include 
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z20
+#define R8A77995_CLK_ZG1
+#define R8A77995_CLK_ZTR   2
+#define R8A77995_CLK_ZT3
+#define R8A77995_CLK_ZX4
+#define R8A77995_CLK_S0D1  5
+#define R8A77995_CLK_S1D1  6
+#define R8A77995_CLK_S1D2  7
+#define R8A77995_CLK_S1D4  8
+#define R8A77995_CLK_S2D1  9
+#define R8A77995_CLK_S2D2  10
+#define R8A77995_CLK_S2D4  11
+#define R8A77995_CLK_S3D1  12
+#define R8A77995_CLK_S3D2  13
+#define R8A77995_CLK_S3D4  14
+#define R8A77995_CLK_S1D4C 15
+#define R8A77995_CLK_S3D1C 16
+#define R8A77995_CLK_S3D2C 17
+#define R8A77995_CLK_S3D4C 18
+#define R8A77995_CLK_LB19
+#define R8A77995_CLK_CL20
+#define R8A77995_CLK_ZB3   21
+#define R8A77995_CLK_ZB3D2 22
+#define R8A77995_CLK_CR23
+#define R8A77995_CLK_CRD2  24
+#define R8A77995_CLK_SD0H  25
+#define R8A77995_CLK_SD0   26
+#define R8A77995_CLK_SSP2  27
+#define R8A77995_CLK_SSP1  28
+#define R8A77995_CLK_RPC   29
+#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_ZA2   31
+#define R8A77995_CLK_ZA8   32
+#define R8A77995_CLK_Z2D   33
+#define R8A77995_CLK_CANFD 34
+#define R8A77995_CLK_MSO   35
+#define R8A77995_CLK_R 36
+#define R8A77995_CLK_OSC   37
+#define R8A77995_CLK_LV0   38
+#define R8A77995_CLK_LV1   39
+#define R8A77995_CLK_CP40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
-- 
2.7.4

[PATCH 2/4] clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3

[Geert Uytterhoeven]

On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one.  Extend struct rcar_gen3_cpg_pll_config to handle
this.  As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c | 34 +-
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 34 +-
 drivers/clk/renesas/rcar-gen3-cpg.c|  2 ++
 drivers/clk/renesas/rcar-gen3-cpg.h|  8 +---
 4 files changed, 41 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index c091a8e024b88d32..762b2f8824f118de 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -305,23 +305,23 @@ static const unsigned int r8a7795_crit_mod_clks[] 
__initconst = {
 (((md) & BIT(17)) >> 17))
 
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = 
{
-   /* EXTAL divPLL1 mult   PLL3 mult */
-   { 1,192,192,},
-   { 1,192,128,},
-   { 0, /* Prohibited setting */   },
-   { 1,192,192,},
-   { 1,160,160,},
-   { 1,160,106,},
-   { 0, /* Prohibited setting */   },
-   { 1,160,160,},
-   { 1,128,128,},
-   { 1,128,84, },
-   { 0, /* Prohibited setting */   },
-   { 1,128,128,},
-   { 2,192,192,},
-   { 2,192,128,},
-   { 0, /* Prohibited setting */   },
-   { 2,192,192,},
+   /* EXTAL divPLL1 mult/div   PLL3 mult/div */
+   { 1,192,1,  192,1,  },
+   { 1,192,1,  128,1,  },
+   { 0, /* Prohibited setting */   },
+   { 1,192,1,  192,1,  },
+   { 1,160,1,  160,1,  },
+   { 1,160,1,  106,1,  },
+   { 0, /* Prohibited setting */   },
+   { 1,160,1,  160,1,  },
+   { 1,128,1,  128,1,  },
+   { 1,128,1,  84, 1,  },
+   { 0, /* Prohibited setting */   },
+   { 1,128,1,  128,1,  },
+   { 2,192,1,  192,1,  },
+   { 2,192,1,  128,1,  },
+   { 0, /* Prohibited setting */   },
+   { 2,192,1,  192,1,  },
 };
 
 static const struct soc_device_attribute r8a7795es1[] __initconst = {
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index acc6d0f153e1b233..22ba3c497aba9701 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -277,23 +277,23 @@ static const unsigned int r8a7796_crit_mod_clks[] 
__initconst = {
 (((md) & BIT(17)) >> 17))
 
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = 
{
-   /* EXTAL divPLL1 mult   PLL3 mult */
-   { 1,192,192,},
-   { 1,192,128,},
-   { 0, /* Prohibited setting */   },
-   { 1,192,192,},
-   { 1,160,160,},
-   { 1,160,106,},
-   { 0, /* Prohibited setting */   },
-   { 1,160,160,},
-   { 1,128,128,},
-   { 1,128,84, },
-   { 0, /* Prohibited setting */   },
-   { 1,128,128,},
-   { 2,192,192,},
-   { 2,192,128,},
-   { 0, /* Prohibited setting */   },
-   { 2,192,192,},
+   /* EXTAL divPLL1 mult/div   PLL3 mult/div */
+   { 1,192,1,  192,1,  },
+   { 1,192,1,  128,1,  },
+   { 0, /* Prohibited setting */   },
+   { 1,192,1,  192,1,  },
+   { 1,160,1,  160,1,  },
+   { 1,160,1,  106,1,  },
+   { 0, /* Prohibited setting */   },
+   { 1,160,1,  160,1,  

[PATCH 4/4] clk: renesas: cpg-mssr: Add R8A77995 support

[Geert Uytterhoeven]

Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.

Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.

Signed-off-by: Geert Uytterhoeven 
Cc: devicet...@vger.kernel.org
---
Notes:
  - I couldn't verify the parent clocks of all module clocks.
For e.g. SYS-DMAC and some multimedia devices, I looked at how
related clocks were changed among R-Car H3, M3-W, and D3.
  - For now, R clock handling is hardwired to internal RCLK.
---
 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   3 +-
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a77995-cpg-mssr.c| 236 +
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 6 files changed, 251 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/renesas/r8a77995-cpg-mssr.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt 
b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 0cd894f987a38e81..27cec325853852fc 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
   - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
   - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
   - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+  - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
 
   - reg: Base address and length of the memory resource used by the CPG/MSSR
 block
@@ -30,7 +31,7 @@ Required Properties:
 clock-names
   - clock-names: List of external parent clock names. Valid names are:
   - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
-r8a7795, r8a7796)
+r8a7795, r8a7796, r8a77995)
   - "extalr" (r8a7795, r8a7796)
   - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
 
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 85526ca3920229c8..eee076deb739c500 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -15,6 +15,7 @@ config CLK_RENESAS
select CLK_R8A7794 if ARCH_R8A7794
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A7796 if ARCH_R8A7796
+   select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -94,6 +95,10 @@ config CLK_R8A7796
bool "R-Car M3-W clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
 
+config CLK_R8A77995
+   bool "R-Car D3 clock support" if COMPILE_TEST
+   select CLK_RCAR_GEN3_CPG
+
 config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 02d04124371f717a..a3bb1fadf1a6f9e7 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7794)  += r8a7794-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7795)  += r8a7795-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7796)  += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_SH73A0)   += clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c 
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
new file mode 100644
index ..e594cf8ee63b64e0
--- /dev/null
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -0,0 +1,236 @@
+/*
+ * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A77995_CLK_CP,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL0,
+   CLK_PLL1,
+   CLK_PLL3,
+   CLK_PLL0D2,
+   CLK_PLL0D3,
+   CLK_PLL0D5,
+   CLK_PLL1D2,
+   CLK_PE,
+   CLK_S0,
+   CLK_S1,
+   CLK_S2,
+   CLK_S3,
+   CLK_SDSRC,
+   CLK_SSPSRC,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct 

[PATCH 3/4] clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks

[Geert Uytterhoeven]

On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.

Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both parents and
dividers are stored in the existing parent resp. div fields.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 20 +++-
 drivers/clk/renesas/rcar-gen3-cpg.h |  7 +++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 3f922fea9671fb4c..9511058165475dd7 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -272,7 +272,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct 
device *dev,
unsigned int div = 1;
u32 value;
 
-   parent = clks[core->parent];
+   parent = clks[core->parent & 0x];   /* CLK_TYPE_PE uses high bits */
if (IS_ERR(parent))
return ERR_CAST(parent);
 
@@ -355,6 +355,24 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct 
device *dev,
parent = clks[cpg_clk_extalr];
break;
 
+   case CLK_TYPE_GEN3_PE:
+   /*
+* Peripheral clock with a fixed divider, selectable between
+* clean and spread spectrum parents using MD12
+*/
+   if (cpg_mode & BIT(12)) {
+   /* Clean */
+   div = core->div & 0x;
+   } else {
+   /* SCCG */
+   parent = clks[core->parent >> 16];
+   if (IS_ERR(parent))
+   return ERR_CAST(parent);
+   div = core->div >> 16;
+   }
+   mult = 1;
+   break;
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h 
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 4eaf02955580a938..d756ef8b78eb6c02 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -20,11 +20,18 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R,
+   CLK_TYPE_GEN3_PE,
 };
 
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)  \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+   _div_clean) \
+   DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,  \
+(_parent_sscg) << 16 | (_parent_clean),\
+.div = (_div_sscg) << 16 | (_div_clean))
+
 struct rcar_gen3_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
-- 
2.7.4

[PATCH 3/4] soc: renesas: rcar-sysc: Add support for R-Car D3 power areas

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Cc: devicet...@vger.kernel.org
---
 .../bindings/power/renesas,rcar-sysc.txt   |  1 +
 drivers/soc/renesas/Kconfig|  5 
 drivers/soc/renesas/Makefile   |  1 +
 drivers/soc/renesas/r8a77995-sysc.c| 31 ++
 drivers/soc/renesas/rcar-sysc.c|  3 +++
 drivers/soc/renesas/rcar-sysc.h|  1 +
 6 files changed, 42 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a77995-sysc.c

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt 
b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index d91715bc8d52c22e..98cc8c09d02d5d85 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -17,6 +17,7 @@ Required properties:
   - "renesas,r8a7794-sysc" (R-Car E2)
   - "renesas,r8a7795-sysc" (R-Car H3)
   - "renesas,r8a7796-sysc" (R-Car M3-W)
+  - "renesas,r8a77995-sysc" (R-Car D3)
   - reg: Address start and address range for the device.
   - #power-domain-cells: Must be 1.
 
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 87a4be46bd9834c1..680a5a29837b42d4 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -13,6 +13,7 @@ config SOC_RENESAS
select SYSC_R8A7794 if ARCH_R8A7794
select SYSC_R8A7795 if ARCH_R8A7795
select SYSC_R8A7796 if ARCH_R8A7796
+   select SYSC_R8A77995 if ARCH_R8A77995
 
 if SOC_RENESAS
 
@@ -53,6 +54,10 @@ config SYSC_R8A7796
bool "R-Car M3-W System Controller support" if COMPILE_TEST
select SYSC_RCAR
 
+config SYSC_R8A77995
+   bool "R-Car D3 System Controller support" if COMPILE_TEST
+   select SYSC_RCAR
+
 # Family
 config RST_RCAR
bool "R-Car Reset Controller support" if COMPILE_TEST
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 1a1a297b26a79613..6b6e7f16104c8dbb 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SYSC_R8A7792)+= r8a7792-sysc.o
 obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
 obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
 obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
+obj-$(CONFIG_SYSC_R8A77995)+= r8a77995-sysc.o
 
 # Family
 obj-$(CONFIG_RST_RCAR) += rcar-rst.o
diff --git a/drivers/soc/renesas/r8a77995-sysc.c 
b/drivers/soc/renesas/r8a77995-sysc.c
new file mode 100644
index ..f718429cab02393d
--- /dev/null
+++ b/drivers/soc/renesas/r8a77995-sysc.c
@@ -0,0 +1,31 @@
+/*
+ * Renesas R-Car D3 System Controller
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "rcar-sysc.h"
+
+static struct rcar_sysc_area r8a77995_areas[] __initdata = {
+   { "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+   { "ca53-scu",  0x140, 0, R8A77995_PD_CA53_SCU,  R8A77995_PD_ALWAYS_ON,
+ PD_SCU },
+   { "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
+ PD_CPU_NOCR },
+};
+
+
+const struct rcar_sysc_info r8a77995_sysc_info __initconst = {
+   .areas = r8a77995_areas,
+   .num_areas = ARRAY_SIZE(r8a77995_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 7c8da3c90011422f..e4d3b0101dfb8838 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] = {
 #ifdef CONFIG_SYSC_R8A7796
{ .compatible = "renesas,r8a7796-sysc", .data = _sysc_info },
 #endif
+#ifdef CONFIG_SYSC_R8A77995
+   { .compatible = "renesas,r8a77995-sysc", .data = _sysc_info },
+#endif
{ /* sentinel */ }
 };
 
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 1a5bebaf54ba191c..2f524922c4d261bf 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info;
 extern const struct rcar_sysc_info r8a7794_sysc_info;
 extern const struct rcar_sysc_info r8a7795_sysc_info;
 extern const struct rcar_sysc_info r8a7796_sysc_info;
+extern const struct rcar_sysc_info r8a77995_sysc_info;
 
 
 /*
-- 
2.7.4

[PATCH 2/4] soc: renesas: Add r8a77995 SYSC PM Domain Binding Definitions

[Geert Uytterhoeven]

Add power domain indices for R-Car D3.

Signed-off-by: Geert Uytterhoeven 
Cc: devicet...@vger.kernel.org
---
 include/dt-bindings/power/r8a77995-sysc.h | 23 +++
 1 file changed, 23 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a77995-sysc.h

diff --git a/include/dt-bindings/power/r8a77995-sysc.h 
b/include/dt-bindings/power/r8a77995-sysc.h
new file mode 100644
index ..09d0ed575b738aea
--- /dev/null
+++ b/include/dt-bindings/power/r8a77995-sysc.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77995_PD_CA53_CPU0   5
+#define R8A77995_PD_CA53_SCU   21
+
+/* Always-on power area */
+#define R8A77995_PD_ALWAYS_ON  32
+
+#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
-- 
2.7.4

[PATCH 4/4] soc: renesas: rcar-rst: Add support for R-Car D3

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Cc: devicet...@vger.kernel.org
---
 Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
 drivers/soc/renesas/Kconfig | 2 +-
 drivers/soc/renesas/rcar-rst.c  | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt 
b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index fe5e0f37b3c93579..e5a03ffe04fb2af7 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -26,6 +26,7 @@ Required properties:
  - "renesas,r8a7794-rst" (R-Car E2)
  - "renesas,r8a7795-rst" (R-Car H3)
  - "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77995-rst" (R-Car D3)
   - reg: Address start and address range for the device.
 
 
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 680a5a29837b42d4..567414cb42ba2075 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,7 +3,7 @@ config SOC_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
-  ARCH_R8A7795 || ARCH_R8A7796
+  ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A7779 if ARCH_R8A7779
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index a6d1c26d31675cf3..d27d0abe6c2aa5eb 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -41,6 +41,7 @@ static const struct of_device_id rcar_rst_matches[] 
__initconst = {
/* R-Car Gen3 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7795-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a7796-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a77995-rst", .data = _rst_gen2 },
{ /* sentinel */ }
 };
 
-- 
2.7.4

[PATCH 0/4] soc: renesas: Add R-Car D3 support

[Geert Uytterhoeven]

Hi Simon, Magnus,

This patch series adds R-Car D3 support to the Renesas-specific SoC
drivers:
  - SoC identification,
  - System controller,
  - Reset controller.

Thanks!

Geert Uytterhoeven (4):
  soc: renesas: Identify R-Car D3
  soc: renesas: Add r8a77995 SYSC PM Domain Binding Definitions
  soc: renesas: rcar-sysc: Add support for R-Car D3 power areas
  soc: renesas: rcar-rst: Add support for R-Car D3

 .../bindings/power/renesas,rcar-sysc.txt   |  1 +
 .../devicetree/bindings/reset/renesas,rst.txt  |  1 +
 drivers/soc/renesas/Kconfig|  7 -
 drivers/soc/renesas/Makefile   |  1 +
 drivers/soc/renesas/r8a77995-sysc.c| 31 ++
 drivers/soc/renesas/rcar-rst.c |  1 +
 drivers/soc/renesas/rcar-sysc.c|  3 +++
 drivers/soc/renesas/rcar-sysc.h|  1 +
 drivers/soc/renesas/renesas-soc.c  |  8 ++
 include/dt-bindings/power/r8a77995-sysc.h  | 23 
 10 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/renesas/r8a77995-sysc.c
 create mode 100644 include/dt-bindings/power/r8a77995-sysc.h

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 1/3] ARM: shmobile: Document R-Car D3 SoC DT bindings

[Geert Uytterhoeven]

Note that r8a77995 is the first Renesas "r8a" SoC matching against a 5
digit number, as r8a77990 will be a different SoC.

Signed-off-by: Geert Uytterhoeven 
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 1a671e3298643d9e..91f92d62650207fd 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ SoCs:
 compatible = "renesas,r8a7795"
   - R-Car M3-W (R8A77960)
 compatible = "renesas,r8a7796"
+  - R-Car D3 (R8A77995)
+compatible = "renesas,r8a77995"
 
 
 Boards:
-- 
2.7.4

[PATCH 2/3] ARM: shmobile: Document Renesas Draak board DT bindings

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 91f92d62650207fd..275cda1469b8b95c 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -55,6 +55,8 @@ Boards:
 compatible = "renesas,blanche", "renesas,r8a7792"
   - BOCK-W
 compatible = "renesas,bockw", "renesas,r8a7778"
+  - Draak (RTP0RC77995SEB0010S)
+compatible = "renesas,draak", "renesas,r8a77995"
   - Genmai (RTK772100BC0BR)
 compatible = "renesas,genmai", "renesas,r7s72100"
   - GR-Peach (X28A-M01-E/F)
-- 
2.7.4

[PATCH 0/3] arm64: renesas: Base R-Car D3 support

[Geert Uytterhoeven]

Hi Simon, Magnus, Rob, Mark, Catalin, Will,

This patch series adds base support for the Renesas R-Car D3 SoC and the
Renesas Draak development board.

It documents SoC and board specific DT compatible values, and adds a
Kconfig symbol.

Thanks!

Geert Uytterhoeven (3):
  ARM: shmobile: Document R-Car D3 SoC DT bindings
  ARM: shmobile: Document Renesas Draak board DT bindings
  arm64: renesas: Add Renesas R8A77995 Kconfig support

 Documentation/devicetree/bindings/arm/shmobile.txt | 4 
 arch/arm64/Kconfig.platforms   | 6 ++
 2 files changed, 10 insertions(+)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 3/3] arm64: renesas: Add Renesas R8A77995 Kconfig support

[Geert Uytterhoeven]

Add a configuration option for the R-Car D3 SoC.

Note that r8a77995 is the first Renesas "r8a" SoC using a 5 digit
number in its Kconfig symbol, as r8a77990 will be a different SoC.

Signed-off-by: Geert Uytterhoeven 
---
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index f5f0c813dfecc56c..a1c9f4ed7a887ab2 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -184,6 +184,12 @@ config ARCH_R8A7796
help
  This enables support for the Renesas R-Car M3-W SoC.
 
+config ARCH_R8A77995
+   bool "Renesas R-Car D3 SoC Platform"
+   depends on ARCH_RENESAS
+   help
+ This enables support for the Renesas R-Car D3 SoC.
+
 config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
help
-- 
2.7.4

Re: [PATCH] media: Convert to using %pOF instead of full_name

[Lad, Prabhakar]

On Tue, Jul 18, 2017 at 10:43 PM, Rob Herring  wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
>
> Signed-off-by: Rob Herring 
> Cc: Kyungmin Park 
> Cc: Andrzej Hajda 
> Cc: Mauro Carvalho Chehab 
> Cc: "Lad, Prabhakar" 
> Cc: Songjun Wu 
> Cc: Sylwester Nawrocki 
> Cc: Kukjin Kim 
> Cc: Krzysztof Kozlowski 
> Cc: Javier Martinez Canillas 
> Cc: Minghsiu Tsai 
> Cc: Houlong Wei 
> Cc: Andrew-CT Chen 
> Cc: Matthias Brugger 
> Cc: Laurent Pinchart 
> Cc: "Niklas Söderlund" 
> Cc: Guennadi Liakhovetski 
> Cc: Hyun Kwon 
> Cc: Michal Simek 
> Cc: "Sören Brinkmann" 
> Cc: linux-me...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> Cc: linux-media...@lists.infradead.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  drivers/media/platform/am437x/am437x-vpfe.c|  4 +-
>  drivers/media/platform/davinci/vpif_capture.c  | 16 

For above:

Acked-by: Lad, Prabhakar 

Cheers,
--Prabhakar Lad

Re: [PATCH] media: Convert to using %pOF instead of full_name

[Mauro Carvalho Chehab]

Em Wed, 19 Jul 2017 11:02:01 -0500
Rob Herring  escreveu:

> On Wed, Jul 19, 2017 at 4:41 AM, Sylwester Nawrocki
>  wrote:
> > On 07/18/2017 11:43 PM, Rob Herring wrote:  
> >> Now that we have a custom printf format specifier, convert users of
> >> full_name to use %pOF instead. This is preparation to remove storing
> >> of the full path string for each node.
> >>
> >> Signed-off-by: Rob Herring   
> >  
> >> ---
> >>   drivers/media/i2c/s5c73m3/s5c73m3-core.c   |  3 +-
> >>   drivers/media/i2c/s5k5baf.c|  7 ++--
> >>   drivers/media/platform/am437x/am437x-vpfe.c|  4 +-
> >>   drivers/media/platform/atmel/atmel-isc.c   |  4 +-
> >>   drivers/media/platform/davinci/vpif_capture.c  | 16 
> >>   drivers/media/platform/exynos4-is/fimc-is.c|  8 ++--
> >>   drivers/media/platform/exynos4-is/fimc-lite.c  |  3 +-
> >>   drivers/media/platform/exynos4-is/media-dev.c  |  8 ++--
> >>   drivers/media/platform/exynos4-is/mipi-csis.c  |  4 +-
> >>   drivers/media/platform/mtk-mdp/mtk_mdp_comp.c  |  6 +--
> >>   drivers/media/platform/mtk-mdp/mtk_mdp_core.c  |  8 ++--
> >>   drivers/media/platform/omap3isp/isp.c  |  8 ++--
> >>   drivers/media/platform/pxa_camera.c|  2 +-
> >>   drivers/media/platform/rcar-vin/rcar-core.c|  4 +-
> >>   drivers/media/platform/soc_camera/soc_camera.c |  6 +--
> >>   drivers/media/platform/xilinx/xilinx-vipp.c| 52 
> >> +-
> >>   drivers/media/v4l2-core/v4l2-async.c   |  4 +-
> >>   drivers/media/v4l2-core/v4l2-clk.c |  3 +-
> >>   include/media/v4l2-clk.h   |  4 +-
> >>   19 files changed, 71 insertions(+), 83 deletions(-)  
> >  
> >> diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c 
> >> b/drivers/media/platform/xilinx/xilinx-vipp.c
> >> index ac4704388920..9233ad0b1b6b 100644
> >> --- a/drivers/media/platform/xilinx/xilinx-vipp.c
> >> +++ b/drivers/media/platform/xilinx/xilinx-vipp.c  
> >  
> >> @@ -144,9 +144,8 @@ static int xvip_graph_build_one(struct 
> >> xvip_composite_device *xdev,
> >>   remote = ent->entity;
> >>
> >>   if (link.remote_port >= remote->num_pads) {
> >> - dev_err(xdev->dev, "invalid port number %u on %s\n",
> >> - link.remote_port,
> >> - to_of_node(link.remote_node)->full_name);
> >> + dev_err(xdev->dev, "invalid port number %u on 
> >> %pOF\n",
> >> + link.remote_port, link.remote_node);  
> >
> > Shouldn't there be to_of_node(link.remote_node) instead of link.remote_node 
> > ?  
> 
> Humm, yes. I thought I fixed that.

After such fix, I'm OK with this patch.

Are you planning to apply it on your tree, or via the media one?

I guess it is probably better to apply via media, in order to avoid
conflicts with other changes.

Thanks,
Mauro

Re: [PATCH] media: Convert to using %pOF instead of full_name

[Sylwester Nawrocki]

On 07/19/2017 06:02 PM, Rob Herring wrote:

diff --git a/drivers/media/v4l2-core/v4l2-async.c 
b/drivers/media/v4l2-core/v4l2-async.c
index 851f128eba22..0a385d1ff28c 100644
--- a/drivers/media/v4l2-core/v4l2-async.c
+++ b/drivers/media/v4l2-core/v4l2-async.c
@@ -47,9 +47,7 @@ static bool match_fwnode(struct v4l2_subdev *sd, struct 
v4l2_async_subdev *asd)
   if (!is_of_node(sd->fwnode) || !is_of_node(asd->match.fwnode.fwnode))
   return sd->fwnode == asd->match.fwnode.fwnode;

- return !of_node_cmp(of_node_full_name(to_of_node(sd->fwnode)),
- of_node_full_name(
- to_of_node(asd->match.fwnode.fwnode)));
+ return to_of_node(sd->fwnode) == to_of_node(asd->match.fwnode.fwnode);

>>

I'm afraid this will not work, please see commit d2180e0cf77dc7a7049671d5d57d
"[media] v4l: async: make v4l2 coexist with devicetree nodes in a dt overlay"

>

Maybe I'm missing something, but how does that work exactly? Before
the overlay is applied, the remote endpoint node (and its parent)
can't be resolved. In the commit example, the endpoint in the
media_bridge would also have to be part of the overlay. If you apply
and un-apply the overlay, then the of_node (and fw_node) in the
overlay is once again invalid. IOW, you should be in the same state as
before the overlay was applied. The node is still around because of
paranoia that actually freeing nodes would break things. It seems this
paranoia is real, so i think we need to do something to prevent this
from spreading.

Furthermore, it does not appear that any media driver supports
overlays and we have no general way to apply them in mainline yet
(other than an in kernel API). So really this scenario is not one we
have to support yet.


Indeed, the motivation of the above mentioned commit was some out of
tree driver. I don't know was the exact use case, assuming that the
endpoint in the bridge node was also part of the overlay the bridge
driver must have not been rescanning device tree after overlay un-apply
and apply. Currently there is no other way to do this than to unbind
and bind. So the bridge driver must have been referencing an already
invalid node as you point out.

I haven't been following DT overlays very closely, as Frank explains
your change seems to be actually an improvement of current code.

--
Thanks,
Sylwester

Re: [PATCH 4/4] drm/sun4i: make sure we don't have a commit pending

[Maxime Ripard]

Hi Daniel,

On Tue, Jul 18, 2017 at 09:35:03AM +0200, Daniel Vetter wrote:
> On Tue, Jul 18, 2017 at 9:07 AM, Maxime Ripard
>  wrote:
> > On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> >> On Mon, Jul 17, 2017 at 2:55 PM, Maxime Ripard
> >>  wrote:
> >> > On Fri, Jul 14, 2017 at 04:56:01PM +0800, Chen-Yu Tsai wrote:
> >> >> Hi,
> >> >>
> >> >> On Thu, Jul 13, 2017 at 10:41 PM, Maxime Ripard
> >> >>  wrote:
> >> >> > In the earlier display engine designs, any register access while a 
> >> >> > commit
> >> >> > is pending is forbidden.
> >> >> >
> >> >> > One of the symptoms is that reading a register will return another, 
> >> >> > random,
> >> >> > register value which can lead to register corruptions if we ever do a
> >> >> > read/modify/write cycle.
> >> >>
> >> >> Alternatively, if changes to the backend (layers) are guaranteed to 
> >> >> happen
> >> >> while the CRTC is disabled (which seems to be the case after looking at
> >> >> drm_atomic_helper_commit_planes and drm_atomic_helper_commit_tail), we
> >> >> could just turn on register auto-commit all the time and not deal with
> >> >> this.
> >> >
> >> > As far as I understand, it will only be the case if we need a new
> >> > modeset or we changed the active CRTC or connectors. But if you change
> >> > only the format, buffers or properties it won't be the case, and we'll
> >> > need to commit.
> >>
> >> So in other words, if someone were to use it for actual compositing and
> >> moved the upper composited layer around, we would need commit support to be
> >> safe.
> >>
> >> Sounds more or less like something a video player would do.
> >
> > Not only that. A change of buffer will happen every frame or so, and
> > we can change the format whenever we want too (even if it's usually
> > going to be in sync with a new buffer). Changing a property can happen
> > any time too (like zpos for example).
> 
> You can upgrade any property change to an atomic modeset by e.g.
> setting connector->mode_changed (and then making sure to call
> check_modeset() helper again perhaps). This is for cases where your hw
> can't handle a property change within 1 vblank. The default is just
> the solution for most common hw.
> 
> The other way round works too, you can clear these flags in your
> atomic_check callbacks. But that requires a bit more care (to make
> sure you never clear it when there's something else also changing that
> still needs a full modeset sequence to commit to hw).

Hmm, that's good to know, but that would imply disabling the CRTC each
time we change even a small property, with all the visual artifacts it
might imply, right?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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