[PATCH 0/2] ARM: shmobile: Add support for RZ/A2
Introduce RZ/A2 (R7S9210) as an SoC that can be selected. Chris Brandt (2): ARM: shmobile: Add basic RZ/A2 SoC support dt-bindings: arm: Document RZ/A2 SoC DT bindings Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ arch/arm/mach-shmobile/Kconfig | 6 + arch/arm/mach-shmobile/Makefile| 1 + arch/arm/mach-shmobile/setup-r7s9210.c | 27 ++ 4 files changed, 36 insertions(+) create mode 100644 arch/arm/mach-shmobile/setup-r7s9210.c -- 2.16.1
[PATCH 2/2] dt-bindings: arm: Document RZ/A2 SoC DT bindings
Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC. Signed-off-by: Chris Brandt --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 89b4a389fbc7..7288c2081cd5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -7,6 +7,8 @@ SoCs: compatible = "renesas,emev2" - RZ/A1H (R7S72100) compatible = "renesas,r7s72100" + - RZ/A2 (R7S9210) +compatible = "renesas,r7s9210" - SH-Mobile AG5 (R8A73A00/SH73A0) compatible = "renesas,sh73a0" - R-Mobile APE6 (R8A73A40) -- 2.16.1
[PATCH 1/2] ARM: shmobile: Add basic RZ/A2 SoC support
Add the RZ/A2 SoC to the Renesas SoC collection.
Signed-off-by: Chris Brandt
---
arch/arm/mach-shmobile/Kconfig | 6 ++
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/setup-r7s9210.c | 27 +++
3 files changed, 34 insertions(+)
create mode 100644 arch/arm/mach-shmobile/setup-r7s9210.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0b67254eabb2..9338eb0d574f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -54,6 +54,12 @@ config ARCH_R7S72100
select SYS_SUPPORTS_SH_MTU2
select RENESAS_OSTM
+config ARCH_R7S9210
+ bool "RZ/A2 (R7S9210)"
+ select PM
+ select PM_GENERIC_DOMAINS
+ select RENESAS_OSTM
+
config ARCH_R8A73A4
bool "R-Mobile APE6 (R8A73A40)"
select ARCH_RMOBILE
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b33dc59d8698..5591646cb9bb 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_R8A7778)+= setup-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
obj-$(CONFIG_ARCH_R7S72100)+= setup-r7s72100.o
+obj-$(CONFIG_ARCH_R7S9210) += setup-r7s9210.o
# CPU reset vector handling objects
cpu-y := platsmp.o headsmp.o
diff --git a/arch/arm/mach-shmobile/setup-r7s9210.c
b/arch/arm/mach-shmobile/setup-r7s9210.c
new file mode 100644
index ..573fb9955e7e
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r7s9210.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r7s9210 processor support
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ * Copyright (C) 2018 Chris Brandt
+ *
+ */
+
+#include
+
+#include
+
+#include "common.h"
+
+static const char *const r7s9210_boards_compat_dt[] __initconst = {
+ "renesas,r7s9210",
+ NULL,
+};
+
+DT_MACHINE_START(R7S72100_DT, "Generic R7S9210 (Flattened Device Tree)")
+ .l2c_aux_val= 0,
+ .l2c_aux_mask = ~0,
+ .init_early = shmobile_init_delay,
+ .init_late = shmobile_init_late,
+ .dt_compat = r7s9210_boards_compat_dt,
+MACHINE_END
--
2.16.1
Re: [GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.17
Hi Geert,
On Thursday, 5 July 2018 13:55:00 EEST Geert Uytterhoeven wrote:
> On Thu, Jun 14, 2018 at 1:36 PM Simon Horman wrote:
> > This series is comprised of backports to v4.14 of the following
> > components from their standard as of v4.16 to that of v4.17:
[snip]
> I subjected it to the same testing I do for each renesas-drivers release.
>
> Regressions from v4.14.48:
[snip]
> - Koelsch, Salvator-X (R-Car M3-W), Salvator-XS (R-Car H3 ES2.0):
>
> +rcar-du feb0.display: no connector for encoder
> /soc/lvds@feb9, skipping
>
> Laurent: do you know what's missing?
That message is printed when no connector node is linked in DT through OF
graph to the encoder DT node output port. That's expected in this case as we
have an LVDS encoder, but not connected panel. However,
rcar_du_encoders_init_one() should return before printing that message due to
if (!of_device_is_available(entity)) {
dev_dbg(rcdu->dev,
"connected entity %pOF is disabled, skipping\n",
entity);
return -ENODEV;
}
as the LVDS encoder nodes in DT should be disabled.
--
Regards,
Laurent Pinchart
Re: [PATCH] gpiolib: use better errno if get_direction is not available
> Do you want me to implement it? Yes, please. Thanks a lot! signature.asc Description: PGP signature
Re: [PATCH] gpiolib: use better errno if get_direction is not available
Hi Wolfram,
On Wed, Jul 11, 2018 at 6:33 PM Wolfram Sang
wrote:
> @Geert: any reason gpio-rcar is missing it? I would need it for the
> i2c-gpio-fault-injector.
Because so far no one had a need for it?
/me thought gpiolib would return a cached value from a previous
set_direction_{in,out}put(), but apparently that must have been a dream...
Do you want me to implement it?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 2/2] clk: renesas: mstp: Document R7S9210 support
Renesas R7S9210 SoC also has the CPG MSTP clocks. Signed-off-by: Chris Brandt --- Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index da578ebdda28..bb470d9bc07f 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -11,6 +11,7 @@ Required Properties: - compatible: Must be one of the following - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks +- "renesas,r7s9210-mstp-clocks" for R7S9210 (RZ A2) MSTP gate clocks - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks -- 2.16.1
[PATCH 0/2] clk: renesas: mstp: Add support for RZ/A2
Add support for RZ/A2 series. The clock HW is similar to RZ/A1, but with different dividers and additional clocks sources. Chris Brandt (2): clk: renesas: mstp: Add support for r7s9210 clk: renesas: mstp: Document R7S9210 support .../bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + drivers/clk/renesas/Kconfig| 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-mstp.c | 3 + drivers/clk/renesas/clk-rz.c | 155 - 5 files changed, 131 insertions(+), 34 deletions(-) -- 2.16.1
[PATCH 1/2] clk: renesas: mstp: Add support for r7s9210
Add support for RZ/A2 series.
The clock HW is similar to RZ/A1, but with different dividers
and additional clocks sources.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/Kconfig| 5 ++
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-mstp.c | 3 +
drivers/clk/renesas/clk-rz.c | 155 -
4 files changed, 130 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 9022bbe1297e..b08d44b8a476 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -3,6 +3,7 @@ config CLK_RENESAS
default y if ARCH_RENESAS
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
+ select CLK_RZA2 if ARCH_R7S9210
select CLK_R8A73A4 if ARCH_R8A73A4
select CLK_R8A7740 if ARCH_R8A7740
select CLK_R8A7743 if ARCH_R8A7743
@@ -45,6 +46,10 @@ config CLK_RZA1
bool "RZ/A1H clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
+config CLK_RZA2
+ bool "RZ/A2 clock support" if COMPILE_TEST
+ select CLK_RENESAS_CPG_MSTP
+
config CLK_R8A73A4
bool "R-Mobile APE6 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index e4aa3d6143d2..6159ee43f7ca 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@
# SoC
obj-$(CONFIG_CLK_EMEV2)+= clk-emev2.o
obj-$(CONFIG_CLK_RZA1) += clk-rz.o
+obj-$(CONFIG_CLK_RZA2) += clk-rz.o
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index e82adcb16a52..9470ab8acc13 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -213,6 +213,9 @@ static void __init cpg_mstp_clocks_init(struct device_node
*np)
if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
group->width_8bit = true;
+ if (of_device_is_compatible(np, "renesas,r7s9210-mstp-clocks"))
+ group->width_8bit = true;
+
for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
clks[i] = ERR_PTR(-ENOENT);
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
index ac2f86d626b6..199c6ae9704c 100644
--- a/drivers/clk/renesas/clk-rz.c
+++ b/drivers/clk/renesas/clk-rz.c
@@ -1,5 +1,5 @@
/*
- * RZ/A1 Core CPG Clocks
+ * RZ/A Core CPG Clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2014 Wolfram Sang, Sang Engineering
@@ -24,44 +24,95 @@ struct rz_cpg {
#define CPG_FRQCR 0x10
#define CPG_FRQCR2 0x14
+#define SWRSTCR3 0xFCFE0468
+/* RZ/A1 */
#define PPR0 0xFCFE3200
#define PIBC0 0xFCFE7000
-#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
+/* RZ/A2 */
+#define PORTL_PIDR 0xFCFFE074
+
+#define RZA1 1
+#define RZA2 2
/*
-
* Initialization
*/
+int detect_rz(void)
+{
+ void __iomem *swrstcr3;
+ static int rz_device;
+
+ if (!rz_device) {
+ swrstcr3 = ioremap_nocache(SWRSTCR3, 1);
+ BUG_ON(!swrstcr3);
+ if (ioread8(swrstcr3))
+ rz_device = RZA1;
+ else
+ rz_device = RZA2;
+ iounmap(swrstcr3);
+ }
+ return rz_device;
+}
-static u16 __init rz_cpg_read_mode_pins(void)
+static u8 __init rz_cpg_read_mode_pin(void)
{
- void __iomem *ppr0, *pibc0;
- u16 modes;
-
- ppr0 = ioremap_nocache(PPR0, 2);
- pibc0 = ioremap_nocache(PIBC0, 2);
- BUG_ON(!ppr0 || !pibc0);
- iowrite16(4, pibc0);/* enable input buffer */
- modes = ioread16(ppr0);
- iounmap(ppr0);
- iounmap(pibc0);
-
- return modes;
+ void __iomem *ppr0, *pibc0, *pidr;
+ u8 mode;
+
+ if (detect_rz() == RZA1) {
+ /* RZ/A1 */
+ /* MD_CLK pin is P0_2 */
+ ppr0 = ioremap_nocache(PPR0, 2);
+ pibc0 = ioremap_nocache(PIBC0, 2);
+ BUG_ON(!ppr0 || !pibc0);
+ iowrite16(4, pibc0);/* enable input buffer */
+ mode = (u8)((ioread16(ppr0) >> 2) & 1);
+ iounmap(ppr0);
+ iounmap(pibc0);
+ } else {
+ /* RZ/A2 */
+ /* MD_CLK pin is PL_1 */
+ pidr = ioremap_nocache(PORTL_PIDR, 1);
+ BUG_ON(!pidr);
+ mode = (ioread8(pidr) >> 1) & 1;
+ iounmap(pidr);
+ }
+
+ return mode;
}
static struct clk * __init
rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char
*name)
{
u32 val;
-
Re: [PATCH 1/2] i2c: recovery: add get_bus_free callback
> Hmmm, the name i2c_generic_bus_free suggests that scl should also be checked, > because the *bus* isn't really free unless both lines are high? No? Or, maybe > just rename to i2c_generic_sda_free (or something)? Well, technically, bus recovery is just for resurrecting a stuck low SDA. So, I'd think checking if SDA went high again should do it. However, there is HW (at least Renesas R-Car) which cannot read SDA directly. It will just return the result of its internal 'bus_free' logic. Whatever that is. I think it wants to see a STOP but that may be only part of it. I wanted to have an option to make use of such a feature if we can't read SDA. It is better than nothing. But since it doesn't reflect the state of SDA directly, I decided for another callback. > More importantly, isn't a ->get_bus_free implementation a sufficient > requirement > for recovery? I.e. even if both ->get_sda and ->set_sda are missing? In my case, it isn't. It needs set_sda (== STOP) to achieve a useful result. Hmm, I think this needs better documentation... signature.asc Description: PGP signature
Re: [PATCH v2 2/3] i2c: recovery: require either get_sda or set_sda
On Wed, Jul 11, 2018 at 07:51:02AM +0200, Peter Rosin wrote: > On 2018-07-10 23:42, Wolfram Sang wrote: > > For bus recovery, we either need to bail out early if we can read SDA or > > we need to send STOP after every pulse. Otherwise recovery might be > > misinterpreted as an unwanted write. So, require one of those SDA > > handling functions to avoid this problem. > > Assuming that all users fulfill the stricter requirement... Yes, I checked all in-tree users for that. signature.asc Description: PGP signature
Re: [PATCH v2 1/3] i2c: recovery: if possible send STOP with recovery pulses
Hi Peter, > Hmmm, should not the ndelay before the loop also be split up in two like > this, with one ndelay(... / 2) on either side of the (possible) set_sda. > Not that it should matter, since SDA is presumably stuck low. But what if > it isn't? I agree it would be better. > I would also change the while (...) to > > for (i = 0; i < RECOVERY_CLK_CNT * 2; i++) Yeah, could be done as well. > but both these "issues" are perhaps not related to this patch... I also think these should be handled incrementally. > Reviewed-by: Peter Rosin Thanks for the review! Regards, Wolfram signature.asc Description: PGP signature
[PATCH] gpiolib: use better errno if get_direction is not available
EINVAL is very generic, use ENOTSUPP in case the gpiochip does not
provide this function. While removing the assignment from the 'status'
variable, use better indentation in the declaration block.
Signed-off-by: Wolfram Sang
---
I got puzzled by the EINVAL until I found out that gpio-rcar simply does not
implement it.
@Geert: any reason gpio-rcar is missing it? I would need it for the
i2c-gpio-fault-injector.
drivers/gpio/gpiolib.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index e11a3bb03820..18719f64e80b 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -210,15 +210,15 @@ static int gpiochip_find_base(int ngpio)
*/
int gpiod_get_direction(struct gpio_desc *desc)
{
- struct gpio_chip*chip;
- unsignedoffset;
- int status = -EINVAL;
+ struct gpio_chip *chip;
+ unsigned offset;
+ int status;
chip = gpiod_to_chip(desc);
offset = gpio_chip_hwgpio(desc);
if (!chip->get_direction)
- return status;
+ return -ENOTSUPP;
status = chip->get_direction(chip, offset);
if (status > 0) {
--
2.11.0
Re: [PATCH v2 1/3] serial: sh-sci: Postpone DMA release when falling back to PIO
Hi Simon,
On Wed, Jul 11, 2018 at 4:41 PM Simon Horman wrote:
> On Fri, Jul 06, 2018 at 11:05:41AM +0200, Geert Uytterhoeven wrote:
> > When the sh-sci driver detects an issue with DMA during operation, it
> > falls backs to PIO, and releases all DMA resources.
> >
> > As releasing DMA resources immediately has no advantages, but
> > complicates the code, and is susceptible to races, it is better to
> > postpone this to port shutdown.
> >
> > This allows to remove the locking from sci_rx_dma_release() and
> > sci_tx_dma_release(), but requires keeping a copy of the DMA channel
> > pointers for release during port shutdown.
> >
> > Signed-off-by: Geert Uytterhoeven
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -1535,7 +1534,6 @@ static void sci_request_dma(struct uart_port *port)
> > chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
> > dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
> > if (chan) {
> > - s->chan_tx = chan;
> > /* UART circular tx buffer is an aligned page. */
> > s->tx_dma_addr = dma_map_single(chan->device->dev,
> > port->state->xmit.buf,
> > @@ -1544,11 +1542,13 @@ static void sci_request_dma(struct uart_port *port)
> > if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
> > dev_warn(port->dev, "Failed mapping Tx DMA
> > descriptor\n");
> > dma_release_channel(chan);
> > - s->chan_tx = NULL;
> > + chan = NULL;
>
> I am sure that I am missing something obvious, but why is chan set here?
> Unless I'm reading the wrong code its set again at the end of the
> block that ends just after the call to INIT_WORK().
I don't see where it's set again at the end of the block?
But indeed, there's no need to set it to NULL here, as chan isn't used
later again.
So the assignment should be removed, cfr. for the RX DMA case below[*].
Probably I missed that due to the asymmetry between the TX and RX DMA paths.
Will send a follow up patch to remove the assignment.
>
> > } else {
> > dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
> > __func__, UART_XMIT_SIZE,
> > port->state->xmit.buf, >tx_dma_addr);
> > +
> > + s->chan_tx_saved = s->chan_tx = chan;
> > }
> >
> > INIT_WORK(>work_tx, work_fn_tx);
> > @@ -1561,8 +1561,6 @@ static void sci_request_dma(struct uart_port *port)
> > dma_addr_t dma;
> > void *buf;
> >
> > - s->chan_rx = chan;
> > -
> > s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
> > buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
> >, GFP_KERNEL);
> > @@ -1570,7 +1568,6 @@ static void sci_request_dma(struct uart_port *port)
> > dev_warn(port->dev,
> >"Failed to allocate Rx dma buffer, using
> > PIO\n");
> > dma_release_channel(chan);
> > - s->chan_rx = NULL;
[*] here.
> > return;
> > }
> >
> > @@ -1591,6 +1588,8 @@ static void sci_request_dma(struct uart_port *port)
> >
> > if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
> > sci_submit_rx(s);
> > +
> > + s->chan_rx_saved = s->chan_rx = chan;
> > }
> > }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 2/3] serial: sh-sci: Stop TX DMA workqueue during port shutdown
Hi Simon,
On Wed, Jul 11, 2018 at 4:52 PM Simon Horman wrote:
> On Fri, Jul 06, 2018 at 11:05:42AM +0200, Geert Uytterhoeven wrote:
> > The transmit DMA workqueue is never stopped, hence the work function may
> > be called after the port has been shut down.
> >
> > Fix this race condition by cancelling queued work, if any, before DMA
> > release. Don't initialize the work if DMA initialization failed, as it
> > won't be used anyway.
> >
> > Signed-off-by: Geert Uytterhoeven
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -1293,6 +1293,7 @@ static void sci_tx_dma_release(struct sci_port *s)
> > {
> > struct dma_chan *chan = s->chan_tx_saved;
> >
> > + cancel_work_sync(>work_tx);
> > s->chan_tx_saved = s->chan_tx = NULL;
> > s->cookie_tx = -EINVAL;
> > dmaengine_terminate_all(chan);
> > @@ -1548,10 +1549,9 @@ static void sci_request_dma(struct uart_port *port)
> > __func__, UART_XMIT_SIZE,
> > port->state->xmit.buf, >tx_dma_addr);
> >
> > + INIT_WORK(>work_tx, work_fn_tx);
> > s->chan_tx_saved = s->chan_tx = chan;
>
> Is it ok that work_fn_tx reads and writes s->work_tx which
writes s->chan_tx?
> is set after the call to INIT_WORK() ?
Yes, unlike interrupt handlers, it isn't called until software kicks the
workqueue using schedule_work(>work_tx);
> > }
> > -
> > - INIT_WORK(>work_tx, work_fn_tx);
> > }
> >
> > chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RE: [PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART
Hi Geert,
On 11 July 2018 13:42, Geert Uytterhoeven wrote:
> On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote:
> > The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has
> > additional registers for DMA. This patch does not address the changes
> > required for DMA support, it simply adds the compatible string.
> >
> > Signed-off-by: Phil Edworthy
>
> Thanks for your patch!
>
> What happens if someone would boot a kernel that has only this patch
> applied and a DTB that already has the to-be-supported dmas properties?
The driver only sets up dma if the fifo depth is >0, and this is read from
CPR register. This is an optional (as in RTL configuration) register for the
Synopsys UART block. On rzn1 devices, this register returns 0, so the
driver will not set up dma => so the uart still works.
Additionally, the uart normally used for the console (used because the
BootROM uses it) does not have any dma capabilities.
Thanks
Phil
> > --- a/drivers/tty/serial/8250/8250_dw.c
> > +++ b/drivers/tty/serial/8250/8250_dw.c
> > @@ -693,6 +693,7 @@ static const struct of_device_id dw8250_of_match[]
> = {
> > { .compatible = "snps,dw-apb-uart" },
> > { .compatible = "cavium,octeon-3860-uart" },
> > { .compatible = "marvell,armada-38x-uart" },
> > + { .compatible = "renesas,uart-rzn1" },
>
> renesas,rzn1-uart
>
> > { /* Sentinel */ }
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH v2 3/3] serial: sh-sci: Stop using deprecated dmaengine_terminate_all()
On Fri, Jul 06, 2018 at 11:05:43AM +0200, Geert Uytterhoeven wrote:
> As of commit b36f09c3c441a6e5 ("dmaengine: Add transfer termination
> synchronization support"), dmaengine_terminate_all() is deprecated.
>
> Replace calls to dmaengine_terminate_all() in DMA release code by calls
> to dmaengine_terminate_sync(), as the latter waits until all running
> completion callbacks have finished.
>
> Replace calls to dmaengine_terminate_all() in DMA failure paths by calls
> to dmaengine_terminate_async(), as these are usually done in atomic
> context.
>
> Signed-off-by: Geert Uytterhoeven
I see this series has been applied, but FWIW
Reviewed-by: Simon Horman
> ---
> v2:
> - No changes.
> ---
> drivers/tty/serial/sh-sci.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 939749073e7bdb11..360664a9adf66632 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -1220,7 +1220,7 @@ static void sci_rx_dma_release(struct sci_port *s)
>
> s->chan_rx_saved = s->chan_rx = NULL;
> s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
> - dmaengine_terminate_all(chan);
> + dmaengine_terminate_sync(chan);
> dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
> sg_dma_address(>sg_rx[0]));
> dma_release_channel(chan);
> @@ -1296,7 +1296,7 @@ static void sci_tx_dma_release(struct sci_port *s)
> cancel_work_sync(>work_tx);
> s->chan_tx_saved = s->chan_tx = NULL;
> s->cookie_tx = -EINVAL;
> - dmaengine_terminate_all(chan);
> + dmaengine_terminate_sync(chan);
> dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
>DMA_TO_DEVICE);
> dma_release_channel(chan);
> @@ -1334,7 +1334,7 @@ static void sci_submit_rx(struct sci_port *s)
>
> fail:
> if (i)
> - dmaengine_terminate_all(chan);
> + dmaengine_terminate_async(chan);
> for (i = 0; i < 2; i++)
> s->cookie_rx[i] = -EINVAL;
> s->active_rx = -EINVAL;
> @@ -1452,7 +1452,7 @@ static enum hrtimer_restart rx_timer_fn(struct hrtimer
> *t)
> }
>
> /* Handle incomplete DMA receive */
> - dmaengine_terminate_all(s->chan_rx);
> + dmaengine_terminate_async(s->chan_rx);
> read = sg_dma_len(>sg_rx[active]) - state.residue;
>
> if (read) {
> --
> 2.17.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Re: [PATCH v2 2/3] serial: sh-sci: Stop TX DMA workqueue during port shutdown
On Fri, Jul 06, 2018 at 11:05:42AM +0200, Geert Uytterhoeven wrote:
> The transmit DMA workqueue is never stopped, hence the work function may
> be called after the port has been shut down.
>
> Fix this race condition by cancelling queued work, if any, before DMA
> release. Don't initialize the work if DMA initialization failed, as it
> won't be used anyway.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> v2:
> - No changes.
> ---
> drivers/tty/serial/sh-sci.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 674dc65454ae0684..939749073e7bdb11 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -1293,6 +1293,7 @@ static void sci_tx_dma_release(struct sci_port *s)
> {
> struct dma_chan *chan = s->chan_tx_saved;
>
> + cancel_work_sync(>work_tx);
> s->chan_tx_saved = s->chan_tx = NULL;
> s->cookie_tx = -EINVAL;
> dmaengine_terminate_all(chan);
> @@ -1548,10 +1549,9 @@ static void sci_request_dma(struct uart_port *port)
> __func__, UART_XMIT_SIZE,
> port->state->xmit.buf, >tx_dma_addr);
>
> + INIT_WORK(>work_tx, work_fn_tx);
> s->chan_tx_saved = s->chan_tx = chan;
Is it ok that work_fn_tx reads and writes s->work_tx which
is set after the call to INIT_WORK() ?
> }
> -
> - INIT_WORK(>work_tx, work_fn_tx);
> }
>
> chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
> --
> 2.17.1
>
[PATCH 2/2] serial: sh-sci: Document r7s9210 bindings
Add R7S9210 (RZ/A2) support Signed-off-by: Chris Brandt --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 106808b55b6d..5c002bce8f42 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. +- "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. -- 2.16.1
[PATCH 0/2] serial: sh-sci: Add support for RZ/A2
The RZ/A2 uses a modified SCIF that until recently was only used in Renesas MCU devices (not MPU devices). So, while it functions mostly the same as a normal SCIF, some things needed to be shifted around. Chris Brandt (2): serial: sh-sci: Add support for R7S9210 serial: sh-sci: Document r7s9210 bindings .../bindings/serial/renesas,sci-serial.txt | 1 + drivers/tty/serial/sh-sci.c| 77 +- include/linux/serial_sci.h | 1 + 3 files changed, 77 insertions(+), 2 deletions(-) -- 2.16.1
[PATCH 1/2] serial: sh-sci: Add support for R7S9210
Add support for a "RZ_SCIFA" which is different than a traditional
SCIFA. It looks like a normal SCIF with FIFO data, but with a
compressed address space. Also, the break out of interrupts
are different then traditinal SCIF: ERI/BRI, RXI, TXI, TEI, DRI.
The R7S9210 (RZ/A2) contains this type of SCIF.
Signed-off-by: Chris Brandt
---
drivers/tty/serial/sh-sci.c | 77 +++--
include/linux/serial_sci.h | 1 +
2 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index c181eb37f985..d3435976ba7e 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -65,6 +65,7 @@ enum {
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
+ SCIx_TEIDRI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS,/* special case */
@@ -76,6 +77,9 @@ enum {
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
+#define SCIx_TEIDRI_IRQ_EXISTS(port) \
+ ((port)->irqs[SCIx_TEIDRI_IRQ] > 0)
+
enum SCI_CLKS {
SCI_FCK,/* Functional Clock */
SCI_SCK,/* Optional External Clock */
@@ -287,6 +291,33 @@ static const struct sci_port_params
sci_port_params[SCIx_NR_REGTYPES] = {
.error_clear = SCIF_ERROR_CLEAR,
},
+ /*
+* The "SCIFA" that is in RZ/T and RZ/A2.
+* It looks like a normal SCIF with FIFO data, but with a
+* compressed address space. Also, the break out of interrupts
+* are different: ERI/BRI, RXI, TXI, TEI, DRI.
+*/
+ [SCIx_RZ_SCIFA_REGTYPE] = {
+ .regs = {
+ [SCSMR] = { 0x00, 16 },
+ [SCBRR] = { 0x02, 8 },
+ [SCSCR] = { 0x04, 16 },
+ [SCxTDR]= { 0x06, 8 },
+ [SCxSR] = { 0x08, 16 },
+ [SCxRDR]= { 0x0A, 8 },
+ [SCFCR] = { 0x0C, 16 },
+ [SCFDR] = { 0x0E, 16 },
+ [SCSPTR]= { 0x10, 16 },
+ [SCLSR] = { 0x12, 16 },
+ },
+ .fifosize = 16,
+ .overrun_reg = SCLSR,
+ .overrun_mask = SCLSR_ORER,
+ .sampling_rate_mask = SCI_SR(32),
+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
+ .error_clear = SCIF_ERROR_CLEAR,
+ },
+
/*
* Common SH-3 SCIF definitions.
*/
@@ -1683,11 +1714,26 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
return IRQ_HANDLED;
}
+static irqreturn_t sci_br_interrupt(int irq, void *ptr);
+
static irqreturn_t sci_er_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
struct sci_port *s = to_sci_port(port);
+ if (SCIx_TEIDRI_IRQ_EXISTS(s)) {
+ /* Break and Error interrupts are muxed */
+ unsigned short ssr_status = serial_port_in(port, SCxSR);
+
+ /* Break Interrupt */
+ if (ssr_status & SCxSR_BRK(port))
+ sci_br_interrupt(irq, ptr);
+
+ /* Break only? */
+ if (!(ssr_status & SCxSR_ERRORS(port)))
+ return IRQ_HANDLED;
+ }
+
/* Handle errors */
if (port->type == PORT_SCI) {
if (sci_handle_errors(port)) {
@@ -1827,8 +1873,31 @@ static int sci_request_irq(struct sci_port *port)
}
desc = sci_irq_desc + i;
- port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
- dev_name(up->dev), desc->desc);
+ if (SCIx_TEIDRI_IRQ_EXISTS(port)) {
+ /*
+* ERI and BRI are muxed, just register ERI and
+* ignore BRI.
+* TEI and DRI are muxed, but only DRI
+* is enabled, so use RXI handler
+*/
+ if (i == SCIx_ERI_IRQ)
+ port->irqstr[j] = kasprintf(GFP_KERNEL,
+ "%s:err + break",
+ dev_name(up->dev));
+ if (i == SCIx_BRI_IRQ)
+ continue;
+ if (i == SCIx_TEIDRI_IRQ) {
+ port->irqstr[j] = kasprintf(GFP_KERNEL,
+ "%s:tx end + rx
ready",
+ dev_name(up->dev));
+ desc = sci_irq_desc + SCIx_RXI_IRQ;
+ }
+ }
+
+ if (!port->irqstr[j])
+ port->irqstr[j] =
[PATCH] ARM: multi_v7_defconfig: Enable support for RZN1D-DB
Enable support for the Renesas RZN1D-DB Board: - RZ/N1D (R9A06G032) base SoC support. Signed-off-by: Geert Uytterhoeven --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 155d1eb10c6580fe..d0dea6cad4eb7613 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -89,6 +89,7 @@ CONFIG_ARCH_R8A7791=y CONFIG_ARCH_R8A7792=y CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y +CONFIG_ARCH_R9A06G032=y CONFIG_ARCH_SH73A0=y CONFIG_ARCH_SOCFPGA=y CONFIG_PLAT_SPEAR=y -- 2.17.1
[PATCH 01/11] clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.
On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.
Inspired by a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/rcar-gen3-cpg.c | 7 +++
drivers/clk/renesas/rcar-gen3-cpg.h | 4
2 files changed, 11 insertions(+)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 628b63b85d3f09c5..7533a51c679bfd54 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, CPG_FRQCRC_Z2FC_MASK);
+ case CLK_TYPE_GEN3_OSC:
+ /*
+* Clock combining OSC EXTAL predivider and a fixed divider
+*/
+ div = cpg_pll_config->osc_prediv * core->div;
+ break;
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index ea4f8fc3c4c972e7..d7d84d9e4a1c9c8b 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -23,6 +23,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PE,
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
+ CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
};
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
@@ -33,6 +34,8 @@ enum rcar_gen3_clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
(_parent_sscg) << 16 | (_parent_clean),\
.div = (_div_sscg) << 16 | (_div_clean))
+#define DEF_GEN3_OSC(_name, _id, _parent, _div)\
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
@@ -40,6 +43,7 @@ struct rcar_gen3_cpg_pll_config {
u8 pll1_div;
u8 pll3_mult;
u8 pll3_div;
+ u8 osc_prediv;
};
#define CPG_RCKCR 0x240
--
2.17.1
[PATCH 04/11] clk: renesas: r8a77965: Add OSC EXTAL predivider configuration
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car M3-N does not
have the CPG_RCKCR register. Change the OSC and RINT clock definitions
to use the OSC EXTAL predivider instead, which is supported on all R-Car
M3-N SoC revisions.
Inspired by a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 66 -
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 8fae5e9c4a77242d..0b508aaf234c35e9 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -104,8 +104,8 @@ static const struct cpg_core_clk r8a77965_core_clks[]
__initconst = {
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
- DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
- DEF_DIV6_RO("r_int",CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
+ DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN3_OSC("r_int", CLK_RINT, CLK_EXTAL, 32),
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
@@ -252,25 +252,25 @@ static const unsigned int r8a77965_crit_mod_clks[]
__initconst = {
*/
/*
- * MDEXTAL PLL0PLL1PLL3PLL4
+ * MDEXTAL PLL0PLL1PLL3PLL4OSC
* 14 13 19 17 (MHz)
- *---
- * 0 0 0 0 16.66 x 1 x180x192x192x144
- * 0 0 0 1 16.66 x 1 x180x192x128x144
+ *-
+ * 0 0 0 0 16.66 x 1 x180x192x192x144/16
+ * 0 0 0 1 16.66 x 1 x180x192x128x144/16
* 0 0 1 0 Prohibited setting
- * 0 0 1 1 16.66 x 1 x180x192x192x144
- * 0 1 0 0 20x 1 x150x160x160x120
- * 0 1 0 1 20x 1 x150x160x106x120
+ * 0 0 1 1 16.66 x 1 x180x192x192x144/16
+ * 0 1 0 0 20x 1 x150x160x160x120/19
+ * 0 1 0 1 20x 1 x150x160x106x120/19
* 0 1 1 0 Prohibited setting
- * 0 1 1 1 20x 1 x150x160x160x120
- * 1 0 0 0 25x 1 x120x128x128x96
- * 1 0 0 1 25x 1 x120x128x84 x96
+ * 0 1 1 1 20x 1 x150x160x160x120/19
+ * 1 0 0 0 25x 1 x120x128x128x96 /24
+ * 1 0 0 1 25x 1 x120x128x84 x96 /24
* 1 0 1 0 Prohibited setting
- * 1 0 1 1 25x 1 x120x128x128x96
- * 1 1 0 0 33.33 / 2 x180x192x192x144
- * 1 1 0 1 33.33 / 2 x180x192x128x144
+ * 1 0 1 1 25x 1 x120x128x128x96 /24
+ * 1 1 0 0 33.33 / 2 x180x192x192x144/32
+ * 1 1 0 1 33.33 / 2 x180x192x128x144/32
* 1 1 1 0 Prohibited setting
- * 1 1 1 1 33.33 / 2 x180x192x192x144
+ * 1 1 1 1 33.33 / 2 x180x192x192x144/32
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
@@ -278,23 +278,23 @@ static const unsigned int r8a77965_crit_mod_clks[]
__initconst = {
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
- /* EXTAL divPLL1 mult/div PLL3 mult/div */
- { 1,192,1, 192,1, },
- { 1,192,1, 128,1, },
- { 0, /* Prohibited setting */ },
- { 1,192,1, 192,1, },
- { 1,160,1, 160,1, },
- { 1,160,1, 106,1, },
- { 0, /* Prohibited setting */ },
- { 1,160,1, 160,1, },
- { 1,128,1, 128,1, },
- { 1,128,1, 84, 1, },
- { 0, /* Prohibited setting */ },
- { 1,128,1, 128,1, },
- { 2,192,1, 192,1, },
- { 2,192,1, 128,1, },
- { 0, /* Prohibited setting */ },
- { 2,
[PATCH 03/11] clk: renesas: r8a7796: Add OSC EXTAL predivider configuration
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR
register was removed in R-Car M3-W ES1.1. Change the OSC and RINT
clock definitions to use the OSC EXTAL predivider instead, which is
supported on all R-Car M3-W SoC revisions.
Inspired by a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 66 +-
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index dfb267a92f2a20d3..faa11bf5969a97ba 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -110,8 +110,8 @@ static const struct cpg_core_clk r8a7796_core_clks[]
__initconst = {
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
- DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
- DEF_DIV6_RO("r_int",CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
+ DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN3_OSC("r_int", CLK_RINT, CLK_EXTAL, 32),
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
@@ -255,25 +255,25 @@ static const unsigned int r8a7796_crit_mod_clks[]
__initconst = {
*/
/*
- * MDEXTAL PLL0PLL1PLL2PLL3PLL4
+ * MDEXTAL PLL0PLL1PLL2PLL3PLL4
OSC
* 14 13 19 17 (MHz)
- *---
- * 0 0 0 0 16.66 x 1 x180x192x144x192x144
- * 0 0 0 1 16.66 x 1 x180x192x144x128x144
+ *-
+ * 0 0 0 0 16.66 x 1 x180x192x144x192x144/16
+ * 0 0 0 1 16.66 x 1 x180x192x144x128x144/16
* 0 0 1 0 Prohibited setting
- * 0 0 1 1 16.66 x 1 x180x192x144x192x144
- * 0 1 0 0 20x 1 x150x160x120x160x120
- * 0 1 0 1 20x 1 x150x160x120x106x120
+ * 0 0 1 1 16.66 x 1 x180x192x144x192x144/16
+ * 0 1 0 0 20x 1 x150x160x120x160x120/19
+ * 0 1 0 1 20x 1 x150x160x120x106x120/19
* 0 1 1 0 Prohibited setting
- * 0 1 1 1 20x 1 x150x160x120x160x120
- * 1 0 0 0 25x 1 x120x128x96 x128x96
- * 1 0 0 1 25x 1 x120x128x96 x84 x96
+ * 0 1 1 1 20x 1 x150x160x120x160x120/19
+ * 1 0 0 0 25x 1 x120x128x96 x128x96 /24
+ * 1 0 0 1 25x 1 x120x128x96 x84 x96 /24
* 1 0 1 0 Prohibited setting
- * 1 0 1 1 25x 1 x120x128x96 x128x96
- * 1 1 0 0 33.33 / 2 x180x192x144x192x144
- * 1 1 0 1 33.33 / 2 x180x192x144x128x144
+ * 1 0 1 1 25x 1 x120x128x96 x128x96 /24
+ * 1 1 0 0 33.33 / 2 x180x192x144x192x144/32
+ * 1 1 0 1 33.33 / 2 x180x192x144x128x144/32
* 1 1 1 0 Prohibited setting
- * 1 1 1 1 33.33 / 2 x180x192x144x192x144
+ * 1 1 1 1 33.33 / 2 x180x192x144x192x144/32
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
@@ -281,23 +281,23 @@ static const unsigned int r8a7796_crit_mod_clks[]
__initconst = {
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
- /* EXTAL divPLL1 mult/div PLL3 mult/div */
- { 1,192,1, 192,1, },
- { 1,192,1, 128,1, },
- { 0, /* Prohibited setting */ },
- { 1,192,1, 192,1, },
- { 1,160,1, 160,1, },
- { 1,160,1, 106,1, },
- { 0, /* Prohibited setting */ },
- { 1,160,1, 160,1, },
- { 1,128,1, 128,1, },
- { 1,128,1, 84, 1, },
- { 0, /* Prohibited setting */ },
- { 1,128,1,
[PATCH 07/11] clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/rcar-gen3-cpg.c | 23 ---
drivers/clk/renesas/rcar-gen3-cpg.h | 8 +++-
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 7533a51c679bfd54..19a77822757d29de 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -1,7 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
*
* Based on clk-rcar-gen3.c
*
@@ -31,6 +31,8 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
+#define CPG_RCKCR_CKSELBIT(15) /* RCLK Clock Source Select */
+
struct cpg_simple_notifier {
struct notifier_block nb;
void __iomem *reg;
@@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
unsigned int div = 1;
u32 value;
- parent = clks[core->parent & 0x]; /* CLK_TYPE_PE uses high bits */
+ parent = clks[core->parent & 0x]; /* some types use high bits */
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
if (clk_get_rate(clks[cpg_clk_extalr])) {
parent = clks[cpg_clk_extalr];
- value |= BIT(15);
+ value |= CPG_RCKCR_CKSEL;
}
writel(value, csn->reg);
@@ -570,6 +572,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
div = cpg_pll_config->osc_prediv * core->div;
break;
+ case CLK_TYPE_GEN3_RCKSEL:
+ /*
+* Clock selectable between two parents and two fixed dividers
+* using RCKCR.CKSEL
+*/
+ if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
+ div = core->div & 0x;
+ } else {
+ parent = clks[core->parent >> 16];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+ div = core->div >> 16;
+ }
+ break;
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index d7d84d9e4a1c9c8b..214df713ce719991 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -1,7 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
+ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
};
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
@@ -37,6 +38,11 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_OSC(_name, _id, _parent, _div)\
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
+#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
+(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
+
+
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
--
2.17.1
[PATCH 06/11] clk: renesas: cpg-mssr: Add support for fixed rate clocks
Add support for defining fixed rate clocks, to be used for on-chip
oscillators.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/renesas-cpg-mssr.c | 5 +
drivers/clk/renesas/renesas-cpg-mssr.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index f4b013e9352d9efc..e04338932786bc14 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct
cpg_core_clk *core,
}
break;
+ case CLK_TYPE_FR:
+ clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
+ core->mult);
+ break;
+
default:
if (info->cpg_clk_register)
clk = info->cpg_clk_register(dev, core, info,
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index 642f720b9b055337..87bb8f368d4ecd18 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -38,6 +38,7 @@ enum clk_types {
CLK_TYPE_FF,/* Fixed Factor Clock */
CLK_TYPE_DIV6P1,/* DIV6 Clock with 1 parent clock */
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
+ CLK_TYPE_FR,/* Fixed Rate Clock */
/* Custom definitions start here */
CLK_TYPE_CUSTOM,
@@ -56,6 +57,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)\
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div
= _div, .mult = 1)
+#define DEF_RATE(_name, _id, _rate)\
+ DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
/*
* Definitions of Module Clocks
--
2.17.1
[PATCH 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock
R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC clock. Hence augment the configuration structure with all
documented predivider values.
Add the OSC clock using the configured predivider.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index d7ebd9ec00594fc8..093677b8927800fa 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -96,6 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[]
__initconst = {
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+
+ DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
};
static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
@@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[]
__initconst = {
*/
/*
- * MDEXTAL PLL2PLL1PLL3
+ * MDEXTAL PLL2PLL1PLL3OSC
* 14 13 (MHz)
- * --
- * 0 016.66 x 1 x240x192x192
- * 0 120x 1 x200x160x160
- * 1 027x 1 x148x118x118
- * 1 133.33 / 2 x240x192x192
+ *
+ * 0 016.66 x 1 x240x192x192/16
+ * 0 120x 1 x200x160x160/19
+ * 1 027x 1 x148x118x118/24
+ * 1 133.33 / 2 x240x192x192/32
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
- /* EXTAL divPLL1 mult/div PLL3 mult/div */
- { 1,192,1, 192,1, },
- { 1,160,1, 160,1, },
- { 1,118,1, 118,1, },
- { 2,192,1, 192,1, },
+ /* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
+ { 1,192,1, 192,1, 16, },
+ { 1,160,1, 160,1, 19, },
+ { 1,118,1, 118,1, 24, },
+ { 2,192,1, 192,1, 32, },
};
static int __init r8a77980_cpg_mssr_init(struct device *dev)
--
2.17.1
[PATCH 09/11] clk: renesas: r8a77995: Correct RCLK handling
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.
Hence change the OSC and RINT clock definitions to use the RCKCR
divider, and add the missing On-Chip Oscillator and RCLK clock source
switching logic.
Signed-off-by: Geert Uytterhoeven
---
As Figure 8.1f "Block Diagram of CPG (R-Car D3)" shows 1/61 and 1/4
dividers after the On-Chip Oscillator, I assume the OCO runs at 8 MHz.
---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index ea4cafbe6e851aca..b242d01fd21e8c09 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -46,6 +46,8 @@ enum clk_ids {
CLK_S3,
CLK_SDSRC,
CLK_SSPSRC,
+ CLK_RINT,
+ CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
@@ -90,8 +92,8 @@ static const struct cpg_core_clk r8a77995_core_clks[]
__initconst = {
DEF_FIXED("cl",R8A77995_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("cp",R8A77995_CLK_CP,CLK_EXTAL, 2, 1),
- DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL,384, 1),
- DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+ DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
+ DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
@@ -102,6 +104,9 @@ static const struct cpg_core_clk r8a77995_core_clks[]
__initconst = {
DEF_DIV6P1("canfd",R8A77995_CLK_CANFD, CLK_PLL0D3,0x244),
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2,0x014),
+
+ DEF_RATE("oco",CLK_OCO,8 * 1000 * 1000),
+ DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
--
2.17.1
[PATCH 08/11] clk: renesas: r8a77990: Correct RCLK handling
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.
Hence change the OSC and RINT clock definitions to use the RCKCR
divider, and add the missing On-Chip Oscillator and RCLK clock source
switching logic.
Signed-off-by: Geert Uytterhoeven
---
As Figure 8.1g "Block Diagram of CPG (R-Car E3)" shows 1/61 and 1/4
dividers after the On-Chip Oscillator, I assume the OCO runs at 8 MHz.
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9e14f1486fbb93cc..6fcc0abdb20c442d 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -44,6 +44,8 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RINT,
+ CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
@@ -100,8 +102,8 @@ static const struct cpg_core_clk r8a77990_core_clks[]
__initconst = {
DEF_FIXED("cl",R8A77990_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("cp",R8A77990_CLK_CP,CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
- DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL,384, 1),
- DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
+ DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
+ DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
@@ -111,6 +113,9 @@ static const struct cpg_core_clk r8a77990_core_clks[]
__initconst = {
DEF_DIV6P1("canfd",R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
+
+ DEF_RATE("oco",CLK_OCO,8 * 1000 * 1000),
+ DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
--
2.17.1
[PATCH 00/11] clk: renesas: rcar-gen3: OSC and RCLK improvements
Hi all,
This patch series contains various improvements for OSC and RCLK
handling on R-Car Gen3 SoCs.
This has been tested on R-Car H3 ES1.0/ES2.0, R-Car M3-W ES1.0, R-Car
D3, and R-Car E3.
The R-Car V3H (r8a77980) patches were compile-tested only due to lack of
hardware.
Thanks for your comments!
Geert Uytterhoeven (11):
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
clk: renesas: r8a7795: Add OSC EXTAL predivider configuration
clk: renesas: r8a7796: Add OSC EXTAL predivider configuration
clk: renesas: r8a77965: Add OSC EXTAL predivider configuration
clk: renesas: r8a77980: Add OSC predivider configuration and clock
clk: renesas: cpg-mssr: Add support for fixed rate clocks
clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
clk: renesas: r8a77990: Correct RCLK handling
clk: renesas: r8a77995: Correct RCLK handling
clk: renesas: rcar-gen3: Add support for mode pin clock selection
clk: renesas: r8a77980: Add RCLK for watchdog timer
drivers/clk/renesas/r8a7795-cpg-mssr.c | 66 -
drivers/clk/renesas/r8a7796-cpg-mssr.c | 66 -
drivers/clk/renesas/r8a77965-cpg-mssr.c | 66 -
drivers/clk/renesas/r8a77980-cpg-mssr.c | 28 ++-
drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +++-
drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +++-
drivers/clk/renesas/rcar-gen3-cpg.c | 40 +++
drivers/clk/renesas/rcar-gen3-cpg.h | 25 --
drivers/clk/renesas/renesas-cpg-mssr.c | 5 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 3 ++
10 files changed, 189 insertions(+), 128 deletions(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 11/11] clk: renesas: r8a77980: Add RCLK for watchdog timer
On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip
Oscillator using mode pin MD19.
Signed-off-by: Geert Uytterhoeven
---
As Figure 8.1e "Block Diagram of CPG (R-Car V3H)" does not show any
divider after the On-Chip Oscillator, I assume the OCO runs at 32768 Hz.
---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index 093677b8927800fa..122d722aca2db7d4 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
@@ -98,6 +99,8 @@ static const struct cpg_core_clk r8a77980_core_clks[]
__initconst = {
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
+ DEF_RATE("oco", CLK_OCO,32768),
+ DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
@@ -119,6 +122,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[]
__initconst = {
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
DEF_MOD("pciec0",319, R8A77980_CLK_S2D2),
+ DEF_MOD("rwdt", 402, R8A77980_CLK_R),
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
DEF_MOD("hscif3",517, R8A77980_CLK_S3D1),
--
2.17.1
[PATCH 02/11] clk: renesas: r8a7795: Add OSC EXTAL predivider configuration
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR
register was removed in R-Car H3 ES2.0. Change the OSC and RINT
clock definitions to use the OSC EXTAL predivider instead, which is
supported on all R-Car H3 SoC revisions.
Inspired by a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 66 +-
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a85dd50e89110d5d..ea0b33ddcc0ea531 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -111,8 +111,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata =
{
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
- DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
- DEF_DIV6_RO("r_int",CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
+ DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN3_OSC("r_int", CLK_RINT, CLK_EXTAL, 32),
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
@@ -283,25 +283,25 @@ static const unsigned int r8a7795_crit_mod_clks[]
__initconst = {
*/
/*
- * MDEXTAL PLL0PLL1PLL2PLL3PLL4
+ * MDEXTAL PLL0PLL1PLL2PLL3PLL4
OSC
* 14 13 19 17 (MHz)
- *---
- * 0 0 0 0 16.66 x 1 x180x192x144x192x144
- * 0 0 0 1 16.66 x 1 x180x192x144x128x144
+ *-
+ * 0 0 0 0 16.66 x 1 x180x192x144x192x144/16
+ * 0 0 0 1 16.66 x 1 x180x192x144x128x144/16
* 0 0 1 0 Prohibited setting
- * 0 0 1 1 16.66 x 1 x180x192x144x192x144
- * 0 1 0 0 20x 1 x150x160x120x160x120
- * 0 1 0 1 20x 1 x150x160x120x106x120
+ * 0 0 1 1 16.66 x 1 x180x192x144x192x144/16
+ * 0 1 0 0 20x 1 x150x160x120x160x120/19
+ * 0 1 0 1 20x 1 x150x160x120x106x120/19
* 0 1 1 0 Prohibited setting
- * 0 1 1 1 20x 1 x150x160x120x160x120
- * 1 0 0 0 25x 1 x120x128x96 x128x96
- * 1 0 0 1 25x 1 x120x128x96 x84 x96
+ * 0 1 1 1 20x 1 x150x160x120x160x120/19
+ * 1 0 0 0 25x 1 x120x128x96 x128x96 /24
+ * 1 0 0 1 25x 1 x120x128x96 x84 x96 /24
* 1 0 1 0 Prohibited setting
- * 1 0 1 1 25x 1 x120x128x96 x128x96
- * 1 1 0 0 33.33 / 2 x180x192x144x192x144
- * 1 1 0 1 33.33 / 2 x180x192x144x128x144
+ * 1 0 1 1 25x 1 x120x128x96 x128x96 /24
+ * 1 1 0 0 33.33 / 2 x180x192x144x192x144/32
+ * 1 1 0 1 33.33 / 2 x180x192x144x128x144/32
* 1 1 1 0 Prohibited setting
- * 1 1 1 1 33.33 / 2 x180x192x144x192x144
+ * 1 1 1 1 33.33 / 2 x180x192x144x192x144/32
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
@@ -309,23 +309,23 @@ static const unsigned int r8a7795_crit_mod_clks[]
__initconst = {
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
- /* EXTAL divPLL1 mult/div PLL3 mult/div */
- { 1,192,1, 192,1, },
- { 1,192,1, 128,1, },
- { 0, /* Prohibited setting */ },
- { 1,192,1, 192,1, },
- { 1,160,1, 160,1, },
- { 1,160,1, 106,1, },
- { 0, /* Prohibited setting */ },
- { 1,160,1, 160,1, },
- { 1,128,1, 128,1, },
- { 1,128,1, 84, 1, },
- { 0, /* Prohibited setting */ },
- { 1,128,1, 128,
[PATCH 10/11] clk: renesas: rcar-gen3: Add support for mode pin clock selection
Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for arbitrary
clock selection.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/rcar-gen3-cpg.c | 10 --
drivers/clk/renesas/rcar-gen3-cpg.h | 13 +
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 19a77822757d29de..4346fdeef01bbeae 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -539,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
parent = clks[cpg_clk_extalr];
break;
- case CLK_TYPE_GEN3_PE:
+ case CLK_TYPE_GEN3_MDSEL:
/*
-* Peripheral clock with a fixed divider, selectable between
-* clean and spread spectrum parents using MD12
+* Clock selectable between two parents and two fixed dividers
+* using a mode pin
*/
- if (cpg_mode & BIT(12)) {
- /* Clean */
+ if (cpg_mode & BIT(core->offset)) {
div = core->div & 0x;
} else {
- /* SCCG */
parent = clks[core->parent >> 16];
if (IS_ERR(parent))
return ERR_CAST(parent);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 214df713ce719991..01619242d8ca6384 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -20,7 +20,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R,
- CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_MDSEL,/* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
@@ -30,11 +30,16 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
+(_parent0) << 16 | (_parent1), \
+.div = (_div0) << 16 | (_div1), .offset = _md)
+
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
-(_parent_sscg) << 16 | (_parent_clean),\
-.div = (_div_sscg) << 16 | (_div_clean))
+ DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
+ _parent_clean, _div_clean)
+
#define DEF_GEN3_OSC(_name, _id, _parent, _div)\
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
--
2.17.1
Re: [PATCH] arm64: dts: renesas: Unify the labels for RWDT
On Wed, Jul 11, 2018 at 02:43:42PM +0200, Geert Uytterhoeven wrote: > On Wed, Jul 11, 2018 at 10:49 AM Yoshihiro Shimoda > wrote: > > The labels for RWDT device node were named as 2 types now: > > > > - wdt0: r8a7795, r8a7796, r8a77965. > > - rwdt: r8a77970, r8a77990, r8a77995. > > > > To be made consistent, this patch unifis the labels as the hardware > > name "rwdt". > > > > Signed-off-by: Yoshihiro Shimoda > > Reviewed-by: Geert Uytterhoeven Thanks, applied.
Re: [PATCH] arm64: dts: renesas: Unify the labels for RWDT
On Wed, Jul 11, 2018 at 10:49 AM Yoshihiro Shimoda
wrote:
> The labels for RWDT device node were named as 2 types now:
>
> - wdt0: r8a7795, r8a7796, r8a77965.
> - rwdt: r8a77970, r8a77990, r8a77995.
>
> To be made consistent, this patch unifis the labels as the hardware
> name "rwdt".
>
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART
Hi Phil,
On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote:
> The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has additional
> registers for DMA. This patch does not address the changes required for DMA
> support, it simply adds the compatible string.
>
> Signed-off-by: Phil Edworthy
Thanks for your patch!
What happens if someone would boot a kernel that has only this patch applied and
a DTB that already has the to-be-supported dmas properties?
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -693,6 +693,7 @@ static const struct of_device_id dw8250_of_match[] = {
> { .compatible = "snps,dw-apb-uart" },
> { .compatible = "cavium,octeon-3860-uart" },
> { .compatible = "marvell,armada-38x-uart" },
> + { .compatible = "renesas,uart-rzn1" },
renesas,rzn1-uart
> { /* Sentinel */ }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/2] dt: serial: Add Renesas RZ/N1 binding documentation
Hi Phil,
On Wed, Jul 11, 2018 at 2:30 PM Phil Edworthy wrote:
> The RZ/N1 UART is a modified Synopsys DesignWare UART.
> The modifications only relate to DMA so you could actually use the
> controller with the Synopsys compatible string if you are not using
> DMA, but you should not do so.
>
> Signed-off-by: Phil Edworthy
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt
> @@ -0,0 +1,10 @@
> +Renesas RZ/N1 UART
> +
> +This controller is based on the Synopsys DesignWare ABP UART and inherits all
> +properties defined in snps-dw-apb-uart.txt except for the compatible
> property.
> +
> +Required properties:
> +- compatible : The device specific string followed by the generic RZ/N1
> string.
> + Therefore it must be one of:
> + "renesas,uart-r9a06g032", "renesas,uart-rzn1"
"renesas,r9a06g032-uart", "renesas,rzn1-uart"
> + "renesas,uart-r9a06g033", "renesas,uart-rzn1"
"renesas,r9a06g033-uart", "renesas,rzn1-uart"
I assume you plan to describe the DMA-related properties later?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 2/2] serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART
The Renesas RZ/N1 UART is based on the Synopsys DW UART, but has additional
registers for DMA. This patch does not address the changes required for DMA
support, it simply adds the compatible string.
Signed-off-by: Phil Edworthy
---
drivers/tty/serial/8250/8250_dw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index aff04f1..c92f5ad 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -693,6 +693,7 @@ static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart" },
{ .compatible = "cavium,octeon-3860-uart" },
{ .compatible = "marvell,armada-38x-uart" },
+ { .compatible = "renesas,uart-rzn1" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
--
2.7.4
[PATCH 1/2] dt: serial: Add Renesas RZ/N1 binding documentation
The RZ/N1 UART is a modified Synopsys DesignWare UART. The modifications only relate to DMA so you could actually use the controller with the Synopsys compatible string if you are not using DMA, but you should not do so. Signed-off-by: Phil Edworthy --- Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt | 10 ++ 1 file changed, 10 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt diff --git a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt new file mode 100644 index 000..4d40587 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt @@ -0,0 +1,10 @@ +Renesas RZ/N1 UART + +This controller is based on the Synopsys DesignWare ABP UART and inherits all +properties defined in snps-dw-apb-uart.txt except for the compatible property. + +Required properties: +- compatible : The device specific string followed by the generic RZ/N1 string. + Therefore it must be one of: + "renesas,uart-r9a06g032", "renesas,uart-rzn1" + "renesas,uart-r9a06g033", "renesas,uart-rzn1" -- 2.7.4
[PATCH 0/2] dt: serial: Add Renesas RZ/N1 binding documentation
Just a new compatible string for the Synopsys UART to allow us to add DMA at some point in the future. Phil Edworthy (2): dt: serial: Add Renesas RZ/N1 binding documentation serial: 8250_dw: Add compatible string for Renesas RZ/N1 UART Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt | 10 ++ drivers/tty/serial/8250/8250_dw.c | 1 + 2 files changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt -- 2.7.4
[PATCH] arm64: dts: renesas: Unify the labels for RWDT
The labels for RWDT device node were named as 2 types now:
- wdt0: r8a7795, r8a7796, r8a77965.
- rwdt: r8a77970, r8a77990, r8a77995.
To be made consistent, this patch unifis the labels as the hardware
name "rwdt".
Signed-off-by: Yoshihiro Shimoda
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77965.dtsi| 2 +-
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +-
arch/arm64/boot/dts/renesas/ulcb.dtsi| 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e07546f..fb9d08a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -288,7 +288,7 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e602 {
+ rwdt: watchdog@e602 {
compatible = "renesas,r8a7795-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
clocks = < CPG_MOD 402>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index af81962..cbd35c0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -266,7 +266,7 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e602 {
+ rwdt: watchdog@e602 {
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index a37749c..59afc55 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -138,7 +138,7 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e602 {
+ rwdt: watchdog@e602 {
compatible = "renesas,r8a77965-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 9687166..7d3d866 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -850,7 +850,7 @@
status = "okay";
};
- {
+ {
timeout-sec = <60>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi
b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 83c546c..0ead552 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -444,7 +444,7 @@
status = "okay";
};
- {
+ {
timeout-sec = <60>;
status = "okay";
};
--
1.9.1
Re: [PATCH v2] i2c: recovery: rename variable for easier understanding
On 2018-07-11 00:27, Wolfram Sang wrote:
> While refactoring the routine before, it occured to me that this will
> make the code much easier to understand.
Acked-by: Peter Rosin
> Signed-off-by: Wolfram Sang
> ---
>
> Change since V1:
> * rebased to the new recovery refactoring
>
> Branch is here:
> git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
> renesas/i2c/recovery/write-byte-fix
>
> drivers/i2c/i2c-core-base.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
> index 59f8dfc5be36..57538d72f2e5 100644
> --- a/drivers/i2c/i2c-core-base.c
> +++ b/drivers/i2c/i2c-core-base.c
> @@ -185,12 +185,12 @@ static int i2c_generic_bus_free(struct i2c_adapter
> *adap)
> int i2c_generic_scl_recovery(struct i2c_adapter *adap)
> {
> struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
> - int i = 0, val = 1, ret;
> + int i = 0, scl = 1, ret;
>
> if (bri->prepare_recovery)
> bri->prepare_recovery(adap);
>
> - bri->set_scl(adap, val);
> + bri->set_scl(adap, scl);
> if (bri->set_sda)
> bri->set_sda(adap, 1);
> ndelay(RECOVERY_NDELAY);
> @@ -199,7 +199,7 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
>* By this time SCL is high, as we need to give 9 falling-rising edges
>*/
> while (i++ < RECOVERY_CLK_CNT * 2) {
> - if (val) {
> + if (scl) {
> /* SCL shouldn't be low here */
> if (!bri->get_scl(adap)) {
> dev_err(>dev,
> @@ -209,8 +209,8 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
> }
> }
>
> - val = !val;
> - bri->set_scl(adap, val);
> + scl = !scl;
> + bri->set_scl(adap, scl);
>
> /*
>* If we can set SDA, we will always create STOP here to ensure
> @@ -220,10 +220,10 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
>*/
> ndelay(RECOVERY_NDELAY / 2);
> if (bri->set_sda)
> - bri->set_sda(adap, val);
> + bri->set_sda(adap, scl);
> ndelay(RECOVERY_NDELAY / 2);
>
> - if (val) {
> + if (scl) {
> ret = i2c_generic_bus_free(adap);
> if (ret == 0)
> break;
>
Re: [PATCH v2 3/3] i2c: recovery: refactor recovery function
On 2018-07-10 23:42, Wolfram Sang wrote:
> After exiting the while loop, we checked if recovery was successful and
> sent a STOP to the clients. Meanwhile however, we send a STOP after
> every pulse, so it is not needed after the loop. If we move the check
> for a free bus to the end of the while loop, we can shorten and simplify
> the logic. It is still ensured that at least one STOP will be sent to
> the wire even if SDA was not stuck low.
Well, there will be no STOP if ->set_sda isn't implemented, but that case
is also handled equivalently after this patch AFAICT, so
Reviewed-by: Peter Rosin
>
> Signed-off-by: Wolfram Sang
> ---
> drivers/i2c/i2c-core-base.c | 24 ++--
> 1 file changed, 6 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
> index 871a9731894f..c7995efd58ea 100644
> --- a/drivers/i2c/i2c-core-base.c
> +++ b/drivers/i2c/i2c-core-base.c
> @@ -191,9 +191,6 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
> ret = -EBUSY;
> break;
> }
> - /* Break if SDA is high */
> - if (bri->get_sda && bri->get_sda(adap))
> - break;
> }
>
> val = !val;
> @@ -209,22 +206,13 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
> if (bri->set_sda)
> bri->set_sda(adap, val);
> ndelay(RECOVERY_NDELAY / 2);
> - }
> -
> - /* check if recovery actually succeeded */
> - if (bri->get_sda && !bri->get_sda(adap))
> - ret = -EBUSY;
>
> - /* If all went well, send STOP for a sane bus state. */
> - if (ret == 0 && bri->set_sda) {
> - bri->set_scl(adap, 0);
> - ndelay(RECOVERY_NDELAY / 2);
> - bri->set_sda(adap, 0);
> - ndelay(RECOVERY_NDELAY / 2);
> - bri->set_scl(adap, 1);
> - ndelay(RECOVERY_NDELAY / 2);
> - bri->set_sda(adap, 1);
> - ndelay(RECOVERY_NDELAY / 2);
> + /* Break if SDA is high */
> + if (val && bri->get_sda) {
> + ret = bri->get_sda(adap) ? 0 : -EBUSY;
> + if (ret == 0)
> + break;
> + }
> }
>
> if (bri->unprepare_recovery)
>
