Re: [PATCH] dmaengine: sh: rcar-dmac: Should not stop the DMAC by rcar_dmac_sync_tcr()

2018-07-30 Thread Vinod 
On 25-07-18, 17:27, Yoshihiro Shimoda wrote:
> rcar_dmac_chan_get_residue() should not stop the DMAC, because
> the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
> CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
> issue. But it had caused the next issue which might stop the cyclic
> mode transferring. Thus, for example R-Car sound might be stopped
> suddenly.
> 
> According to the commit 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB
> instead of TCR for residue"), the purpose of clearing CHCR.DE bit is
> flushing buffered data to calculate the exact residue.
> 
> Such the "exact" residue had been required by sh-sci driver. sh-sci
> driver is calling dmaengine_pause() to stop transferring, and get
> "exact" residue. Otherwise, it might receive extra data during
> getting residue without pausing.
> 
> In rx_timer_fn() of sh-sci driver:
>   dmaengine_tx_status();  /* For checking roughly */
>   dmaengine_pause();
>   dmaengine_tx_status();  /* For getting residue */
>   dmaengine_terminate_all();
> 
> But, unfortunately the rcar-dmac driver didn't support dmaengine_pause()
> at that time. So, the sh-sci driver cannot get the "exact" residue
> without stopping the transferring, because rcar-dmac is buffering data
> inside.
> 
> Because of these backgrounds, rcar-dmac had been cleared/set CHCR.DE
> bit in rcar_dmac_chan_get_residue() to synchronizing data and getting
> "exact" residue.
> 
> However, rcar-dmac driver has rcar_dmac_chan_pause() now, and clearing
> CHCR.DE bit in rcar_dmac_chan_get_residue() doesn't need anymore.
> So, this patch removes the rcar_dmac_sync_tcr().

Applied, thanks

-- 
~Vinod

Re: [PATCH v2 3/3] serial: sh-sci: Document r7s9210 bindings

2018-07-30 Thread Rob Herring 
On Wed, Jul 25, 2018 at 09:38:50AM -0500, Chris Brandt wrote:
> Add R7S9210 (RZ/A2) support.
> Also describe interrupts property in more detail.
> 
> Signed-off-by: Chris Brandt 
> ---
> v2:
>  * Add more details to interrupts property
>  * Geert gave a Reviewed-by for V1, but then later said that was a
>mistake because it was missing the interrupts description, so
>I didn't include his Reviewed-by yet.
> ---
>  .../devicetree/bindings/serial/renesas,sci-serial.txt   | 17 
> -
>  1 file changed, 16 insertions(+), 1 deletion(-)

Reviewed-by: Rob Herring

Re: [PATCH v3 2/2] dt-bindings: arm: Document RZ/A2 SoC DT bindings

2018-07-30 Thread Rob Herring 
On Fri, Jul 27, 2018 at 11:53:33AM -0500, Chris Brandt wrote:
> Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC.
> Also document new option for "renesas,bsid"
> 
> Signed-off-by: Chris Brandt 
> Reviewed-by: Geert Uytterhoeven 
> ---
> v3:
> * added "or Boundary Scan ID Register" to description
> v2:
>  * added Reviewed-by
>  * added renesas,bsid comment
> ---
>  Documentation/devicetree/bindings/arm/shmobile.txt | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)

Reviewed-by: Rob Herring

[PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node

2018-07-30 Thread Sergei Shtylyov 
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device  trees,  according to  the alphanumeric node sorting rule...

Signed-off-by: Sergei Shtylyov 

---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.

 arch/arm64/boot/dts/renesas/r8a77970.dtsi |   14 +++---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi |   14 +++---
 2 files changed, 14 insertions(+), 14 deletions(-)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -24,6 +24,13 @@
i2c4 = 
};
 
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,13 +89,6 @@
method = "smc";
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -25,6 +25,13 @@
i2c5 = 
};
 
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +84,6 @@
};
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;

Re: [PATCH] arm64: dts: renesas: r8a77990: Enable PWM for Ebisu board

2018-07-30 Thread Geert Uytterhoeven 
Hi Shimoda-san,

On Mon, Jul 30, 2018 at 1:55 PM Yoshihiro Shimoda
 wrote:
> This patch adds PWM device nodes and enables PWM3 and PWM5 for
> R-Car E3 Ebisu board.

Thanks for your patch!

This is used for blacklight control, right?
It may be a good idea to mention that in the comments and/or patch
description.

> Signed-off-by: Yoshihiro Shimoda 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] pinctrl: sh-pfc: r8a77990: Add PWM pins, groups and functions

2018-07-30 Thread Geert Uytterhoeven 
On Mon, Jul 30, 2018 at 1:49 PM Yoshihiro Shimoda
 wrote:
> From: Takeshi Kihara 
>
> This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
> the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Shimoda 

Reviewed-by: Geert Uytterhoeven 
i.e. will queue in sh-pfc-for-v4.20.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] dt-bindings: pwm: rcar: Add bindings for R-Car E3 support

2018-07-30 Thread Geert Uytterhoeven 
On Mon, Jul 30, 2018 at 1:51 PM Yoshihiro Shimoda
 wrote:
> This patch adds bindings for R-Car E3. No driver update is needed.
>
> Signed-off-by: Yoshihiro Shimoda 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 4/4] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB

2018-07-30 Thread Geert Uytterhoeven 
Hi Biju,

On Fri, Jul 27, 2018 at 11:57 AM Biju Das  wrote:
> Adding pinctrl support for EtherAVB interface.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Thanks for the update!

> --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

> @@ -46,6 +49,11 @@
>  };
>
>   {
> +   avb_pins: avb {
> +   groups = "avb_mdio", "avb_gmii_tx_rx";

avb_crs is wired, but deemed unused, right?

In that case:
Reviewed-by: Geert Uytterhoeven 

> +   function = "avb";
> +   };
> +
> scif1_pins: scif1 {
> groups = "scif1_data_b";
> function = "scif1";

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v4 0/2] mmc: {tmio,renesas_sdhi}: fix tuning behavior

2018-07-30 Thread Ulf Hansson 
On 24 July 2018 at 16:51, Niklas Söderlund
 wrote:
> Hi,
>
> Tuning failed on my R-Car H3 ES2.0 board using latest mmc/next while the
> Renesas BSP kernel worked. After some digging I found patches in the BSP
> which remedied this and whit these applied tuning now works for me.
>
> I have done small fixes, updated commit messages and rebased on latest
> mmc/next but Hayakawa-san did all the real work. This change helped me
> to successfully tune a stubborn card I have had trouble in the past to
> get to work.
>
> Since v3 of this patchset I have dropped 2 patches as they requier more
> work as HS400 have been merged since the initial posting. These two
> patches stand alone still fixes tuning issues so while work continues on
> the dropped two these two are ready for upstream consumption.
>
> Masaharu Hayakawa (1):
>   mmc: tmio: Fix tuning flow
>
> Niklas Söderlund (1):
>   mmc: renesas_sdhi: Fix sampling clock position selecting
>
>  drivers/mmc/host/renesas_sdhi_core.c | 12 
>  drivers/mmc/host/tmio_mmc_core.c |  2 --
>  2 files changed, 12 insertions(+), 2 deletions(-)
>
> --
> 2.18.0
>

Thanks, applied for next!

Kind regards
Uffe

Re: [PATCH 1/2] mmc: tmio: rename files and CONFIG options to have the same prefix

2018-07-30 Thread Ulf Hansson 
On 26 July 2018 at 05:28, Masahiro Yamada  wrote:
> As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and
> MFD glue") said, these MMC controllers use the IP from Panasonic.
>
> TMIO (Toshiba Mobile IO) MMC was the first upstreamed user of this IP.
> The common driver code was split and expanded as 'tmio-mmc-core', then
> it become historical misnomer since 'tmio' is not the name of this IP.
>
> I pointed out this [1], and suggested to re-organize the names in the
> form of:
>
>   .c(common code for this IP)
>   _tmio.c   (Toshiba Mobile IO)
>   _sdhi.c   (Renesas SDHI)
>   _uniphier.c   (Socionext UniPhier)
>
> The  in my mind was 'mnsd' because names of Panasonic chips
> are prefixed with 'MN'.
>
> This is the naming scheme as we see in dw_mmc* and sdhci-*.
>
> In the discussion with Wolfram Sang, my suggestion was rejected
> because it implied drastic function renaming, which is too invasive.
>
> Ulf Hansson was still happy with file renaming to clarify the
> relationship between variants.  So, the accepted solution was:
>
>  - Make 'tmio_mmc' the _right_ core name
>  - Align all variant files with the same prefix.
>  - Do not rename functions
>
> This commit renames files as follows:
>
>   tmio_mmc_core.c  -> tmio_mmc.c
>   tmio_mmc.c   -> tmio_mmc_original.c
>   renesas_sdhi_core.c  -> tmio_mmc_sdhi.c
>   renesas_sdhi.h   -> tmio_mmc_sdhi.h
>   renesas_sdhi_internal_dmac.c -> tmio_mmc_sdhi_internal_dmac.c
>   renesas_sdhi_sys_dmac.c  -> tmio_mmc_sdhi_sys_dmac.c
>
> Also rename CONFIG options to match to the file names:
>
>   MMC_TMIO_CORE  -> MMC_TMIO
>   MMC_TMIO   -> MMC_TMIO_ORIGINAL
>   MMC_SDHI   -> MMC_TMIO_SDHI
>   MMC_SDHI_SYS_DMAC  -> MMC_TMIO_SDHI_SYS_DMAC
>   MMC_SDHI_INTERNAL_DMAC -> MMC_TMIO_SDHI_INTERNAL_DMAC
>
> I touched eseries_pxa_defconfig and pxa_defconfig in this commit
> because they are inactive, but renaming of CONFIG options generally
> takes some development cycles.  Old names will be kept until the
> migration is completed, like Renesas folks did when they renamed
> ARCH_SHMOBILE_MULTI to ARCH_RENESAS.
>
> [1] https://www.spinics.net/lists/linux-mmc/msg46952.html
>
> Signed-off-by: Masahiro Yamada 

I am awaiting some feedback from Wolfram before applying.

> ---
>
>  MAINTAINERS|1 -
>  arch/arm/configs/eseries_pxa_defconfig |2 +-
>  arch/arm/configs/pxa_defconfig |2 +-
>  drivers/mmc/host/Kconfig   |   25 +-
>  drivers/mmc/host/Makefile  |8 +-
>  drivers/mmc/host/tmio_mmc.c| 1415 
> ++--
>  drivers/mmc/host/tmio_mmc_core.c   | 1394 ---
>  drivers/mmc/host/tmio_mmc_original.c   |  167 +++

I think there should be another way to format the patch to get better diffstat.

I guess it depends a bit on what version of git you are using, but
trying the -M option may help.


>  .../host/{renesas_sdhi_core.c => tmio_mmc_sdhi.c}  |2 +-
>  .../mmc/host/{renesas_sdhi.h => tmio_mmc_sdhi.h}   |0
>  ...ternal_dmac.c => tmio_mmc_sdhi_internal_dmac.c} |2 +-
>  ...as_sdhi_sys_dmac.c => tmio_mmc_sdhi_sys_dmac.c} |2 +-
>  12 files changed, 1518 insertions(+), 1502 deletions(-)
>  delete mode 100644 drivers/mmc/host/tmio_mmc_core.c
>  create mode 100644 drivers/mmc/host/tmio_mmc_original.c
>  rename drivers/mmc/host/{renesas_sdhi_core.c => tmio_mmc_sdhi.c} (99%)
>  rename drivers/mmc/host/{renesas_sdhi.h => tmio_mmc_sdhi.h} (100%)
>  rename drivers/mmc/host/{renesas_sdhi_internal_dmac.c => 
> tmio_mmc_sdhi_internal_dmac.c} (99%)
>  rename drivers/mmc/host/{renesas_sdhi_sys_dmac.c => 
> tmio_mmc_sdhi_sys_dmac.c} (99%)
>

[...]

Kind regards
Uffe

Re: [PATCH] mmc: renesas_sdhi: Add r8a77990 support

2018-07-30 Thread Ulf Hansson 
On 21 July 2018 at 13:14, Wolfram Sang  wrote:
> This patch adds SDHI support for the R8A77990 SoC (R-Car E3). No driver 
> changes
> needed for anything except HS400 which we will enable separately later.
>
> Signed-off-by: Wolfram Sang 

Thanks, applied for next!

Kind regards
Uffe

> ---
>
> Note: we shouldn't enable HS400 in the DTS files yet, since we don't have the 
> 8
> tap support. But I think we can enable basic support.
>
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt 
> b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> index 839f469f4525..c434200d19d5 100644
> --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
> @@ -28,6 +28,7 @@ Required properties:
> "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
> "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
> "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
> +   "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
> "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
> "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
> "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI 
> controller
> --
> 2.11.0
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups

2018-07-30 Thread Geert Uytterhoeven 
Hi Biju,

On Fri, Jul 27, 2018 at 11:29 AM Biju Das  wrote:
>
> + sergie
>
> > -Original Message-
> > From: Biju Das [mailto:biju@bp.renesas.com]
> > Sent: 27 July 2018 10:22
> > To: Laurent Pinchart ; Geert
> > Uytterhoeven ; Linus Walleij
> > 
> > Cc: Biju Das ; linux-renesas-
> > s...@vger.kernel.org; linux-g...@vger.kernel.org; Simon Horman
> > ; Chris Paterson ;
> > Fabrizio Castro 
> > Subject: [PATCH] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups
> >
> > Add EtherAVB groups and functions definitions for R8A77470 SoC.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Fabrizio Castro 
> > ---
> > This patch is based on the following discussion https://www.mail-
> > archive.com/linux-renesas-soc@vger.kernel.org/msg27480.html
> >
> > and
> >
> > https://en.wikipedia.org/wiki/Media-independent_interface
> > ---
> >  drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 133

Thanks for the update!

Reviewed-by: Geert Uytterhoeven 

I'll wait to see if Sergei has some comments before applying...

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 2/4] serial: sh-sci: Allow for compressed SCIF address

2018-07-30 Thread Geert Uytterhoeven 
On Mon, Jul 30, 2018 at 3:17 PM Chris Brandt  wrote:
> Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> Use the register area size to determine the spacing between register.
>
> Signed-off-by: Chris Brandt 
> ---
> v2:
> * adjust for case of SCIx_PROBE_REGTYPE

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 3/4] serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE

2018-07-30 Thread Chris Brandt 
There is no more need for SCIx_RZ_SCIFA_REGTYPE now that
SCIx_SH4_SCIF_REGTYPE can provide the same register/address definitions.

Also, R7S9210 no longer needs a special compatible since the standard
"renesas,scif" will work just fine.

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v2:
* add Reviewed-by
---
 drivers/tty/serial/sh-sci.c | 31 ---
 include/linux/serial_sci.h  |  1 -
 2 files changed, 32 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index c29244f76057..54ea58bbe3c9 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -293,33 +293,6 @@ static const struct sci_port_params 
sci_port_params[SCIx_NR_REGTYPES] = {
.error_clear = SCIF_ERROR_CLEAR,
},
 
-   /*
-* The "SCIFA" that is in RZ/T and RZ/A2.
-* It looks like a normal SCIF with FIFO data, but with a
-* compressed address space. Also, the break out of interrupts
-* are different: ERI/BRI, RXI, TXI, TEI, DRI.
-*/
-   [SCIx_RZ_SCIFA_REGTYPE] = {
-   .regs = {
-   [SCSMR] = { 0x00, 16 },
-   [SCBRR] = { 0x02,  8 },
-   [SCSCR] = { 0x04, 16 },
-   [SCxTDR]= { 0x06,  8 },
-   [SCxSR] = { 0x08, 16 },
-   [SCxRDR]= { 0x0A,  8 },
-   [SCFCR] = { 0x0C, 16 },
-   [SCFDR] = { 0x0E, 16 },
-   [SCSPTR]= { 0x10, 16 },
-   [SCLSR] = { 0x12, 16 },
-   },
-   .fifosize = 16,
-   .overrun_reg = SCLSR,
-   .overrun_mask = SCLSR_ORER,
-   .sampling_rate_mask = SCI_SR(32),
-   .error_mask = SCIF_DEFAULT_ERROR_MASK,
-   .error_clear = SCIF_ERROR_CLEAR,
-   },
-
/*
 * Common SH-3 SCIF definitions.
 */
@@ -3148,10 +3121,6 @@ static const struct of_device_id of_sci_match[] = {
.compatible = "renesas,scif-r7s72100",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
},
-   {
-   .compatible = "renesas,scif-r7s9210",
-   .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
-   },
/* Family-specific types */
{
.compatible = "renesas,rcar-gen1-scif",
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 1c89611e0e06..c0e795d95477 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -36,7 +36,6 @@ enum {
SCIx_SH4_SCIF_FIFODATA_REGTYPE,
SCIx_SH7705_SCIF_REGTYPE,
SCIx_HSCIF_REGTYPE,
-   SCIx_RZ_SCIFA_REGTYPE,
 
SCIx_NR_REGTYPES,
 };
-- 
2.16.1

[PATCH v2 4/4] serial: sh-sci: Improve support for separate TEI and DRI interrupts

2018-07-30 Thread Chris Brandt 
Some SCIF versions mux error and break interrupts together and then provide
a separate interrupt ID for just TEI/DRI.

Allow all 6 types of interrupts to be specified via platform data (or DT)
and for any signals that are muxed together (have the same interrupt
number) simply register one handler.

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v2:
* Removed - 1 from loop
* Added Reviewed-by
---
 drivers/tty/serial/sh-sci.c | 90 -
 1 file changed, 40 insertions(+), 50 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 54ea58bbe3c9..377b2c1b52b9 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -65,7 +65,8 @@ enum {
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
-   SCIx_TEIDRI_IRQ,
+   SCIx_DRI_IRQ,
+   SCIx_TEI_IRQ,
SCIx_NR_IRQS,
 
SCIx_MUX_IRQ = SCIx_NR_IRQS,/* special case */
@@ -77,9 +78,6 @@ enum {
((port)->irqs[SCIx_ERI_IRQ] &&  \
 ((port)->irqs[SCIx_RXI_IRQ] < 0))
 
-#define SCIx_TEIDRI_IRQ_EXISTS(port)   \
-   ((port)->irqs[SCIx_TEIDRI_IRQ] > 0)
-
 enum SCI_CLKS {
SCI_FCK,/* Functional Clock */
SCI_SCK,/* Optional External Clock */
@@ -1685,14 +1683,23 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
return IRQ_HANDLED;
 }
 
-static irqreturn_t sci_br_interrupt(int irq, void *ptr);
+static irqreturn_t sci_br_interrupt(int irq, void *ptr)
+{
+   struct uart_port *port = ptr;
+
+   /* Handle BREAKs */
+   sci_handle_breaks(port);
+   sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
+
+   return IRQ_HANDLED;
+}
 
 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
 {
struct uart_port *port = ptr;
struct sci_port *s = to_sci_port(port);
 
-   if (SCIx_TEIDRI_IRQ_EXISTS(s)) {
+   if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
/* Break and Error interrupts are muxed */
unsigned short ssr_status = serial_port_in(port, SCxSR);
 
@@ -1727,17 +1734,6 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
return IRQ_HANDLED;
 }
 
-static irqreturn_t sci_br_interrupt(int irq, void *ptr)
-{
-   struct uart_port *port = ptr;
-
-   /* Handle BREAKs */
-   sci_handle_breaks(port);
-   sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
-
-   return IRQ_HANDLED;
-}
-
 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
 {
unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
@@ -1811,6 +1807,16 @@ static const struct sci_irq_desc {
.handler = sci_br_interrupt,
},
 
+   [SCIx_DRI_IRQ] = {
+   .desc = "rx ready",
+   .handler = sci_rx_interrupt,
+   },
+
+   [SCIx_TEI_IRQ] = {
+   .desc = "tx end",
+   .handler = sci_tx_interrupt,
+   },
+
/*
 * Special muxed handler.
 */
@@ -1823,12 +1829,19 @@ static const struct sci_irq_desc {
 static int sci_request_irq(struct sci_port *port)
 {
struct uart_port *up = >port;
-   int i, j, ret = 0;
+   int i, j, w, ret = 0;
 
for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
const struct sci_irq_desc *desc;
int irq;
 
+   /* Check if already registered (muxed) */
+   for (w = 0; w < i; w++)
+   if (port->irqs[w] == port->irqs[i])
+   w = i + 1;
+   if (w > i)
+   continue;
+
if (SCIx_IRQ_IS_MUXED(port)) {
i = SCIx_MUX_IRQ;
irq = up->irq;
@@ -1845,31 +1858,8 @@ static int sci_request_irq(struct sci_port *port)
 
desc = sci_irq_desc + i;
port->irqstr[j] = NULL;
-   if (SCIx_TEIDRI_IRQ_EXISTS(port)) {
-   /*
-* ERI and BRI are muxed, just register ERI and
-* ignore BRI.
-* TEI and DRI are muxed, but only DRI
-* is enabled, so use RXI handler
-*/
-   if (i == SCIx_ERI_IRQ)
-   port->irqstr[j] = kasprintf(GFP_KERNEL,
-   "%s:err + break",
-   dev_name(up->dev));
-   if (i == SCIx_BRI_IRQ)
-   continue;
-   if (i == SCIx_TEIDRI_IRQ) {
-   port->irqstr[j] = kasprintf(GFP_KERNEL,
-   "%s:tx end + rx 
ready",
-   dev_name(up->dev));
-   desc = sci_irq_desc + SCIx_RXI_IRQ;
-

[PATCH v2 2/4] serial: sh-sci: Allow for compressed SCIF address

2018-07-30 Thread Chris Brandt 
Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
Use the register area size to determine the spacing between register.

Signed-off-by: Chris Brandt 
---
v2:
* adjust for case of SCIx_PROBE_REGTYPE
---
 drivers/tty/serial/sh-sci.c | 25 +++--
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 6ff6f2bf3b9b..c29244f76057 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -348,15 +348,15 @@ static const struct sci_port_params 
sci_port_params[SCIx_NR_REGTYPES] = {
[SCIx_SH4_SCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
-   [SCBRR] = { 0x04,  8 },
-   [SCSCR] = { 0x08, 16 },
-   [SCxTDR]= { 0x0c,  8 },
-   [SCxSR] = { 0x10, 16 },
-   [SCxRDR]= { 0x14,  8 },
-   [SCFCR] = { 0x18, 16 },
-   [SCFDR] = { 0x1c, 16 },
-   [SCSPTR]= { 0x20, 16 },
-   [SCLSR] = { 0x24, 16 },
+   [SCBRR] = { 0x02,  8 },
+   [SCSCR] = { 0x04, 16 },
+   [SCxTDR]= { 0x06,  8 },
+   [SCxSR] = { 0x08, 16 },
+   [SCxRDR]= { 0x0a,  8 },
+   [SCFCR] = { 0x0c, 16 },
+   [SCFDR] = { 0x0e, 16 },
+   [SCSPTR]= { 0x10, 16 },
+   [SCLSR] = { 0x12, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
@@ -2848,7 +2848,7 @@ static int sci_init_single(struct platform_device *dev,
 {
struct uart_port *port = _port->port;
const struct resource *res;
-   unsigned int i;
+   unsigned int i, regtype;
int ret;
 
sci_port->cfg   = p;
@@ -2885,6 +2885,7 @@ static int sci_init_single(struct platform_device *dev,
if (unlikely(sci_port->params == NULL))
return -EINVAL;
 
+   regtype = sci_port->params - sci_port_params;
switch (p->type) {
case PORT_SCIFB:
sci_port->rx_trigger = 48;
@@ -2939,6 +2940,10 @@ static int sci_init_single(struct platform_device *dev,
port->regshift = 1;
}
 
+   if (regtype == SCIx_SH4_SCIF_REGTYPE)
+   if (sci_port->reg_size >= 0x20)
+   port->regshift = 1;
+
/*
 * The UART port needs an IRQ value, so we peg this to the RX IRQ
 * for the multi-IRQ ports, which is where we are primarily
-- 
2.16.1

[PATCH v2 0/4] serial: sh-sci: Clean up previous RZ/A2 support

2018-07-30 Thread Chris Brandt 
This patch series doesn't really provide much new functionality, but
rather provides a cleaner solution for adding RZ/A2 support.

This series applies on top of tty-next

v2:
* Incorporated feedback from Geert
* Added Reviewed-by


Chris Brandt (4):
  serial: sh-sci: Improve interrupts description
  serial: sh-sci: Allow for compressed SCIF address
  serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE
  serial: sh-sci: Improve support for separate TEI and DRI interrupts

 .../bindings/serial/renesas,sci-serial.txt |  16 ++-
 drivers/tty/serial/sh-sci.c| 146 -
 include/linux/serial_sci.h |   1 -
 3 files changed, 70 insertions(+), 93 deletions(-)

-- 
2.16.1

[PATCH v2 1/4] serial: sh-sci: Improve interrupts description

2018-07-30 Thread Chris Brandt 
Describe interrupts property in more detail, especially when there are
more than one interrupt.

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
 .../devicetree/bindings/serial/renesas,sci-serial.txt| 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt 
b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index a7cda6550100..eaca9da79d83 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -73,7 +73,21 @@ Required properties:
 family-specific and/or generic versions.
 
   - reg: Base address and length of the I/O registers used by the UART.
-  - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
+  - interrupts: Must contain one or more interrupt-specifiers for the SCIx.
+If a single interrupt is expressed, then all events are
+multiplexed into this single interrupt.
+
+If multiple interrupts are provided by the hardware, the order
+in which the interrupts are listed must match order below. Note
+that some HW interrupt events may be muxed together resulting
+in duplicate entries.
+The interrupt order is as follows:
+  1. Error (ERI)
+  2. Receive buffer full (RXI)
+  3. Transmit buffer empty (TXI)
+  4. Break (BRI)
+  5. Data Ready (DRI)
+  6. Transmit End (TEI)
 
   - clocks: Must contain a phandle and clock-specifier pair for each entry
 in clock-names.
-- 
2.16.1

RE: [PATCH 4/4] serial: sh-sci: Improve support for separate TEI and DRI interrupts

2018-07-30 Thread Chris Brandt 
Hi Geert,

On Monday, July 30, 2018, Geert Uytterhoeven wrote:
> That's not the array, but the enum.
> 
> The array is in struct sci_port:
> 
> int irqs[SCIx_NR_IRQS];
> 
> It has four entries, at indices 0..3.

> irqs[SCIx_NR_IRQS] does not exist!
> 
> sci_irq_desc[SCIx_NR_IRQS] aka sci_irq_desc[SCIx_MUX_IRQ] does exit,
> but that's a different array.


> Your loop is:
> 
> for (i = 1; i < ARRAY_SIZE(sci_port->irqs) - 1; i++)
> 
> It loops over 1..ARRAY_SIZE(sci_port->irqs) - 2.
> Note the "<" and the "- 1".


A, you're right!
Sorry about that.

Thanks,
Chris

Re: [PATCH 4/4] serial: sh-sci: Improve support for separate TEI and DRI interrupts

2018-07-30 Thread Geert Uytterhoeven 
Hi Chris,

On Mon, Jul 30, 2018 at 2:33 PM Chris Brandt  wrote:
> On Monday, July 30, 2018, Geert Uytterhoeven wrote:
> > > if (sci_port->irqs[0] < 0)
> > > return -ENXIO;
> > >
> > > -   if (sci_port->irqs[1] < 0) {
> > > -   sci_port->irqs[1] = sci_port->irqs[0];
> > > -   sci_port->irqs[2] = sci_port->irqs[0];
> > > -   sci_port->irqs[3] = sci_port->irqs[0];
> > > -   }
> > > +   if (sci_port->irqs[1] < 0)
> > > +   for (i = 1; i < ARRAY_SIZE(sci_port->irqs) - 1; i++)
> >
> > Shouldn't the "- 1" be dropped?
>
> In reality, the last entry of the array is 'SCIx_NR_IRQS', so it's not
> really used anywhere.
>
> The original array was:
> enum {
> SCIx_ERI_IRQ,   (the only IRQ specified in DT)

=0

> SCIx_RXI_IRQ,   << copy from irqs[0]

= 1

> SCIx_TXI_IRQ,   << copy from irqs[0]

= 2

> SCIx_BRI_IRQ,   << copy from irqs[0]

= 3

> SCIx_NR_IRQS,   (didn’t' touch)

= 4

>
> SCIx_MUX_IRQ = SCIx_NR_IRQS,/* special case */
> };

That's not the array, but the enum.

The array is in struct sci_port:

int irqs[SCIx_NR_IRQS];

It has four entries, at indices 0..3.

> So the new for loop used "- "1 in order to create the same outcome.
>
> But as far as I can tell irqs[SCIx_NR_IRQS] is never used anywhere, it
> doesn't really matter.

irqs[SCIx_NR_IRQS] does not exist!

sci_irq_desc[SCIx_NR_IRQS] aka sci_irq_desc[SCIx_MUX_IRQ] does exit,
but that's a different array.

> > With the above fixed:
> > Reviewed-by: Geert Uytterhoeven 
>
> I have no problem taking the "- 1" out.
>
> But...here's the funny part: It was you that suggested the "- 1"  ;)
>
> On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > > @@ -2809,6 +2845,8 @@ static int sci_init_single(struct platform_device
> > *dev,
> > > sci_port->irqs[1] = sci_port->irqs[0];
> > > sci_port->irqs[2] = sci_port->irqs[0];
> > > sci_port->irqs[3] = sci_port->irqs[0];
> > > +   sci_port->irqs[4] = sci_port->irqs[0];
> > > +   sci_port->irqs[5] = sci_port->irqs[0];
> >
> > You may want to start using a loop from 1 to ARRAY_SIZE(sci_port->irqs) - 1
> > instead.

Your loop is:

for (i = 1; i < ARRAY_SIZE(sci_port->irqs) - 1; i++)

It loops over 1..ARRAY_SIZE(sci_port->irqs) - 2.
Note the "<" and the "- 1".

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] arm64: dts: renesas: r8a77990: Enable PWM for Ebisu board

2018-07-30 Thread Yoshihiro Shimoda 
This patch adds PWM device nodes and enables PWM3 and PWM5 for
R-Car E3 Ebisu board.

Signed-off-by: Yoshihiro Shimoda 
---
 I have submitted dt-bindings for R-Car E3 (not merged into PWM subsystem yet):
 https://patchwork.kernel.org/patch/10548969/

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 24 +
 arch/arm64/boot/dts/renesas/r8a77990.dtsi  | 70 ++
 2 files changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 2bc3a48..31934a3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -67,6 +67,16 @@
};
};
 
+   pwm3_pins: pwm3 {
+   groups = "pwm3_b";
+   function = "pwm3";
+   };
+
+   pwm5_pins: pwm5 {
+   groups = "pwm5_a";
+   function = "pwm5";
+   };
+
usb0_pins: usb {
groups = "usb0_b";
function = "usb0";
@@ -78,6 +88,20 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+};
+
  {
timeout-sec = <60>;
status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 2c8f119..2ee0edf 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -337,6 +337,76 @@
status = "disabled";
};
 
+   pwm0: pwm@e6e3 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e3 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm1: pwm@e6e31000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e31000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm2: pwm@e6e32000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e32000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm3: pwm@e6e33000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e33000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm4: pwm@e6e34000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e34000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm5: pwm@e6e35000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e35000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm6: pwm@e6e36000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e36000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
1.9.1

[PATCH] pinctrl: sh-pfc: r8a77990: Add PWM pins, groups and functions

2018-07-30 Thread Yoshihiro Shimoda 
From: Takeshi Kihara 

This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 211 ++
 1 file changed, 211 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index b81c807..5ea63e5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1507,6 +1507,157 @@ enum {
SCL7_B_MARK, SDA7_B_MARK,
 };
 
+/* - PWM0 
*/
+static const unsigned int pwm0_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int pwm0_a_mux[] = {
+   PWM0_A_MARK,
+};
+
+static const unsigned int pwm0_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 3),
+};
+
+static const unsigned int pwm0_b_mux[] = {
+   PWM0_B_MARK,
+};
+
+/* - PWM1 
*/
+static const unsigned int pwm1_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 23),
+};
+
+static const unsigned int pwm1_a_mux[] = {
+   PWM1_A_MARK,
+};
+
+static const unsigned int pwm1_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 4),
+};
+
+static const unsigned int pwm1_b_mux[] = {
+   PWM1_B_MARK,
+};
+
+/* - PWM2 
*/
+static const unsigned int pwm2_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 0),
+};
+
+static const unsigned int pwm2_a_mux[] = {
+   PWM2_A_MARK,
+};
+
+static const unsigned int pwm2_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 4),
+};
+
+static const unsigned int pwm2_b_mux[] = {
+   PWM2_B_MARK,
+};
+
+static const unsigned int pwm2_c_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 5),
+};
+
+static const unsigned int pwm2_c_mux[] = {
+   PWM2_C_MARK,
+};
+
+/* - PWM3 
*/
+static const unsigned int pwm3_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 1),
+};
+
+static const unsigned int pwm3_a_mux[] = {
+   PWM3_A_MARK,
+};
+
+static const unsigned int pwm3_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 5),
+};
+
+static const unsigned int pwm3_b_mux[] = {
+   PWM3_B_MARK,
+};
+
+static const unsigned int pwm3_c_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 6),
+};
+
+static const unsigned int pwm3_c_mux[] = {
+   PWM3_C_MARK,
+};
+
+/* - PWM4 
*/
+static const unsigned int pwm4_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 3),
+};
+
+static const unsigned int pwm4_a_mux[] = {
+   PWM4_A_MARK,
+};
+
+static const unsigned int pwm4_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 7),
+};
+
+static const unsigned int pwm4_b_mux[] = {
+   PWM4_B_MARK,
+};
+
+/* - PWM5 
*/
+static const unsigned int pwm5_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int pwm5_a_mux[] = {
+   PWM5_A_MARK,
+};
+
+static const unsigned int pwm5_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 10),
+};
+
+static const unsigned int pwm5_b_mux[] = {
+   PWM5_B_MARK,
+};
+
+/* - PWM6 
*/
+static const unsigned int pwm6_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 25),
+};
+
+static const unsigned int pwm6_a_mux[] = {
+   PWM6_A_MARK,
+};
+
+static const unsigned int pwm6_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(6, 11),
+};
+
+static const unsigned int pwm6_b_mux[] = {
+   PWM6_B_MARK,
+};
+
 /* - SCIF0 -- 
*/
 static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -1854,6 +2005,22 @@ enum {
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c7_a),
SH_PFC_PIN_GROUP(i2c7_b),
+   SH_PFC_PIN_GROUP(pwm0_a),
+   SH_PFC_PIN_GROUP(pwm0_b),
+   SH_PFC_PIN_GROUP(pwm1_a),
+   SH_PFC_PIN_GROUP(pwm1_b),
+   SH_PFC_PIN_GROUP(pwm2_a),
+   SH_PFC_PIN_GROUP(pwm2_b),
+   SH_PFC_PIN_GROUP(pwm2_c),
+   SH_PFC_PIN_GROUP(pwm3_a),
+   SH_PFC_PIN_GROUP(pwm3_b),
+   SH_PFC_PIN_GROUP(pwm3_c),
+   SH_PFC_PIN_GROUP(pwm4_a),
+   SH_PFC_PIN_GROUP(pwm4_b),
+   SH_PFC_PIN_GROUP(pwm5_a),
+   SH_PFC_PIN_GROUP(pwm5_b),
+   SH_PFC_PIN_GROUP(pwm6_a),
+   SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@@ -1934,6 +2101,43 @@ enum {
"i2c7_b",
 };
 
+static const char * const pwm0_groups[] = {
+   "pwm0_a",
+   "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+   "pwm1_a",
+

Re: [PATCH V5] ARM: shmobile: Rework the PMIC IRQ line quirk

2018-07-30 Thread Marek Vasut 
On 06/13/2018 01:21 PM, Geert Uytterhoeven wrote:
> Hi Simon,

Hi,

> On Wed, Jun 13, 2018 at 1:06 PM Simon Horman  wrote:
>> On Mon, Jun 11, 2018 at 02:15:13PM +0200, Marek Vasut wrote:
>>> Rather than hard-coding the quirk topology, which stopped scaling,
>>> parse the information from DT. The code looks for all compatible
>>> PMICs -- da9063 and da9210 -- and checks if their IRQ line is tied
>>> to the same pin. If so, the code sends a matching sequence to the
>>> PMIC to deassert the IRQ.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Geert Uytterhoeven 
>>> Cc: Kuninori Morimoto 
>>> Cc: Simon Horman 
>>> Cc: Wolfram Sang 
>>> Cc: linux-renesas-soc@vger.kernel.org
>>> Acked-by: Wolfram Sang 
>>> Tested-by: Geert Uytterhoeven  (on Koelsch)
>>
>> This looks fine to me but I will wait to see if there are other reviews
>> before applying.
>>
>> Reviewed-by: Simon Horman 
> 
> Note that applying it now will break gose, as its DTS doesn't describe all
> regulators yet.

https://patchwork.kernel.org/patch/10548919/ should fix this.
https://patchwork.kernel.org/patch/10548923/ for Silk.

-- 
Best regards,
Marek Vasut

[PATCH] ARM: shmobile: silk: Add DA9063 PMIC node

2018-07-30 Thread Marek Vasut 
Add DA9063 PMIC node to the I2C bus.

Signed-off-by: Marek Vasut 
Cc: Geert Uytterhoeven 
Cc: Kuninori Morimoto 
Cc: Simon Horman 
Cc: Wolfram Sang 
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm/boot/dts/r8a7794-silk.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts 
b/arch/arm/boot/dts/r8a7794-silk.dts
index daec965889d3..bf7e8ffd1e69 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -403,6 +403,18 @@
pinctrl-names = "i2c-hdmi";
 
clock-frequency = <40>;
+
+   pmic@5a {
+   compatible = "dlg,da9063";
+   reg = <0x5a>;
+   interrupt-parent = <>;
+   interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+   interrupt-controller;
+
+   wdt {
+   compatible = "dlg,da9063-watchdog";
+   };
+   };
 };
 
  {
-- 
2.16.2

[PATCH] ARM: shmobile: gose: Add DA9210 node for CPU DVFS

2018-07-30 Thread Marek Vasut 
Add DA9210 DVFS node to the I2C bus and link it to CPU0 for DVFS.

Signed-off-by: Marek Vasut 
Cc: Geert Uytterhoeven 
Cc: Kuninori Morimoto 
Cc: Simon Horman 
Cc: Wolfram Sang 
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm/boot/dts/r8a7793-gose.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793-gose.dts 
b/arch/arm/boot/dts/r8a7793-gose.dts
index 6b2f3a4fd13d..f51601af89a2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -596,6 +596,10 @@
status = "okay";
 };
 
+ {
+   cpu0-supply = <_dvfs>;
+};
+
  {
timeout-sec = <60>;
status = "okay";
@@ -725,6 +729,18 @@
compatible = "dlg,da9063-watchdog";
};
};
+
+   vdd_dvfs: regulator@68 {
+   compatible = "dlg,da9210";
+   reg = <0x68>;
+   interrupt-parent = <>;
+   interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <100>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
 };
 
  {
-- 
2.16.2

RE: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support

2018-07-30 Thread Biju Das 
Hi Geert,

Thanks for the feedback.

> -Original Message-
> From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
> Sent: 30 July 2018 11:04
> To: Biju Das 
> Cc: Linus Walleij ; open list:GPIO SUBSYSTEM
> ; Simon Horman ;
> Geert Uytterhoeven ; Chris Paterson
> ; Fabrizio Castro
> ; Linux-Renesas  s...@vger.kernel.org>
> Subject: Re: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support
>
> Hi Biju,
>
> On Fri, Jul 27, 2018 at 11:57 AM Biju Das  wrote:
> > Enhance gpio-ranges to support more than one gpio-range.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Fabrizio Castro 
>
> Thanks for your patch!
>
> However, I'm wondering if this works as intended, as the discontinuity is not
> in the pins, but in the GPIO bits.
>
> > ---
> > cat /sys/kernel/debug/pinctrl/e606.pin-controller-sh-pfc/gpio-
> > GPIO ranges handled:
> > 0: e605.gpio GPIOS [1001 - 1023] PINS [0 - 22]
> > 0: e6051000.gpio GPIOS [978 - 1000] PINS [32 - 54]
> > 0: e6052000.gpio GPIOS [946 - 977] PINS [64 - 95]
> > 0: e6053000.gpio GPIOS [926 - 942] PINS [96 - 112]
> > 17: e6053000.gpio GPIOS [943 - 945] PINS [123 - 125]
>
> The above two lines are the result of:
>
> +   gpio-ranges = < 0 96 17>, < 17 123 3>;
>
> > 0: e6054000.gpio GPIOS [900 - 925] PINS [128 - 153]
> > 0: e6055000.gpio GPIOS [868 - 899] PINS [160 - 191]
> > ---
> >  drivers/gpio/gpio-rcar.c | 15 ---
> >  1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index
> > 350390c..a7bbe78 100644
> > --- a/drivers/gpio/gpio-rcar.c
> > +++ b/drivers/gpio/gpio-rcar.c
> > @@ -399,13 +399,22 @@ static int gpio_rcar_parse_dt(struct
> gpio_rcar_priv *p, unsigned int *npins)
> > struct device_node *np = p->pdev->dev.of_node;
> > const struct gpio_rcar_info *info;
> > struct of_phandle_args args;
> > -   int ret;
> > +   int index = 0, ret;
> >
> > info = of_device_get_match_data(>pdev->dev);
> >
> > -   ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
> );
> > -   *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
> > p->has_both_edge_trigger = info->has_both_edge_trigger;
> > +   *npins = 0;
> > +   for (;; index++) {
> > +   ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
> > +   index, );
> > +   if (ret) {
> > +   if (index == 0)
> > +   *npins = RCAR_MAX_GPIO_PER_BANK;
> > +   break;
> > +   }
> > +   *npins += args.args[2];
> > +   }
>
> So after this, *npins will be the total number of GPIOs present in this bank
> (17 + 3 = 20), which will be used as gpio_chip.ngpio.
>
> All GPIO operations will use the passed offset as the bit number.
> gpio_rcar_resume() will resume bits 0..ngpio - 1 of each register.
> gpio_rcar_set_multiple() uses GENMASK(chip->ngpio - 1, 0) as the bank
> mask, and uses it to mask of bits in the registers.
>
> Hence all of the above assumes the register bits for the GPIOs are 0..19.
> However, according to the datasheet, the GPIOs in bank 3 are 0..16 and
> 27..29. So accessing GPIOs 17..19 in the bank will write to bits 17..19, not 
> to
> 27..29!

I have done the below  GPIO operation using sysfs to check this. (As per this 
gpio 943 mapped to gpiobit 17 which request Pin123(GP3_27)
But I haven't checked GPIO registers to check whether it is actually setting 
the values to  GP3_17 or GP3_27. Will check this.

root@iwg23s:~# echo 943 > /sys/class/gpio/export
[   51.796570] sh-pfc e606.pin-controller: request pin 123 (GP_3_27) for 
e6053000.gpio:943
[   51.804960] sh-pfc e606.pin-controller: write_reg addr = e6060010, value 
= 0x0, field = 4, r_width = 32, f_width = 1

Kernel logs:-

[0.110156] gpio gpiochip3: (e6053000.gpio): created GPIO range 0->16 ==> 
e606.pin-controller PIN 96->112
[0.110187] gpio gpiochip3: (e6053000.gpio): created GPIO range 17->19 ==> 
e606.pin-controller PIN 123->125
[0.110363] gpio gpiochip3: (e6053000.gpio): added GPIO chardev (254:3)
[0.110460] gpiochip_setup_dev: registered GPIOs 926 to 945 on device: 
gpiochip3 (e6053000.gpio)

PIncontrol  related for GPIO 3


pin 96 (GP_3_0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 97 (GP_3_1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 98 (GP_3_2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 99 (GP_3_3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 100 (GP_3_4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 101 (GP_3_5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 102 (GP_3_6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 103 (GP_3_7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 104 (GP_3_8): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 105 (GP_3_9): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 106 (GP_3_10): (MUX UNCLAIMED) (GPIO UNCLAIMED)
 pin 107 (GP_3_11): (MUX UNCLAIMED) (GPIO

Re: [PATCH 3/4] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ

2018-07-30 Thread Geert Uytterhoeven 
On Fri, Jul 27, 2018 at 11:57 AM Biju Das  wrote:
> Specify  EtherAVB PHY IRQ  in the board specific device tree, now that we
> have GPIO support.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support

2018-07-30 Thread Geert Uytterhoeven 
Hi Biju,

On Fri, Jul 27, 2018 at 11:57 AM Biju Das  wrote:
> Enhance gpio-ranges to support more than one gpio-range.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Thanks for your patch!

However, I'm wondering if this works as intended, as the discontinuity is
not in the pins, but in the GPIO bits.

> ---
> cat /sys/kernel/debug/pinctrl/e606.pin-controller-sh-pfc/gpio-
> GPIO ranges handled:
> 0: e605.gpio GPIOS [1001 - 1023] PINS [0 - 22]
> 0: e6051000.gpio GPIOS [978 - 1000] PINS [32 - 54]
> 0: e6052000.gpio GPIOS [946 - 977] PINS [64 - 95]
> 0: e6053000.gpio GPIOS [926 - 942] PINS [96 - 112]
> 17: e6053000.gpio GPIOS [943 - 945] PINS [123 - 125]

The above two lines are the result of:

+   gpio-ranges = < 0 96 17>, < 17 123 3>;

> 0: e6054000.gpio GPIOS [900 - 925] PINS [128 - 153]
> 0: e6055000.gpio GPIOS [868 - 899] PINS [160 - 191]
> ---
>  drivers/gpio/gpio-rcar.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
> index 350390c..a7bbe78 100644
> --- a/drivers/gpio/gpio-rcar.c
> +++ b/drivers/gpio/gpio-rcar.c
> @@ -399,13 +399,22 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, 
> unsigned int *npins)
> struct device_node *np = p->pdev->dev.of_node;
> const struct gpio_rcar_info *info;
> struct of_phandle_args args;
> -   int ret;
> +   int index = 0, ret;
>
> info = of_device_get_match_data(>pdev->dev);
>
> -   ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, 
> );
> -   *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
> p->has_both_edge_trigger = info->has_both_edge_trigger;
> +   *npins = 0;
> +   for (;; index++) {
> +   ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
> +   index, );
> +   if (ret) {
> +   if (index == 0)
> +   *npins = RCAR_MAX_GPIO_PER_BANK;
> +   break;
> +   }
> +   *npins += args.args[2];
> +   }

So after this, *npins will be the total number of GPIOs present in this bank
(17 + 3 = 20), which will be used as gpio_chip.ngpio.

All GPIO operations will use the passed offset as the bit number.
gpio_rcar_resume() will resume bits 0..ngpio - 1 of each register.
gpio_rcar_set_multiple() uses GENMASK(chip->ngpio - 1, 0) as the bank mask,
and uses it to mask of bits in the registers.

Hence all of the above assumes the register bits for the GPIOs are 0..19.
However, according to the datasheet, the GPIOs in bank 3 are 0..16 and
27..29. So accessing GPIOs 17..19 in the bank will write to bits 17..19,
not to 27..29!

A simple way to work around this is to set ngpios to the highest bit number
in use + 1. But you still need a mechanism to avoid accessing the unused
bits in the gap between 16 and 27.

>
> if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
> dev_warn(>pdev->dev,

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-07-30 Thread Geert Uytterhoeven 
Hi Kaneko-san,

On Wed, Jul 25, 2018 at 10:42 PM Yoshihiro Kaneko  wrote:
> From: Dien Pham 
>
> This patch adds OPPs table for CA57{0,1} cpu devices
>
> Signed-off-by: Dien Pham 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Syntax looks good, but I cannot review the actual values.
Acked-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] dmaengine: sh: rcar-dmac: Should not stop the DMAC by rcar_dmac_sync_tcr()

2018-07-30 Thread Geert Uytterhoeven 
On Wed, Jul 25, 2018 at 10:29 AM Yoshihiro Shimoda
 wrote:
> rcar_dmac_chan_get_residue() should not stop the DMAC, because
> the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
> CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
> issue. But it had caused the next issue which might stop the cyclic
> mode transferring. Thus, for example R-Car sound might be stopped
> suddenly.
>
> According to the commit 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB
> instead of TCR for residue"), the purpose of clearing CHCR.DE bit is
> flushing buffered data to calculate the exact residue.
>
> Such the "exact" residue had been required by sh-sci driver. sh-sci
> driver is calling dmaengine_pause() to stop transferring, and get
> "exact" residue. Otherwise, it might receive extra data during
> getting residue without pausing.
>
> In rx_timer_fn() of sh-sci driver:
> dmaengine_tx_status();  /* For checking roughly */
> dmaengine_pause();
> dmaengine_tx_status();  /* For getting residue */
> dmaengine_terminate_all();
>
> But, unfortunately the rcar-dmac driver didn't support dmaengine_pause()
> at that time. So, the sh-sci driver cannot get the "exact" residue
> without stopping the transferring, because rcar-dmac is buffering data
> inside.
>
> Because of these backgrounds, rcar-dmac had been cleared/set CHCR.DE
> bit in rcar_dmac_chan_get_residue() to synchronizing data and getting
> "exact" residue.
>
> However, rcar-dmac driver has rcar_dmac_chan_pause() now, and clearing
> CHCR.DE bit in rcar_dmac_chan_get_residue() doesn't need anymore.
> So, this patch removes the rcar_dmac_sync_tcr().
>
> Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for 
> residue")
> Signed-off-by: Yoshihiro Shimoda 
> Tested-by: Hiroyuki Yokoyama 

Makes sense, so
Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 4/4] serial: sh-sci: Improve support for separate TEI and DRI interrupts

2018-07-30 Thread Geert Uytterhoeven 
Hi Chris,

On Fri, Jul 27, 2018 at 11:09 PM Chris Brandt  wrote:
> Some SCIF versions mux error and break interrupts together and then provide
> a separate interrupt ID for just TEI/DRI.
>
> Allow all 6 types of interrupts to be specified via platform data (or DT)
> and for any signals that are muxed together (have the same interrupt
> number) simply register one handler.
>
> Signed-off-by: Chris Brandt 

Thanks for your patch!

> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c

> @@ -2842,17 +2832,17 @@ static int sci_init_single(struct platform_device 
> *dev,
>
> /* The SCI generates several interrupts. They can be muxed together or
>  * connected to different interrupt lines. In the muxed case only one
> -* interrupt resource is specified. In the non-muxed case three or 
> four
> -* interrupt resources are specified, as the BRI interrupt is 
> optional.
> +* interrupt resource is specified as there is only one interrupt ID.
> +* In the non-muxed case, up to 6 interrupt signals might be generated
> +* from the SCI, however those signals might have their own individual
> +* interrupt ID numbers, or muxed together with another interrupt.
>  */
> if (sci_port->irqs[0] < 0)
> return -ENXIO;
>
> -   if (sci_port->irqs[1] < 0) {
> -   sci_port->irqs[1] = sci_port->irqs[0];
> -   sci_port->irqs[2] = sci_port->irqs[0];
> -   sci_port->irqs[3] = sci_port->irqs[0];
> -   }
> +   if (sci_port->irqs[1] < 0)
> +   for (i = 1; i < ARRAY_SIZE(sci_port->irqs) - 1; i++)

Shouldn't the "- 1" be dropped?

> +   sci_port->irqs[i] = sci_port->irqs[0];
>
> sci_port->params = sci_probe_regmap(p);
> if (unlikely(sci_port->params == NULL))

With the above fixed:
Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] thermal: rcar_gen3_thermal: convert to SPDX identifiers

2018-07-30 Thread Niklas Söderlund 
Hi Morimoto-san,

Thanks for your patch.

On 2018-07-30 07:57:22 +, Kuninori Morimoto wrote:
> 
> From: Kuninori Morimoto 
> 
> Signed-off-by: Kuninori Morimoto 

Reviewed-by: Niklas Söderlund 

> ---
>  drivers/thermal/rcar_gen3_thermal.c | 11 +--
>  1 file changed, 1 insertion(+), 10 deletions(-)
> 
> diff --git a/drivers/thermal/rcar_gen3_thermal.c 
> b/drivers/thermal/rcar_gen3_thermal.c
> index 766521e..7aed533 100644
> --- a/drivers/thermal/rcar_gen3_thermal.c
> +++ b/drivers/thermal/rcar_gen3_thermal.c
> @@ -1,19 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
>  /*
>   *  R-Car Gen3 THS thermal sensor driver
>   *  Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen.
>   *
>   * Copyright (C) 2016 Renesas Electronics Corporation.
>   * Copyright (C) 2016 Sang Engineering
> - *
> - *  This program is free software; you can redistribute it and/or modify
> - *  it under the terms of the GNU General Public License as published by
> - *  the Free Software Foundation; version 2 of the License.
> - *
> - *  This program is distributed in the hope that it will be useful, but
> - *  WITHOUT ANY WARRANTY; without even the implied warranty of
> - *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> - *  General Public License for more details.
> - *
>   */
>  #include 
>  #include 
> -- 
> 2.7.4
> 

-- 
Regards,
Niklas Söderlund

Re: [PATCH] thermal: rcar_gen3_thermal: convert to SPDX identifiers

2018-07-30 Thread Daniel Lezcano 
On 30/07/2018 09:57, Kuninori Morimoto wrote:
> 
> From: Kuninori Morimoto 
> 
> Signed-off-by: Kuninori Morimoto 

Reviewed-by: Daniel Lezcano 

Adding Cc: Philippe Ombredanne 

> ---
>  drivers/thermal/rcar_gen3_thermal.c | 11 +--
>  1 file changed, 1 insertion(+), 10 deletions(-)
> 
> diff --git a/drivers/thermal/rcar_gen3_thermal.c 
> b/drivers/thermal/rcar_gen3_thermal.c
> index 766521e..7aed533 100644
> --- a/drivers/thermal/rcar_gen3_thermal.c
> +++ b/drivers/thermal/rcar_gen3_thermal.c
> @@ -1,19 +1,10 @@
> +// SPDX-License-Identifier: GPL-2.0
>  /*
>   *  R-Car Gen3 THS thermal sensor driver
>   *  Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen.
>   *
>   * Copyright (C) 2016 Renesas Electronics Corporation.
>   * Copyright (C) 2016 Sang Engineering
> - *
> - *  This program is free software; you can redistribute it and/or modify
> - *  it under the terms of the GNU General Public License as published by
> - *  the Free Software Foundation; version 2 of the License.
> - *
> - *  This program is distributed in the hope that it will be useful, but
> - *  WITHOUT ANY WARRANTY; without even the implied warranty of
> - *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> - *  General Public License for more details.
> - *
>   */
>  #include 
>  #include 
> 


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Re: [PATCH] thermal: rcar_gen3_thermal: convert to SPDX identifiers

2018-07-30 Thread Geert Uytterhoeven 
On Mon, Jul 30, 2018 at 9:57 AM Kuninori Morimoto
 wrote:
> From: Kuninori Morimoto 
>
> Signed-off-by: Kuninori Morimoto 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] thermal: rcar_thermal: convert to SPDX identifiers

2018-07-30 Thread Geert Uytterhoeven 
On Mon, Jul 30, 2018 at 9:56 AM Kuninori Morimoto
 wrote:
> From: Kuninori Morimoto 
>
> As original license mentioned, it is GPL-2.0 in SPDX.
> Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
> See ${LINUX}/include/linux/module.h
>
> "GPL"   [GNU Public License v2 or later]
> "GPL v2"[GNU Public License v2]
>
> Signed-off-by: Kuninori Morimoto 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] thermal: rcar_thermal: convert to SPDX identifiers

2018-07-30 Thread Daniel Lezcano 
On 30/07/2018 09:56, Kuninori Morimoto wrote:
> 
> From: Kuninori Morimoto 
> 
> As original license mentioned, it is GPL-2.0 in SPDX.
> Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
> See ${LINUX}/include/linux/module.h
> 
>   "GPL"   [GNU Public License v2 or later]
>   "GPL v2"[GNU Public License v2]
> 
> Signed-off-by: Kuninori Morimoto 

Reviewed-by: Daniel Lezcano 

Adding Cc: Philippe Ombredanne 



> ---
>  drivers/thermal/rcar_thermal.c | 16 ++--
>  1 file changed, 2 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
> index 45fb284..14ab4a9 100644
> --- a/drivers/thermal/rcar_thermal.c
> +++ b/drivers/thermal/rcar_thermal.c
> @@ -1,21 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0
>  /*
>   *  R-Car THS/TSC thermal sensor driver
>   *
>   * Copyright (C) 2012 Renesas Solutions Corp.
>   * Kuninori Morimoto 
> - *
> - *  This program is free software; you can redistribute it and/or modify
> - *  it under the terms of the GNU General Public License as published by
> - *  the Free Software Foundation; version 2 of the License.
> - *
> - *  This program is distributed in the hope that it will be useful, but
> - *  WITHOUT ANY WARRANTY; without even the implied warranty of
> - *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> - *  General Public License for more details.
> - *
> - *  You should have received a copy of the GNU General Public License along
> - *  with this program; if not, write to the Free Software Foundation, Inc.,
> - *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
>   */
>  #include 
>  #include 
> @@ -660,6 +648,6 @@ static struct platform_driver rcar_thermal_driver = {
>  };
>  module_platform_driver(rcar_thermal_driver);
>  
> -MODULE_LICENSE("GPL");
> +MODULE_LICENSE("GPL v2");
>  MODULE_DESCRIPTION("R-Car THS/TSC thermal sensor driver");
>  MODULE_AUTHOR("Kuninori Morimoto ");
> 


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Re: [PATCH v3 1/2] soc: renesas: identify RZ/A2

2018-07-30 Thread Geert Uytterhoeven 
On Fri, Jul 27, 2018 at 6:53 PM Chris Brandt  wrote:
> Add support for identifying the RZ/A2M (R7S9210) SoC.

+ correct the original RZ/A SoC family name to RZ/A1?

> Also add support for reading the BSID register which is a different format
> than the PRR.
>
> Signed-off-by: Chris Brandt 
> ---
> v2:
> * Remove 'hard coded' section because there will not be andy non-DT
>   legacy support needed
> * Make displaying the chip revision more flexible for the future case
>   when the revision number from the BSID will be displayed

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 2/4] serial: sh-sci: Allow for compressed SCIF address

2018-07-30 Thread Geert Uytterhoeven 
Hi Chris,

On Sun, Jul 29, 2018 at 1:11 PM Geert Uytterhoeven  wrote:
> On Fri, Jul 27, 2018 at 11:09 PM Chris Brandt  
> wrote:
> > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> > Use the register area size to determine the spacing between register.
> >
> > Signed-off-by: Chris Brandt 
> > ---
> >  drivers/tty/serial/sh-sci.c | 22 +-
> >  1 file changed, 13 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> > index 6ff6f2bf3b9b..138296ec9a7d 100644
> > --- a/drivers/tty/serial/sh-sci.c
> > +++ b/drivers/tty/serial/sh-sci.c
> > @@ -348,15 +348,15 @@ static const struct sci_port_params 
> > sci_port_params[SCIx_NR_REGTYPES] = {
> > [SCIx_SH4_SCIF_REGTYPE] = {
> > .regs = {
> > [SCSMR] = { 0x00, 16 },
> > -   [SCBRR] = { 0x04,  8 },
> > -   [SCSCR] = { 0x08, 16 },
> > -   [SCxTDR]= { 0x0c,  8 },
> > -   [SCxSR] = { 0x10, 16 },
> > -   [SCxRDR]= { 0x14,  8 },
> > -   [SCFCR] = { 0x18, 16 },
> > -   [SCFDR] = { 0x1c, 16 },
> > -   [SCSPTR]= { 0x20, 16 },
> > -   [SCLSR] = { 0x24, 16 },
> > +   [SCBRR] = { 0x02,  8 },
> > +   [SCSCR] = { 0x04, 16 },
> > +   [SCxTDR]= { 0x06,  8 },
> > +   [SCxSR] = { 0x08, 16 },
> > +   [SCxRDR]= { 0x0a,  8 },
> > +   [SCFCR] = { 0x0c, 16 },
> > +   [SCFDR] = { 0x0e, 16 },
> > +   [SCSPTR]= { 0x10, 16 },
> > +   [SCLSR] = { 0x12, 16 },
> > },
> > .fifosize = 16,
> > .overrun_reg = SCLSR,
> > @@ -2939,6 +2939,10 @@ static int sci_init_single(struct platform_device 
> > *dev,
> > port->regshift = 1;
> > }
> >
> > +   if (p->regtype == SCIx_SH4_SCIF_REGTYPE)
> > +   if (sci_port->reg_size >= 0x20)
> > +   port->regshift = 1;
>
> I've accidentally discovered this breaks SCIF on SH7751R2D (QEMU), as the
> board code doesn't fill in regtype, so it is 0 = SCIx_PROBE_REGTYPE.
> The proper (default) regtype of SCIx_SH4_SCIF_REGTYPE is derived by
> sci_probe_regmap(). However, that value is never fed back to 
> sci_init_single(),
> as plat_sci_port is const. So regshift ends up being wrong.
>
> I made it work by changing the check to:
>
> -   if (p->regtype == SCIx_SH4_SCIF_REGTYPE)
> +   if (p->regtype == SCIx_SH4_SCIF_REGTYPE ||
> +   (p->regtype == SCIx_PROBE_REGTYPE && port->type == PORT_SCIF))
>
> Perhaps there's a better way?

Like (whitespace-damaged-gmail):

--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3340,7 +3340,7 @@ static int sci_init_single(struct platform_device *dev,
 {
struct uart_port *port = _port->port;
const struct resource *res;
-   unsigned int i;
+   unsigned int i, regtype;
int ret;

sci_port->cfg   = p;
@@ -3381,6 +3381,7 @@ static int sci_init_single(struct platform_device *dev,
if (unlikely(sci_port->params == NULL))
return -EINVAL;

+   regtype = sci_port->params - sci_port_params;
switch (p->type) {
case PORT_SCIFB:
sci_port->rx_trigger = 48;
@@ -3435,7 +3436,7 @@ static int sci_init_single(struct platform_device *dev,
port->regshift = 1;
}

-   if (p->regtype == SCIx_SH4_SCIF_REGTYPE)
+   if (regtype == SCIx_SH4_SCIF_REGTYPE)
if (sci_port->reg_size >= 0x20)
port->regshift = 1;

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] thermal: rcar_gen3_thermal: convert to SPDX identifiers

2018-07-30 Thread Kuninori Morimoto 


From: Kuninori Morimoto 

Signed-off-by: Kuninori Morimoto 
---
 drivers/thermal/rcar_gen3_thermal.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/thermal/rcar_gen3_thermal.c 
b/drivers/thermal/rcar_gen3_thermal.c
index 766521e..7aed533 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -1,19 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  R-Car Gen3 THS thermal sensor driver
  *  Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen.
  *
  * Copyright (C) 2016 Renesas Electronics Corporation.
  * Copyright (C) 2016 Sang Engineering
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful, but
- *  WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- *  General Public License for more details.
- *
  */
 #include 
 #include 
-- 
2.7.4

[PATCH] thermal: rcar_thermal: convert to SPDX identifiers

2018-07-30 Thread Kuninori Morimoto 


From: Kuninori Morimoto 

As original license mentioned, it is GPL-2.0 in SPDX.
Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
See ${LINUX}/include/linux/module.h

"GPL"   [GNU Public License v2 or later]
"GPL v2"[GNU Public License v2]

Signed-off-by: Kuninori Morimoto 
---
 drivers/thermal/rcar_thermal.c | 16 ++--
 1 file changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 45fb284..14ab4a9 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -1,21 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  R-Car THS/TSC thermal sensor driver
  *
  * Copyright (C) 2012 Renesas Solutions Corp.
  * Kuninori Morimoto 
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful, but
- *  WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- *  General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  */
 #include 
 #include 
@@ -660,6 +648,6 @@ static struct platform_driver rcar_thermal_driver = {
 };
 module_platform_driver(rcar_thermal_driver);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("R-Car THS/TSC thermal sensor driver");
 MODULE_AUTHOR("Kuninori Morimoto ");
-- 
2.7.4

[PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M

2018-07-30 Thread Biju Das 
Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
---
 Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
 drivers/soc/renesas/Kconfig | 6 +++---
 drivers/soc/renesas/rcar-rst.c  | 4 +++-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt 
b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index 67e83b0..e4fe0ab 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -18,6 +18,7 @@ Required properties:
  - "renesas,r8a7743-rst" (RZ/G1M)
  - "renesas,r8a7745-rst" (RZ/G1E)
  - "renesas,r8a77470-rst" (RZ/G1C)
+ - "renesas,r8a774a1-rst" (RZ/G2M)
  - "renesas,r8a7778-reset-wdt" (R-Car M1A)
  - "renesas,r8a7779-reset-wdt" (R-Car H1)
  - "renesas,r8a7790-rst" (R-Car H2)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index d769330..00d4c9d 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,9 +3,9 @@ config SOC_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
-  ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
-  ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \
-  ARCH_R8A77995
+  ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \
+  ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \
+  ARCH_R8A77990 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index d9c1034..a447873 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -41,10 +41,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
 };
 
 static const struct of_device_id rcar_rst_matches[] __initconst = {
-   /* RZ/G is handled like R-Car Gen2 */
+   /* RZ/G1 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7743-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a77470-rst", .data = _rst_gen2 },
+   /* RZ/G2 is handled like R-Car Gen3 */
+   { .compatible = "renesas,r8a774a1-rst", .data = _rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = _rst_gen1 },
{ .compatible = "renesas,r8a7779-reset-wdt", .data = _rst_gen1 },
-- 
2.7.4

[PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

2018-07-30 Thread Biju Das 
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 +++
 1 file changed, 59 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h 
b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
new file mode 100644
index 000..144c341
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+
+#include 
+
+/* r8a774a1 CPG Core Clocks */
+#define R8A774A1_CLK_Z 0
+#define R8A774A1_CLK_Z21
+#define R8A774A1_CLK_ZG2
+#define R8A774A1_CLK_ZTR   3
+#define R8A774A1_CLK_ZTRD2 4
+#define R8A774A1_CLK_ZT5
+#define R8A774A1_CLK_ZX6
+#define R8A774A1_CLK_S0D1  7
+#define R8A774A1_CLK_S0D2  8
+#define R8A774A1_CLK_S0D3  9
+#define R8A774A1_CLK_S0D4  10
+#define R8A774A1_CLK_S0D6  11
+#define R8A774A1_CLK_S0D8  12
+#define R8A774A1_CLK_S0D12 13
+#define R8A774A1_CLK_S1D2  14
+#define R8A774A1_CLK_S1D4  15
+#define R8A774A1_CLK_S2D1  16
+#define R8A774A1_CLK_S2D2  17
+#define R8A774A1_CLK_S2D4  18
+#define R8A774A1_CLK_S3D1  19
+#define R8A774A1_CLK_S3D2  20
+#define R8A774A1_CLK_S3D4  21
+#define R8A774A1_CLK_LB22
+#define R8A774A1_CLK_CL23
+#define R8A774A1_CLK_ZB3   24
+#define R8A774A1_CLK_ZB3D2 25
+#define R8A774A1_CLK_ZB3D4 26
+#define R8A774A1_CLK_CR27
+#define R8A774A1_CLK_CRD2  28
+#define R8A774A1_CLK_SD0H  29
+#define R8A774A1_CLK_SD0   30
+#define R8A774A1_CLK_SD1H  31
+#define R8A774A1_CLK_SD1   32
+#define R8A774A1_CLK_SD2H  33
+#define R8A774A1_CLK_SD2   34
+#define R8A774A1_CLK_SD3H  35
+#define R8A774A1_CLK_SD3   36
+#define R8A774A1_CLK_RPC   37
+#define R8A774A1_CLK_RPCD2 38
+#define R8A774A1_CLK_MSO   39
+#define R8A774A1_CLK_HDMI  40
+#define R8A774A1_CLK_CSI0  41
+#define R8A774A1_CLK_CP42
+#define R8A774A1_CLK_POST2 43
+#define R8A774A1_CLK_CPEX  44
+#define R8A774A1_CLK_R 45
+#define R8A774A1_CLK_OSC   46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
-- 
2.7.4

[PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support

2018-07-30 Thread Biju Das 
Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
Reset support.

Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
Hardware ((Rev. 0.61, June 12, 2018)".

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   9 +-
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a774a1-cpg-mssr.c| 322 +
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 6 files changed, 340 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt 
b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index db542ab..42d0f83 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -16,6 +16,7 @@ Required Properties:
   - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
   - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
   - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
+  - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
   - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
   - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
   - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -35,10 +36,10 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
 clock-names
   - clock-names: List of external parent clock names. Valid names are:
-  - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
-r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
-r8a77980, r8a77990, r8a77995)
-  - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
+  - "extal" (r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, r8a7791,
+r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
+r8a77970, r8a77980, r8a77990, r8a77995)
+  - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
   - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
 r8a7794)
 
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f9ba71311..fd36f18 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -8,6 +8,7 @@ config CLK_RENESAS
select CLK_R8A7743 if ARCH_R8A7743
select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A77470 if ARCH_R8A77470
+   select CLK_R8A774A1 if ARCH_R8A774A1
select CLK_R8A7778 if ARCH_R8A7778
select CLK_R8A7779 if ARCH_R8A7779
select CLK_R8A7790 if ARCH_R8A7790
@@ -66,6 +67,10 @@ config CLK_R8A77470
bool "RZ/G1C clock support" if COMPILE_TEST
select CLK_RCAR_GEN2_CPG
 
+config CLK_R8A774A1
+   bool "RZ/G2M clock support" if COMPILE_TEST
+   select CLK_RCAR_GEN3_CPG
+
 config CLK_R8A7778
bool "R-Car M1A clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index fe5bac9..0eb56bc 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_R8A7740)   += clk-r8a7740.o
 obj-$(CONFIG_CLK_R8A7743)  += r8a7743-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7745)  += r8a7745-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7778)  += clk-r8a7778.o
 obj-$(CONFIG_CLK_R8A7779)  += clk-r8a7779.o
 obj-$(CONFIG_CLK_R8A7790)  += r8a7790-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c 
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
new file mode 100644
index 000..0993513
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on r8a7796-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL0,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL4,
+   CLK_PLL1_DIV2,
+   CLK_PLL1_DIV4,
+   CLK_S0,
+   CLK_S1,
+   CLK_S2,
+   CLK_S3,
+   CLK_SDSRC,
+

[PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support

2018-07-30 Thread Biju Das 
Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
---
 .../bindings/power/renesas,rcar-sysc.txt   |  1 +
 drivers/soc/renesas/Kconfig|  5 +++
 drivers/soc/renesas/Makefile   |  1 +
 drivers/soc/renesas/r8a774a1-sysc.c| 45 ++
 drivers/soc/renesas/rcar-sysc.c|  3 ++
 drivers/soc/renesas/rcar-sysc.h|  1 +
 6 files changed, 56 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt 
b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 180ae65..4e3ec6a 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -10,6 +10,7 @@ Required properties:
   - "renesas,r8a7743-sysc" (RZ/G1M)
   - "renesas,r8a7745-sysc" (RZ/G1E)
   - "renesas,r8a77470-sysc" (RZ/G1C)
+  - "renesas,r8a774a1-sysc" (RZ/G2M)
   - "renesas,r8a7779-sysc" (R-Car H1)
   - "renesas,r8a7790-sysc" (R-Car H2)
   - "renesas,r8a7791-sysc" (R-Car M2-W)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1d824cb..d769330 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -9,6 +9,7 @@ config SOC_RENESAS
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
+   select SYSC_R8A774A1 if ARCH_R8A774A1
select SYSC_R8A7779 if ARCH_R8A7779
select SYSC_R8A7790 if ARCH_R8A7790
select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -37,6 +38,10 @@ config SYSC_R8A77470
bool "RZ/G1C System Controller support" if COMPILE_TEST
select SYSC_RCAR
 
+config SYSC_R8A774A1
+   bool "RZ/G2M System Controller support" if COMPILE_TEST
+   select SYSC_RCAR
+
 config SYSC_R8A7779
bool "R-Car H1 System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index c37b080..6adb9d6 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS)   += renesas-soc.o
 obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
 obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
 obj-$(CONFIG_SYSC_R8A77470)+= r8a77470-sysc.o
+obj-$(CONFIG_SYSC_R8A774A1)+= r8a774a1-sysc.o
 obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
 obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
 obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a774a1-sysc.c 
b/drivers/soc/renesas/r8a774a1-sysc.c
new file mode 100644
index 000..9db51ff
--- /dev/null
+++ b/drivers/soc/renesas/r8a774a1-sysc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2M System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car M3-W System Controller
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
+   { "always-on",  0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+   { "ca57-scu",   0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+   { "ca57-cpu0",   0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+   { "ca57-cpu1",   0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+   { "ca53-scu",   0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+   { "ca53-cpu0",  0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+   { "ca53-cpu1",  0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+   { "ca53-cpu2",  0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+   { "ca53-cpu3",  0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+   { "a3vc",   0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
+   { "a2vc0",  0x3c0, 0, R8A774A1_PD_A2VC0,R8A774A1_PD_A3VC },
+   { "a2vc1",  0x3c0, 1, R8A774A1_PD_A2VC1,R8A774A1_PD_A3VC },
+   { "3dg-a",  0x100, 0, R8A774A1_PD_3DG_A,R8A774A1_PD_ALWAYS_ON },
+   { "3dg-b",  0x100, 1, R8A774A1_PD_3DG_B,R8A774A1_PD_3DG_A },
+};
+
+const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
+   .areas = r8a774a1_areas,
+   .num_areas = ARRAY_SIZE(r8a774a1_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 029188e..fe32f7a 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -275,6 +275,9 @@ static const struct of_device_id rcar_sysc_matches[]

[PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions

2018-07-30 Thread Biju Das 
This patch adds power domain indices for RZ/G2M.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
---
 include/dt-bindings/power/r8a774a1-sysc.h | 31 +++
 1 file changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h

diff --git a/include/dt-bindings/power/r8a774a1-sysc.h 
b/include/dt-bindings/power/r8a774a1-sysc.h
new file mode 100644
index 000..580f431
--- /dev/null
+++ b/include/dt-bindings/power/r8a774a1-sysc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A1_PD_CA57_CPU0   0
+#define R8A774A1_PD_CA57_CPU1   1
+#define R8A774A1_PD_CA53_CPU0   5
+#define R8A774A1_PD_CA53_CPU1   6
+#define R8A774A1_PD_CA53_CPU2   7
+#define R8A774A1_PD_CA53_CPU3   8
+#define R8A774A1_PD_CA57_SCU   12
+#define R8A774A1_PD_A3VC   14
+#define R8A774A1_PD_3DG_A  17
+#define R8A774A1_PD_3DG_B  18
+#define R8A774A1_PD_CA53_SCU   21
+#define R8A774A1_PD_A2VC0  25
+#define R8A774A1_PD_A2VC1  26
+
+/* Always-on power area */
+#define R8A774A1_PD_ALWAYS_ON  32
+
+#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
-- 
2.7.4

[PATCH 0/5] Add RZ/G2M SYSC/RST/Clock support

2018-07-30 Thread Biju Das 
This patch series aims to add SYSC/RST/Clock support for 
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.

Biju Das (5):
  dt-bindings: power: Add r8a774a1 SYSC power domain definitions
  soc: renesas: rcar-sysc: Add r8a774a1 support
  soc: renesas: rcar-rst: Add support for RZ/G2M
  clk: renesas: Add r8a774a1 CPG Core Clock Definitions
  clk: renesas: cpg-mssr: Add r8a774a1 support

 .../devicetree/bindings/clock/renesas,cpg-mssr.txt |   9 +-
 .../bindings/power/renesas,rcar-sysc.txt   |   1 +
 .../devicetree/bindings/reset/renesas,rst.txt  |   1 +
 drivers/clk/renesas/Kconfig|   5 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r8a774a1-cpg-mssr.c| 322 +
 drivers/clk/renesas/renesas-cpg-mssr.c |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h |   1 +
 drivers/soc/renesas/Kconfig|  11 +-
 drivers/soc/renesas/Makefile   |   1 +
 drivers/soc/renesas/r8a774a1-sysc.c|  45 +++
 drivers/soc/renesas/rcar-rst.c |   4 +-
 drivers/soc/renesas/rcar-sysc.c|   3 +
 drivers/soc/renesas/rcar-sysc.h|   1 +
 include/dt-bindings/clock/r8a774a1-cpg-mssr.h  |  59 
 include/dt-bindings/power/r8a774a1-sysc.h  |  31 ++
 16 files changed, 493 insertions(+), 8 deletions(-)
 create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c
 create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c
 create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h

-- 
2.7.4

[PATCH v2] arm64: dts: renesas: salvator-xs: enable SATA

2018-07-30 Thread Wolfram Sang 
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.

Signed-off-by: Wolfram Sang 
Reviewed-by: Geert Uytterhoeven 
---

Changes since v1:
* fixed indentation (Thanks, Geert!)
* merged two patches into one (Thanks, Simon!)
* Added Geert's tag

 arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts  | 14 ++
 arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 14 ++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8ded64d0a4d5..368be55eda4e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -152,6 +152,15 @@
};
 };
 
+ {
+   pcie_sata_switch {
+   gpio-hog;
+   gpios = <7 GPIO_ACTIVE_HIGH>;
+   output-low; /* enable SATA by default */
+   line-name = "PCIE/SATA switch";
+   };
+};
+
  {
usb2_pins: usb2 {
groups = "usb2";
@@ -176,6 +185,11 @@
};
 };
 
+/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+ {
+   status = "okay";
+};
+
 _phy2 {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 9de4e3db1621..45016a06fab1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -47,3 +47,17 @@
 _con {
remote-endpoint = <_dw_hdmi0_out>;
 };
+
+ {
+   pcie_sata_switch {
+   gpio-hog;
+   gpios = <7 GPIO_ACTIVE_HIGH>;
+   output-low; /* enable SATA by default */
+   line-name = "PCIE/SATA switch";
+   };
+};
+
+/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+ {
+   status = "okay";
+};
-- 
2.11.0

[PATCH v2] arm64: dts: r8a77965: Add SATA controller node

2018-07-30 Thread Wolfram Sang 
From: Takeshi Kihara 

This patch adds SATA controller node for the R8A77965 SoC.

Signed-off-by: Takeshi Kihara 
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Wolfram Sang 
---

Changes since v1:
* sorted it according to address (Thanks, Geert!)
* added Geert's tag

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd44461a0bd..bf22efb82cbf 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1507,6 +1507,17 @@
status = "disabled";
};
 
+   sata: sata@ee30 {
+   compatible = "renesas,sata-r8a77965",
+"renesas,rcar-gen3-sata";
+   reg = <0 0xee30 0 0x20>;
+   interrupts = ;
+   clocks = < CPG_MOD 815>;
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 815>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0