Re: [PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
Dear Laurent-san Thank you for your reply and comments! On 2018/10/22 20:23, Laurent Pinchart wrote: Hello Hoan, Thank you for the patch. On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote: From: Hoan Nguyen An From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure known initial value" What exact commit are you referring to ? The mainline commit that has this subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296. Seems I have cited the wrong Commit-ID、it is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296 drm: rcar-du: Cache DSYSR value to ensure known initial value We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may be different. Is this fixing an actual problem ? If you look at the code, the line struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2]; makes sure that we select DU0 or DU2 only, so the register write rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, start ? DSYSR_DEN : DSYSR_DRES); should only access DSYSR0 and DSYSR2. This seems I think to fix the rcar-du problem with M3N-r8a77965, With M3N-R8a77965 we have DU0, DU1, DU3 So, when Laurent-san divide objetcs into rcar_du_group, rcar_du_crtc. DU0, DU1 -> du_group[0] rgrp-> mmio_offset = DU0_REG_OFFSET DU3->du_group[1] and rgrp-> mmio_offset = DU2_REG_OFFSET, but rcrtc->mmio_offset=DU3_REG_OFFSET (with M3N) M3N-R8a77965 not have DU2, So after the command: struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2]; So in fact, with M3N we are updating DSYSR3 (In this my TC, this reference to start/stop DU3-RGB) This will not affect H3, since the H3 lines always have enough DU0, DU1,DU2,DU3. Thank you very much ! Hoan.
Re: [PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
Dear Sergei Shtylyov-san
On 2018/10/22 17:21, Sergei Shtylyov wrote:
Hello!
On 22.10.2018 9:30, Nguyen An Hoan wrote:
From: Hoan Nguyen An
From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to
ensure known initial value"
When you cite an commit, at least 12 digits of SHA1 are needed, and
the summary needs to enclosed in (""), no just "".
We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp->
mmio_offset is enough,
the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc
leading to
mmio addresses for DSYSR may be different.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index d85f0a1..a5f7eed 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp,
bool start)
{
- struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
-
- rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
- start ? DSYSR_DEN : DSYSR_DRES);
The continuation line indentation style used above is different
from yours below.
would be preferable to keep the existing style...
Thank you for the comments, and the notes to me about code rules.
I note and improve for the next time, thank you!
Hoan.
+ rcar_du_group_write(rgrp, DSYSR,
+ (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
DSYSR_DEN)) |
+ (start ? DSYSR_DEN : DSYSR_DRES));
}
void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
MBR, Sergei
Re: [PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
Hello Hoan,
Thank you for the patch.
On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure
> known initial value"
What exact commit are you referring to ? The mainline commit that has this
subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296.
> We only need to update DSYSR0, DSYSR2 for start/stop.
> So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc ->
> rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may be
> different.
Is this fixing an actual problem ? If you look at the code, the line
struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
makes sure that we select DU0 or DU2 only, so the register write
rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
start ? DSYSR_DEN : DSYSR_DRES);
should only access DSYSR0 and DSYSR2.
> Signed-off-by: Hoan Nguyen An
> ---
> drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> b/drivers/gpu/drm/rcar-du/rcar_du_group.c index d85f0a1..a5f7eed 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> @@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
>
> static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool
> start) {
> - struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
> -
> - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
> -start ? DSYSR_DEN : DSYSR_DRES);
> + rcar_du_group_write(rgrp, DSYSR,
> + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
> DSYSR_DEN)) |
> + (start ? DSYSR_DEN : DSYSR_DRES));
> }
>
> void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
--
Regards,
Laurent Pinchart
Re: [PATCH 03/03] arm: dts: Include SoC name in DTSI for sh73a0
Hello! 2 patches with the same name? On 21.10.2018 21:21, Magnus Damm wrote: From: Magnus Damm Update the Emma Mobile EV2 DTSI to include product name. Shouldn't this be in the subject instead of sh73a0? Signed-off-by: Magnus Damm [...] MBR, Sergei
[PATCH] arm64: dts: renesas: salvator-common: add companion property in usb3_peri0
This patch adds a property "companion" with xhci0 phandle to
the usb3_peri0 node in salvator-common.dtsi.
About the detail of this property for renesas_usb3 udc driver, please
refer to the commit 39facfa01c9f ("usb: gadget: udc: renesas_usb3:
Add register of usb role switch").
Signed-off-by: Yoshihiro Shimoda
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 054a7ee..a3e8950 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -817,6 +817,8 @@
phys = <_phy0>;
phy-names = "usb";
+ companion = <>;
+
status = "okay";
};
--
1.9.1
[PATCH] arm64: dts: renesas: r8a77990: add/enable USB3.0 peripheral device node
This patch adds/enables USB3.0 peripheral device node for r8a77990
ebisu board.
Signed-off-by: Yoshihiro Shimoda
---
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 5 +
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 11 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index f85655d..0ba8e33 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -370,6 +370,11 @@
status = "okay";
};
+_peri0 {
+ companion = <>;
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 4bafc38..e2d9601 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -860,6 +860,17 @@
status = "disabled";
};
+ usb3_peri0: usb@ee02 {
+ compatible = "renesas,r8a77990-usb3-peri",
+"renesas,rcar-gen3-usb3-peri";
+ reg = <0 0xee02 0 0x400>;
+ interrupts = ;
+ clocks = < CPG_MOD 328>;
+ power-domains = < R8A77990_PD_ALWAYS_ON>;
+ resets = < 328>;
+ status = "disabled";
+ };
+
ohci0: usb@ee08 {
compatible = "generic-ohci";
reg = <0 0xee08 0 0x100>;
--
1.9.1
[PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
From: Hoan Nguyen An
>From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure known
>initial value"
We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp->
mmio_offset is enough,
the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc leading to
mmio addresses for DSYSR may be different.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index d85f0a1..a5f7eed 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
- struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
-
- rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
- start ? DSYSR_DEN : DSYSR_DRES);
+ rcar_du_group_write(rgrp, DSYSR,
+ (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
DSYSR_DEN)) |
+ (start ? DSYSR_DEN : DSYSR_DRES));
}
void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
--
2.7.4
