Re: [PATCH 2/2] ARM: dts: r8a77470: Add USB-DMAC device nodes
On Fri, Oct 26, 2018 at 09:47:09AM +, Fabrizio Castro wrote: > > Subject: [PATCH 2/2] ARM: dts: r8a77470: Add USB-DMAC device nodes > > > > This patch adds USB DMAC nodes. > > > > Signed-off-by: Biju Das > > Reviewed-by: Fabrizio Castro Thanks, applied for v4.21.
Re: [PATCH 1/2] dt-bindings: dmaengine: usb-dmac: Add binding for r8a77470
On Thu, Oct 25, 2018 at 03:53:37PM +0100, Biju Das wrote: > This patch adds usb high-speed dmac binding for r8a77470 (RZ/G1C) SoC. > > Signed-off-by: Biju Das Reviewed-by: Simon Horman
Re: [PATCH 2/2] ARM: dts: iwg23s-sbc: Enable watchdog support
On Fri, Oct 26, 2018 at 09:42:40AM +, Fabrizio Castro wrote: > > Subject: [PATCH 2/2] ARM: dts: iwg23s-sbc: Enable watchdog support > > > > This patch enables watchdog support on the iWave iwg23s sbc. > > > > Signed-off-by: Biju Das > > Reviewed-by: Fabrizio Castro Thanks, applied for v4.21.
Re: [PATCH 1/2] ARM: dts: r8a77470: Add watchdog support to SoC dtsi
On Fri, Oct 26, 2018 at 09:42:38AM +, Fabrizio Castro wrote: > > Subject: [PATCH 1/2] ARM: dts: r8a77470: Add watchdog support to SoC dtsi > > > > This patch adds watchdog support to the r8a77470 SoC dtsi. > > > > Signed-off-by: Biju Das > > Reviewed-by: Fabrizio Castro Thanks, applied for v4.21.
Re: [PATCH v3] arm64: dts: renesas: add/enable USB2.0 peripheral for R-Car [DE]3
On Wed, Oct 24, 2018 at 05:32:33PM +0900, Yoshihiro Shimoda wrote: > This patch adds/enables USB2.0 peripheral for R-Car [DE]3 boards. > > R-Car E3 Ebisu board connects the ID pin to the SoC, so this adds > a group "usb0_id" into usb0_pins node. Also, to use SW15 pin 3 side, > this patch adds vbus0_usb2 node on r8a77990-ebisu.dts. > > R-Car D3 Draak board doesn't connect the ID pin, so this adds > "renesas,no-otg-pins" property into usb2_phy0 node. > > Signed-off-by: Yoshihiro Shimoda > --- > Changed from v2: > - Use otg pin on r8a77990-ebisu board. So, I revise the commit log. > - I got Reviewed-by from Simon-san at v2. However, since I change >the integration at v3 as above. I didn't add Reviewed-by on this. > > Changed from v1: > - Revise the reg size for each hsusb node. Thanks, applied for v4.21.
Re: [PATCH 01/03] arm: dts: Include SoC name in DTSI for r8a7740
On Mon, Oct 22, 2018 at 03:21:20AM +0900, Magnus Damm wrote: > From: Magnus Damm > > Update the R-Mobile A1 DTSI to include product name. > > Signed-off-by: Magnus Damm Thanks, applied for v4.21.
Re: [PATCH 02/03] arm: dts: Include SoC name in DTSI for sh73a0
On Mon, Oct 22, 2018 at 03:21:30AM +0900, Magnus Damm wrote: > From: Magnus Damm > > Update the SH-Mobile AG5 DTSI to include product name. > > Signed-off-by: Magnus Damm Thanks, applied for v4.21.
Re: [PATCH 03/03] arm: dts: Include SoC name in DTSI for sh73a0
On Mon, Oct 22, 2018 at 11:07:08AM +0300, Sergei Shtylyov wrote: > Hello! > >2 patches with the same name? > > On 21.10.2018 21:21, Magnus Damm wrote: > > > From: Magnus Damm > > > > Update the Emma Mobile EV2 DTSI to include product name. > >Shouldn't this be in the subject instead of sh73a0? I have applied this with an updated subject: From: Magnus Damm Date: Mon, 22 Oct 2018 03:21:39 +0900 Subject: [PATCH] arm: dts: Include SoC name in DTSI for Emma Mobile EV2 Update the Emma Mobile EV2 DTSI to include product name. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 373ea8720769..67d86012a85c 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the EMEV2 SoC + * Device Tree Source for the Emma Mobile EV2 SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ -- 2.11.0
Re: [PATCH] arm64: dts: renesas: salvator-common: add companion property in usb3_peri0
On Mon, Oct 22, 2018 at 03:47:29PM +0900, Yoshihiro Shimoda wrote:
> This patch adds a property "companion" with xhci0 phandle to
> the usb3_peri0 node in salvator-common.dtsi.
>
> About the detail of this property for renesas_usb3 udc driver, please
> refer to the commit 39facfa01c9f ("usb: gadget: udc: renesas_usb3:
> Add register of usb role switch").
>
> Signed-off-by: Yoshihiro Shimoda
Thanks Shimoda-san,
applied for v4.21.
> ---
> arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> index 054a7ee..a3e8950 100644
> --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
> @@ -817,6 +817,8 @@
> phys = <_phy0>;
> phy-names = "usb";
>
> + companion = <>;
> +
> status = "okay";
> };
>
> --
> 1.9.1
>
Re: [PATCH 02/03] arm64: dts: renesas: r8a77980: Connect R-Car V3H AVB to IPMMU
On Mon, Oct 22, 2018 at 02:14:54AM +0900, Magnus Damm wrote: > From: Magnus Damm > > Hook up the R-Car V3H AVB device to IPMMU-DS1 33 as described in > the data sheet. > > Signed-off-by: Magnus Damm Thanks Magnus, applied for v4.21.
Re: [PATCH 01/03] arm64: dts: renesas: r8a77965: Connect R-Car M3-N AVB to IPMMU
On Mon, Oct 22, 2018 at 02:14:44AM +0900, Magnus Damm wrote: > From: Magnus Damm > > Hook up the R-Car M3-N AVB device to IPMMU-DS0 16 as described in > the data sheet. > > Signed-off-by: Magnus Damm Tested-by: Simon Horman I will apply this for v4.21. > --- > > arch/arm64/boot/dts/renesas/r8a77965.dtsi |1 + > 1 file changed, 1 insertion(+) > > --- 0001/arch/arm64/boot/dts/renesas/r8a77965.dtsi > +++ work/arch/arm64/boot/dts/renesas/r8a77965.dtsi2018-10-22 > 01:46:02.498689171 +0900 > @@ -900,6 +900,7 @@ > power-domains = < R8A77965_PD_ALWAYS_ON>; > resets = < 812>; > phy-mode = "rgmii"; > + iommus = <_ds0 16>; > #address-cells = <1>; > #size-cells = <0>; > status = "disabled"; >
Re: [PATCH 03/03] arm64: dts: renesas: r8a77990: Connect R-Car E3 AVB to IPMMU
On Mon, Oct 22, 2018 at 02:15:03AM +0900, Magnus Damm wrote: > From: Magnus Damm > > Hook up the R-Car E3 AVB device to IPMMU-DS0 16 as described in > the data sheet. > > Signed-off-by: Magnus Damm Tested-by: Simon Horman I will apply this for v4.21. > --- > > arch/arm64/boot/dts/renesas/r8a77990.dtsi |1 + > 1 file changed, 1 insertion(+) > > --- 0001/arch/arm64/boot/dts/renesas/r8a77990.dtsi > +++ work/arch/arm64/boot/dts/renesas/r8a77990.dtsi2018-10-22 > 01:48:50.488496607 +0900 > @@ -604,6 +604,7 @@ > power-domains = < R8A77990_PD_ALWAYS_ON>; > resets = < 812>; > phy-mode = "rgmii"; > + iommus = <_ds0 16>; > #address-cells = <1>; > #size-cells = <0>; > status = "disabled"; >
Re: [PATCH] arm64: dts: renesas: r8a77990: add/enable USB3.0 peripheral device node
On Mon, Oct 22, 2018 at 03:47:08PM +0900, Yoshihiro Shimoda wrote: > This patch adds/enables USB3.0 peripheral device node for r8a77990 > ebisu board. > > Signed-off-by: Yoshihiro Shimoda Thanks Shimoda-san, applied for v4.21.
RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
HI Shimoda-San,
Thanks for the feedback.
> Subject: RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
>
> Hi Biju-san,
>
> > From: Biju Das, Sent: Monday, October 29, 2018 6:15 PM
> > > -Original Message-
> > > From: Yoshihiro Shimoda
> > > Sent: 29 October 2018 08:42
> > >
> > > Hi Biju-san,
> > >
> > > > From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
> > > >
> > > > Define the r8a77470 generic part of the USB PHY device node.
> > > >
> > > > Signed-off-by: Biju Das
> > > > ---
> > > > This patch is tested against renesas-devel
> > >
> > > Thank you for the patch!
> > >
> > >
> > > > +usbphy1: usb-phy@e6598100 {
> > > > +compatible = "renesas,usb-phy-r8a77470",
> > > > + "renesas,rcar-gen2-usb-phy";
> > > > +reg = <0 0xe6598100 0 0x100>,
> > > > + <0 0xee0c0200 0 0x118>;
> > > > +#address-cells = <1>;
> > > > +#size-cells = <0>;
> > > > +clocks = < CPG_MOD 706>, < CPG_MOD
> > > 705>;
> > > > +clock-names = "usbhs", "usb20_host";
> > > > +status = "disabled";
> >
> > 'status = "disabled"'.
>
> Oops! I overlooked this line...
>
> > > > +resets = < 706>, < 705>;
> > > > +power-domains = <
> > > R8A77470_PD_ALWAYS_ON>;
> > > > +
> > > > +usb1: usb-channel@0 {
> > > > +reg = <0>;
> > > > +#phy-cells = <1>;
> > > > +};
> > > > +};
> > >
> > > I think this usbphy1 has to have 'status = "disabled"'.
> >
> > It is already disabled please see above.
>
> Indeed.
> However, I prefer that properties order of both usbphy0 and usbphy1 are
> the same because it improves readability.
OK. Will fix this.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
Hi Biju-san,
> From: Biju Das, Sent: Monday, October 29, 2018 6:15 PM
> > -Original Message-
> > From: Yoshihiro Shimoda
> > Sent: 29 October 2018 08:42
> >
> > Hi Biju-san,
> >
> > > From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
> > >
> > > Define the r8a77470 generic part of the USB PHY device node.
> > >
> > > Signed-off-by: Biju Das
> > > ---
> > > This patch is tested against renesas-devel
> >
> > Thank you for the patch!
> >
> >
> > > + usbphy1: usb-phy@e6598100 {
> > > + compatible = "renesas,usb-phy-r8a77470",
> > > + "renesas,rcar-gen2-usb-phy";
> > > + reg = <0 0xe6598100 0 0x100>,
> > > + <0 0xee0c0200 0 0x118>;
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + clocks = < CPG_MOD 706>, < CPG_MOD
> > 705>;
> > > + clock-names = "usbhs", "usb20_host";
> > > + status = "disabled";
>
> 'status = "disabled"'.
Oops! I overlooked this line...
> > > + resets = < 706>, < 705>;
> > > + power-domains = <
> > R8A77470_PD_ALWAYS_ON>;
> > > +
> > > + usb1: usb-channel@0 {
> > > + reg = <0>;
> > > + #phy-cells = <1>;
> > > + };
> > > + };
> >
> > I think this usbphy1 has to have 'status = "disabled"'.
>
> It is already disabled please see above.
Indeed.
However, I prefer that properties order of both usbphy0 and usbphy1
are the same because it improves readability.
Best regards,
Yoshihiro Shimoda
> Regards,
> Biju
Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Add SCIF-{0,1,3,4,5} device nodes
On Sun, Oct 21, 2018 at 06:30:00AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara
>
> This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports to
> the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Yoshihiro Kaneko
Thanks.
I don't believe this can (easily) be tested as SCIF-{0,1,3,4,5}
do not appear to be exposed on the Ebisu board.
I have checked this patch with reference to the documentation
and it looks good to me. I have applied if for v4.21.
Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
On Fri, Oct 19, 2018 at 10:10:44PM +0300, Sergei Shtylyov wrote:
> Describe MSIOF in the R8A779{7|8}0 device trees.
>
> The DMA props are omitted for R8A77980 as the RT-DMAC isn't supported
> (yet?)...
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
> Simon Horman's 'renesas.git' repo.
>
> Changes in version 2:
> - removed the aliases;
> - restored the DMA props on R8A77970, updated the description accordingly;
> - mentioned Vladimir in the description and added his signoff;
> - refreshed the patch.
Thanks, applied for v4.21.
Re: [PATCH] arm64: renesas_defconfig: Enable R-Car thermal driver
On Wed, Oct 17, 2018 at 12:07:22PM +0200, Simon Horman wrote: > Enable the R-Car thermal driver. > > This driver is used in conjunction with the R-Car V3M (r8a77970), > E3 (r8a77990) and D3 (r8a77995) SoCs. > > Signed-off-by: Simon Horman > --- > N.B: This is targeted at the devel branch of the renesas tree > but not upstream where renesas_defconfig does not currently exist Applied to the topic/renesas_defconfig branch of the renesas tree which is carried in the devel branch of the same tree but not targeted at upstream.
Re: [PATCH] arm64: defconfig: Enable R-Car thermal driver
On Wed, Oct 17, 2018 at 12:07:18PM +0200, Simon Horman wrote: > Enable the R-Car thermal driver as a module. > > This driver is used in conjunction with the R-Car V3M (r8a77970), > E3 (r8a77990) and D3 (r8a77995) SoCs. > > Signed-off-by: Simon Horman Applied for v4.21. > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index e6ec9858d33d..205d212eac58 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -365,6 +365,7 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y > CONFIG_CPU_THERMAL=y > CONFIG_THERMAL_EMULATION=y > CONFIG_ROCKCHIP_THERMAL=m > +CONFIG_RCAR_THERMAL=m > CONFIG_RCAR_GEN3_THERMAL=y > CONFIG_ARMADA_THERMAL=y > CONFIG_BRCMSTB_THERMAL=m > -- > 2.11.0 >
RE: [PATCH 2/7] phy: renesas: phy-rcar-gen2: Add support for r8a77470
Hi Shimoda-San,
Thanks for the feedback.
> Subject: RE: [PATCH 2/7] phy: renesas: phy-rcar-gen2: Add support for
> r8a77470
>
> Hi Biju-san,
>
> > From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
> >
> > This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a
> > PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1
> > and R-Car Gen2/3, USB Host needs to deassert the pll reset.
> >
> > Signed-off-by: Biju Das
> > ---
> > This patch is tested against phy-next
>
> Thank you for the patch!
>
> > ---
> > drivers/phy/renesas/phy-rcar-gen2.c | 188
> > +++-
> > 1 file changed, 184 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/renesas/phy-rcar-gen2.c
> > b/drivers/phy/renesas/phy-rcar-gen2.c
> > index 72eeb06..3d3ebc8 100644
> > --- a/drivers/phy/renesas/phy-rcar-gen2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen2.c
> > @@ -4,6 +4,7 @@
> > *
> > * Copyright (C) 2014 Renesas Solutions Corp.
> > * Copyright (C) 2014 Cogent Embedded, Inc.
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > */
> >
> > #include
> > @@ -15,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #define USBHS_LPSTS0x02
> > #define USBHS_UGCTRL0x80
> > @@ -35,10 +37,36 @@
> > #define USBHS_UGCTRL2_USB0SEL0x0030
> > #define USBHS_UGCTRL2_USB0SEL_PCI0x0010
> > #define USBHS_UGCTRL2_USB0SEL_HS_USB0x0030
> > +#define USBHS_UGCTRL2_USB0SEL_USB200x0010
> > +#define USBHS_UGCTRL2_USB0SEL_HS_USB_USB200x0020
> >
> > /* USB General status register (UGSTS) */
> > #define USBHS_UGSTS_LOCK0x0100 /* From technical
> update */
> >
> > +/* USB2.0 Host registers (original offset is +0x200) */
> > +#define USB2_INT_ENABLE0x000
> > +#define USB2_USBCTR0x00c
> > +#define USB2_SPD_RSM_TIMSET0x10c
> > +#define USB2_OC_TIMSET0x110
> > +
> > +/* RZ/G1C shared PLL RESET REG */
> > +#define USBHS_UGCTRL_PLL_RESET_REG0xE6590180
>
> I don't think this is acceptable for upstream...
> This register area may be mapped by usbphy0 on this driver's probe as base.
I was under the impression that ioremap with same cachetype won't be a problem.
OK, will change this.
> > +
> > +/* INT_ENABLE */
> > +#define USB2_INT_ENABLE_USBH_INTB_ENBIT(2)
> > +#define USB2_INT_ENABLE_USBH_INTA_ENBIT(1)
> > +#define USB2_INT_ENABLE_INIT
> (USB2_INT_ENABLE_USBH_INTB_EN | \
> > + USB2_INT_ENABLE_USBH_INTA_EN)
> > +
> > +/* USBCTR */
> > +#define USB2_USBCTR_PLL_RSTBIT(1)
> > +
> > +/* SPD_RSM_TIMSET */
> > +#define USB2_SPD_RSM_TIMSET_INIT0x014e029b
> > +
> > +/* OC_TIMSET */
> > +#define USB2_OC_TIMSET_INIT0x000209ab
> > +
> > #define PHYS_PER_CHANNEL2
> >
> > struct rcar_gen2_phy {
> > @@ -57,8 +85,8 @@ struct rcar_gen2_channel { };
> >
> > struct rcar_gen2_phy_driver {
> > -void __iomem *base;
> > -struct clk *clk;
> > +void __iomem *base, *host_base;
> > +struct clk *clk, *host_clk;
> > spinlock_t lock;
> > int num_channels;
> > struct rcar_gen2_channel *channels;
> > @@ -180,6 +208,111 @@ static int rcar_gen2_phy_power_off(struct phy
> *p)
> > return 0;
> > }
> >
> > +/* UGCTRL PLLRESET is shared between HSUSB0 and HSUSB1 */ static void
> > +__iomem *pll_reg_base;
>
> HSUSB0 (usbphy0) has this register.
> So, mapping this register on usbphy1 is not good, I think.
OK, will change this.
> > +static atomic_t pll_reset_ref_cnt;
> >
> > +static int rz_g1c_phy_init(struct phy *p) {
> > +struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> > +struct rcar_gen2_channel *channel = phy->channel;
> > +struct rcar_gen2_phy_driver *drv = channel->drv;
> > +int retval;
> > +
> > +retval = rcar_gen2_phy_init(p);
> > +if (retval)
> > +return retval;
> > +
> > +/* Initialize USB2 part */
> > +if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB_USB20)
> {
> > +clk_prepare_enable(drv->host_clk);
> > +writel(USB2_INT_ENABLE_INIT, drv->host_base +
> USB2_INT_ENABLE);
> > +writel(USB2_SPD_RSM_TIMSET_INIT,
> > +drv->host_base +
> USB2_SPD_RSM_TIMSET);
> > +writel(USB2_OC_TIMSET_INIT, drv->host_base +
> USB2_OC_TIMSET);
> > +}
> > +
> > +return 0;
> > +}
> > +
> > +static int rz_g1c_phy_exit(struct phy *p) {
> > +struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> > +struct rcar_gen2_channel *channel = phy->channel;
> > +struct rcar_gen2_phy_driver *drv = channel->drv;
> > +
> > +if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB_USB20)
> {
> > +writel(0, drv->host_base + USB2_INT_ENABLE);
> > +clk_disable_unprepare(channel->drv->host_clk);
> > +}
> > +
> > +clk_disable_unprepare(channel->drv->clk);
> > +
> > +channel->selected_phy = -1;
> > +
> > +return 0;
> > +}
> > +
> > +static int rz_g1c_phy_power_on(struct phy *p) {
> > +struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> > +struct rcar_gen2_phy_driver *drv = phy->channel->drv;
> > +void __iomem *base = drv->base;
> > +unsigned long flags;
> > +u32 value;
> > +
> > +spin_lock_irqsave(>lock, flags);
> > +
> > +/* Power on USBHS PHY */
> > +if (atomic_read(_reset_ref_cnt) == 0) {
> >
RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
Hi Shimoda-San,
Thanks for the feedback.
Regards,
Biju
> -Original Message-
> From: Yoshihiro Shimoda
> Sent: 29 October 2018 08:42
> To: Biju Das ; Rob Herring
> ; Mark Rutland
> Cc: Biju Das ; Simon Horman
> ; Magnus Damm ;
> linux-renesas-soc@vger.kernel.org; devicet...@vger.kernel.org; Geert
> Uytterhoeven ; Chris Paterson
> ; Fabrizio Castro
>
> Subject: RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
>
> Hi Biju-san,
>
> > From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
> >
> > Define the r8a77470 generic part of the USB PHY device node.
> >
> > Signed-off-by: Biju Das
> > ---
> > This patch is tested against renesas-devel
>
> Thank you for the patch!
>
>
> > +usbphy1: usb-phy@e6598100 {
> > +compatible = "renesas,usb-phy-r8a77470",
> > + "renesas,rcar-gen2-usb-phy";
> > +reg = <0 0xe6598100 0 0x100>,
> > + <0 0xee0c0200 0 0x118>;
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +clocks = < CPG_MOD 706>, < CPG_MOD
> 705>;
> > +clock-names = "usbhs", "usb20_host";
> > +status = "disabled";
'status = "disabled"'.
> > +resets = < 706>, < 705>;
> > +power-domains = <
> R8A77470_PD_ALWAYS_ON>;
> > +
> > +usb1: usb-channel@0 {
> > +reg = <0>;
> > +#phy-cells = <1>;
> > +};
> > +};
>
> I think this usbphy1 has to have 'status = "disabled"'.
It is already disabled please see above.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
Re: [PATCH 2/2] arm64: dts: renesas: salvator: Switch eMMC bus to 1V8
> > <_pins>;". So, basically the same phandles for both pinctrls. We > > can re-add the second one when we need it. > > I wonder if removing the sdhi2_pins_uhs is what we want to do, given > that we might need to adjust TDSEL or pull resistor configurations for > the HS200/HS400 modes in the future. Well, quoting myself "We can re-add the second one when we need it". It is possible but a tad unlikely. That's my take on it but it is ultimately up to Simon, of course. signature.asc Description: PGP signature
RE: [PATCH 2/7] phy: renesas: phy-rcar-gen2: Add support for r8a77470
Hi Biju-san,
> From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
>
> This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a
> PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1
> and R-Car Gen2/3, USB Host needs to deassert the pll reset.
>
> Signed-off-by: Biju Das
> ---
> This patch is tested against phy-next
Thank you for the patch!
> ---
> drivers/phy/renesas/phy-rcar-gen2.c | 188
> +++-
> 1 file changed, 184 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/renesas/phy-rcar-gen2.c
> b/drivers/phy/renesas/phy-rcar-gen2.c
> index 72eeb06..3d3ebc8 100644
> --- a/drivers/phy/renesas/phy-rcar-gen2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen2.c
> @@ -4,6 +4,7 @@
> *
> * Copyright (C) 2014 Renesas Solutions Corp.
> * Copyright (C) 2014 Cogent Embedded, Inc.
> + * Copyright (C) 2018 Renesas Electronics Corp.
> */
>
> #include
> @@ -15,6 +16,7 @@
> #include
> #include
> #include
> +#include
>
> #define USBHS_LPSTS 0x02
> #define USBHS_UGCTRL 0x80
> @@ -35,10 +37,36 @@
> #define USBHS_UGCTRL2_USB0SEL0x0030
> #define USBHS_UGCTRL2_USB0SEL_PCI0x0010
> #define USBHS_UGCTRL2_USB0SEL_HS_USB 0x0030
> +#define USBHS_UGCTRL2_USB0SEL_USB20 0x0010
> +#define USBHS_UGCTRL2_USB0SEL_HS_USB_USB20 0x0020
>
> /* USB General status register (UGSTS) */
> #define USBHS_UGSTS_LOCK 0x0100 /* From technical update */
>
> +/* USB2.0 Host registers (original offset is +0x200) */
> +#define USB2_INT_ENABLE 0x000
> +#define USB2_USBCTR 0x00c
> +#define USB2_SPD_RSM_TIMSET 0x10c
> +#define USB2_OC_TIMSET 0x110
> +
> +/* RZ/G1C shared PLL RESET REG */
> +#define USBHS_UGCTRL_PLL_RESET_REG 0xE6590180
I don't think this is acceptable for upstream...
This register area may be mapped by usbphy0 on this driver's probe as base.
> +
> +/* INT_ENABLE */
> +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
> +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
> +#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_USBH_INTB_EN | \
> + USB2_INT_ENABLE_USBH_INTA_EN)
> +
> +/* USBCTR */
> +#define USB2_USBCTR_PLL_RST BIT(1)
> +
> +/* SPD_RSM_TIMSET */
> +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
> +
> +/* OC_TIMSET */
> +#define USB2_OC_TIMSET_INIT 0x000209ab
> +
> #define PHYS_PER_CHANNEL 2
>
> struct rcar_gen2_phy {
> @@ -57,8 +85,8 @@ struct rcar_gen2_channel {
> };
>
> struct rcar_gen2_phy_driver {
> - void __iomem *base;
> - struct clk *clk;
> + void __iomem *base, *host_base;
> + struct clk *clk, *host_clk;
> spinlock_t lock;
> int num_channels;
> struct rcar_gen2_channel *channels;
> @@ -180,6 +208,111 @@ static int rcar_gen2_phy_power_off(struct phy *p)
> return 0;
> }
>
> +/* UGCTRL PLLRESET is shared between HSUSB0 and HSUSB1 */
> +static void __iomem *pll_reg_base;
HSUSB0 (usbphy0) has this register.
So, mapping this register on usbphy1 is not good, I think.
> +static atomic_t pll_reset_ref_cnt;
>
> +static int rz_g1c_phy_init(struct phy *p)
> +{
> + struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> + struct rcar_gen2_channel *channel = phy->channel;
> + struct rcar_gen2_phy_driver *drv = channel->drv;
> + int retval;
> +
> + retval = rcar_gen2_phy_init(p);
> + if (retval)
> + return retval;
> +
> + /* Initialize USB2 part */
> + if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB_USB20) {
> + clk_prepare_enable(drv->host_clk);
> + writel(USB2_INT_ENABLE_INIT, drv->host_base + USB2_INT_ENABLE);
> + writel(USB2_SPD_RSM_TIMSET_INIT,
> + drv->host_base + USB2_SPD_RSM_TIMSET);
> + writel(USB2_OC_TIMSET_INIT, drv->host_base + USB2_OC_TIMSET);
> + }
> +
> + return 0;
> +}
> +
> +static int rz_g1c_phy_exit(struct phy *p)
> +{
> + struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> + struct rcar_gen2_channel *channel = phy->channel;
> + struct rcar_gen2_phy_driver *drv = channel->drv;
> +
> + if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB_USB20) {
> + writel(0, drv->host_base + USB2_INT_ENABLE);
> + clk_disable_unprepare(channel->drv->host_clk);
> + }
> +
> + clk_disable_unprepare(channel->drv->clk);
> +
> + channel->selected_phy = -1;
> +
> + return 0;
> +}
> +
> +static int rz_g1c_phy_power_on(struct phy *p)
> +{
> + struct rcar_gen2_phy *phy = phy_get_drvdata(p);
> + struct rcar_gen2_phy_driver *drv = phy->channel->drv;
> + void __iomem *base = drv->base;
> + unsigned long flags;
> + u32 value;
> +
> + spin_lock_irqsave(>lock, flags);
> +
> + /* Power on USBHS PHY */
> + if (atomic_read(_reset_ref_cnt) == 0) {
> + value = readl(pll_reg_base);
> +
RE: [PATCH 3/7] ARM: dts: r8a77470: Add USB PHY DT support
Hi Biju-san,
> From: Biju Das, Sent: Thursday, October 25, 2018 10:57 PM
>
> Define the r8a77470 generic part of the USB PHY device node.
>
> Signed-off-by: Biju Das
> ---
> This patch is tested against renesas-devel
Thank you for the patch!
> + usbphy1: usb-phy@e6598100 {
> + compatible = "renesas,usb-phy-r8a77470",
> + "renesas,rcar-gen2-usb-phy";
> + reg = <0 0xe6598100 0 0x100>,
> + <0 0xee0c0200 0 0x118>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = < CPG_MOD 706>, < CPG_MOD 705>;
> + clock-names = "usbhs", "usb20_host";
> + status = "disabled";
> + resets = < 706>, < 705>;
> + power-domains = < R8A77470_PD_ALWAYS_ON>;
> +
> + usb1: usb-channel@0 {
> + reg = <0>;
> + #phy-cells = <1>;
> + };
> + };
I think this usbphy1 has to have 'status = "disabled"'.
Best regards,
Yoshihiro Shimoda
Re: [PATCH 2/2] arm64: dts: renesas: salvator: Switch eMMC bus to 1V8
On 10/28/2018 10:34 PM, Wolfram Sang wrote:
> Hi Marek,
Hi,
> On Sat, Oct 27, 2018 at 06:34:10PM +0200, Marek Vasut wrote:
>> The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND
>> array and the VCCQ supplies the bus. On this particular board, the VCC is
>> connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust
>> the pinmux to match the bus, which is always operating in 1.8V mode.
>>
>> Signed-off-by: Marek Vasut
>
> Thanks for this!
>
> I think Olof (and thus, Simon ;)) will be happy if those two patches are
> merged.
Fine by me.
> Other than that, I think we should remove sdhi2_pins_uhs then because it
> is the same as sdhi2_pins. And then use later "pinctrl-1 =
> <_pins>;". So, basically the same phandles for both pinctrls. We
> can re-add the second one when we need it.
I wonder if removing the sdhi2_pins_uhs is what we want to do, given
that we might need to adjust TDSEL or pull resistor configurations for
the HS200/HS400 modes in the future.
Thoughts ?
>> Cc: Geert Uytterhoeven
>> Cc: Simon Horman
>> Cc: Wolfram Sang
>> Cc: Yoshihiro Shimoda
>> Cc: linux-renesas-soc@vger.kernel.org
>> ---
>> arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
>> b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
>> index 7d3d866a0063..d9a309b28fcf 100644
>> --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
>> @@ -602,7 +602,7 @@
>> sdhi2_pins: sd2 {
>> groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
>> function = "sdhi2";
>> -power-source = <3300>;
>> +power-source = <1800>;
>> };
>>
>> sdhi2_pins_uhs: sd2_uhs {
>> --
>> 2.17.1
>>
--
Best regards,
Marek Vasut
