[PATCH v2 2/2] arm64: dts: renesas: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on
dhrystone. The average in 10 times of dhrystone result as follows:
r8a7795 SoC (A57x4 + A53x4)
CPU max-freq dhrystone
-
A57 1500 MHz 11470943 lps/s
A53 1200 MHz 4798583 lps/s
r8a7796 SoC (A57x2 + A53x4)
CPU max-freq dhrystone
-
A57 1500 MHz 11463526 lps/s
A53 1200 MHz 4793276 lps/s
Based on above, capacity-dmips-mhz values are calculated as follows:
r8a7795 SoC
A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024
A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535
r8a7796 SoC
A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024
A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535
However, since each CPUs have different max frequencies, the final
CPU capacities of A53 are scaled by this difference, the values are
as follows.
[r8a7795 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 < CPU capacity of A57
1024
1024
1024
428 < CPU capacity of A53
428
428
428
[r8a7796 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 < CPU capacity of A57
1024
428 < CPU capacity of A53
428
428
428
Signed-off-by: Gaku Inami
---
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
- Add the formula for capacity-dmips-mhz into description
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 63d5b61..94a4ab6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -157,6 +157,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -169,6 +170,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -181,6 +183,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -193,6 +196,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -205,6 +209,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_1: cpu@101 {
@@ -216,6 +221,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_2: cpu@102 {
@@ -227,6 +233,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_3: cpu@103 {
@@ -238,6 +245,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
L2_CA57: cache-controller-0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index b12bf73..369d0bc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -162,6 +162,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -174,6 +175,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
[PATCH v2 0/2] Optimization with aware of cpu capacity for R-Car Gen3
The commit 05484e098448 ("sched/topology: Add SD_ASYM_CPUCAPACITY
flag detection") to automatically detect asymmetric CPU capacity
has been merged into v4.20-rc1, so I will post this patch series
as v2 again.
These add the scheduler information to be aware cpu capacity. Some
R-Car SoCs have big LITTLE architecture(e.g. CA57/CA53). It has a
difference performance/power consumption for each CPUs.
As the scheduler will be aware the capacity of CPU, the scheduler is
balancing so that the free capacity of each CPU is even. This means
that it aggressively migrates tasks to big CPUs(e.g. CA57) with large
capacity in case of the system load is low and middle, the performance
of user application is improved than before.
Since most users for IVI are using CPU with performance oriented than
power consumption, this change will benefit for their use-cases. Some
benchmark is improved as an example below.
UnixBench (1 parallel) on r8a7796 SoC (CA57x2 + CA53x4) :
before after
- Dhrystone 2 using register variables4777159 11353624 +58%
- Double-Precision Whetstone 866 1218 +29%
- Execl Throughput728920 +21%
- File Copy 1024 bufsize 2000 maxblocks 69405 115962 +40%
- File Copy 256 bufsize 500 maxblocks 21404 28685 +25%
- File Copy 4096 bufsize 8000 maxblocks102749 159978 +36%
- Pipe Throughput 93876 150848 +38%
- Pipe-based Context Switching 27257 25317-8%
- Process Creation 1885 2292 +18%
- Shell Scripts (1 concurrent)135137+1%
- Shell Scripts (8 concurrent) 35 34-3%
- System Call Overhead 99169 140146 +29%
- System Benchmarks Index Score 112152 +26%
UnixBench (8 parallel) on r8a7795 SoC (CA57x4 + CA53x4) :
before after
- Dhrystone 2 using register variables 64686060 64472624 0%
- Double-Precision Whetstone 8380 8423+1%
- Execl Throughput 5856 6147+5%
- File Copy 1024 bufsize 2000 maxblocks142923 164482 +13%
- File Copy 256 bufsize 500 maxblocks 46257 51344 +10%
- File Copy 4096 bufsize 8000 maxblocks360398 393339+8%
- Pipe Throughput 974106 972545 0%
- Pipe-based Context Switching 162455 146567 -11%
- Process Creation 10164 9659-5%
- Shell Scripts (1 concurrent)317317 0%
- Shell Scripts (8 concurrent) 30 31+3%
- System Call Overhead 897596 899274 0%
- System Benchmarks Index Score 523534+2%
based on renesas-devel-20181105-v4.20-rc1
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
- Add the formula for capacity-dmips-mhz into description
- Remove the static setting of SD_ASYM_CPUCAPACITY for R-Car
Gaku Inami (2):
arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
arm64: dts: renesas: Add CPU capacity-dmips-mhz
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 32 +
2 files changed, 72 insertions(+)
--
2.7.4
[PATCH v2 1/2] arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
This patch adds the "cpu-map" into r8a7795/r8a7796 composed of
multi-cluster. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami
---
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++
2 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 0b54c53..63d5b61 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -116,6 +116,38 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 3baee26..b12bf73 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -127,6 +127,32 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
--
2.7.4
Re: [PATCH] serial: sh-sci: Improve type-safety calling sci_receive_chars()
Thanks for your patch!
> On November 7, 2018 at 2:37 PM Geert Uytterhoeven
> wrote:
>
>
> While ptr and port both point to the uart_port structure, the former is
> the untyped pointer cookie passed to interrupt handlers.
> Use the correctly typed port variable instead, to improve type-safety.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> drivers/tty/serial/sh-sci.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 8863689a6eebcc72..f1ee992532717a34 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -1710,7 +1710,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
>* of whether the I_IXOFF is set, otherwise, how is the interrupt
>* to be disabled?
>*/
> - sci_receive_chars(ptr);
> + sci_receive_chars(port);
>
> return IRQ_HANDLED;
> }
> @@ -1766,7 +1766,7 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
> } else {
> sci_handle_fifo_overrun(port);
> if (!s->chan_rx)
> - sci_receive_chars(ptr);
> + sci_receive_chars(port);
> }
>
> sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
> --
> 2.17.1
>
Reviewed-by: Ulrich Hecht
CU
Uli
[-----] arm64: renesas: r8a7795: remove BUSIF0 settings from rcar_sound,ssi
From: Kuninori Morimoto
Before, BUSIF which is needed for DMA transfer was automatically handled
via SSI, but it cared BUSIF0 only.
Now, rsnd driver can handle BUSIF0-7 (= for Gen3) BUSIF0-3 (= for Gen2)
via SSIU, and it is keeping compatibility.
Thus, BUSIF0 settings via SSI had been kept to avoid git merge timing
issue / git bisect issue, but it is no longer needed.
This patch removes it.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 497c416..56951fa 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -2134,53 +2134,53 @@
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = ;
- dmas = < 0x01>, < 0x02>,
< 0x15>, < 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x01>, < 0x02>;
+ dma-names = "rx", "tx";
};
ssi1: ssi-1 {
interrupts = ;
- dmas = < 0x03>, < 0x04>,
< 0x49>, < 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x03>, < 0x04>;
+ dma-names = "rx", "tx";
};
ssi2: ssi-2 {
interrupts = ;
- dmas = < 0x05>, < 0x06>,
< 0x63>, < 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x05>, < 0x06>;
+ dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = ;
- dmas = < 0x07>, < 0x08>,
< 0x6f>, < 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x07>, < 0x08>;
+ dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = ;
- dmas = < 0x09>, < 0x0a>,
< 0x71>, < 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x09>, < 0x0a>;
+ dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = ;
- dmas = < 0x0b>, < 0x0c>,
< 0x73>, < 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x0b>, < 0x0c>;
+ dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = ;
- dmas = < 0x0d>, < 0x0e>,
< 0x75>, < 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x0d>, < 0x0e>;
+ dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = ;
- dmas = < 0x0f>, < 0x10>,
< 0x79>, < 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x0f>, < 0x10>;
+ dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = ;
- dmas = < 0x11>, < 0x12>,
< 0x7b>, < 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = < 0x11>, < 0x12>;
+ dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = ;
- dmas = < 0x13>, < 0x14>,
< 0x7d>, < 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
+
[PATCH] arm64: renesas: r8a7795: add SSIU support for sound
From: Kuninori Morimoto
rsnd driver supports SSIU now, let's use it.
Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are
no longer needed.
To avoid git merge timing issue / git bisect issue,
this patch doesn't remove it so far, but will be removed in
the future.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 211 +++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 0b54c53..497c416 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1920,6 +1920,217 @@
};
};
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = < 0x15>, < 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = < 0x35>, < 0x36>;
+ dma-names = "rx", "tx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = < 0x37>, < 0x38>;
+ dma-names = "rx", "tx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = < 0x47>, < 0x48>;
+ dma-names = "rx", "tx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = < 0x3F>, < 0x40>;
+ dma-names = "rx", "tx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = < 0x43>, < 0x44>;
+ dma-names = "rx", "tx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = < 0x4F>, < 0x50>;
+ dma-names = "rx", "tx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = < 0x53>, < 0x54>;
+ dma-names = "rx", "tx";
+ };
+ ssiu10: ssiu-8 {
+ dmas = < 0x49>, < 0x4a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu11: ssiu-9 {
+ dmas = < 0x4B>, < 0x4C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu12: ssiu-10 {
+ dmas = < 0x57>, < 0x58>;
+ dma-names = "rx", "tx";
+ };
+ ssiu13: ssiu-11 {
+ dmas = < 0x59>, < 0x5A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu14: ssiu-12 {
+ dmas = < 0x5F>, < 0x60>;
+ dma-names = "rx", "tx";
+ };
+ ssiu15: ssiu-13 {
+ dmas = < 0xC3>, < 0xC4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu16: ssiu-14 {
+ dmas = < 0xC7>, < 0xC8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu17: ssiu-15 {
+ dmas = < 0xCB>, < 0xCC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu20: ssiu-16 {
+ dmas = < 0x63>, < 0x64>;
+ dma-names = "rx", "tx";
+ };
+ ssiu21: ssiu-17 {
+ dmas = < 0x67>, < 0x68>;
+ dma-names = "rx", "tx";
+ };
+ ssiu22: ssiu-18 {
+ dmas = < 0x6B>, < 0x6C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu23: ssiu-19 {
+ dmas = < 0x6D>, < 0x6E>;
+
[PATCH] arm64: renesas: r8a7795: add SSIU support for sound
Hi Simon rsnd sound driver will handle SSIU from v4.21 via DT. Of course it is keeping compatibility, thus, no SSIU settings is no problem. SSIU handles BUSIFn, but rsnd driver had been assumed only BUSIF0 was used. Thus, SSIU / BUSIF0 was attached via SSI automatically, but it was not enough for TDM Split mode. To enable TDM Split mode, we need to select BUSIFn via SSIU. This patch adds SSIU DT settings to r8a7795. If we had SSIU DT settings, existing BUSIF0 settings via SSI is no longer needed. We want to remove it. To avoid git merge timing issue / git bisect issue, I will re-post "remove" patch later (= for v4.22). Please consider 1st patch and ignore 2nd patch so far. Kuninori Morimoto (2): arm64: renesas: r8a7795: add SSIU support for sound arm64: renesas: r8a7795: remove BUSIF0 settings from rcar_sound,ssi arch/arm64/boot/dts/renesas/r8a7795.dtsi | 251 --- 1 file changed, 231 insertions(+), 20 deletions(-) -- 2.7.4
[PATCH 5/4] arm64: defconfig: select Kingfisher Sound related configs
From: Kuninori Morimoto This patch selects PCM3168A which is missing for Kingfisher Sound Signed-off-by: Kuninori Morimoto --- Hi Simon I missed this patch. Please include this, too. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9d0b42d..1d994b8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -490,6 +490,7 @@ CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5514=m CONFIG_SND_SOC_RT5514_SPI=m CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_PCM3168A_I2C=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_SIMPLE_SCU_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=m -- 2.7.4
[PATCH 1/4] arm64: renesas: ulcb: use audio-graph-card
From: Kuninori Morimoto
ULCB can use daughter board which is called as KingFisher.
It has extra sound interface, thus we want to use it.
But, basically, ALSA SoC can't use Multiple sound card with single
CPU sound interface (= SSI). Thus we need to use Single Sound Card
with multiple DAI interface.
To be easy to expand ULCB sound card on KingFisher, it is better to
use multi-dai-link style sound card on ULCB sound DT.
Now, "simple-audio-card" / "audio-graph-card" both can support
multi-dai-link style, but HDMI sound support (which is not yet supported
on ULCB) needs "audio-graph-card".
Using audio-graph-card is better selection.
This patch exchange current sound card to use it.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 42 +--
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi
b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 89daca7..a936f06 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -83,20 +83,11 @@
regulator-always-on;
};
- rsnd_ak4613: sound {
- compatible = "simple-audio-card";
+ sound_card: sound {
+ compatible = "audio-graph-card";
+ label = "rcar-sound";
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <>;
- simple-audio-card,frame-master = <>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <>;
- };
+ dais = <_port0>;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
@@ -211,6 +202,12 @@
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
+
+ port {
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <_endpoint0>;
+ };
+ };
};
cs2000: clk-multiplier@4f {
@@ -390,10 +387,21 @@
<_clk_c>,
< CPG_CORE CPG_AUDIO_CLK_I>;
- rcar_sound,dai {
- dai0 {
- playback = < >;
- capture = < >;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rsnd_port0: port@0 {
+ reg = <0>;
+ rsnd_endpoint0: endpoint {
+ remote-endpoint = <_endpoint>;
+
+ dai-format = "left_j";
+ bitclock-master = <_endpoint0>;
+ frame-master = <_endpoint0>;
+
+ playback = < >;
+ capture = < >;
+ };
};
};
};
--
2.7.4
[PATCH 4/4] arm64: renesas_defconfig: select Kingfisher Sound related configs
From: Kuninori Morimoto This patch selects PCA954x, PCM3168A which are missing for Kingfisher Sound. Signed-off-by: Kuninori Morimoto --- arch/arm64/configs/renesas_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/renesas_defconfig b/arch/arm64/configs/renesas_defconfig index bc227d1..51e8386 100644 --- a/arch/arm64/configs/renesas_defconfig +++ b/arch/arm64/configs/renesas_defconfig @@ -136,6 +136,7 @@ CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_RCAR=y @@ -242,6 +243,7 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_AK4613=y +CONFIG_SND_SOC_PCM3168A_I2C=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_SIMPLE_SCU_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y -- 2.7.4
[PATCH 3/4] arm64: renesas: ulcb-kf: add pcm3168 sound codec
From: Kuninori Morimoto
KingFisher has pcm3168 sound codec. This patch enables it.
Because pcm3168 can't handle symmetric channel on playback/
capture, we need to handle it as different DAI.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 151 +++
1 file changed, 151 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 1b316d79..fdd625d 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -6,11 +6,50 @@
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
+/*
+ * SSI-PCM3168A
+ * aplay -D plughw:0,2 xxx.wav
+ * arecord -D plughw:0,3 xxx.wav
+ */
+
/ {
aliases {
serial1 =
serial2 =
};
+
+ clk8snd: clk8snd {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ clksnd: clksnd {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22579200>;
+ };
+
+ clksndsel: clksndsel {
+ #clock-cells = <0>;
+ compatible = "gpio-mux-clock";
+ clocks = <>, <>;
+ select-gpios = <_exp_75 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ snd_3p3v: regulator-snd_3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "snd-3.3v";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ snd_vcc5v: regulator-snd_vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "snd-vcc5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
};
{
@@ -44,6 +83,7 @@
};
{
+ /* U11 */
gpio_exp_74: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
@@ -53,6 +93,13 @@
interrupt-parent = <>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ audio_out_off {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */
+ output-high;
+ line-name = "Audio_Out_OFF";
+ };
+
hub_pwen {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
@@ -80,8 +127,16 @@
output-high;
line-name = "OTG EXTLPn";
};
+
+ snd_rst {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */
+ output-high;
+ line-name = "SND_RST";
+ };
};
+ /* U5 */
gpio_exp_75: gpio@75 {
compatible = "ti,tca9539";
reg = <0x75>;
@@ -98,6 +153,49 @@
#size-cells = <0>;
reg = <0x71>;
reset-gpios = < 3 GPIO_ACTIVE_LOW>;
+
+ /* Audio_SDA, Audio_SCL */
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+
+ pcm3168a: audio-codec@44 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,pcm3168a";
+ reg = <0x44>;
+ clocks = <>;
+ clock-names = "scki";
+
+ VDD1-supply = <_3p3v>;
+ VDD2-supply = <_3p3v>;
+ VCCAD1-supply = <_vcc5v>;
+ VCCAD2-supply = <_vcc5v>;
+ VCCDA1-supply = <_vcc5v>;
+ VCCDA2-supply = <_vcc5v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ pcm3168a_endpoint_p: endpoint {
+ remote-endpoint =
<_endpoint2>;
+ clocks = <>;
+ mclk-fs = <512>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ pcm3168a_endpoint_c: endpoint {
+ remote-endpoint =
<_endpoint3>;
+
[PATCH 2/4] arm64: renesas: ulcb: add HDMI sound support
From: Kuninori Morimoto
This patch adds missing ULCB HDMI sound support.
To use sound card, HDMI video is mandatory.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi
b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index a936f06..de49b2a 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -6,6 +6,14 @@
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
+/*
+ * SSI-AK4613
+ * aplay -D plughw:0,0 xxx.wav
+ * arecord -D plughw:0,0 xxx.wav
+ * SSI-HDMI
+ * aplay -D plughw:0,1 xxx.wav
+ */
+
#include
#include
@@ -87,7 +95,9 @@
compatible = "audio-graph-card";
label = "rcar-sound";
- dais = <_port0>;
+ dais = <_port0 /* ak4613 */
+ _port1 /* HDMI0 */
+ >;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
@@ -173,6 +183,12 @@
remote-endpoint = <_con>;
};
};
+ port@2 {
+ reg = <2>;
+ dw_hdmi0_snd_in: endpoint {
+ remote-endpoint = <_endpoint1>;
+ };
+ };
};
};
@@ -403,6 +419,18 @@
capture = < >;
};
};
+ rsnd_port1: port@1 {
+ reg = <1>;
+ rsnd_endpoint1: endpoint {
+ remote-endpoint = <_hdmi0_snd_in>;
+
+ dai-format = "i2s";
+ bitclock-master = <_endpoint1>;
+ frame-master = <_endpoint1>;
+
+ playback = <>;
+ };
+ };
};
};
--
2.7.4
[PATCH 0/4] arm64: renesas: enable ULCB HDMI / ULCB-KF sound
Hi Simon
These patches adds sound support for KingFisher.
We can enable it on top of v4.20-rc1, but, it is not stable.
We need this patch (= from ASoC for-v4.21 branch) to be stable it.
223bc10b84970fd772c105b550beeef3ac3502be
("ASoC: pcm3168a: remove read-only status register from
snd_kcontrol_new")
Kuninori Morimoto (4):
arm64: renesas: ulcb: use audio-graph-card
arm64: renesas: ulcb: add HDMI sound support
arm64: renesas: ulcb-kf: add pcm3168 sound codec
arm64: renesas_defconfig: select Kingfisher Sound related configs
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 151 +++
arch/arm64/boot/dts/renesas/ulcb.dtsi| 70 ++
arch/arm64/configs/renesas_defconfig | 2 +
3 files changed, 206 insertions(+), 17 deletions(-)
--
2.7.4
Best regards
---
Kuninori Morimoto
Re: HDMI doesn't work on ULCB board
Hi Laurent Thank you for your help > > I tried to reproduce the problem, starting with drm-next which seems to work > > fine, moving to renesas-drivers-2018-10-09-v4.19-rc7 which also didn't > > exhibit any issue. I then used your kernel configuration, and got a WARN_ON > > \o/ > > Investigations revealed that you're missing the CONFIG_COMMON_CLK_VC5=y > option > in your kernel configuration. It also revealed a bug in the error handling > code of the DU driver, for which I have just sent "[PATCH] drm: rcar-du: Fix > external clock error checks". Thanks !! I tried your posted patch, and it solved Oops issue, and CONFIG_COMMON_CLK_VC5 solved HDMI outputs !! Best regards --- Kuninori Morimoto
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
On 11/07/2018 08:23 PM, Wolfram Sang wrote: > >> We discussed this on IRC already, which is why I need to look into that. >> The HS200 works well on the M3N though. > > Can you push the branch you used somewhere? I retested the branch from > Dunbar with my M3N and it works fine with my tests. Sure. btw I think this might even have something to do with ATF 1.0.24 or mainline U-Boot, which switches the eMMC card to HS200 mode. -- Best regards, Marek Vasut
Re: [PATCH v2] watchdog: renesas_wdt: don't set divider while watchdog is running
On Wed, Nov 07, 2018 at 08:46:02PM +0100, Wolfram Sang wrote:
> The datasheet says we must stop the timer before changing the clock
> divider. This can happen when the restart handler is called while the
> watchdog is running.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Guenter Roeck
> ---
>
> Change since V1: reworded commit message.
>
> I sent V1 back then when it was more a recommendation of the datasheet to do
> it
> like this. But meanwhile the code changed, so we actually need to do it.
>
> drivers/watchdog/renesas_wdt.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index 0d74c3e48979..55c9eb6c6e51 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -74,12 +74,17 @@ static int rwdt_init_timeout(struct watchdog_device *wdev)
> static int rwdt_start(struct watchdog_device *wdev)
> {
> struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
> + u8 val;
>
> pm_runtime_get_sync(wdev->parent);
>
> - rwdt_write(priv, 0, RWTCSRB);
> - rwdt_write(priv, priv->cks, RWTCSRA);
> + /* Stop the timer before we modify any register */
> + val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
> + rwdt_write(priv, val, RWTCSRA);
> +
> rwdt_init_timeout(wdev);
> + rwdt_write(priv, priv->cks, RWTCSRA);
> + rwdt_write(priv, 0, RWTCSRB);
>
> while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
> cpu_relax();
> --
> 2.11.0
>
RE: [PATCH v2] watchdog: renesas_wdt: don't set divider while watchdog is running
Hi Wolfram,
Thank you for your patch!
> Subject: [PATCH v2] watchdog: renesas_wdt: don't set divider while watchdog
> is running
>
> The datasheet says we must stop the timer before changing the clock
> divider. This can happen when the restart handler is called while the
> watchdog is running.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Fabrizio Castro
> ---
>
> Change since V1: reworded commit message.
>
> I sent V1 back then when it was more a recommendation of the datasheet to do
> it
> like this. But meanwhile the code changed, so we actually need to do it.
>
> drivers/watchdog/renesas_wdt.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index 0d74c3e48979..55c9eb6c6e51 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -74,12 +74,17 @@ static int rwdt_init_timeout(struct watchdog_device *wdev)
> static int rwdt_start(struct watchdog_device *wdev)
> {
> struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
> +u8 val;
>
> pm_runtime_get_sync(wdev->parent);
>
> -rwdt_write(priv, 0, RWTCSRB);
> -rwdt_write(priv, priv->cks, RWTCSRA);
> +/* Stop the timer before we modify any register */
> +val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
> +rwdt_write(priv, val, RWTCSRA);
> +
> rwdt_init_timeout(wdev);
> +rwdt_write(priv, priv->cks, RWTCSRA);
> +rwdt_write(priv, 0, RWTCSRB);
>
> while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
> cpu_relax();
> --
> 2.11.0
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
[PATCH v2] watchdog: renesas_wdt: don't set divider while watchdog is running
The datasheet says we must stop the timer before changing the clock
divider. This can happen when the restart handler is called while the
watchdog is running.
Signed-off-by: Wolfram Sang
---
Change since V1: reworded commit message.
I sent V1 back then when it was more a recommendation of the datasheet to do it
like this. But meanwhile the code changed, so we actually need to do it.
drivers/watchdog/renesas_wdt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 0d74c3e48979..55c9eb6c6e51 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -74,12 +74,17 @@ static int rwdt_init_timeout(struct watchdog_device *wdev)
static int rwdt_start(struct watchdog_device *wdev)
{
struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
+ u8 val;
pm_runtime_get_sync(wdev->parent);
- rwdt_write(priv, 0, RWTCSRB);
- rwdt_write(priv, priv->cks, RWTCSRA);
+ /* Stop the timer before we modify any register */
+ val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
+ rwdt_write(priv, val, RWTCSRA);
+
rwdt_init_timeout(wdev);
+ rwdt_write(priv, priv->cks, RWTCSRA);
+ rwdt_write(priv, 0, RWTCSRB);
while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
cpu_relax();
--
2.11.0
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
> We discussed this on IRC already, which is why I need to look into that. > The HS200 works well on the M3N though. Can you push the branch you used somewhere? I retested the branch from Dunbar with my M3N and it works fine with my tests. signature.asc Description: PGP signature
[PATCH v4 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v3:
- Changed names from Px to PORTx because "PC" is already defined
v2:
- fixed SOC part number in comments
- sorted #includes
- removed spaces in pfc_pin_port_name enum
- put RZA2_NPORTS at the end of pfc_pin_port_name enum
- added RZA2_ to the beginning of all #define macros
- put ( ) around all passed arguments in #define macros
- made helper macros to get register address easier
- use defines for pin direction bit settings
---
drivers/pinctrl/Kconfig| 11 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza2.c | 530 +
3 files changed, 542 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-rza2.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4d8c00eac742..3e4d890d4bd9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
+config PINCTRL_RZA2
+ bool "Renesas RZ/A2 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S9210 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects pinctrl driver for Renesas RZ/A2 platforms.
+
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 18a13c1e2c21..712184b74a5c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
new file mode 100644
index ..3781c3f693e8
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
+ *
+ * Copyright (C) 2018 Chris Brandt
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
+ * family.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME"pinctrl-rza2"
+
+#define RZA2_PINS_PER_PORT 8
+#define RZA2_NPINS (RZA2_PINS_PER_PORT * RZA2_NPORTS)
+#define RZA2_PIN_ID_TO_PORT(id)((id) / RZA2_PINS_PER_PORT)
+#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASKGENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+
+enum pfc_pin_port_name {PORT0, PORT1, PORT2, PORT3, PORT4, PORT5, PORT6, PORT7,
+ PORT8, PORT9, PORTA, PORTB, PORTC, PORTD, PORTE, PORTF,
+ PORTG, PORTH, PORTJ, PORTK, PORTL, PORTM, RZA2_NPORTS};
+static const char port_names[] = "0123456789ABCDEFGHJKLM";
+
+struct rza2_pinctrl_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+};
+
+#define RZA2_PDR_BASE(_b) ((_b) + 0x) /* 16-bit, 2 bytes apart */
+#define RZA2_PODR_BASE(_b) ((_b) + 0x0040) /* 8-bit, 1 byte apart */
+#define RZA2_PIDR_BASE(_b) ((_b) + 0x0060) /* 8-bit, 1 byte apart */
+#define RZA2_PMR_BASE(_b) ((_b) + 0x0080) /* 8-bit, 1 byte apart */
+#define RZA2_DSCR_BASE(_b) ((_b) + 0x0140) /* 16-bit, 2 bytes apart */
+#define RZA2_PFS_BASE(_b) ((_b) + 0x0200) /* 8-bit, 8 bytes apart */
+#define RZA2_PWPR(_b) ((_b) + 0x02FF) /* 8-bit */
+#define RZA2_PFENET(_b)((_b) + 0x0820) /* 8-bit */
+#define RZA2_PPOC(_b) ((_b) + 0x0900) /* 32-bit */
+#define RZA2_PHMOMO(_b)((_b) + 0x0980) /* 32-bit */
+#define RZA2_PCKIO(_b) ((_b) + 0x09D0) /* 8-bit */
+
+#define RZA2_PDR(_b, _port)(RZA2_PDR_BASE(_b) + ((_port) * 2))
+#define RZA2_PODR(_b, _port) (RZA2_PODR_BASE(_b) + (_port))
+#define RZA2_PIDR(_b, _port) (RZA2_PIDR_BASE(_b) + (_port))
+#define RZA2_PMR(_b, _port)(RZA2_PMR_BASE(_b) + (_port))
+#define RZA2_DSCR(_b, _port) (RZA2_DSCR_BASE(_b) + ((_port) * 2))
+#define RZA2_PFS(_b, _port, _pin) (RZA2_PFS_BASE(_b) +
[PATCH v4 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
---
v3:
- Added Reviewed-by
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID to RZA2_PIN
---
.../bindings/pinctrl/renesas,rza2-pinctrl.txt | 88 ++
include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47
2 files changed, 135 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
new file mode 100644
index ..622d37a7225b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
@@ -0,0 +1,88 @@
+Renesas RZ/A2 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
controller.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+Each port features up to 8 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+---
+
+Required properties:
+ - compatible: should be:
+- "renesas,r7s9210-pinctrl": for RZ/A2M
+ - reg
+Address base and length of the memory area where the pin controller
+hardware is mapped to.
+ - gpio-controller
+This pin controller also controls pins as GPIO
+ - #gpio-cells
+Must be 2
+ - gpio-ranges
+Expresses the total number GPIO ports/pins in this SoC
+
+
+Example: Pin controller node for RZ/A2M SoC (r7s9210)
+
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x9D1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 176>;
+ };
+
+Sub-nodes
+-
+
+The child nodes of the pin controller designate pins to be used for
+specific peripheral functions or as GPIO.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name, pin
+ number and the desired function index. Use the RZA2_PINMUX macro located
+ in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
+ For assigning GPIO pins, use the macro RZA2_PIN_ID also in r7s9210-pinctrl.h
+ to express the desired port pin.
+
+ Required properties:
+- pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 8 + PIN) | MUX_FUNC << 16)
+
+ Example: Board specific pins configuration
+
+{
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = , /* TxD4 */
+; /* RxD4 */
+ };
+ };
+
+ Example: Assigning a GPIO:
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led0 {
+ /* P6_0 */
+ gpios = < RZA2_PIN(P6, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
new file mode 100644
index ..1e2671b61c0a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A2 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
+
+#define RZA2_PINS_PER_PORT 8
+
+/* Port names as labeled in the Hardware Manual */
+#define P0 0
+#define P1 1
+#define P2 2
+#define P3 3
+#define P4 4
+#define P5 5
+#define P6 6
+#define P7 7
+#define P8 8
+#define P9 9
+#define PA 10
+#define PB 11
+#define PC 12
+#define PD 13
+#define
[PATCH v4 0/2] pinctrl: Add RZ/A2 pin and gpio driver
The pin controller in the RZ/A2 is nothing like the pin controller in the RZ/A1. That's a good thing! This pin controller is much more simple and easier to configure. So, this driver is faily simple (I hope). V3 -> V4: Sorry...I forgot Rob's Reviewed-by !! Chris Brandt (2): pinctrl: Add RZ/A2 pin and gpio controller dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 88 drivers/pinctrl/Kconfig| 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rza2.c | 530 + include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 ++ 5 files changed, 677 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-rza2.c create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h -- 2.16.1
[PATCH v3 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID to RZA2_PIN
---
.../bindings/pinctrl/renesas,rza2-pinctrl.txt | 88 ++
include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47
2 files changed, 135 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
new file mode 100644
index ..622d37a7225b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
@@ -0,0 +1,88 @@
+Renesas RZ/A2 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
controller.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+Each port features up to 8 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+---
+
+Required properties:
+ - compatible: should be:
+- "renesas,r7s9210-pinctrl": for RZ/A2M
+ - reg
+Address base and length of the memory area where the pin controller
+hardware is mapped to.
+ - gpio-controller
+This pin controller also controls pins as GPIO
+ - #gpio-cells
+Must be 2
+ - gpio-ranges
+Expresses the total number GPIO ports/pins in this SoC
+
+
+Example: Pin controller node for RZ/A2M SoC (r7s9210)
+
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x9D1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 176>;
+ };
+
+Sub-nodes
+-
+
+The child nodes of the pin controller designate pins to be used for
+specific peripheral functions or as GPIO.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name, pin
+ number and the desired function index. Use the RZA2_PINMUX macro located
+ in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
+ For assigning GPIO pins, use the macro RZA2_PIN_ID also in r7s9210-pinctrl.h
+ to express the desired port pin.
+
+ Required properties:
+- pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 8 + PIN) | MUX_FUNC << 16)
+
+ Example: Board specific pins configuration
+
+{
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = , /* TxD4 */
+; /* RxD4 */
+ };
+ };
+
+ Example: Assigning a GPIO:
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led0 {
+ /* P6_0 */
+ gpios = < RZA2_PIN(P6, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
new file mode 100644
index ..1e2671b61c0a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A2 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
+
+#define RZA2_PINS_PER_PORT 8
+
+/* Port names as labeled in the Hardware Manual */
+#define P0 0
+#define P1 1
+#define P2 2
+#define P3 3
+#define P4 4
+#define P5 5
+#define P6 6
+#define P7 7
+#define P8 8
+#define P9 9
+#define PA 10
+#define PB 11
+#define PC 12
+#define PD 13
+#define PE 14
+#define PF 15
+#define PG 16
+#define PH 17
[PATCH v3 0/2] pinctrl: Add RZ/A2 pin and gpio driver
The pin controller in the RZ/A2 is nothing like the pin controller in the RZ/A1. That's a good thing! This pin controller is much more simple and easier to configure. So, this driver is faily simple (I hope). Chris Brandt (2): pinctrl: Add RZ/A2 pin and gpio controller dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 88 drivers/pinctrl/Kconfig| 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rza2.c | 530 + include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 ++ 5 files changed, 677 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-rza2.c create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h -- 2.16.1
[PATCH v3 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v3:
- Changed names from Px to PORTx because "PC" is already defined
v2:
- fixed SOC part number in comments
- sorted #includes
- removed spaces in pfc_pin_port_name enum
- put RZA2_NPORTS at the end of pfc_pin_port_name enum
- added RZA2_ to the beginning of all #define macros
- put ( ) around all passed arguments in #define macros
- made helper macros to get register address easier
- use defines for pin direction bit settings
---
drivers/pinctrl/Kconfig| 11 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza2.c | 530 +
3 files changed, 542 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-rza2.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4d8c00eac742..3e4d890d4bd9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
+config PINCTRL_RZA2
+ bool "Renesas RZ/A2 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S9210 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects pinctrl driver for Renesas RZ/A2 platforms.
+
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 18a13c1e2c21..712184b74a5c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
new file mode 100644
index ..3781c3f693e8
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
+ *
+ * Copyright (C) 2018 Chris Brandt
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
+ * family.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME"pinctrl-rza2"
+
+#define RZA2_PINS_PER_PORT 8
+#define RZA2_NPINS (RZA2_PINS_PER_PORT * RZA2_NPORTS)
+#define RZA2_PIN_ID_TO_PORT(id)((id) / RZA2_PINS_PER_PORT)
+#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASKGENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+
+enum pfc_pin_port_name {PORT0, PORT1, PORT2, PORT3, PORT4, PORT5, PORT6, PORT7,
+ PORT8, PORT9, PORTA, PORTB, PORTC, PORTD, PORTE, PORTF,
+ PORTG, PORTH, PORTJ, PORTK, PORTL, PORTM, RZA2_NPORTS};
+static const char port_names[] = "0123456789ABCDEFGHJKLM";
+
+struct rza2_pinctrl_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+};
+
+#define RZA2_PDR_BASE(_b) ((_b) + 0x) /* 16-bit, 2 bytes apart */
+#define RZA2_PODR_BASE(_b) ((_b) + 0x0040) /* 8-bit, 1 byte apart */
+#define RZA2_PIDR_BASE(_b) ((_b) + 0x0060) /* 8-bit, 1 byte apart */
+#define RZA2_PMR_BASE(_b) ((_b) + 0x0080) /* 8-bit, 1 byte apart */
+#define RZA2_DSCR_BASE(_b) ((_b) + 0x0140) /* 16-bit, 2 bytes apart */
+#define RZA2_PFS_BASE(_b) ((_b) + 0x0200) /* 8-bit, 8 bytes apart */
+#define RZA2_PWPR(_b) ((_b) + 0x02FF) /* 8-bit */
+#define RZA2_PFENET(_b)((_b) + 0x0820) /* 8-bit */
+#define RZA2_PPOC(_b) ((_b) + 0x0900) /* 32-bit */
+#define RZA2_PHMOMO(_b)((_b) + 0x0980) /* 32-bit */
+#define RZA2_PCKIO(_b) ((_b) + 0x09D0) /* 8-bit */
+
+#define RZA2_PDR(_b, _port)(RZA2_PDR_BASE(_b) + ((_port) * 2))
+#define RZA2_PODR(_b, _port) (RZA2_PODR_BASE(_b) + (_port))
+#define RZA2_PIDR(_b, _port) (RZA2_PIDR_BASE(_b) + (_port))
+#define RZA2_PMR(_b, _port)(RZA2_PMR_BASE(_b) + (_port))
+#define RZA2_DSCR(_b, _port) (RZA2_DSCR_BASE(_b) + ((_port) * 2))
+#define RZA2_PFS(_b, _port, _pin) (RZA2_PFS_BASE(_b) +
[PATCH 1/3] clk: renesas: r7s9210: Add USB clocks
Add USB clocks for RZ/A2
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 3922967ba811..efbbf56e6766 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -87,6 +87,8 @@ static const struct mssr_mod_clk r7s9210_mod_clks[]
__initconst = {
DEF_MOD_STB("scif1", 46,R7S9210_CLK_P1C),
DEF_MOD_STB("scif0", 47,R7S9210_CLK_P1C),
+ DEF_MOD_STB("usb1", 60,R7S9210_CLK_B),
+ DEF_MOD_STB("usb0", 61,R7S9210_CLK_B),
DEF_MOD_STB("ether1",64,R7S9210_CLK_B),
DEF_MOD_STB("ether0",65,R7S9210_CLK_B),
--
2.16.1
[PATCH 3/3] dt-bindings: rcar-gen3-phy-usb2: Add r7s9210 support
Document RZ/A2 (R7S9210) SoC bindings. Signed-off-by: Chris Brandt --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index de7b5393c163..b545daf8ccb3 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -1,10 +1,12 @@ * Renesas R-Car generation 3 USB 2.0 PHY This file provides information on what the device node for the R-Car generation -3 and RZ/G2 USB 2.0 PHY contain. +3, RZ/G2 and RZ/A2 USB 2.0 PHY contain. Required properties: -- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1 +- compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an R7S9210 + SoC. + "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1 SoC. "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 SoC. @@ -16,8 +18,8 @@ Required properties: R8A77990 SoC. "renesas,usb2-phy-r8a77995" if the device is a part of an R8A77995 SoC. - "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 or RZ/G2 - compatible device. + "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3, RZ/G2 or + RZ/A2 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first -- 2.16.1
[PATCH 2/3] phy: renesas: rcar-gen3-usb2: Add support for R7S9210
The RZ/A2 has the same USB2 host controller as R-Car Gen3 with only some
minor differences.
Signed-off-by: Chris Brandt
---
drivers/phy/renesas/Kconfig | 2 +-
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 12
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index e340a925bbb1..beebeba31e84 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -19,7 +19,7 @@ config PHY_RCAR_GEN3_PCIE
config PHY_RCAR_GEN3_USB2
tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
depends on ARCH_RENESAS
- depends on EXTCON
+ depends on EXTCON || ARCH_R7S9210
depends on USB_SUPPORT
select GENERIC_PHY
select USB_COMMON
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index d0f412c25981..96ac75ba40ea 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -34,6 +34,7 @@
#define USB2_VBCTRL0x60c
#define USB2_LINECTRL1 0x610
#define USB2_ADPCTRL 0x630
+#define USB2_PHYCLK_CTRL 0x644
/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
@@ -88,6 +89,7 @@ struct rcar_gen3_chan {
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool uses_usb_x1;
};
/*
@@ -326,6 +328,9 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
struct rcar_gen3_chan *channel = phy_get_drvdata(p);
void __iomem *usb2_base = channel->base;
+ if (channel->uses_usb_x1)
+ writel(0x0001, usb2_base + USB2_PHYCLK_CTRL);
+
/* Initialize USB2 part */
writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
@@ -334,6 +339,9 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
/* Initialize otg part */
if (channel->is_otg_channel)
rcar_gen3_init_otg(channel);
+ else
+ /* No otg, so default to host mode */
+ writel(0x, usb2_base + USB2_COMMCTRL);
return 0;
}
@@ -406,6 +414,7 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void
*_ch)
}
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
+ { .compatible = "renesas,usb2-phy-r7s9210" },
{ .compatible = "renesas,usb2-phy-r8a7795" },
{ .compatible = "renesas,usb2-phy-r8a7796" },
{ .compatible = "renesas,usb2-phy-r8a77965" },
@@ -471,6 +480,9 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
*pdev)
}
}
+ if (of_property_read_bool(dev->of_node, "renesas,uses_usb_x1"))
+ channel->uses_usb_x1 = true;
+
/*
* devm_phy_create() will call pm_runtime_enable(>dev);
* And then, phy-core will manage runtime pm for this device.
--
2.16.1
[PATCH 0/3] usb: renesas: rcar-gen3-usb2: Add support for RZ/A2
Add support for RZ/A2. Basically has the same IP as R-Car Gen3. Chris Brandt (3): clk: renesas: r7s9210: Add USB clocks phy: renesas: rcar-gen3-usb2: Add support for R7S9210 dt-bindings: rcar-gen3-phy-usb2: Add r7s9210 support Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++ drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 ++ drivers/phy/renesas/Kconfig | 2 +- drivers/phy/renesas/phy-rcar-gen3-usb2.c | 12 4 files changed, 21 insertions(+), 5 deletions(-) -- 2.16.1
Re: [PATCH v2] arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering
Hi Simon,
On Tuesday, 6 November 2018 16:00:35 EET Simon Horman wrote:
> On Mon, Nov 05, 2018 at 02:12:43PM +0100, Jacopo Mondi wrote:
> > The VIN driver bindings dictates fixed numbering for VIN endpoints
> > connected to CSI-2 endpoints, even when a single endpoint exists.
> >
> > Without proper endpoint numbering the VIN driver fails to probe.
> >
> > Based on a patch in BSP from Koji Matsuoka
> >
> > Fixes: ec70407ae7d7 ("arm64: dts: renesas: r8a77990: Add VIN and CSI-2
> > device nodes") Signed-off-by: Koji Matsuoka
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-by: Jacopo Mondi
> > Reviewed-by: Laurent Pinchart
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
>
> Reviewed-by: Simon Horman
I think you can go ahead and apply it.
--
Regards,
Laurent Pinchart
Re: [GIT PULL] Renesas ARM Based SoC Fixes for v4.20
On Wed, Nov 7, 2018 at 3:25 AM Simon Horman wrote: > > Hi Olof, Hi Kevin, Hi Arnd, > > Please consider these Renesas ARM based SoC fixes for v4.20. > > > The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a: > > Linux 4.20-rc1 (2018-11-04 15:37:52 -0800) > > are available in the git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git > tags/renesas-fixes-for-v4.20 > > for you to fetch changes up to eab53fdfd60a84b0cc514d4f1f5d79226c76df01: > > arm64: dts: renesas: condor: switch from EtherAVB to GEther (2018-11-05 > 15:08:44 +0100) > > > Renesas ARM Based SoC Fixes for v4.20 > > * R-Car V3H (r8a77980) based Condor board > - Switch from EtherAVB to GEther to match offical boards > > * RZ/G2E (ra8774c0) SoC: correct documentation of part number I have to admit, Renesas part numbers have got to be _really_ hard to deal with for anyone who has even the slightest hint of dyslexia. :-) > * R-Car H3 (r8a7795) SoC: reinstate all DMA channels on HSCIF2 Thanks Simon! I've merged this branch now. -Olof
Applied "spi: rspi: Add r8a77470 to the compatible list" to the spi tree
The patch spi: rspi: Add r8a77470 to the compatible list has been applied to the spi tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From df80e0478972260bf285c5ed33f99b2424fba2af Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 1 Nov 2018 12:35:02 + Subject: [PATCH] spi: rspi: Add r8a77470 to the compatible list Add r8a77470 to the list of examples with soctypes. No driver change is needed as "renesas,qspi" will activate the right code within the corresponding driver. Signed-off-by: Fabrizio Castro Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt index fc97ad64fbf2..421722b93992 100644 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt @@ -15,6 +15,7 @@ Required properties: - "renesas,qspi-r8a7743" (RZ/G1M) - "renesas,qspi-r8a7744" (RZ/G1N) - "renesas,qspi-r8a7745" (RZ/G1E) + - "renesas,qspi-r8a77470" (RZ/G1C) - "renesas,qspi-r8a7790" (R-Car H2) - "renesas,qspi-r8a7791" (R-Car M2-W) - "renesas,qspi-r8a7792" (R-Car V2H) -- 2.19.0.rc2
[PATCH 2/2] arm64: dts: renesas: r8a774a1: Replace clock magic numbers
Now that include/dt-bindings/clock/r8a774a1-cpg-mssr.h is in Linus'
master branch we can replace clock related magic numbers with the
corresponding labels.
Signed-off-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index d549755..e0f8bd9 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -7,7 +7,7 @@
#include
#include
-#include
+#include
#include
/ {
@@ -67,7 +67,7 @@
power-domains = < R8A774A1_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
- clocks = < CPG_CORE 0>;
+ clocks = < CPG_CORE R8A774A1_CLK_Z>;
};
a57_1: cpu@1 {
@@ -77,7 +77,7 @@
power-domains = < R8A774A1_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
- clocks = < CPG_CORE 0>;
+ clocks = < CPG_CORE R8A774A1_CLK_Z>;
};
a53_0: cpu@100 {
@@ -87,7 +87,7 @@
power-domains = < R8A774A1_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
- clocks =< CPG_CORE 1>;
+ clocks =< CPG_CORE R8A774A1_CLK_Z2>;
};
a53_1: cpu@101 {
@@ -97,7 +97,7 @@
power-domains = < R8A774A1_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
- clocks =< CPG_CORE 1>;
+ clocks =< CPG_CORE R8A774A1_CLK_Z2>;
};
a53_2: cpu@102 {
@@ -107,7 +107,7 @@
power-domains = < R8A774A1_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
- clocks =< CPG_CORE 1>;
+ clocks =< CPG_CORE R8A774A1_CLK_Z2>;
};
a53_3: cpu@103 {
@@ -117,7 +117,7 @@
power-domains = < R8A774A1_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
- clocks =< CPG_CORE 1>;
+ clocks =< CPG_CORE R8A774A1_CLK_Z2>;
};
L2_CA57: cache-controller-0 {
@@ -515,7 +515,7 @@
reg = <0 0xe654 0 0x60>;
interrupts = ;
clocks = < CPG_MOD 520>,
-< CPG_CORE 19>,
+< CPG_CORE R8A774A1_CLK_S3D1>,
<_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x31>, < 0x30>,
@@ -533,7 +533,7 @@
reg = <0 0xe655 0 0x60>;
interrupts = ;
clocks = < CPG_MOD 519>,
-< CPG_CORE 19>,
+< CPG_CORE R8A774A1_CLK_S3D1>,
<_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x33>, < 0x32>,
@@ -551,7 +551,7 @@
reg = <0 0xe656 0 0x60>;
interrupts = ;
clocks = < CPG_MOD 518>,
-< CPG_CORE 19>,
+< CPG_CORE R8A774A1_CLK_S3D1>,
<_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x35>, < 0x34>,
@@ -569,7 +569,7 @@
reg = <0 0xe66a 0 0x60>;
interrupts = ;
clocks = < CPG_MOD 517>,
-< CPG_CORE 19>,
+< CPG_CORE R8A774A1_CLK_S3D1>,
<_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x37>, < 0x36>;
@@ -586,7 +586,7 @@
reg = <0 0xe66b 0 0x60>;
interrupts = ;
clocks = < CPG_MOD 516>,
-< CPG_CORE 19>,
+< CPG_CORE R8A774A1_CLK_S3D1>,
<_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x39>, < 0x38>;
@@ -974,7 +974,7 @@
reg = <0 0xe6e6 0 0x40>;
interrupts = ;
[PATCH 1/2] arm64: dts: renesas: r8a774a1: Replace power magic numbers
Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus'
master branch we can replace power related magic numbers with
the corresponding labels.
Signed-off-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 201 +++---
1 file changed, 101 insertions(+), 100 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 78ac8e3..d549755 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
/ {
compatible = "renesas,r8a774a1";
@@ -63,7 +64,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
- power-domains = < 0>;
+ power-domains = < R8A774A1_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
clocks = < CPG_CORE 0>;
@@ -73,7 +74,7 @@
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
device_type = "cpu";
- power-domains = < 1>;
+ power-domains = < R8A774A1_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
clocks = < CPG_CORE 0>;
@@ -83,7 +84,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x100>;
device_type = "cpu";
- power-domains = < 5>;
+ power-domains = < R8A774A1_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
clocks =< CPG_CORE 1>;
@@ -93,7 +94,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>;
device_type = "cpu";
- power-domains = < 6>;
+ power-domains = < R8A774A1_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
clocks =< CPG_CORE 1>;
@@ -103,7 +104,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>;
device_type = "cpu";
- power-domains = < 7>;
+ power-domains = < R8A774A1_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
clocks =< CPG_CORE 1>;
@@ -113,7 +114,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>;
device_type = "cpu";
- power-domains = < 8>;
+ power-domains = < R8A774A1_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
clocks =< CPG_CORE 1>;
@@ -121,14 +122,14 @@
L2_CA57: cache-controller-0 {
compatible = "cache";
- power-domains = < 12>;
+ power-domains = < R8A774A1_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
L2_CA53: cache-controller-1 {
compatible = "cache";
- power-domains = < 21>;
+ power-domains = < R8A774A1_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -195,7 +196,7 @@
"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
clocks = < CPG_MOD 402>;
- power-domains = < 32>;
+ power-domains = < R8A774A1_PD_ALWAYS_ON>;
resets = < 402>;
status = "disabled";
};
@@ -211,7 +212,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 912>;
- power-domains = < 32>;
+ power-domains = < R8A774A1_PD_ALWAYS_ON>;
resets = < 912>;
};
@@ -226,7 +227,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 911>;
- power-domains = < 32>;
+ power-domains = < R8A774A1_PD_ALWAYS_ON>;
resets = < 911>;
};
@@ -241,7 +242,7 @@
[PATCH 0/2] Replace magic numbers in RZ/G2M dtsi
Dear All, We were waiting for v4.20 RC1 to be out for replacing clock and power magic numbers within r8a774a1.dtsi as there was a dependency with the corresponding bindings. This series takes care of the magic numbers now that the bindings are available by replacing them with the corresponding macros. Thanks, Fab Fabrizio Castro (2): arm64: dts: renesas: r8a774a1: Replace power magic numbers arm64: dts: renesas: r8a774a1: Replace clock magic numbers arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 239 +++--- 1 file changed, 120 insertions(+), 119 deletions(-) -- 2.7.4
RE: [PATCH] dt-bindings: thermal: rcar-gen3-thermal: All variants use 3 interrupts
> Subject: [PATCH] dt-bindings: thermal: rcar-gen3-thermal: All variants use 3
> interrupts
>
> RZ/G2M also has 3 interrupts routed to the TSC, but the list was not
> updated to reflect this.
>
> Just drop the list, as this is the case for this TSC variant in all
> R-Car Gen3 and RZ/G2 SoCs.
>
> Fixes: be6af481f3b2d508 ("dt-bindings: thermal: rcar-gen3-thermal: Add
> r8a774a1 support")
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Fabrizio Castro
> ---
> .../devicetree/bindings/thermal/rcar-gen3-thermal.txt | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
> b/Documentation/devicetree/bindings/thermal/rcar-
> gen3-thermal.txt
> index ad9a435afef446f6..b6ab60f6abbf95fd 100644
> --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
> @@ -21,8 +21,7 @@ Required properties:
>
> Optional properties:
>
> -- interrupts: interrupts routed to the TSC (3 for H3, M3-W, M3-N,
> - and V3H)
> +- interrupts: interrupts routed to the TSC (must be 3).
> - power-domain: Must contain a reference to the power domain. This
>property is mandatory if the thermal sensor instance
>is part of a controllable power domain.
> --
> 2.17.1
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
Re: [renesas:arm64-dt-for-v4.21 25/25] Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:622.1-7 Label or path sdhi0 not found
On 11/07/2018 02:57 PM, kbuild test robot wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git > arm64-dt-for-v4.21 > head: 3e8f76c61511f3c4f0c25c36172605d6aeaec37c > commit: 3e8f76c61511f3c4f0c25c36172605d6aeaec37c [25/25] arm64: dts: > r8a77990: ebisu: Add and enable SDHI device nodes > config: arm64-defconfig (attached as .config) > compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 > reproduce: > wget > https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O > ~/bin/make.cross > chmod +x ~/bin/make.cross > git checkout 3e8f76c61511f3c4f0c25c36172605d6aeaec37c > # save the attached .config to linux build tree > GCC_VERSION=7.2.0 make.cross ARCH=arm64 > > All errors (new ones prefixed by >>): > >>> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:622.1-7 Label or path >>> sdhi0 not found >>> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:637.1-7 Label or path >>> sdhi1 not found >>> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:651.1-7 Label or path >>> sdhi3 not found >>> FATAL ERROR: Syntax error parsing input tree Commit 3e8f76c61511f3c4f0c25c36172605d6aeaec37c seems to be missing the arch/arm64/boot/dts/renesas/r8a77990.dtsi | 36 + part from [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes thus the error. -- Best regards, Marek Vasut
[renesas:arm64-dt-for-v4.21 25/25] Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:622.1-7 Label or path sdhi0 not found
tree: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git arm64-dt-for-v4.21 head: 3e8f76c61511f3c4f0c25c36172605d6aeaec37c commit: 3e8f76c61511f3c4f0c25c36172605d6aeaec37c [25/25] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 3e8f76c61511f3c4f0c25c36172605d6aeaec37c # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=arm64 All errors (new ones prefixed by >>): >> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:622.1-7 Label or path >> sdhi0 not found >> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:637.1-7 Label or path >> sdhi1 not found >> Error: arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts:651.1-7 Label or path >> sdhi3 not found >> FATAL ERROR: Syntax error parsing input tree --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip
[PATCH] [trivial] mfd: tmio: Typo s/use use/use/
Signed-off-by: Geert Uytterhoeven --- include/linux/mfd/tmio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 1e70060c92ce0a11..aa696bcb1d12e750 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -83,7 +83,7 @@ /* Some controllers have a CBSY bit */ #define TMIO_MMC_HAVE_CBSY BIT(11) -/* Some controllers that support HS400 use use 4 taps while others use 8. */ +/* Some controllers that support HS400 use 4 taps while others use 8. */ #define TMIO_MMC_HAVE_4TAP_HS400 BIT(13) int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); -- 2.17.1
[PATCH] serial: sh-sci: Improve type-safety calling sci_receive_chars()
While ptr and port both point to the uart_port structure, the former is
the untyped pointer cookie passed to interrupt handlers.
Use the correctly typed port variable instead, to improve type-safety.
Signed-off-by: Geert Uytterhoeven
---
drivers/tty/serial/sh-sci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 8863689a6eebcc72..f1ee992532717a34 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1710,7 +1710,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
* of whether the I_IXOFF is set, otherwise, how is the interrupt
* to be disabled?
*/
- sci_receive_chars(ptr);
+ sci_receive_chars(port);
return IRQ_HANDLED;
}
@@ -1766,7 +1766,7 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
} else {
sci_handle_fifo_overrun(port);
if (!s->chan_rx)
- sci_receive_chars(ptr);
+ sci_receive_chars(port);
}
sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
--
2.17.1
[PATCH] dt-bindings: thermal: rcar-gen3-thermal: All variants use 3 interrupts
RZ/G2M also has 3 interrupts routed to the TSC, but the list was not
updated to reflect this.
Just drop the list, as this is the case for this TSC variant in all
R-Car Gen3 and RZ/G2 SoCs.
Fixes: be6af481f3b2d508 ("dt-bindings: thermal: rcar-gen3-thermal: Add r8a774a1
support")
Signed-off-by: Geert Uytterhoeven
---
.../devicetree/bindings/thermal/rcar-gen3-thermal.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
index ad9a435afef446f6..b6ab60f6abbf95fd 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
@@ -21,8 +21,7 @@ Required properties:
Optional properties:
-- interrupts : interrupts routed to the TSC (3 for H3, M3-W, M3-N,
- and V3H)
+- interrupts : interrupts routed to the TSC (must be 3).
- power-domain : Must contain a reference to the power domain. This
property is mandatory if the thermal sensor instance
is part of a controllable power domain.
--
2.17.1
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
On 11/07/2018 02:08 PM, Wolfram Sang wrote: > >> Nope. I tried that patchset on M3N again yesterday and got error -84 >> while initing the eMMC, so I need to look into that first. Then I'll >> try it on E3. > > Hmmm, we tried M3N at the hackfest and it worked great there. > > First idea: are you sure you have all depending patch series applied as > well? > > @Niklas: Have you/can you push a publich branch out with everything > included. We discussed this on IRC already, which is why I need to look into that. The HS200 works well on the M3N though. -- Best regards, Marek Vasut
[PATCH] iommu/ipmmu-vmsa: Fix crash on early domain free
If iommu_ops.add_device() fails, iommu_ops.domain_free() is still
called, leading to a crash, as the domain was only partially
initialized:
ipmmu-vmsa e67b.mmu: Cannot accommodate DMA translation for IOMMU page
tables
sata_rcar ee30.sata: Unable to initialize IPMMU context
iommu: Failed to add device ee30.sata to group 0: -22
Unable to handle kernel NULL pointer dereference at virtual address
0038
...
Call trace:
ipmmu_domain_free+0x1c/0xa0
iommu_group_release+0x48/0x68
kobject_put+0x74/0xe8
kobject_del.part.0+0x3c/0x50
kobject_put+0x60/0xe8
iommu_group_get_for_dev+0xa8/0x1f0
ipmmu_add_device+0x1c/0x40
of_iommu_configure+0x118/0x190
Fix this by checking if the domain's context already exists, before
trying to destroy it.
Signed-off-by: Geert Uytterhoeven
---
drivers/iommu/ipmmu-vmsa.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
index c4114b92652eb0c9..a8b2c649c1d1f1b9 100644
--- a/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@ -498,6 +498,9 @@ static int ipmmu_domain_init_context(struct
ipmmu_vmsa_domain *domain)
static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
{
+ if (!domain->mmu)
+ return;
+
/*
* Disable the context. Flush the TLB as required when modifying the
* context registers.
--
2.17.1
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
> Nope. I tried that patchset on M3N again yesterday and got error -84 > while initing the eMMC, so I need to look into that first. Then I'll > try it on E3. Hmmm, we tried M3N at the hackfest and it worked great there. First idea: are you sure you have all depending patch series applied as well? @Niklas: Have you/can you push a publich branch out with everything included. signature.asc Description: PGP signature
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
On 11/07/2018 09:50 AM, Wolfram Sang wrote:
> On Tue, Nov 06, 2018 at 09:46:47PM +0100, Marek Vasut wrote:
>> From: Takeshi Kihara
>>
>> This patch adds SDHI{0,1,3} device nodes for the r8a77990 SoC
>> and enables SD card slot connected to SDHI0, micro SD card slot
>> connected to SDHI1 and eMMC connected to SDHI3 on the Ebisu board
>> using the R8A77990 SoC.
>>
>> Signed-off-by: Takeshi Kihara
>> Signed-off-by: Marek Vasut
>
> Acked-by: Wolfram Sang
>
> Out of curiosity: have you tested HS400 on that board based on Niklas'
> recent patches as well?
Nope. I tried that patchset on M3N again yesterday and got error -84
while initing the eMMC, so I need to look into that first. Then I'll
try it on E3.
--
Best regards,
Marek Vasut
Re: [PATCH/RFT] arm64: dts: renesas: r8a77990: Add I2C-DVFS device node
On Mon, Nov 05, 2018 at 09:52:48AM +0100, Geert Uytterhoeven wrote:
> Hi Kaneko-san,
>
> On Sat, Oct 20, 2018 at 11:35 PM Yoshihiro Kaneko
> wrote:
> > From: Takeshi Kihara
> >
> > This patch adds I2C-DVFS device node for the R8A77990 SoC.
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-by: Yoshihiro Kaneko
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -22,7 +22,8 @@
> > i2c4 =
> > i2c5 =
> > i2c6 =
> > - i2c7 =
> > + i2c7 = _dvfs;
> > + i2c8 =
>
> Please don't change existing aliases.
> While this makes the use of i2c7 for PMIC access uniform across the
> range of R-Car Gen3 SoCs that have it, I think this is a bad idea, and that
> it is better not to rely on I2C aliases at all.
>
> I guess the BSP did this to configure the BD9571 PMIC for DDR backup
> mode using i2cset? Upstream has another method, avoiding the need for
> i2cset, cfr. Documentation/ABI/testing/sysfs-driver-bd9571mwv-regulator.
Dropping the above hung makes sense to me.
Out of interest, what would be the implication of removing
existing aliases?
>
> > };
> >
> > cpus {
> > @@ -337,6 +338,22 @@
> > reg = <0 0xe606 0 0x508>;
> > };
> >
> > + i2c_dvfs: i2c@e60b {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "renesas,iic-r8a77990",
>
> "renesas,iic-r8a77990" is not yet documented.
Thanks, as per my comment below I wonder if as well as documenting
"renesas,iic-r8a77990" we also to teach the driver about it.
>
> > +"renesas,rcar-gen3-iic",
> > +"renesas,rmobile-iic";
>
> Also, IIC on R-Car E3 does not have the automatic transmission registers.
> Does this affect claiming compatibility with the family-specific or generic
> compatible values?
My cursory reading of the driver indicates that only register that is
used by it but documented as not existing on E3 is ICSTART (offset 0x70).
It seems to me that we should confirm with Renesas that the register does
indeed not exist - as this patch comes from the BSP which implies it is
being used there. And if it does not exist we should try teaching the
driver not to use ICSTART via the "renesas,iic-r8a77990" compat string.
What do you think?
> > + reg = <0 0xe60b 0 0x34>;
>
> Why 0x34? Last (byte-sized) register documented is at 0x14 => 0x15?
I can't explain 0x34 but I agree 0x15 would match the documentation.
>
> > + interrupts = ;
> > + clocks = < CPG_MOD 926>;
> > + power-domains = < R8A77990_PD_ALWAYS_ON>;
> > + resets = < 926>;
> > + dmas = < 0x11>, < 0x10>;
> > + dma-names = "tx", "rx";
> > + status = "disabled";
> > + };
> > +
[PATCH v3 resend] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB
From: Biju Das
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Fabrizio Castro
---
v4.20 RC1 is out, this update rebases the patch on top of
renesas-devel-20181107-v4.20-rc1
Thanks,
Fab
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 18d2263..52f23b8 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -60,6 +60,9 @@
};
{
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
phy-handle = <>;
phy-mode = "gmii";
renesas,no-ether-link;
@@ -82,6 +85,11 @@
};
{
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii_tx_rx";
+ function = "avb";
+ };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
--
2.7.4
Re: [PATCH v4 2/4] pinctrl: sh-pfc: Fix VIN versioned groups name
On Wed, Nov 07, 2018 at 11:59:49AM +0100, jacopo mondi wrote: > Hi Simon, > > On Wed, Nov 07, 2018 at 11:41:34AM +0100, Simon Horman wrote: > > On Tue, Nov 06, 2018 at 11:35:31AM +0100, Jacopo Mondi wrote: > > > Versioned VIN groups can appear on different sets of pins. Using the > > > VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through > > > an optional 'version' argument. > > > > > > Use the 'version' argument for said macro to fix naming of versioned > > > groups for R-Car SoCs that defines them. > > > > > > Signed-off-by: Jacopo Mondi > > > > Reviewed-by: Simon Horman > > > > I'm going to split this patch for each SoC to ease backporting, as > Geert suggested. Provided the single patches content is the same as > here, can I retain your R-b tag? Yes, sure.
[PATCH 2/3] dt-bindings: arm: Fix RZ/G2E part number
From: Fabrizio Castro Fix RZ/G2E part number from its description. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index f5e0f82fd503..58c4256d37a3 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -27,7 +27,7 @@ SoCs: compatible = "renesas,r8a77470" - RZ/G2M (R8A774A1) compatible = "renesas,r8a774a1" - - RZ/G2E (RA8774C0) + - RZ/G2E (R8A774C0) compatible = "renesas,r8a774c0" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" -- 2.11.0
[GIT PULL] Renesas ARM Based SoC Fixes for v4.20
Hi Olof, Hi Kevin, Hi Arnd, Please consider these Renesas ARM based SoC fixes for v4.20. The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a: Linux 4.20-rc1 (2018-11-04 15:37:52 -0800) are available in the git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-fixes-for-v4.20 for you to fetch changes up to eab53fdfd60a84b0cc514d4f1f5d79226c76df01: arm64: dts: renesas: condor: switch from EtherAVB to GEther (2018-11-05 15:08:44 +0100) Renesas ARM Based SoC Fixes for v4.20 * R-Car V3H (r8a77980) based Condor board - Switch from EtherAVB to GEther to match offical boards * RZ/G2E (ra8774c0) SoC: correct documentation of part number * R-Car H3 (r8a7795) SoC: reinstate all DMA channels on HSCIF2 Fabrizio Castro (1): dt-bindings: arm: Fix RZ/G2E part number Kuninori Morimoto (1): arm64: dts: renesas: r8a7795: add missing dma-names on hscif2 Sergei Shtylyov (1): arm64: dts: renesas: condor: switch from EtherAVB to GEther Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77980-condor.dts| 47 +++--- 3 files changed, 26 insertions(+), 25 deletions(-)
[PATCH 1/3] arm64: dts: renesas: r8a7795: add missing dma-names on hscif2
From: Kuninori Morimoto
hscif2 has 4 dmas, but has only 2 dma-names.
This patch add missing dma-names.
Signed-off-by: Kuninori Morimoto
Reviewed-by: Geert Uytterhoeven
Fixes: e0f0bda79337701a ("arm64: dts: renesas: r8a7795: sort subnodes
of the soc node")
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index b5f2273caca4..a79c8d369e0b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -652,7 +652,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = < 0x35>, < 0x34>,
< 0x35>, < 0x34>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = < R8A7795_PD_ALWAYS_ON>;
resets = < 518>;
status = "disabled";
--
2.11.0
[PATCH 3/3] arm64: dts: renesas: condor: switch from EtherAVB to GEther
From: Sergei Shtylyov
The "official" Condor boards have always been wired to mount NFS via
GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
to Cogent Embedded, so we've been having an unpleasant situation where
a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
extension board is plugged in). Switch from EtherAVB to GEther at last!
Fixes: 8091788f3d38 ("arm64: dts: renesas: condor: add EtherAVB support")
Signed-off-by: Sergei Shtylyov
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 47 +
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index fe2e2c051cc9..5a7012be0d6a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -15,7 +15,7 @@
aliases {
serial0 =
- ethernet0 =
+ ethernet0 =
};
chosen {
@@ -97,23 +97,6 @@
};
};
- {
- pinctrl-0 = <_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii-id";
- phy-handle = <>;
- renesas,no-ether-link;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
@@ -139,6 +122,23 @@
clock-frequency = <32768>;
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
@@ -236,16 +236,17 @@
};
{
- avb_pins: avb {
- groups = "avb_mdio", "avb_rgmii";
- function = "avb";
- };
-
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
+ gether_pins: gether {
+ groups = "gether_mdio_a", "gether_rgmii",
+"gether_txcrefclk", "gether_txcrefclk_mega";
+ function = "gether";
+ };
+
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
--
2.11.0
Re: [PATCH 00/03] Connect R-Car Gen3 Ethernet-AVB to IPMMU
On Mon, Oct 22, 2018 at 02:14:34AM +0900, Magnus Damm wrote: > Connect R-Car Gen3 Ethernet-AVB to IPMMU > > [PATCH 01/03] arm64: dts: renesas: r8a77965: Connect R-Car M3-N AVB to IPMMU > [PATCH 02/03] arm64: dts: renesas: r8a77980: Connect R-Car V3H AVB to IPMMU > [PATCH 03/03] arm64: dts: renesas: r8a77990: Connect R-Car E3 AVB to IPMMU > > For each SoC describe Ethernet-AVB to IPMMU hardware connection in the > Device Tree. This series affects R-Car M3-N, V3H and E3. Other members > of the R-Car Gen3 family such as H3, M3-W, V3M and D3 already includes > this information in their DT files. > > Signed-off-by: Magnus Damm Hi, I have already queued-up these patches but I noticed that they do the same thing to different SoCs and recently the ARM-SoC maintainers have asked us to consolidate such patches. With that in mind I am considering squashing the three patches that comprise this series into one. Are there any objections?
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
On Tue, Nov 06, 2018 at 09:46:47PM +0100, Marek Vasut wrote:
> From: Takeshi Kihara
>
> This patch adds SDHI{0,1,3} device nodes for the r8a77990 SoC
> and enables SD card slot connected to SDHI0, micro SD card slot
> connected to SDHI1 and eMMC connected to SDHI3 on the Ebisu board
> using the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Marek Vasut
> Cc: Geert Uytterhoeven
> Cc: Simon Horman
> Cc: Wolfram Sang
> Cc: Yoshihiro Shimoda
> Cc: linux-renesas-soc@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> ---
> V2: - Deduplicated regular and UHS pins
> - Added sdhi3_ds pin pinmux
> V3: - Squash two patches, one adding SDHI nodes to R8A77990 E3 DTSI
> and another enabling them on E3 Ebisu, together.
> ---
> .../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 130 ++
> arch/arm64/boot/dts/renesas/r8a77990.dtsi | 36 +
> 2 files changed, 166 insertions(+)
Thanks, applied for v4.21.
Re: [PATCH] pinctrl: sh-pfc: r8a77970: add QSPI pins, groups, and functions
On Tue, Nov 06, 2018 at 09:52:55PM +0300, Sergei Shtylyov wrote:
> From: Dmitry Shifrin
>
> Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver.
>
> [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
> SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
> be in the alphanumeric order, removed unneeded empty lines, renamed the
> patch.]
>
> Signed-off-by: Dmitry Shifrin
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
RE: [renesas-drivers:topic/pinctrl-rza2-v2 1/2] drivers//pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here (not in a function); did you mean 'RZA2_NPINS'?
Hi Geert,
> > Great, so MIPS defines PC, precluding it use in any driver that includes
> > in some way.
That really stinks!!!
> Anyway, drivers//pinctrl/pinctrl-rza2.c doesn't really use the enum
> values it defines,
> so they can be renamed (PC -> PORTC, or PORT_C).
Of course that means I have to go back and change everything to PORTx.
:(
Damn you MIPS!
Chris
On Wednesday, November 07, 2018, Geert Uytterhoeven wrote:
> On Wed, Nov 7, 2018 at 10:22 AM Geert Uytterhoeven
> wrote:
> > On Wed, Nov 7, 2018 at 10:12 AM kbuild test robot wrote:
> > > tree: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-
> drivers.git topic/pinctrl-rza2-v2
> > > head: bb0f488fb2907f47250f7f34af60a482fd3dbfe4
> > > commit: feac9e8cb1ad7b4979e4b553fcdf2d8582049227 [1/2] pinctrl: Add
> RZ/A2 pin and gpio controller
> > > config: mips-allmodconfig (attached as .config)
> > > compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> > > reproduce:
> > > wget https://raw.githubusercontent.com/intel/lkp-
> tests/master/sbin/make.cross -O ~/bin/make.cross
> > > chmod +x ~/bin/make.cross
> > > git checkout feac9e8cb1ad7b4979e4b553fcdf2d8582049227
> > > # save the attached .config to linux build tree
> > > GCC_VERSION=7.2.0 make.cross ARCH=mips
> > >
> > > All error/warnings (new ones prefixed by >>):
> > >
> > >In file included from arch/mips/include/asm/ptrace.h:19:0,
> > > from include/linux/irq.h:24,
> > > from include/linux/gpio/driver.h:7,
> > > from include/asm-generic/gpio.h:13,
> > > from include/linux/gpio.h:62,
> > > from drivers//pinctrl/pinctrl-rza2.c:14:
> > > >> arch/mips/include/uapi/asm/ptrace.h:17:13: error: expected
> identifier before numeric constant
> > > #define PC 64
> > > ^
> >
> > Great, so MIPS defines PC, precluding it use in any driver that includes
> > in some way.
> >
> > However, it looks like doesn't really need
> .
> > Will send a patch to try that...
>
> Doesn't work, as it also includes , which is needed.
>
> Anyway, drivers//pinctrl/pinctrl-rza2.c doesn't really use the enum
> values it defines,
> so they can be renamed (PC -> PORTC, or PORT_C).
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH v4 2/4] pinctrl: sh-pfc: Fix VIN versioned groups name
Hi Simon, On Wed, Nov 07, 2018 at 11:41:34AM +0100, Simon Horman wrote: > On Tue, Nov 06, 2018 at 11:35:31AM +0100, Jacopo Mondi wrote: > > Versioned VIN groups can appear on different sets of pins. Using the > > VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through > > an optional 'version' argument. > > > > Use the 'version' argument for said macro to fix naming of versioned > > groups for R-Car SoCs that defines them. > > > > Signed-off-by: Jacopo Mondi > > Reviewed-by: Simon Horman > I'm going to split this patch for each SoC to ease backporting, as Geert suggested. Provided the single patches content is the same as here, can I retain your R-b tag? signature.asc Description: PGP signature
Re: [PATCH v4 4/4] pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Hi Simon,
On Wed, Nov 07, 2018 at 11:34:50AM +0100, Simon Horman wrote:
> On Tue, Nov 06, 2018 at 11:35:33AM +0100, Jacopo Mondi wrote:
> > Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
> >
> > Signed-off-by: Jacopo Mondi
> >
> > ---
> > v3 -> v4:
> > - Use new variadic version of VIN_DATA_PIN_GROUP macro
>
> I may be missing something but this patch seems to be the same as v3,
> using the VIN_DATA_PIN_GROUP_VER macro.
>
Oooops, I forgot to add the changes and lost them while rebasing.
Sorry about this, I'll resend.
Thanks
j
> >
> > v2 -> v3:
> > - Rebased on v4.20-rc1
> > - Use the newly introduced VIN_DATA_PIN_GROUP_VER macro
> >
> > Incorporate Geert's comments:
> > - vin5_data8_b is only used with 8 pins: use regular SH_PFC_PIN_GROUP()
> > - remove stf groups for vin4/vin5
> > - confirmed that pins [23-8] of vin4's groups 'a' and 'b' are shared
> > - confirmed with HW team the synchronism pins in vin5 are only for group 'a'
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244
> > ++
> > 1 file changed, 244 insertions(+)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > index 1fdafa4..16fd139 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > @@ -2433,6 +2433,190 @@ static const unsigned int usb30_id_mux[] = {
> > USB3HS0_ID_MARK,
> > };
> >
> > +/* - VIN4
> > --- */
> > +static const union vin_data vin4_data_a_pins = {
> > + .data24 = {
> > + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
> > + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
> > + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
> > + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
> > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> > + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> > + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> > + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> > + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
> > + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> > + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_a_mux = {
> > + .data24 = {
> > + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
> > + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
> > + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
> > + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
> > + VI4_DATA8_MARK, VI4_DATA9_MARK,
> > + VI4_DATA10_MARK, VI4_DATA11_MARK,
> > + VI4_DATA12_MARK, VI4_DATA13_MARK,
> > + VI4_DATA14_MARK, VI4_DATA15_MARK,
> > + VI4_DATA16_MARK, VI4_DATA17_MARK,
> > + VI4_DATA18_MARK, VI4_DATA19_MARK,
> > + VI4_DATA20_MARK, VI4_DATA21_MARK,
> > + VI4_DATA22_MARK, VI4_DATA23_MARK,
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_b_pins = {
> > + .data24 = {
> > + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
> > + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
> > + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
> > + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
> > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> > + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> > + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> > + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> > + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15),
> > + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> > + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_b_mux = {
> > + .data24 = {
> > + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
> > + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
> > + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
> > + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
> > + VI4_DATA8_MARK, VI4_DATA9_MARK,
> > + VI4_DATA10_MARK, VI4_DATA11_MARK,
> > + VI4_DATA12_MARK, VI4_DATA13_MARK,
> > + VI4_DATA14_MARK, VI4_DATA15_MARK,
> > + VI4_DATA16_MARK, VI4_DATA17_MARK,
> > + VI4_DATA18_MARK, VI4_DATA19_MARK,
> > + VI4_DATA20_MARK, VI4_DATA21_MARK,
> > + VI4_DATA22_MARK, VI4_DATA23_MARK,
> > + },
> > +};
> > +
> > +static const unsigned int vin4_sync_pins[] = {
> > + /* HSYNC, VSYNC */
> > + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
> > +};
> > +
> > +static const unsigned int vin4_sync_mux[] = {
> > + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
> > +};
> > +
> > +static const unsigned int vin4_field_pins[] = {
> > + RCAR_GP_PIN(2, 23),
> > +};
> > +
> > +static const unsigned int vin4_field_mux[] = {
> > + VI4_FIELD_MARK,
> > +};
> > +
> > +static const unsigned int vin4_clkenb_pins[] = {
> > +
Re: [PATCH v4 3/4] pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions
On Tue, Nov 06, 2018 at 11:35:32AM +0100, Jacopo Mondi wrote: > The VIN4 and VIN5 interfaces supports parallel video input. > Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N. > > Reviewed-by: Ulrich Hecht > Signed-off-by: Jacopo Mondi Reviewed-by: Simon Horman
Re: [PATCH v4 2/4] pinctrl: sh-pfc: Fix VIN versioned groups name
On Tue, Nov 06, 2018 at 11:35:31AM +0100, Jacopo Mondi wrote: > Versioned VIN groups can appear on different sets of pins. Using the > VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through > an optional 'version' argument. > > Use the 'version' argument for said macro to fix naming of versioned > groups for R-Car SoCs that defines them. > > Signed-off-by: Jacopo Mondi Reviewed-by: Simon Horman
Re: [PATCH v4 1/4] pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP
On Tue, Nov 06, 2018 at 11:35:30AM +0100, Jacopo Mondi wrote:
> VIN data groups may appear on different sets of pins, usually named
> "vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support
> appending the '_a' or '_b' suffix, leading to the definition of groups
> names not consistent with the ones defined using SH_PFC_PIN_GROUP() macro.
>
> Fix this by adding making the VIN_DATA_PIN_GROUP macro a variadic one,
> which accepts an optional 'version' argument.
FWIW I prefered the VIN_DATA_PIN_GROUP_VER() approach as it pinned down
what the parameters to the macro should be, albeit with parameter naming
conundrum. While we could have any number f varargs present.
But I don't think we need to debate the colour of the bike shed at this
point.
Reviewed-by: Simon Horman
> Signed-off-by: Jacopo Mondi
> ---
> drivers/pinctrl/sh-pfc/sh_pfc.h | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
> index 458ae0a..0e0b4cc 100644
> --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> @@ -54,15 +54,16 @@ struct sh_pfc_pin_group {
>
> /*
> * Using union vin_data saves memory occupied by the VIN data pins.
> - * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
> - * in this case.
> + * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
> + * in this case. It accepts an optional 'version' argument used when the
> + * same group can appear on a different set of pins.
> */
> -#define VIN_DATA_PIN_GROUP(n, s) \
> - { \
> - .name = #n#s, \
> - .pins = n##_pins.data##s, \
> - .mux = n##_mux.data##s, \
> - .nr_pins = ARRAY_SIZE(n##_pins.data##s),\
> +#define VIN_DATA_PIN_GROUP(n, s, ...)
> \
> + { \
> + .name = #n#s#__VA_ARGS__, \
> + .pins = n##__VA_ARGS__##_pins.data##s, \
> + .mux = n##__VA_ARGS__##_mux.data##s,\
> + .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
> }
>
> union vin_data {
> --
> 2.7.4
>
Re: [PATCH v4 4/4] pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
On Tue, Nov 06, 2018 at 11:35:33AM +0100, Jacopo Mondi wrote:
> Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
>
> Signed-off-by: Jacopo Mondi
>
> ---
> v3 -> v4:
> - Use new variadic version of VIN_DATA_PIN_GROUP macro
I may be missing something but this patch seems to be the same as v3,
using the VIN_DATA_PIN_GROUP_VER macro.
>
> v2 -> v3:
> - Rebased on v4.20-rc1
> - Use the newly introduced VIN_DATA_PIN_GROUP_VER macro
>
> Incorporate Geert's comments:
> - vin5_data8_b is only used with 8 pins: use regular SH_PFC_PIN_GROUP()
> - remove stf groups for vin4/vin5
> - confirmed that pins [23-8] of vin4's groups 'a' and 'b' are shared
> - confirmed with HW team the synchronism pins in vin5 are only for group 'a'
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244
> ++
> 1 file changed, 244 insertions(+)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> index 1fdafa4..16fd139 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> @@ -2433,6 +2433,190 @@ static const unsigned int usb30_id_mux[] = {
> USB3HS0_ID_MARK,
> };
>
> +/* - VIN4
> --- */
> +static const union vin_data vin4_data_a_pins = {
> + .data24 = {
> + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
> + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
> + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
> + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
> + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> + },
> +};
> +
> +static const union vin_data vin4_data_a_mux = {
> + .data24 = {
> + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
> + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
> + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
> + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> + VI4_DATA16_MARK, VI4_DATA17_MARK,
> + VI4_DATA18_MARK, VI4_DATA19_MARK,
> + VI4_DATA20_MARK, VI4_DATA21_MARK,
> + VI4_DATA22_MARK, VI4_DATA23_MARK,
> + },
> +};
> +
> +static const union vin_data vin4_data_b_pins = {
> + .data24 = {
> + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
> + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
> + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
> + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15),
> + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> + },
> +};
> +
> +static const union vin_data vin4_data_b_mux = {
> + .data24 = {
> + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
> + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
> + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
> + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
> + VI4_DATA8_MARK, VI4_DATA9_MARK,
> + VI4_DATA10_MARK, VI4_DATA11_MARK,
> + VI4_DATA12_MARK, VI4_DATA13_MARK,
> + VI4_DATA14_MARK, VI4_DATA15_MARK,
> + VI4_DATA16_MARK, VI4_DATA17_MARK,
> + VI4_DATA18_MARK, VI4_DATA19_MARK,
> + VI4_DATA20_MARK, VI4_DATA21_MARK,
> + VI4_DATA22_MARK, VI4_DATA23_MARK,
> + },
> +};
> +
> +static const unsigned int vin4_sync_pins[] = {
> + /* HSYNC, VSYNC */
> + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
> +};
> +
> +static const unsigned int vin4_sync_mux[] = {
> + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
> +};
> +
> +static const unsigned int vin4_field_pins[] = {
> + RCAR_GP_PIN(2, 23),
> +};
> +
> +static const unsigned int vin4_field_mux[] = {
> + VI4_FIELD_MARK,
> +};
> +
> +static const unsigned int vin4_clkenb_pins[] = {
> + RCAR_GP_PIN(1, 2),
> +};
> +
> +static const unsigned int vin4_clkenb_mux[] = {
> + VI4_CLKENB_MARK,
> +};
> +
> +static const unsigned int vin4_clk_pins[] = {
> + RCAR_GP_PIN(2, 22),
> +};
> +
> +static const unsigned int vin4_clk_mux[] = {
> + VI4_CLK_MARK,
> +};
> +
> +/* - VIN5
Re: [PATCH] pinctrl: sh-pfc: r8a77990: Add VIN pins, groups and functions
On Mon, Nov 05, 2018 at 12:59:33PM +0100, Jacopo Mondi wrote:
> This patch adds VIN{4,5} pins, groups and functions to the R8A77990 SoC.
>
> Signed-off-by: Jacopo Mondi
Reviewed-by: Simon Horman
[PATCH LOCAL 2/2] arm64: renesas_defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function on the Renesas Condor board. Signed-off-by: Geert Uytterhoeven --- Not intended for upstream merge. --- arch/arm64/configs/renesas_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/renesas_defconfig b/arch/arm64/configs/renesas_defconfig index 0021497c967ea1a6..db66d9a37bac4112 100644 --- a/arch/arm64/configs/renesas_defconfig +++ b/arch/arm64/configs/renesas_defconfig @@ -300,6 +300,7 @@ CONFIG_MAX9611=y CONFIG_PWM=y CONFIG_PWM_RCAR=y CONFIG_RESET_CONTROLLER=y +CONFIG_PHY_RCAR_GEN3_PCIE=y CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_RCAR_GEN3_USB3=y CONFIG_TEE=y -- 2.17.1
[PATCH LOCAL 0/2] arm64: renesas_defconfig: Updates for v4.20-rc1
Hi Simon, Magnus,
This patch series updates renesas_defconfig for dropped and new support in
v4.20-rc1.
Note that this is not intended for upstream merge.
Thanks!
Geert Uytterhoeven (2):
[LOCAL] arm64: renesas_defconfig: Drop CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
[LOCAL] arm64: renesas_defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
arch/arm64/configs/renesas_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH LOCAL 1/2] arm64: renesas_defconfig: Drop CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
CONFIG_ARM_BIG_LITTLE_CPUFREQ was removed on arm64 in commit
a7314405d83c8f95 ("cpufreq: drop ARM_BIG_LITTLE_CPUFREQ support for
ARM64").
Signed-off-by: Geert Uytterhoeven
---
Not intended for upstream merge.
---
arch/arm64/configs/renesas_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/configs/renesas_defconfig
b/arch/arm64/configs/renesas_defconfig
index a8113a721c11b812..0021497c967ea1a6 100644
--- a/arch/arm64/configs/renesas_defconfig
+++ b/arch/arm64/configs/renesas_defconfig
@@ -69,7 +69,6 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPUFREQ_DT=y
-CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
# CONFIG_DMIID is not set
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
--
2.17.1
Re: [PATCH v2] watchdog: renesas_wdt: Fix typos
On Mon, Nov 05, 2018 at 10:53:47AM +, Fabrizio Castro wrote: > Do not use "," but ";" to separate instructions. > > Signed-off-by: Fabrizio Castro > Reviewed-by: Guenter Roeck > > --- > v1->v2: > * Added changelog as suggested by Guenter Roeck Reviewed-by: Simon Horman > > drivers/watchdog/renesas_wdt.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c > index 0d74c3e..b570962 100644 > --- a/drivers/watchdog/renesas_wdt.c > +++ b/drivers/watchdog/renesas_wdt.c > @@ -220,8 +220,8 @@ static int rwdt_probe(struct platform_device *pdev) > goto out_pm_disable; > } > > - priv->wdev.info = _ident, > - priv->wdev.ops = _ops, > + priv->wdev.info = _ident; > + priv->wdev.ops = _ops; > priv->wdev.parent = >dev; > priv->wdev.min_timeout = 1; > priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); > -- > 2.7.4 >
Re: [renesas-drivers:topic/pinctrl-rza2-v2 1/2] drivers//pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here (not in a function); did you mean 'RZA2_NPINS'?
On Wed, Nov 7, 2018 at 10:22 AM Geert Uytterhoeven wrote:
> On Wed, Nov 7, 2018 at 10:12 AM kbuild test robot wrote:
> > tree:
> > https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> > topic/pinctrl-rza2-v2
> > head: bb0f488fb2907f47250f7f34af60a482fd3dbfe4
> > commit: feac9e8cb1ad7b4979e4b553fcdf2d8582049227 [1/2] pinctrl: Add RZ/A2
> > pin and gpio controller
> > config: mips-allmodconfig (attached as .config)
> > compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> > reproduce:
> > wget
> > https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
> > ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > git checkout feac9e8cb1ad7b4979e4b553fcdf2d8582049227
> > # save the attached .config to linux build tree
> > GCC_VERSION=7.2.0 make.cross ARCH=mips
> >
> > All error/warnings (new ones prefixed by >>):
> >
> >In file included from arch/mips/include/asm/ptrace.h:19:0,
> > from include/linux/irq.h:24,
> > from include/linux/gpio/driver.h:7,
> > from include/asm-generic/gpio.h:13,
> > from include/linux/gpio.h:62,
> > from drivers//pinctrl/pinctrl-rza2.c:14:
> > >> arch/mips/include/uapi/asm/ptrace.h:17:13: error: expected identifier
> > >> before numeric constant
> > #define PC 64
> > ^
>
> Great, so MIPS defines PC, precluding it use in any driver that includes
> in some way.
>
> However, it looks like doesn't really need
> .
> Will send a patch to try that...
Doesn't work, as it also includes , which is needed.
Anyway, drivers//pinctrl/pinctrl-rza2.c doesn't really use the enum
values it defines,
so they can be renamed (PC -> PORTC, or PORT_C).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [renesas-drivers:topic/pinctrl-rza2-v2 1/2] drivers//pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here (not in a function); did you mean 'RZA2_NPINS'?
On Wed, Nov 7, 2018 at 10:12 AM kbuild test robot wrote:
> tree:
> https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> topic/pinctrl-rza2-v2
> head: bb0f488fb2907f47250f7f34af60a482fd3dbfe4
> commit: feac9e8cb1ad7b4979e4b553fcdf2d8582049227 [1/2] pinctrl: Add RZ/A2 pin
> and gpio controller
> config: mips-allmodconfig (attached as .config)
> compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> git checkout feac9e8cb1ad7b4979e4b553fcdf2d8582049227
> # save the attached .config to linux build tree
> GCC_VERSION=7.2.0 make.cross ARCH=mips
>
> All error/warnings (new ones prefixed by >>):
>
>In file included from arch/mips/include/asm/ptrace.h:19:0,
> from include/linux/irq.h:24,
> from include/linux/gpio/driver.h:7,
> from include/asm-generic/gpio.h:13,
> from include/linux/gpio.h:62,
> from drivers//pinctrl/pinctrl-rza2.c:14:
> >> arch/mips/include/uapi/asm/ptrace.h:17:13: error: expected identifier
> >> before numeric constant
> #define PC 64
> ^
Great, so MIPS defines PC, precluding it use in any driver that includes
in some way.
However, it looks like doesn't really need .
Will send a patch to try that...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[renesas-drivers:topic/pinctrl-rza2-v2 1/2] drivers//pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here (not in a function); did you mean 'RZA2_NPINS'?
tree:
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
topic/pinctrl-rza2-v2
head: bb0f488fb2907f47250f7f34af60a482fd3dbfe4
commit: feac9e8cb1ad7b4979e4b553fcdf2d8582049227 [1/2] pinctrl: Add RZ/A2 pin
and gpio controller
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout feac9e8cb1ad7b4979e4b553fcdf2d8582049227
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=mips
All error/warnings (new ones prefixed by >>):
In file included from arch/mips/include/asm/ptrace.h:19:0,
from include/linux/irq.h:24,
from include/linux/gpio/driver.h:7,
from include/asm-generic/gpio.h:13,
from include/linux/gpio.h:62,
from drivers//pinctrl/pinctrl-rza2.c:14:
>> arch/mips/include/uapi/asm/ptrace.h:17:13: error: expected identifier before
>> numeric constant
#define PC 64
^
>> drivers//pinctrl/pinctrl-rza2.c:38:73: note: in expansion of macro 'PC'
enum pfc_pin_port_name {P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC,
PD,
^~
>> drivers//pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here
>> (not in a function); did you mean 'RZA2_NPINS'?
#define RZA2_NPINS (RZA2_PINS_PER_PORT * RZA2_NPORTS)
^
>> drivers//pinctrl/pinctrl-rza2.c:230:11: note: in expansion of macro
>> 'RZA2_NPINS'
.ngpio = RZA2_NPINS,
^~
--
In file included from arch/mips/include/asm/ptrace.h:19:0,
from include/linux/irq.h:24,
from include/linux/gpio/driver.h:7,
from include/asm-generic/gpio.h:13,
from include/linux/gpio.h:62,
from drivers/pinctrl/pinctrl-rza2.c:14:
>> arch/mips/include/uapi/asm/ptrace.h:17:13: error: expected identifier before
>> numeric constant
#define PC 64
^
drivers/pinctrl/pinctrl-rza2.c:38:73: note: in expansion of macro 'PC'
enum pfc_pin_port_name {P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC,
PD,
^~
drivers/pinctrl/pinctrl-rza2.c:25:43: error: 'RZA2_NPORTS' undeclared here
(not in a function); did you mean 'RZA2_NPINS'?
#define RZA2_NPINS (RZA2_PINS_PER_PORT * RZA2_NPORTS)
^
drivers/pinctrl/pinctrl-rza2.c:230:11: note: in expansion of macro
'RZA2_NPINS'
.ngpio = RZA2_NPINS,
^~
vim +25 drivers//pinctrl/pinctrl-rza2.c
> 14 #include
15 #include
16 #include
17 #include
18
19 #include "core.h"
20 #include "pinmux.h"
21
22 #define DRIVER_NAME "pinctrl-rza2"
23
24 #define RZA2_PINS_PER_PORT 8
> 25 #define RZA2_NPINS (RZA2_PINS_PER_PORT * RZA2_NPORTS)
26 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
27 #define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
28
29 /*
30 * Use 16 lower bits [15:0] for pin identifier
31 * Use 16 higher bits [31:16] for pin mux function
32 */
33 #define MUX_PIN_ID_MASK GENMASK(15, 0)
34 #define MUX_FUNC_MASK GENMASK(31, 16)
35 #define MUX_FUNC_OFFS 16
36 #define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >>
MUX_FUNC_OFFS)
37
> 38 enum pfc_pin_port_name {P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB,
PC, PD,
39 PE, PF, PG, PH, PJ, PK, PL, PM, RZA2_NPORTS};
40 static const char port_names[] = "0123456789ABCDEFGHJKLM";
41
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH V3] arm64: dts: r8a77990: ebisu: Add and enable SDHI device nodes
On Tue, Nov 06, 2018 at 09:46:47PM +0100, Marek Vasut wrote:
> From: Takeshi Kihara
>
> This patch adds SDHI{0,1,3} device nodes for the r8a77990 SoC
> and enables SD card slot connected to SDHI0, micro SD card slot
> connected to SDHI1 and eMMC connected to SDHI3 on the Ebisu board
> using the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Marek Vasut
Acked-by: Wolfram Sang
Out of curiosity: have you tested HS400 on that board based on Niklas'
recent patches as well?
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