[PATCH v2 2/4] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95
1 file changed, 74 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 0af737d..6f3a969 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -550,6 +550,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST)
FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
@@ -575,6 +578,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@@ -588,9 +592,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
- PINMUX_SINGLE(I2C_SEL_0_1),
- PINMUX_SINGLE(I2C_SEL_3_1),
- PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -614,14 +615,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
- PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
+ PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -674,14 +677,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+ PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+ PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1113,11 +1118,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_15_12,SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
-
[PATCH v2 3/4] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97
1 file changed, 75 insertions(+), 22 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 8c7de44..59cb0d7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -537,6 +537,9 @@ MOD_SEL0_2_1MOD_SEL1_2 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST)
FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
@@ -562,6 +565,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@@ -574,9 +578,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
- PINMUX_SINGLE(I2C_SEL_0_1),
- PINMUX_SINGLE(I2C_SEL_3_1),
- PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -608,13 +609,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_TANS_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -664,16 +667,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_GPSR(IP1_23_20, A21),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+ PINMUX_IPSR_MSEL(IP1_23_20, A21,I2C_SEL_3_0),
+ PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_GPSR(IP1_27_24, A20),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+ PINMUX_IPSR_MSEL(IP1_27_24, A20,I2C_SEL_3_0),
+ PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1067,11 +1072,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_15_12,SD0_WP),
[PATCH v2 4/4] pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 98
1 file changed, 77 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3a6d21d..b1f45d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -556,6 +556,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST)
FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
@@ -581,6 +584,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@@ -617,13 +621,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0,
SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C, I2C_SEL_5_0,
SEL_MSIOF2_2),
+ PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A, I2C_SEL_5_0,
SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -675,14 +681,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+ PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+ PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+ PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+ PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1115,13 +1123,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12,NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_GPSR(IP11_19_16,SD1_CD),
- PINMUX_IPSR_MSEL(IP11_19_16,NFRB_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_19_16,SIM0_CLK_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_19_16,SD1_CD, I2C_SEL_0_0),
+ PINMUX_IPSR_MSEL2(IP11_19_16, NFRB_N_A, I2C_SEL_0_0,
SEL_NDFC_0),
+ PINMUX_IPSR_MSEL2(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0,
SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_19_16,SCL0, I2C_SEL_0_1),
[PATCH v2 1/4] pinctrl: sh-pfc: Add physical pin multiplexing helper macros
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by: Ulrich Hecht --- drivers/pinctrl/sh-pfc/sh_pfc.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 1fc1336..6bb9c6b 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -386,6 +386,28 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) /* + * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with + * an additional select register that controls physical multiplexing + * with another pin. + * - ipsr: IPSR field + * - fn: Function name, also referring to the IPSR field + * - msel1: Physical multiplexing selector + * - msel2: Module selector + */ +#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ + PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr) + +/* + * Describe a pinmux configuration in which a pin is physically multiplexed + * with other pins. + * - ipsr: IPSR field + * - fn: Function name, also referring to the IPSR field + * - msel: Phyiscal multiplexing selector + */ +#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ + PINMUX_DATA(fn##_MARK, FN_##msel) + +/* * Describe a pinmux configuration for a single-function pin with GPIO * capability. * - fn: Function name -- 2.7.4
[PATCH v2 0/4] I2C0/3/5 pin control for H3 and M3-W
This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.
This revision incorporates the suggestions made by Geert; see below for
details.
CU
Uli
Changes since v1:
- factor out identical macros to sh_pfc.h, comment them
- sort pin groups
- adjust for common/automotive split in r8a7796
Takeshi Kihara (3):
pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and
functions
pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions
Ulrich Hecht (1):
pinctrl: sh-pfc: Add physical pin multiplexing helper macros
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97 ---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95 ---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 98 +---
drivers/pinctrl/sh-pfc/sh_pfc.h | 22 +++
4 files changed, 248 insertions(+), 64 deletions(-)
--
2.7.4
RE: [PATCH v6 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Hi Jacopo,
On Thursday, November 15, 2018 1, jacopo mondi wrote:
> > v5:
> > * Specify number of ports using of_device_id.data and save as priv-
> >npins
> > * Use priv->npins everywhere instead of hard coded RZA2_NPINS
> > * Check gpio-ranges to make sure args matches SOC
>
> Sorry about this, I didn't want to ask you to do this now, it might
> have had post-poned to when a new SoC will have to be supported, but..
As long as I can get this driver in for 4.21, I'll still be happy.
> > +static const struct of_device_id rza2_pinctrl_of_match[] = {
> > + { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
>
> ... I really don't like this, I'm sorry.
>
> I would rather make a 'struct rza_pinctrl_info' or similar which
> contains all the fields you now hardcode (number of ports, pins per
> port etc) and which is easily extensible in case you need to do so.
I was going by if there is only 1 value being set, just pass in a number
(don't make a struct). That is what is being done for the R-Car/RZA
SDHI driver (renesas_sdhi_internal_dmac.c), and what I was also asked to do
for the RZ/A watchdog timer (rza_wdt.c).
At the moment, the number of ports in the SOC is the only variable that
would be different between SoCs. For example, "pins per port" will
always be 8 (it's part of the HW design of this pin controller, it can never
change).
We can have Geert give his opinion on the topic since it was his
suggestion to begin with.
> I'm sorry this is more work, and again, it might be post-poned imo,
> provided you drop this change you have introduced here.
Since Geert is the maintainer of the Renesas pinctrl drivers, I'll let
him decide if I should drop that part for now since only 1 SOC exists
today.
Chris
[PATCH/RFT v2] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions
From: Takeshi Kihara
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.
v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
- Fix the definition of the hscif3_data_d_pins
- Update the size of the sh_pfc_pin_group.common and the
sh_pfc_function.common
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 370 +-
1 file changed, 368 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 5d6a13f..6868753 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1626,6 +1626,290 @@ enum {
DU_DISP_MARK,
};
+/* - HSCIF0 --*/
+static const unsigned int hscif0_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int hscif0_data_a_mux[] = {
+ HRX0_A_MARK, HTX0_A_MARK,
+};
+
+static const unsigned int hscif0_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int hscif0_clk_a_mux[] = {
+ HSCK0_A_MARK,
+};
+
+static const unsigned int hscif0_ctrl_a_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int hscif0_ctrl_a_mux[] = {
+ HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+
+static const unsigned int hscif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+
+static const unsigned int hscif0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 13),
+};
+
+static const unsigned int hscif0_clk_b_mux[] = {
+ HSCK0_B_MARK,
+};
+
+/* - HSCIF1 - */
+static const unsigned int hscif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int hscif1_data_a_mux[] = {
+ HRX1_A_MARK, HTX1_A_MARK,
+};
+
+static const unsigned int hscif1_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int hscif1_clk_a_mux[] = {
+ HSCK1_A_MARK,
+};
+
+static const unsigned int hscif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int hscif1_data_b_mux[] = {
+ HRX1_B_MARK, HTX1_B_MARK,
+};
+
+static const unsigned int hscif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int hscif1_clk_b_mux[] = {
+ HSCK1_B_MARK,
+};
+
+static const unsigned int hscif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int hscif1_ctrl_b_mux[] = {
+ HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+
+/* - HSCIF2 - */
+static const unsigned int hscif2_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int hscif2_data_a_mux[] = {
+ HRX2_A_MARK, HTX2_A_MARK,
+};
+
+static const unsigned int hscif2_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 14),
+};
+
+static const unsigned int hscif2_clk_a_mux[] = {
+ HSCK2_A_MARK,
+};
+
+static const unsigned int hscif2_ctrl_a_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int hscif2_ctrl_a_mux[] = {
+ HRTS2_N_A_MARK, HCTS2_N_A_MARK,
+};
+
+static const unsigned int hscif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int hscif2_data_b_mux[] = {
+ HRX2_B_MARK, HTX2_B_MARK,
+};
+
+/* - HSCIF3 */
+static const unsigned int hscif3_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+
+static const unsigned int hscif3_data_a_mux[] = {
+ HRX3_A_MARK, HTX3_A_MARK,
+};
+
+static const unsigned int hscif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int hscif3_data_b_mux[] = {
+ HRX3_B_MARK, HTX3_B_MARK,
+};
+
+static const unsigned int hscif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 4),
+};
+
+static const unsigned int hscif3_clk_b_mux[] = {
+ HSCK3_B_MARK,
+};
+
+static const unsigned int hscif3_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int hscif3_data_c_mux[] = {
+ HRX3_C_MARK, HTX3_C_MARK,
+};
+
+static const unsigned int hscif3_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int hscif3_clk_c_mux[] = {
+
Re: [PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions
Hi Geert-san,
Thanks for your review!!
2018年11月6日(火) 0:30 Geert Uytterhoeven :
>
> Hi Kaneko-san,
>
> On Sat, Oct 20, 2018 at 11:31 PM Yoshihiro Kaneko
> wrote:
> > From: Takeshi Kihara
> >
> > This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
> > the R8A77990 SoC.
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-by: Yoshihiro Kaneko
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
> > +static const unsigned int hscif3_data_d_pins[] = {
> > + /* RX, TX */
> > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),
>
> These two pins are exchanged.
> According to the datasheet, it should be:
>
> RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
I will fix it in v2.
>
> > +};
> > +
> > +static const unsigned int hscif3_data_d_mux[] = {
> > + HRX3_D_MARK, HTX3_D_MARK,
> > +};
>
> > @@ -2454,6 +2738,37 @@ enum {
> > SH_PFC_PIN_GROUP(du_disp_cde),
> > SH_PFC_PIN_GROUP(du_cde),
> > SH_PFC_PIN_GROUP(du_disp),
> > + SH_PFC_PIN_GROUP(hscif0_data_a),
> > + SH_PFC_PIN_GROUP(hscif0_clk_a),
> > + SH_PFC_PIN_GROUP(hscif0_ctrl_a),
> > + SH_PFC_PIN_GROUP(hscif0_data_b),
> > + SH_PFC_PIN_GROUP(hscif0_clk_b),
> > + SH_PFC_PIN_GROUP(hscif1_data_a),
> > + SH_PFC_PIN_GROUP(hscif1_clk_a),
> > + SH_PFC_PIN_GROUP(hscif1_data_b),
> > + SH_PFC_PIN_GROUP(hscif1_clk_b),
> > + SH_PFC_PIN_GROUP(hscif1_ctrl_b),
> > + SH_PFC_PIN_GROUP(hscif2_data_a),
> > + SH_PFC_PIN_GROUP(hscif2_clk_a),
> > + SH_PFC_PIN_GROUP(hscif2_ctrl_a),
> > + SH_PFC_PIN_GROUP(hscif2_data_b),
> > + SH_PFC_PIN_GROUP(hscif3_data_a),
> > + SH_PFC_PIN_GROUP(hscif3_data_b),
> > + SH_PFC_PIN_GROUP(hscif3_clk_b),
> > + SH_PFC_PIN_GROUP(hscif3_data_c),
> > + SH_PFC_PIN_GROUP(hscif3_clk_c),
> > + SH_PFC_PIN_GROUP(hscif3_ctrl_c),
> > + SH_PFC_PIN_GROUP(hscif3_data_d),
> > + SH_PFC_PIN_GROUP(hscif3_data_e),
> > + SH_PFC_PIN_GROUP(hscif3_ctrl_e),
> > + SH_PFC_PIN_GROUP(hscif4_data_a),
> > + SH_PFC_PIN_GROUP(hscif4_clk_a),
> > + SH_PFC_PIN_GROUP(hscif4_ctrl_a),
> > + SH_PFC_PIN_GROUP(hscif4_data_b),
> > + SH_PFC_PIN_GROUP(hscif4_clk_b),
> > + SH_PFC_PIN_GROUP(hscif4_data_c),
> > + SH_PFC_PIN_GROUP(hscif4_data_d),
> > + SH_PFC_PIN_GROUP(hscif4_data_e),
> > SH_PFC_PIN_GROUP(i2c1_a),
> > SH_PFC_PIN_GROUP(i2c1_b),
> > SH_PFC_PIN_GROUP(i2c1_c),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_groups.common[] array.
I will fix it.
>
> > @@ -2781,6 +3142,11 @@ enum {
> > .common = {
> > SH_PFC_FUNCTION(avb),
> > SH_PFC_FUNCTION(du),
> > + SH_PFC_FUNCTION(hscif0),
> > + SH_PFC_FUNCTION(hscif1),
> > + SH_PFC_FUNCTION(hscif2),
> > + SH_PFC_FUNCTION(hscif3),
> > + SH_PFC_FUNCTION(hscif4),
> > SH_PFC_FUNCTION(i2c1),
> > SH_PFC_FUNCTION(i2c2),
> > SH_PFC_FUNCTION(i2c4),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_functions.common[] array.
I will fix it.
Best regards,
Kaneko
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH v6 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Hi Chris,
On Thu, Nov 15, 2018 at 09:00:44AM -0500, Chris Brandt wrote:
> Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Jacopo Mondi
> ---
> v5:
> * Specify number of ports using of_device_id.data and save as priv->npins
> * Use priv->npins everywhere instead of hard coded RZA2_NPINS
> * Check gpio-ranges to make sure args matches SOC
Sorry about this, I didn't want to ask you to do this now, it might
have had post-poned to when a new SoC will have to be supported, but..
[snip]
> +
> +static const struct of_device_id rza2_pinctrl_of_match[] = {
> + { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
... I really don't like this, I'm sorry.
I would rather make a 'struct rza_pinctrl_info' or similar which
contains all the fields you now hardcode (number of ports, pins per
port etc) and which is easily extensible in case you need to do so.
I'm sorry this is more work, and again, it might be post-poned imo,
provided you drop this change you have introduced here.
Thanks
j
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver rza2_pinctrl_driver = {
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = rza2_pinctrl_of_match,
> + },
> + .probe = rza2_pinctrl_probe,
> +};
> +
> +static int __init rza2_pinctrl_init(void)
> +{
> + return platform_driver_register(_pinctrl_driver);
> +}
> +core_initcall(rza2_pinctrl_init);
> +
> +MODULE_AUTHOR("Chris Brandt ");
> +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
> +MODULE_LICENSE("GPL v2");
> --
> 2.16.1
>
signature.asc
Description: PGP signature
[PATCH v7 0/2] pinctrl: Add RZ/A2 pin and gpio driver
The pin controller in the RZ/A2 is nothing like the pin controller in the RZ/A1. That's a good thing! This pin controller is much more simple and easier to configure. So, this driver is faily simple (I hope). Chris Brandt (2): pinctrl: Add RZ/A2 pin and gpio controller dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 drivers/pinctrl/Kconfig| 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rza2.c | 519 + include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 ++ 5 files changed, 665 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-rza2.c create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h -- 2.16.1
[PATCH v7 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v6:
* Bug fix: Output value not being set in rza2_chip_direction_output()
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
* Use priv->npins everywhere instead of hard coded RZA2_NPINS
* Check gpio-ranges to make sure args matches SOC
v4:
* Mention GPIO in Kconfig
* Removed port enum and just define RZA2_NPORTS
* Moved gpio_range from global to private data
* Condensed and simplify register macros
* Added register bit definitions to remove magic numbers
* Reverse Christmas Tree style for local variables
* rza2_pin_to_gpio now takes 'offset' instead of 'port' and 'pin'
* Use !! to return 0 or 1 for rza2_chip_get
* Removed check for gpio-controller since dt-bindings say it's mandatory
* Reuse rza2_gpio_names[] for pins[i].name since it's the same strings
* Use %pOF for printing DT node names
* Use dev_err for "Unable to parse DT node" message
* Changed pr_info to dev_info for message at the end of probe
* Changed probe message to print out what ports were registered
* Removed extra newlines
* Added Reviewed-by
v3:
* Changed names from Px to PORTx because "PC" is already defined
v2:
* fixed SOC part number in comments
* sorted #includes
* removed spaces in pfc_pin_port_name enum
* put RZA2_NPORTS at the end of pfc_pin_port_name enum
* added RZA2_ to the beginning of all #define macros
* put ( ) around all passed arguments in #define macros
* made helper macros to get register address easier
* use defines for pin direction bit settings
---
drivers/pinctrl/Kconfig| 11 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza2.c | 519 +
3 files changed, 531 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-rza2.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4d8c00eac742..4c6e83ef716d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
+config PINCTRL_RZA2
+ bool "Renesas RZ/A2 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S9210 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
+
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 18a13c1e2c21..712184b74a5c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
new file mode 100644
index ..5b951c7422cc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
+ *
+ * Copyright (C) 2018 Chris Brandt
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
+ * family.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME"pinctrl-rza2"
+
+#define RZA2_PINS_PER_PORT 8
+#define RZA2_PIN_ID_TO_PORT(id)((id) / RZA2_PINS_PER_PORT)
+#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASKGENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+
+static const char port_names[] = "0123456789ABCDEFGHJKLM";
+
+struct rza2_pinctrl_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_gpio_range gpio_range;
+ int npins;
+};
+
+#define RZA2_PDR(port) (0x + (port) * 2) /* Direction 16-bit */
+#define RZA2_PODR(port)(0x0040 + (port)) /* Output Data
8-bit */
+#define RZA2_PIDR(port)(0x0060 + (port)) /* Input Data
8-bit */
+#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
[PATCH v7 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up reg range
* Changed 'should' to 'shall' because when there is only 1 in a list, you
have no choice but to choose it.
* Commented that Port M pins are also called JP_x in HW manual
* Fixed typos and grammar
* Added more Reviewed-by
v3:
* Added Reviewed-by
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID to RZA2_PIN
---
.../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 ++
include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47
2 files changed, 134 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
new file mode 100644
index ..a63ccd476cda
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
@@ -0,0 +1,87 @@
+Renesas RZ/A2 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
controller.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+Each port features up to 8 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+---
+
+Required properties:
+ - compatible: shall be:
+- "renesas,r7s9210-pinctrl": for RZ/A2M
+ - reg
+Address base and length of the memory area where the pin controller
+hardware is mapped to.
+ - gpio-controller
+This pin controller also controls pins as GPIO
+ - #gpio-cells
+Must be 2
+ - gpio-ranges
+Expresses the total number of GPIO ports/pins in this SoC
+
+Example: Pin controller node for RZ/A2M SoC (r7s9210)
+
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 176>;
+ };
+
+Sub-nodes
+-
+
+The child nodes of the pin controller designate pins to be used for
+specific peripheral functions or as GPIO.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name, pin
+ number and the desired function index. Use the RZA2_PINMUX macro located
+ in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
+ For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
+ to express the desired port pin.
+
+ Required properties:
+- pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 8 + PIN) | MUX_FUNC << 16)
+
+ Example: Board specific pins configuration
+
+{
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = ,/* TxD4 */
+;/* RxD4 */
+ };
+ };
+
+ Example: Assigning a GPIO:
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led0 {
+ /* P6_0 */
+ gpios = < RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
new file mode 100644
index ..2d0c23e5d3a7
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A2 pin controller pin
+ * muxing functions.
+ */
+#ifndef
Re: [PATCH] arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
On 11/15/2018 03:33 PM, Simon Horman wrote: > On Wed, Nov 14, 2018 at 04:32:05PM +0100, Marek Vasut wrote: >> On 11/13/2018 04:22 PM, Geert Uytterhoeven wrote: >>> Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function >>> on the Renesas Condor board. >>> >>> Signed-off-by: Geert Uytterhoeven >> >> This helps >> >> Reviewed-by: Marek Vasut > > Thanks, would it be better to use enable this driver as a module rather > than a built-in? I think not, since the pcie-rcar cannot be compiled in as module, so the associated phy driver shouldn't be compiled in as module either. >>> --- >>> arch/arm64/configs/defconfig | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >>> index 9d0b42d96f03156e..77f98a7e860b8850 100644 >>> --- a/arch/arm64/configs/defconfig >>> +++ b/arch/arm64/configs/defconfig >>> @@ -657,6 +657,7 @@ CONFIG_PHY_HISI_INNO_USB2=y >>> CONFIG_PHY_MVEBU_CP110_COMPHY=y >>> CONFIG_PHY_QCOM_QMP=m >>> CONFIG_PHY_QCOM_USB_HS=y >>> +CONFIG_PHY_RCAR_GEN3_PCIE=y >>> CONFIG_PHY_RCAR_GEN3_USB2=y >>> CONFIG_PHY_RCAR_GEN3_USB3=m >>> CONFIG_PHY_ROCKCHIP_EMMC=y >>> >> >> >> -- >> Best regards, >> Marek Vasut >> -- Best regards, Marek Vasut
Re: [PATCH 00/03] Connect R-Car Gen3 Ethernet-AVB to IPMMU
On Tue, Nov 13, 2018 at 04:20:23PM +0100, Geert Uytterhoeven wrote: > Hi Simon, > > On Tue, Nov 13, 2018 at 3:31 PM Simon Horman wrote: > > On Wed, Nov 07, 2018 at 12:21:16PM +0100, Simon Horman wrote: > > > On Mon, Oct 22, 2018 at 02:14:34AM +0900, Magnus Damm wrote: > > > > Connect R-Car Gen3 Ethernet-AVB to IPMMU > > > > > > > > [PATCH 01/03] arm64: dts: renesas: r8a77965: Connect R-Car M3-N AVB to > > > > IPMMU > > > > [PATCH 02/03] arm64: dts: renesas: r8a77980: Connect R-Car V3H AVB to > > > > IPMMU > > > > [PATCH 03/03] arm64: dts: renesas: r8a77990: Connect R-Car E3 AVB to > > > > IPMMU > > > > > > > > For each SoC describe Ethernet-AVB to IPMMU hardware connection in the > > > > Device Tree. This series affects R-Car M3-N, V3H and E3. Other members > > > > of the R-Car Gen3 family such as H3, M3-W, V3M and D3 already includes > > > > this information in their DT files. > > > > > > > > Signed-off-by: Magnus Damm > > > > > > Hi, > > > > > > I have already queued-up these patches but I noticed that > > > they do the same thing to different SoCs and recently the ARM-SoC > > > maintainers have asked us to consolidate such patches. With that in mind > > > I am considering squashing the three patches that comprise this series > > > into > > > one. Are there any objections? > > > > I have now gone ahead and done so. The result is as follows: > > > > From: Magnus Damm > > Subject: [PATCH] ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSI > > > > Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and > > SH-Mobile AG5 (sh72a0) DTSI to include product name. > > > > Signed-off-by: Magnus Damm > > [simon: squashed similar patches] > > Signed-off-by: Simon Horman > > Wrong email thread? Yes, oops.
Re: [PATCH] arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
On Wed, Nov 14, 2018 at 04:32:05PM +0100, Marek Vasut wrote: > On 11/13/2018 04:22 PM, Geert Uytterhoeven wrote: > > Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function > > on the Renesas Condor board. > > > > Signed-off-by: Geert Uytterhoeven > > This helps > > Reviewed-by: Marek Vasut Thanks, would it be better to use enable this driver as a module rather than a built-in? > > > --- > > arch/arm64/configs/defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > index 9d0b42d96f03156e..77f98a7e860b8850 100644 > > --- a/arch/arm64/configs/defconfig > > +++ b/arch/arm64/configs/defconfig > > @@ -657,6 +657,7 @@ CONFIG_PHY_HISI_INNO_USB2=y > > CONFIG_PHY_MVEBU_CP110_COMPHY=y > > CONFIG_PHY_QCOM_QMP=m > > CONFIG_PHY_QCOM_USB_HS=y > > +CONFIG_PHY_RCAR_GEN3_PCIE=y > > CONFIG_PHY_RCAR_GEN3_USB2=y > > CONFIG_PHY_RCAR_GEN3_USB3=m > > CONFIG_PHY_ROCKCHIP_EMMC=y > > > > > -- > Best regards, > Marek Vasut >
Re: [PATCH v2 2/2] arm64: dts: renesas: Add CPU capacity-dmips-mhz
On Wed, Nov 14, 2018 at 10:56:04AM +0100, Geert Uytterhoeven wrote: > Hi Inami-san, > > On Thu, Nov 8, 2018 at 8:25 AM Gaku Inami wrote: > > Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on > > dhrystone. The average in 10 times of dhrystone result as follows: > > [...] > > > Signed-off-by: Gaku Inami > > --- > > v1 -> v2: > > - Consolidate two patches for r8a7795 and r8a7796 into one patch > > - Add the formula for capacity-dmips-mhz into description > > Thanks for the update, and the extensive and clear description! > > Reviewed-by: Geert Uytterhoeven Thanks, applied for v4.21.
Re: [PATCH v2 1/2] arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
On Wed, Nov 14, 2018 at 10:50:03AM +0100, Geert Uytterhoeven wrote: > Hi Inami-san, > > On Thu, Nov 8, 2018 at 8:25 AM Gaku Inami wrote: > > This patch adds the "cpu-map" into r8a7795/r8a7796 composed of > > multi-cluster. This definition is used to parse the cpu topology. > > > > Signed-off-by: Gaku Inami > > Thanks for your patch! > > Next time, please collect tags provided by reviewers on the previous > version. > > Reviewed-by: Geert Uytterhoeven Thanks, applied for v4.21.
Re: [PATCH] ARM: shmobile: sh73a0: Remove obsolete inclusion of
On Thu, Nov 15, 2018 at 10:57:31AM +0100, Geert Uytterhoeven wrote:
> As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code
> for SH-Mobile AG5"), this header file is no longer used.
>
> Signed-off-by: Geert Uytterhoeven
Thanks Geert,
applied for v4.21.
Re: [PATCH 1/2] ARM: shmobile: Restrict SCU support to SoCs that have it
On Thu, Nov 15, 2018 at 10:56:38AM +0100, Geert Uytterhoeven wrote: > Currently support for the ARM Cortex-A9 Snoop Control Unit is included > unconditionally, while only Renesas multicore Cortex-A9 SoCs have this > kind of SCU. > > This decreases kernel image size by ca. 300 bytes on SoCs without such > an SCU. > > Signed-off-by: Geert Uytterhoeven Thanks Geert, applied for v4.21.
Re: [PATCH 2/2] ARM: shmobile: Restrict TWD support to SoCs that have it
On Thu, Nov 15, 2018 at 10:56:39AM +0100, Geert Uytterhoeven wrote: > Currently support for the ARM Timer and Watchdog Unit is included > unconditionally, while only some Renesas multicore Cortex-A9 SoCs have > a TWD. > > This decreases kernel image size by ca. 2 KiB on SoCs without a TWD. > > Signed-off-by: Geert Uytterhoeven Thanks Geert, applied for v4.21.
Re: [PATCH] arm64: renesas: Enable GPIOLIB to allow GPIO driver selection
On Thu, Nov 15, 2018 at 10:46:49AM +0100, Geert Uytterhoeven wrote: > From: Takeshi Kihara > > The R-Car GPIO driver cannot be enabled when Renesas SoC's ARCH configs > (ARCH_RENESAS, ARCH_R8A7795, ARCH_R8A7796 and ARCH_R8A77965) are enabled > only. > > As GPIOs are a critical resource for proper operation on Renesas > platforms, this patch selects GPIOLIB, just like is done for other SoC > vendors, and on Renesas arm32 SoCs. > > Reported-by: Alexandru Gheorghe > Signed-off-by: Takeshi Kihara > [geert: Improve patch description] > Signed-off-by: Geert Uytterhoeven Thanks Geert, applied for v4.21.
[PATCH v6 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
* Use priv->npins everywhere instead of hard coded RZA2_NPINS
* Check gpio-ranges to make sure args matches SOC
v4:
* Mention GPIO in Kconfig
* Removed port enum and just define RZA2_NPORTS
* Moved gpio_range from global to private data
* Condensed and simplify register macros
* Added register bit definitions to remove magic numbers
* Reverse Christmas Tree style for local variables
* rza2_pin_to_gpio now takes 'offset' instead of 'port' and 'pin'
* Use !! to return 0 or 1 for rza2_chip_get
* Removed check for gpio-controller since dt-bindings say it's mandatory
* Reuse rza2_gpio_names[] for pins[i].name since it's the same strings
* Use %pOF for printing DT node names
* Use dev_err for "Unable to parse DT node" message
* Changed pr_info to dev_info for message at the end of probe
* Changed probe message to print out what ports were registered
* Removed extra newlines
* Added Reviewed-by
v3:
* Changed names from Px to PORTx because "PC" is already defined
v2:
* fixed SOC part number in comments
* sorted #includes
* removed spaces in pfc_pin_port_name enum
* put RZA2_NPORTS at the end of pfc_pin_port_name enum
* added RZA2_ to the beginning of all #define macros
* put ( ) around all passed arguments in #define macros
* made helper macros to get register address easier
* use defines for pin direction bit settings
---
drivers/pinctrl/Kconfig| 11 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza2.c | 518 +
3 files changed, 530 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-rza2.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4d8c00eac742..4c6e83ef716d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
+config PINCTRL_RZA2
+ bool "Renesas RZ/A2 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S9210 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
+
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 18a13c1e2c21..712184b74a5c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
new file mode 100644
index ..f05da0ef0793
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
+ *
+ * Copyright (C) 2018 Chris Brandt
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
+ * family.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "core.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME"pinctrl-rza2"
+
+#define RZA2_PINS_PER_PORT 8
+#define RZA2_PIN_ID_TO_PORT(id)((id) / RZA2_PINS_PER_PORT)
+#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASKGENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+
+static const char port_names[] = "0123456789ABCDEFGHJKLM";
+
+struct rza2_pinctrl_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_gpio_range gpio_range;
+ int npins;
+};
+
+#define RZA2_PDR(port) (0x + (port) * 2) /* Direction 16-bit */
+#define RZA2_PODR(port)(0x0040 + (port)) /* Output Data
8-bit */
+#define RZA2_PIDR(port)(0x0060 + (port)) /* Input Data
8-bit */
+#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
+#define RZA2_DSCR(port)(0x0140 + (port) * 2) /* Drive
[PATCH v6 0/2] pinctrl: Add RZ/A2 pin and gpio driver
The pin controller in the RZ/A2 is nothing like the pin controller in the RZ/A1. That's a good thing! This pin controller is much more simple and easier to configure. So, this driver is faily simple (I hope). Chris Brandt (2): pinctrl: Add RZ/A2 pin and gpio controller dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 drivers/pinctrl/Kconfig| 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rza2.c | 518 + include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 ++ 5 files changed, 664 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-rza2.c create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h -- 2.16.1
[PATCH v6 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up reg range
* Changed 'should' to 'shall' because when there is only 1 in a list, you
have no choice but to choose it.
* Commented that Port M pins are also called JP_x in HW manual
* Fixed typos and grammar
* Added more Reviewed-by
v3:
* Added Reviewed-by
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID to RZA2_PIN
---
.../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 ++
include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47
2 files changed, 134 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
new file mode 100644
index ..a63ccd476cda
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
@@ -0,0 +1,87 @@
+Renesas RZ/A2 combined Pin and GPIO controller
+
+The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
controller.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis.
+Each port features up to 8 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+---
+
+Required properties:
+ - compatible: shall be:
+- "renesas,r7s9210-pinctrl": for RZ/A2M
+ - reg
+Address base and length of the memory area where the pin controller
+hardware is mapped to.
+ - gpio-controller
+This pin controller also controls pins as GPIO
+ - #gpio-cells
+Must be 2
+ - gpio-ranges
+Expresses the total number of GPIO ports/pins in this SoC
+
+Example: Pin controller node for RZ/A2M SoC (r7s9210)
+
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 176>;
+ };
+
+Sub-nodes
+-
+
+The child nodes of the pin controller designate pins to be used for
+specific peripheral functions or as GPIO.
+
+- Pin multiplexing sub-nodes:
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name, pin
+ number and the desired function index. Use the RZA2_PINMUX macro located
+ in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
+ For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
+ to express the desired port pin.
+
+ Required properties:
+- pinmux:
+ integer array representing pin number and pin multiplexing configuration.
+ When a pin has to be configured in alternate function mode, use this
+ property to identify the pin by its global index, and provide its
+ alternate function configuration number along with it.
+ When multiple pins are required to be configured as part of the same
+ alternate function they shall be specified as members of the same
+ argument list of a single "pinmux" property.
+ Helper macros to ease assembling the pin index from its position
+ (port where it sits on and pin number) and alternate function identifier
+ are provided by the pin controller header file at:
+
+ Integers values in "pinmux" argument list are assembled as:
+ ((PORT * 8 + PIN) | MUX_FUNC << 16)
+
+ Example: Board specific pins configuration
+
+{
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = ,/* TxD4 */
+;/* RxD4 */
+ };
+ };
+
+ Example: Assigning a GPIO:
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led0 {
+ /* P6_0 */
+ gpios = < RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
new file mode 100644
index ..2d0c23e5d3a7
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A2 pin controller pin
+ * muxing functions.
+ */
+#ifndef
RE: [PATCH v2] gpio: rcar: Request GPIO while enabling interrupt
Hello Geert, Thank you for your feedback! > From: Geert Uytterhoeven > Sent: 14 November 2018 12:52 > Subject: Re: [PATCH v2] gpio: rcar: Request GPIO while enabling interrupt > > Hi Fabrizio, > > On Tue, Nov 6, 2018 at 8:19 PM Fabrizio Castro > wrote: > > There are cases when the bootloader configures a pin to work > > as a function rather than GPIO, and other cases when the pin > > is configured as a function at POR. > > This commit makes sure the pin is configured as a GPIO the > > moment we need it to work as an interrupt. > > > > Signed-off-by: Fabrizio Castro > > > > --- > > v1->v2: > > * Moved gpio_rcar_request call from gpio_rcar_irq_set_type to > > rcar_gpio_irq_request_resources > > * Added rcar_gpio_irq_release_resources for calling gpio_rcar_free > > Thanks for your patch! > > While I could see no obvious deficiencies at first glance, I gave your > patch a try on Koelsch and Salvator-XS. Thank you for testing the patch! These issues seem to be related to a few patches that were merged only recently, I have rebased my work on top of the next-20181115 now, and I get the same thing. I need to look into this from scratch again, I'll be in touch as soon as I have found an alternative way to fix the issue. Thanks, Fab > > Koelsch: > > - ADV7511 HDMI encoder WARN_ON(!test_bit(FLAG_USED_AS_IRQ, >flags) > in gpiochip_enable_irq(): > > WARNING: CPU: 0 PID: 1 at drivers/gpio/gpiolib.c:3513 > gpiochip_irq_enable+0x18/0x34 > Modules linked in: > CPU: 0 PID: 1 Comm: swapper/0 Not tainted > 4.20.0-rc2-koelsch-00873-gf433e294a90792da-dirty #179 > Hardware name: Generic R-Car Gen2 (Flattened Device Tree) > [] (unwind_backtrace) from [] (show_stack+0x10/0x14) > [] (show_stack) from [] (dump_stack+0x7c/0x9c) > [] (dump_stack) from [] (__warn+0xd0/0xec) > [] (__warn) from [] (warn_slowpath_null+0x38/0x44) > [] (warn_slowpath_null) from [] > (gpiochip_irq_enable+0x18/0x34) > [] (gpiochip_irq_enable) from [] > (irq_enable+0x3c/0x50) > [] (irq_enable) from [] (__irq_startup+0x94/0xa4) > [] (__irq_startup) from [] (irq_startup+0x4c/0x11c) > [] (irq_startup) from [] (__setup_irq+0x4d0/0x6a4) > [] (__setup_irq) from [] > (request_threaded_irq+0x9c/0x134) > [] (request_threaded_irq) from [] > (devm_request_threaded_irq+0x68/0xa4) > [] (devm_request_threaded_irq) from [] > (adv7511_probe+0x748/0x860) > [] (adv7511_probe) from [] > (i2c_device_probe+0x210/0x228) > [] (i2c_device_probe) from [] > (really_probe+0x1f0/0x2c0) > [] (really_probe) from [] > (driver_probe_device+0x140/0x15c) > [] (driver_probe_device) from [] > (bus_for_each_drv+0xa0/0xb4) > [] (bus_for_each_drv) from [] > (__device_attach+0xb0/0x124) > [] (__device_attach) from [] > (bus_probe_device+0x28/0x80) > [] (bus_probe_device) from [] (device_add+0x438/0x570) > [] (device_add) from [] (i2c_new_device+0x238/0x278) > [] (i2c_new_device) from [] > (of_i2c_register_device+0x40/0x80) > [] (of_i2c_register_device) from [] > (of_i2c_register_devices+0x80/0xc0) > [] (of_i2c_register_devices) from [] > (i2c_register_adapter+0x1ec/0x390) > [] (i2c_register_adapter) from [] > (i2c_demux_activate_master+0xd4/0x158) > [] (i2c_demux_activate_master) from [] > (i2c_demux_pinctrl_probe+0x190/0x1f0) > [] (i2c_demux_pinctrl_probe) from [] > (platform_drv_probe+0x48/0x94) > [] (platform_drv_probe) from [] > (really_probe+0x1f0/0x2c0) > [] (really_probe) from [] > (driver_probe_device+0x140/0x15c) > [] (driver_probe_device) from [] > (__driver_attach+0x8c/0xc8) > [] (__driver_attach) from [] > (bus_for_each_dev+0x64/0xa0) > [] (bus_for_each_dev) from [] > (bus_add_driver+0x16c/0x1d4) > [] (bus_add_driver) from [] > (driver_register+0xac/0xf0) > [] (driver_register) from [] > (do_one_initcall+0x70/0x170) > [] (do_one_initcall) from [] > (kernel_init_freeable+0x194/0x1d8) > [] (kernel_init_freeable) from [] > (kernel_init+0x8/0x110) > [] (kernel_init) from [] (ret_from_fork+0x14/0x3c) > Exception stack(0xeb44dfb0 to 0xeb44dff8) > dfa0: > > dfc0: > > dfe0: 0013 > > - SDHI CD pin failure (first channel shown only): > > sh-pfc e606.pin-controller: pin GP_6_6 already requested by > e6055400.gpio:812; cannot claim for e6055400.gpio:812 > sh-pfc e606.pin-controller: pin-198 (e6055400.gpio:812) status -2
RE: [PATCH 2/3] phy: renesas: rcar-gen3-usb2: Add support for R7S9210
Hi Shimodaさん > From: Yoshihiro Shimoda > Sent: Thursday, November 15, 2018 4:20 AM > > Host does NOT work: > > //else > > // /* No otg, so default to host mode */ > > // writel(0x, usb2_base + USB2_COMMCTRL); > > I got it. However, I have a concern how to set the mode to peripheral on > RZ/A2 > if we applied this code. If someone would like to use the USB as > peripheral > on his board, this code is not suitable. But USB peripheral is a different driver. So, this code will not run. So USB2_COMMCTRL will keep the default value 0x8000. Correct? > So, I have an idea to set the default mode by using "dr_mode" property, > instead of hardcoded. Since the driver already has such a function, > we can reuse rcar_gen3_device_recognition() to set the default value. > To achieve that, we need to modify the following though. > - Don't enable "is_otg_channel". > - Don't call rcar_gen3_enable_vbus_ctrl() to avoid ADPCTRL register >because RZ/A2 doesn't have it. > - Don't need to call rcar_gen3_set_linectrl to avoid LINECTRL1 register >because RZ/A2 doesn't seem to need the setting on host mode. > > What do you think? If a board is designed for USB peripheral, why would they enable a EHCI host driver for the same USB channel? I am confused. > > > (In other words, if we use the port as peripheral with the reset value > > > 0x8000, does it work?) > > > > We have not been able to get USB peripheral working on RZ/A2 yet. > > For peripheral, RZ/A2 has HS-USB. > > After plugging into the PC, HS-USB goes to Suspended state (DVSQ = > "0110"). > > It should go to Configured state (DVSQ = "0011") > > I guess we need to modify ./drivers/usb/renesas_usbhs/rza.c for RZ/A2 > because RZ/A2's HS-USB has SYSCFG.CNEN, but doesn't have SYSCFG.UPLLE? Today for RZ/A1, we tell people to use USB0 first in their board design, then use USB1 if they need a second USB channel. USB pins are dedicated (no other function) so there should be no design conflicts. If only USB1 is used, USB0 must also be enabled in DT as a dummy driver (so SYSCFG.UPLLE can get set for USB1). > > According to the RZ/A2 Hardware Manual, COMMCTRL should be 0x8000 > when > > using HS-USB. > > > > There are 2 channels of USB on RZ/A2 (host x 2, HS_USB x 2) > > I got it. So, I guess someone wants to use 1 host and 1 peripheral :) Yes. Chris
RE: [PATCH v4 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Hi Geert, On Thursday, November 15, 2018, Geert Uytterhoeven wrote: > > As for validating the values, the only thing I can really check is that: > > of_args.args[2] == RZA2_NPINS > > > > Of course, now that I say that, I realize that if/when it does come time > > to expand this driver beyond the 1 SOC that exists today, I will have > > to stop using that hard coded RZA2_NPINS value...but I'll deal with that > > when the time comes. > > Not that there is an inherent danger in taking of_args.args[2] without > validation to support future SoCs without driver changes. > port_names[] is a fixed size array, so an SoC with more pins will > cause memory access beyond the end of the array. Possibly there are > other locations that need to be changed. > > So IMHO it's better to have explicit support for different SoCs using > different compatible values, so you can store the number of pins in > of_device_id.data, and validate against that. I will fill in of_device_id.data with the number of ports for each SOC (only 1 SOC today) and then use that number throughout the driver instead of the hard coded number. I'll also check that of_args.args[2] matches of_device_id.data. Then, it should be real easy to add support for another SOC when it comes along. RZ/T1 which has the same controller has ports up to Port "U" for example. Chris
[PATCH resend] dt-bindings: dmaengine: usb-dmac: Add binding for r8a774a1
From: Biju Das This patch adds binding for r8a774a1 (RZ/G2M). Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Acked-by: Vinod Koul Reviewed-by: Simon Horman Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index a1e7b814..5e2c7e8 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,r8a7744-usb-dmac" (RZ/G1N) - "renesas,r8a7745-usb-dmac" (RZ/G1E) - "renesas,r8a77470-usb-dmac" (RZ/G1C) + - "renesas,r8a774a1-usb-dmac" (RZ/G2M) - "renesas,r8a7790-usb-dmac" (R-Car H2) - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - "renesas,r8a7793-usb-dmac" (R-Car M2-N) -- 2.7.4
[PATCH resend] dmaengine: rcar-dmac: Document R8A774A1 bindings
Renesas' RZ/G2M (R8A774A1) SoC has DMA controllers compatible with this driver, therefore document RZ/G2M specific bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Simon Horman --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index a5a7c3f..cdf32b2 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -1,6 +1,6 @@ * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings -Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA +Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA controller instances named DMAC capable of serving multiple clients. Channels can be dedicated to specific clients or shared between a large number of clients. @@ -20,6 +20,7 @@ Required Properties: - "renesas,dmac-r8a7744" (RZ/G1N) - "renesas,dmac-r8a7745" (RZ/G1E) - "renesas,dmac-r8a77470" (RZ/G1C) + - "renesas,dmac-r8a774a1" (RZ/G2M) - "renesas,dmac-r8a7790" (R-Car H2) - "renesas,dmac-r8a7791" (R-Car M2-W) - "renesas,dmac-r8a7792" (R-Car V2H) -- 2.7.4
[PATCH 2/2] ARM: shmobile: Restrict TWD support to SoCs that have it
Currently support for the ARM Timer and Watchdog Unit is included unconditionally, while only some Renesas multicore Cortex-A9 SoCs have a TWD. This decreases kernel image size by ca. 2 KiB on SoCs without a TWD. Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 32f8297d993ac10e..a35eb5913dfdf4ba 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -30,7 +30,6 @@ menuconfig ARCH_RENESAS depends on ARCH_MULTI_V7 && MMU select ARM_GIC select GPIOLIB - select HAVE_ARM_TWD if SMP select NO_IOPORT_MAP select PINCTRL select SOC_BUS @@ -95,6 +94,7 @@ config ARCH_R8A7778 config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP select ARCH_RCAR_GEN1 config ARCH_R8A7790 @@ -137,5 +137,6 @@ config ARCH_SH73A0 bool "SH-Mobile AG5 (R8A73A00)" select ARCH_RMOBILE select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP select RENESAS_INTC_IRQPIN endif -- 2.17.1
[PATCH 0/2] ARM: shmobile: Restrict SCU/TWD support to SoCs that have it
Hi Simon, Magnus,
When Renesas ARM multi-platform support was conceived in commit
efacfce5f8a52345 ("ARM: shmobile: Introduce ARCH_SHMOBILE_MULTI"),
support for the ARM Cortex-A9 Snoop Control Unit and the Timer and
Watchdog Unit was enabled unconditionally.
However, only some Renesas multicore Cortex-A9 SoCs have these units,
and in the modern world, the share of Cortex-A9 SoCs is decreasing.
Hence only enable support for the SCU and TWD when building a kernel
that includes support for SoCs that have these units.
Thanks!
Geert Uytterhoeven (2):
ARM: shmobile: Restrict SCU support to SoCs that have it
ARM: shmobile: Restrict TWD support to SoCs that have it
arch/arm/mach-shmobile/Kconfig | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH] arm64: renesas: Enable GPIOLIB to allow GPIO driver selection
From: Takeshi Kihara The R-Car GPIO driver cannot be enabled when Renesas SoC's ARCH configs (ARCH_RENESAS, ARCH_R8A7795, ARCH_R8A7796 and ARCH_R8A77965) are enabled only. As GPIOs are a critical resource for proper operation on Renesas platforms, this patch selects GPIOLIB, just like is done for other SoC vendors, and on Renesas arm32 SoCs. Reported-by: Alexandru Gheorghe Signed-off-by: Takeshi Kihara [geert: Improve patch description] Signed-off-by: Geert Uytterhoeven --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 51bc479334a43f5d..2eb02734ae4575a0 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -157,6 +157,7 @@ config ARCH_REALTEK config ARCH_RENESAS bool "Renesas SoC Platforms" + select GPIOLIB select PINCTRL select PM select PM_GENERIC_DOMAINS -- 2.17.1
[PATCH] ARM: OMAP2+: timer: Remove obsolete inclusion of
As of commit d1dabab2841d546f ("ARM: OMAP2+: Clean up
omap4_local_timer_init"), this header file is no longer used.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-omap2/timer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 98ed5ac073bc1fca..07bea84c5d6e4f2a 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -44,7 +44,6 @@
#include
#include
-#include
#include "omap_hwmod.h"
#include "omap_device.h"
--
2.17.1
[PATCH] ARM: shmobile: sh73a0: Remove obsolete inclusion of
As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code
for SH-Mobile AG5"), this header file is no longer used.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/smp-sh73a0.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c
b/arch/arm/mach-shmobile/smp-sh73a0.c
index 9bc543faba96af6e..0403aa8629ddc10a 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -12,7 +12,6 @@
#include
#include
-#include
#include "common.h"
#include "sh73a0.h"
--
2.17.1
[PATCH 1/2] ARM: shmobile: Restrict SCU support to SoCs that have it
Currently support for the ARM Cortex-A9 Snoop Control Unit is included unconditionally, while only Renesas multicore Cortex-A9 SoCs have this kind of SCU. This decreases kernel image size by ca. 300 bytes on SoCs without such an SCU. Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index b100c26a858f9015..32f8297d993ac10e 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -30,7 +30,6 @@ menuconfig ARCH_RENESAS depends on ARCH_MULTI_V7 && MMU select ARM_GIC select GPIOLIB - select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select NO_IOPORT_MAP select PINCTRL @@ -43,6 +42,7 @@ if ARCH_RENESAS config ARCH_EMEV2 bool "Emma Mobile EV2" + select HAVE_ARM_SCU if SMP select SYS_SUPPORTS_EM_STI config ARCH_R7S72100 @@ -94,6 +94,7 @@ config ARCH_R8A7778 config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" + select HAVE_ARM_SCU if SMP select ARCH_RCAR_GEN1 config ARCH_R8A7790 @@ -135,5 +136,6 @@ config ARCH_RZN1 config ARCH_SH73A0 bool "SH-Mobile AG5 (R8A73A00)" select ARCH_RMOBILE + select HAVE_ARM_SCU if SMP select RENESAS_INTC_IRQPIN endif -- 2.17.1
RE: [PATCH 2/2] arm64: dts: renesas: r8a774a1: Replace clock magic numbers
Thank you Geert for spotting the issue, thank you Simon for fixing.
Cheers,
Fab
> From: Simon Horman
> Sent: 13 November 2018 14:46
> Subject: Re: [PATCH 2/2] arm64: dts: renesas: r8a774a1: Replace clock magic
> numbers
>
> On Tue, Nov 13, 2018 at 09:53:55AM +0100, Geert Uytterhoeven wrote:
> > On Wed, Nov 7, 2018 at 4:24 PM Fabrizio Castro
> > wrote:
> > > Now that include/dt-bindings/clock/r8a774a1-cpg-mssr.h is in Linus'
> > > master branch we can replace clock related magic numbers with the
> > > corresponding labels.
> > >
> > > Signed-off-by: Fabrizio Castro
> >
> > Reviewed-by: Geert Uytterhoeven
> >
> > > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> >
> > > @@ -87,7 +87,7 @@
> > > power-domains = < R8A774A1_PD_CA53_CPU0>;
> > > next-level-cache = <_CA53>;
> > > enable-method = "psci";
> > > - clocks =< CPG_CORE 1>;
> > > + clocks =< CPG_CORE R8A774A1_CLK_Z2>;
> >
> > There are a few pre-existing whitespace issues in the CPU nodes' clocks
> > properties.
>
> Thanks I have fixed that when applying this patch for v4.21.
> The result is as follows:
>
> From: Fabrizio Castro
> Subject: [PATCH] arm64: dts: renesas: r8a774a1: Replace clock magic numbers
>
> Now that include/dt-bindings/clock/r8a774a1-cpg-mssr.h is in Linus'
> master branch we can replace clock related magic numbers with the
> corresponding labels.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Geert Uytterhoeven
> [simon: corrected whitespace]
> Signed-off-by: Simon Horman
> ---
> arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38
> +++
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index d549755a4025..20745a8528c5 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -7,7 +7,7 @@
>
> #include
> #include
> -#include
> +#include
> #include
>
> / {
> @@ -67,7 +67,7 @@
> power-domains = < R8A774A1_PD_CA57_CPU0>;
> next-level-cache = <_CA57>;
> enable-method = "psci";
> -clocks = < CPG_CORE 0>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z>;
> };
>
> a57_1: cpu@1 {
> @@ -77,7 +77,7 @@
> power-domains = < R8A774A1_PD_CA57_CPU1>;
> next-level-cache = <_CA57>;
> enable-method = "psci";
> -clocks = < CPG_CORE 0>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z>;
> };
>
> a53_0: cpu@100 {
> @@ -87,7 +87,7 @@
> power-domains = < R8A774A1_PD_CA53_CPU0>;
> next-level-cache = <_CA53>;
> enable-method = "psci";
> -clocks =< CPG_CORE 1>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z2>;
> };
>
> a53_1: cpu@101 {
> @@ -97,7 +97,7 @@
> power-domains = < R8A774A1_PD_CA53_CPU1>;
> next-level-cache = <_CA53>;
> enable-method = "psci";
> -clocks =< CPG_CORE 1>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z2>;
> };
>
> a53_2: cpu@102 {
> @@ -107,7 +107,7 @@
> power-domains = < R8A774A1_PD_CA53_CPU2>;
> next-level-cache = <_CA53>;
> enable-method = "psci";
> -clocks =< CPG_CORE 1>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z2>;
> };
>
> a53_3: cpu@103 {
> @@ -117,7 +117,7 @@
> power-domains = < R8A774A1_PD_CA53_CPU3>;
> next-level-cache = <_CA53>;
> enable-method = "psci";
> -clocks =< CPG_CORE 1>;
> +clocks = < CPG_CORE R8A774A1_CLK_Z2>;
> };
>
> L2_CA57: cache-controller-0 {
> @@ -515,7 +515,7 @@
> reg = <0 0xe654 0 0x60>;
> interrupts = ;
> clocks = < CPG_MOD 520>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x31>, < 0x30>,
> @@ -533,7 +533,7 @@
> reg = <0 0xe655 0 0x60>;
> interrupts = ;
> clocks = < CPG_MOD 519>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x33>, < 0x32>,
> @@ -551,7 +551,7 @@
> reg = <0 0xe656 0 0x60>;
> interrupts = ;
> clocks = < CPG_MOD 518>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x35>, < 0x34>,
> @@ -569,7 +569,7 @@
> reg = <0 0xe66a 0 0x60>;
> interrupts = ;
> clocks = < CPG_MOD 517>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x37>, < 0x36>;
> @@ -586,7 +586,7 @@
> reg = <0 0xe66b 0 0x60>;
> interrupts = ;
> clocks = < CPG_MOD 516>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x39>, < 0x38>;
> @@ -974,7 +974,7 @@
> reg = <0 0xe6e6 0 0x40>;
> interrupts = ;
> clocks = < CPG_MOD 207>,
> - < CPG_CORE 19>,
> + < CPG_CORE R8A774A1_CLK_S3D1>,
> <_clk>;
> clock-names = "fck", "brg_int", "scif_clk";
> dmas = < 0x51>, < 0x50>,
> @@ -991,7 +991,7 @@
> reg = <0 0xe6e68000 0 0x40>;
> interrupts = ;
> clocks =
RE: [PATCH 2/3] phy: renesas: rcar-gen3-usb2: Add support for R7S9210
Hi Chris-san, > From: Chris Brandt, Sent: Wednesday, November 14, 2018 10:03 PM > > Hi Shimoda-san, > > > From: Yoshihiro Shimoda > > Sent: Wednesday, November 14, 2018 7:24 AM > > > > > config PHY_RCAR_GEN3_USB2 > > > > > tristate "Renesas R-Car generation 3 USB 2.0 PHY driver" > > > > > depends on ARCH_RENESAS > > > > > - depends on EXTCON > > > > > + depends on EXTCON || ARCH_R7S9210 > > > > > > > > Does this mean that you don't want to use EXTCON if ARCH_R7S9210=y? > > > > > > EXTCON is not required for RZ/A2. So, I want to be able to leave EXTCON > > > un-selected (save flash space). > > > > I got it. > > I added the depend on EXTCON, but R-Car Gen3 environment can build > > EXTCON=n. > > However, I realized that build error happens if EXTCON=m. > > So, I think we have to revise this line as following at first: > > > > "depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in" > > like drivers/phy/qualcomm/Kconfig. > > OK. I will change it. > >(should this be a separate patch?) Yes, this should be a separate patch. > > > Without this code, RZ/A2 will not work. > > > > I'd like to clarify this. Does this mean RZ/A2 will not work as host mode? > > Correct. If I remove 'else' code, RZ/A2 host mode does not work. > I just tested again now. > > Host works: > else > /* No otg, so default to host mode */ > writel(0x, usb2_base + USB2_COMMCTRL); > > Host does NOT work: > //else > // /* No otg, so default to host mode */ > // writel(0x, usb2_base + USB2_COMMCTRL); I got it. However, I have a concern how to set the mode to peripheral on RZ/A2 if we applied this code. If someone would like to use the USB as peripheral on his board, this code is not suitable. So, I have an idea to set the default mode by using "dr_mode" property, instead of hardcoded. Since the driver already has such a function, we can reuse rcar_gen3_device_recognition() to set the default value. To achieve that, we need to modify the following though. - Don't enable "is_otg_channel". - Don't call rcar_gen3_enable_vbus_ctrl() to avoid ADPCTRL register because RZ/A2 doesn't have it. - Don't need to call rcar_gen3_set_linectrl to avoid LINECTRL1 register because RZ/A2 doesn't seem to need the setting on host mode. What do you think? > > (In other words, if we use the port as peripheral with the reset value > > 0x8000, does it work?) > > We have not been able to get USB peripheral working on RZ/A2 yet. > For peripheral, RZ/A2 has HS-USB. > After plugging into the PC, HS-USB goes to Suspended state (DVSQ = "0110"). > It should go to Configured state (DVSQ = "0011") I guess we need to modify ./drivers/usb/renesas_usbhs/rza.c for RZ/A2 because RZ/A2's HS-USB has SYSCFG.CNEN, but doesn't have SYSCFG.UPLLE? > According to the RZ/A2 Hardware Manual, COMMCTRL should be 0x8000 when > using HS-USB. > > There are 2 channels of USB on RZ/A2 (host x 2, HS_USB x 2) I got it. So, I guess someone wants to use 1 host and 1 peripheral :) Best regards, Yoshihiro Shimoda > Chris
