Re: [PATCH 2/2] clk: renesas: rcar-gen3: add HS400 quirk for SD clock
Hi Geert,
On 2018-11-28 19:02:33 +0100, Niklas Söderlund wrote:
> Hi Geert,
>
> Thanks for your feedback.
>
> On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> > Hi Niklas,
> >
> > On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> > wrote:
> > > On 2018-11-05 11:43:24 +0100, Geert Uytterhoeven wrote:
> > > > On Thu, Nov 1, 2018 at 12:26 AM Niklas Söderlund
> > > > wrote:
> > > > > From: Niklas Söderlund
> > > > >
> > > > > On H3 (ES1.0,ES2.0) and M3-W (ES1.0,ES1.1) the clock setting for HS400
> > > >
> > > > H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1)
> > >
> > > Thanks.
> > >
> > > >
> > > > > needs a quirk to function properly. The reason for the quirk is that
> > > > > there are two settings which produces same divider vale for the SDn
> > > > > clock. On the effected boards the one currently selected results in
> > > > > HS00
> > > >
> > > > HS200 or HS400?
> > >
> > > Wops, HS400 :-)
> > >
> > > >
> > > > > not working.
> > > > >
> > > > > This change uses the same method as the Gen2 CPG driver and simply
> > > > > ignores the first clock setting as this is the offending one when
> > > > > selecting the settings. Which of the two possible settings is used
> > > > > have
> > > > > no effect for SDR104.
> > > > >
> > > > > Signed-off-by: Niklas Söderlund
> > > > >
> > > > > ---
> > > > > drivers/clk/renesas/rcar-gen3-cpg.c | 28 ++--
> > > > > 1 file changed, 22 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > > b/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > > index ff56ac6134111c38..8cc524a29c855dd2 100644
> > > > > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> >
> > > > > @@ -377,6 +382,7 @@ static struct clk * __init
> > > > > cpg_sd_clk_register(const struct cpg_core_clk *core,
> > > > > clock->hw.init =
> > > > > clock->div_table = cpg_sd_div_table;
> > > > > clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
> > > > > + clock->skip_first = skip_first;
> > > >
> > > > What about
> > > >
> > > > if (cpg_quirks & SD_SKIP_FIRST) {
> > > > clock->div_table++;
> > > > clock->div_num--;
> > > > }
> > > >
> > > > instead?
> > >
> > > This was my first approach as well, unfortunately it won't work :-(
> > >
> > > If the bootloader leaves the clock settings in a state which matches the
> > > first row in the table the clock fails to register as the check in
> > > cpg_sd_clk_register() makes sure it have a row for the state the
> > > hardware is in. If it can't find that state the clock fails to register.
> > > Whit this quirk the limitation of the effected boards only have an
> > > effect when setting the clock.
> >
> > IC...
> >
> > > I thought this solution solved this quiet neatly with the robustness
> > > principle, 'Be conservative in what you do, be liberal in what you
> > > accept from others' :-)
> >
> > Will it ever use the settings as inherited from boot loader or reset state?
> > If it does, I assume it will fail badly, due to an inconsistency between the
> > SD and SDH clock rates?
> > And what if the kernel is ever booted when the SDnSRCFC or SDnFC field
> > has an invalid value? Then the driver will fail, too?
> >
> > Hence, isn't it safer to initialize the registers to a known safe value?
>
> I agree with you that we should not trust the value fro the bootloader
> and the sdhi driver do not trust this and resets it. The problem is
> rcar-gen3-cpg. From cpg_sd_clk_register()
>
> sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
> for (i = 0; i < clock->div_num; i++)
> if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
> break;
>
> if (WARN_ON(i >= clock->div_num)) {
> kfree(clock);
> return ERR_PTR(-EINVAL);
> }
>
> clock->cur_div_idx = i;
>
> If the bootloader sets the register to a value not known by the clock
> driver or if we us the moth you prefer to modify clock->div_table and
> clock->div_num the clock driver would need to set a safe default. I
> think this would be fine as the SDHI driver could handle this (I need to
> test it tho). My proposal is therefor that I add a patch to this series
> where the clock driver try to set a known divider when it registers the
> clock.
>
> My suggestion would be that the divider to be set to 4 as this appears
> to be what current boot loaders do. Would this work for you?
I have now created a patch which do almost this [1]. But instead of
setting the divider to 4 just use the first row of clock->div_table and
make sure the clock is stopped. Any user of the clock needs to set the
rate it expects before enabling the clock. I tested this on H3 ES1 and
ES2 and M3-N and it works just fine.
1. [PATCH] clk: renesas: rcar-gen3: set state when registering SD clocks
--
Regards,
Niklas Söderlund
[PATCH v2 1/2] clk: renesas: rcar-gen3: add documentation for SD clocks
Document the known use cases of the different clock settings. This is
useful as different SoC and ES versions uses different settings to do
the same thing as there are more then one combination to achieve the
same SDn clock speed.
Signed-off-by: Niklas Söderlund
Reviewed-by: Wolfram Sang
---
drivers/clk/renesas/rcar-gen3-cpg.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index f6335357c85505df..bca6c7f51de18db7 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -232,13 +232,13 @@ struct sd_clock {
* sd_srcfc sd_fc div
* stp_hck stp_ck(div) (div) = sd_srcfc x sd_fc
*---
- * 0 0 0 (1) 1 (4) 4
- * 0 0 1 (2) 1 (4) 8
- * 1 0 2 (4) 1 (4) 16
- * 1 0 3 (8) 1 (4) 32
+ * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8
TAP)
+ * 0 0 1 (2) 1 (4) 8 : SDR50
+ * 1 0 2 (4) 1 (4) 16 : HS / SDR25
+ * 1 0 3 (8) 1 (4) 32 : NS / SDR12
* 1 0 4 (16) 1 (4) 64
* 0 0 0 (1) 0 (2) 2
- * 0 0 1 (2) 0 (2) 4
+ * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4
TAP)
* 1 0 2 (4) 0 (2) 8
* 1 0 3 (8) 0 (2) 16
* 1 0 4 (16) 0 (2) 32
--
2.19.1
[PATCH v2 2/2] clk: renesas: rcar-gen3: add HS400 quirk for SD clock
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.
This change uses the same method as the Gen2 CPG driver and simply
ignores the first clock setting as this is the offending one when
selecting the settings. Which of the two possible settings is used have
no effect for SDR104.
Signed-off-by: Niklas Söderlund
---
* Changes since v1
- Fixed spelling in commit message, thanks Sergei and Geert!
- Reworked the whole patch per Geerts suggestion. Instead of only
skipping the first row on the effected boards when setting the clock
rete totally ignore it. This is made possible by another change to the
clock driver posted separately from this series and which this patch
now depends on [1].
1. [PATCH] clk: renesas: rcar-gen3: set state when registering SD clocks
---
drivers/clk/renesas/rcar-gen3-cpg.c | 33 +++--
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index bca6c7f51de18db7..bad062150cd486f6 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -242,6 +242,10 @@ struct sd_clock {
* 1 0 2 (4) 0 (2) 8
* 1 0 3 (8) 0 (2) 16
* 1 0 4 (16) 0 (2) 32
+ *
+ * NOTE: There is a quirk option to ignore the first row of the dividers
+ * table when searching for suitable settings. This is because HS400 on
+ * early ES versions of H3 and M3-W requires a specific setting to work.
*/
static const struct sd_div_table cpg_sd_div_table[] = {
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
@@ -352,6 +356,12 @@ static const struct clk_ops cpg_sd_clock_ops = {
.set_rate = cpg_sd_clock_set_rate,
};
+static u32 cpg_quirks __initdata;
+
+#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
+#define RCKCR_CKSELBIT(1) /* Manual RCLK parent selection */
+#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
+
static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
void __iomem *base, const char *parent_name,
struct raw_notifier_head *notifiers)
@@ -377,6 +387,11 @@ static struct clk * __init cpg_sd_clk_register(const
struct cpg_core_clk *core,
clock->div_table = cpg_sd_div_table;
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
+ if (cpg_quirks & SD_SKIP_FIRST) {
+ clock->div_table++;
+ clock->div_num--;
+ }
+
val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
writel(val, clock->csn.reg);
@@ -406,23 +421,27 @@ static struct clk * __init cpg_sd_clk_register(const
struct cpg_core_clk *core,
static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
static unsigned int cpg_clk_extalr __initdata;
static u32 cpg_mode __initdata;
-static u32 cpg_quirks __initdata;
-
-#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
-#define RCKCR_CKSELBIT(1) /* Manual RCLK parent selection */
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
{
.soc_id = "r8a7795", .revision = "ES1.0",
- .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
+ .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
},
{
.soc_id = "r8a7795", .revision = "ES1.*",
- .data = (void *)RCKCR_CKSEL,
+ .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
+ },
+ {
+ .soc_id = "r8a7795", .revision = "ES2.0",
+ .data = (void *)SD_SKIP_FIRST,
},
{
.soc_id = "r8a7796", .revision = "ES1.0",
- .data = (void *)RCKCR_CKSEL,
+ .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
+ },
+ {
+ .soc_id = "r8a7796", .revision = "ES1.1",
+ .data = (void *)SD_SKIP_FIRST,
},
{ /* sentinel */ }
};
--
2.19.1
[PATCH v2 0/2] renesas: rcar-gen3: add HS400 quirk for SD clock
Hi Geert,
This series aims to solve the clock quirk needed to enabled HS400 on
SoCs needing special clock handeling. It uses the same method as v1 of
this series and which was discussed during the SDHI hackathon. However
patch 2/2 have been completely rewritten to take your comments from v1
into account. Due to this change this series now depends on [1].
This is tested on H3 (ES1.0, ES2.0), M3-W (ES1.0) and M3-N together with
patches to enable HS400 with great results. No regressions found for
eMMC HS200/HS400 modes nor for SDR{25,50,104} on any of the SoCs.
Patch 1/2 adds documentation on which settings is used while 2/2 is the
real change where the quirk is implemented.
1. [PATCH] clk: renesas: rcar-gen3: set state when registering SD clocks
Niklas Söderlund (2):
clk: renesas: rcar-gen3: add documentation for SD clocks
clk: renesas: rcar-gen3: add HS400 quirk for SD clock
drivers/clk/renesas/rcar-gen3-cpg.c | 43 +
1 file changed, 31 insertions(+), 12 deletions(-)
--
2.19.1
[PATCH] clk: renesas: rcar-gen3: set state when registering SD clocks
The driver tries to figure out which state a SD clock is in when the
clock is register instead of setting a known state. This can be
problematic for two reasons.
1. If the clock driver can't figure out the state of the clock
registration of the clock fails and setting of a known state by a
clock user is not possible.
2. The state of the clock depends on if and how the bootloader
configured it. The driver only checks that the rate is known not if
the clock is stopped or not for example.
Fix this by setting a known state and make sure the clock is stopped.
Signed-off-by: Niklas Söderlund
---
drivers/clk/renesas/rcar-gen3-cpg.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 4ba38f98cc7bab82..f6335357c85505df 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -360,7 +360,7 @@ static struct clk * __init cpg_sd_clk_register(const struct
cpg_core_clk *core,
struct sd_clock *clock;
struct clk *clk;
unsigned int i;
- u32 sd_fc;
+ u32 val;
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
if (!clock)
@@ -377,17 +377,11 @@ static struct clk * __init cpg_sd_clk_register(const
struct cpg_core_clk *core,
clock->div_table = cpg_sd_div_table;
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
- sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
- for (i = 0; i < clock->div_num; i++)
- if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
- break;
-
- if (WARN_ON(i >= clock->div_num)) {
- kfree(clock);
- return ERR_PTR(-EINVAL);
- }
+ val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
+ val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
+ writel(val, clock->csn.reg);
- clock->cur_div_idx = i;
+ clock->cur_div_idx = 0;
clock->div_max = clock->div_table[0].div;
clock->div_min = clock->div_max;
--
2.19.1
Re: [PATCH v3 0/3] mmc: renesas_sdhi: extend quirk selection to handle ES revisions
Hi Wolfram, On 2018-11-28 23:06:37 +0100, Niklas Söderlund wrote: > Hi Wolfram, > > On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote: > > Hi Niklas, > > > > thanks for the updates! Do you happen to have a branch ready for > > testing? > > I will push a new branch once I'm done updating the clock patch so all > changes can be tested in one go. Will let you know once that is > available. Hopefully later tonight. I have pushed the latest and greatest to [1]. I tested this on H3 ES1, H3 ES2.0 and M3-N and it looks good. Speeds for both MMC and SD cards match what we saw in Edinburgh. I still have to post the clock patches to the mailing list but in case you wish to test right away I thought I send this mail out before I do that :-) 1. git://git.ragnatech.se/linux mmc/hackfest -- Regards, Niklas Söderlund
Re: [PATCH v3 0/3] mmc: renesas_sdhi: extend quirk selection to handle ES revisions
Hi Wolfram, On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote: > Hi Niklas, > > thanks for the updates! Do you happen to have a branch ready for > testing? I will push a new branch once I'm done updating the clock patch so all changes can be tested in one go. Will let you know once that is available. Hopefully later tonight. -- Regards, Niklas Söderlund
Re: [PATCH v3 0/3] mmc: renesas_sdhi: extend quirk selection to handle ES revisions
Hi Niklas, thanks for the updates! Do you happen to have a branch ready for testing? Thanks, Wolfram signature.asc Description: PGP signature
Re: [git pull] clk: renesas: Updates for v4.21
Quoting Geert Uytterhoeven (2018-11-23 00:56:35) > Hi Mike, Stephen, > > The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a: > > Linux 4.20-rc1 (2018-11-04 15:37:52 -0800) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git > tags/clk-renesas-for-v4.21-tag1 > > for you to fetch changes up to eb38c119dd91c61de26f67050671a84064554f7d: > > clk: renesas: r7s9210: Add USB clocks (2018-11-13 09:58:51 +0100) > > > clk: renesas: Updates for v4.21 > > - Add support for SDHI and USB clocks on RZ/A2, > - Add support for RPC (SPI Multi I/O Bus Controller) clocks on R-Car > V3M. > > Thanks for pulling! > Thanks. Pulled into clk-next. Plus I threw a sparse warning fix into the pile.
Re: [PATCH 2/2] clk: renesas: rcar-gen3: add HS400 quirk for SD clock
Hi Geert,
Thanks for your feedback.
On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> wrote:
> > On 2018-11-05 11:43:24 +0100, Geert Uytterhoeven wrote:
> > > On Thu, Nov 1, 2018 at 12:26 AM Niklas Söderlund
> > > wrote:
> > > > From: Niklas Söderlund
> > > >
> > > > On H3 (ES1.0,ES2.0) and M3-W (ES1.0,ES1.1) the clock setting for HS400
> > >
> > > H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1)
> >
> > Thanks.
> >
> > >
> > > > needs a quirk to function properly. The reason for the quirk is that
> > > > there are two settings which produces same divider vale for the SDn
> > > > clock. On the effected boards the one currently selected results in HS00
> > >
> > > HS200 or HS400?
> >
> > Wops, HS400 :-)
> >
> > >
> > > > not working.
> > > >
> > > > This change uses the same method as the Gen2 CPG driver and simply
> > > > ignores the first clock setting as this is the offending one when
> > > > selecting the settings. Which of the two possible settings is used have
> > > > no effect for SDR104.
> > > >
> > > > Signed-off-by: Niklas Söderlund
> > > > ---
> > > > drivers/clk/renesas/rcar-gen3-cpg.c | 28 ++--
> > > > 1 file changed, 22 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > b/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > index ff56ac6134111c38..8cc524a29c855dd2 100644
> > > > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > > > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
>
> > > > @@ -377,6 +382,7 @@ static struct clk * __init
> > > > cpg_sd_clk_register(const struct cpg_core_clk *core,
> > > > clock->hw.init =
> > > > clock->div_table = cpg_sd_div_table;
> > > > clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
> > > > + clock->skip_first = skip_first;
> > >
> > > What about
> > >
> > > if (cpg_quirks & SD_SKIP_FIRST) {
> > > clock->div_table++;
> > > clock->div_num--;
> > > }
> > >
> > > instead?
> >
> > This was my first approach as well, unfortunately it won't work :-(
> >
> > If the bootloader leaves the clock settings in a state which matches the
> > first row in the table the clock fails to register as the check in
> > cpg_sd_clk_register() makes sure it have a row for the state the
> > hardware is in. If it can't find that state the clock fails to register.
> > Whit this quirk the limitation of the effected boards only have an
> > effect when setting the clock.
>
> IC...
>
> > I thought this solution solved this quiet neatly with the robustness
> > principle, 'Be conservative in what you do, be liberal in what you
> > accept from others' :-)
>
> Will it ever use the settings as inherited from boot loader or reset state?
> If it does, I assume it will fail badly, due to an inconsistency between the
> SD and SDH clock rates?
> And what if the kernel is ever booted when the SDnSRCFC or SDnFC field
> has an invalid value? Then the driver will fail, too?
>
> Hence, isn't it safer to initialize the registers to a known safe value?
I agree with you that we should not trust the value fro the bootloader
and the sdhi driver do not trust this and resets it. The problem is
rcar-gen3-cpg. From cpg_sd_clk_register()
sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
for (i = 0; i < clock->div_num; i++)
if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
break;
if (WARN_ON(i >= clock->div_num)) {
kfree(clock);
return ERR_PTR(-EINVAL);
}
clock->cur_div_idx = i;
If the bootloader sets the register to a value not known by the clock
driver or if we us the moth you prefer to modify clock->div_table and
clock->div_num the clock driver would need to set a safe default. I
think this would be fine as the SDHI driver could handle this (I need to
test it tho). My proposal is therefor that I add a patch to this series
where the clock driver try to set a known divider when it registers the
clock.
My suggestion would be that the divider to be set to 4 as this appears
to be what current boot loaders do. Would this work for you?
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
--
Regards,
Niklas Söderlund
Re: Issue with enabling VSP source on rcar gen2 koelsch board
Hi Biju, On Wednesday, 28 November 2018 15:20:58 EET Biju Das wrote: > Hi all, > > On the past, I have tested vsp source on rcar gen2 koelsch board, using the > patches series below(Apart from the below patch series, I have enabled > "CONFIG_DRM_RCAR_VSP=y") > https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels > > 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU > 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D > 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 > > But on the latest renesas-dev branch looks like it is broken That doesn't surprise me too much as I don't actively maintain that code. For my information, what are your use cases ? Do you think this approach should be pursued and patches merged upstream ? The amount of work will be quite high though, given that it introduces a new userspace API, we will have to publish an open-source implementation in an X.org or Wayland driver. > The issue is kernel doesn't boot, if I connect display panel. Looks like it > is hanging in register_framebuffer. > > [5.344412] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [5.364250] [drm] No driver support for vblank timestamp query. > > Have any one noticed this issue? This usually means that the kernel crashes with the console lock taken, preventing the oops from being printed. As a debugging hack you can comment out the locking calls in console_lock(), console_trylock() and console_unlock() (kernel/printk/printk.c). -- Regards, Laurent Pinchart
[PATCH 2/5] ARM: dts: r8a7744: Add VSP support
Add VSP support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3b8aa3b..0937349 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1493,6 +1493,33 @@
status = "disabled";
};
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 131>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 131>;
+ };
+
+ vsp@fe93 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe93 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 128>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = ;
+ clocks = < CPG_MOD 127>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 127>;
+ };
+
du: display@feb0 {
compatible = "renesas,du-r8a7744";
reg = <0 0xfeb0 0 0x4>,
--
2.7.4
[PATCH 5/5] ARM: dts: r8a7744: Add TPU support
Add TPU support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 43da6a0..40de227 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -272,6 +272,16 @@
reg = <0 0xe606 0 0x164>;
};
+ tpu: pwm@e60f {
+ compatible = "renesas,tpu-r8a7744", "renesas,tpu";
+ reg = <0 0xe60f 0 0x148>;
+ clocks = < CPG_MOD 304>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a7744-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
--
2.7.4
[PATCH 4/5] ARM: dts: r8a7744: Add PWM SoC support
Add the definitions for pwm[0123456] to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 70 ++
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 152431c..43da6a0 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1050,6 +1050,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e3 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e3 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7744",
"renesas,rcar-gen2-can";
--
2.7.4
[PATCH 3/5] ARM: dts: r8a7744: Add IPMMU DT nodes
Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 0937349..152431c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -340,6 +340,64 @@
#thermal-sensor-cells = <0>;
};
+ ipmmu_sy0: mmu@e628 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe628 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: mmu@e629 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe629 0 0x1000>;
+ interrupts = ;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: mmu@e674 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe674 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec68 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xec68 0 0x1000>;
+ interrupts = ;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: mmu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_gp: mmu@e62a {
+ compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+ reg = <0 0xe62a 0 0x1000>;
+ interrupts = ,
+;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
--
2.7.4
[PATCH 1/5] ARM: dts: r8a7744: add VIN dt support
Add VIN[012] support to SoC dt.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2eae905..3b8aa3b 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1020,6 +1020,39 @@
status = "disabled";
};
+ vin0: video@e6ef {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 811>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 810>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = ;
+ clocks = < CPG_MOD 809>;
+ power-domains = < R8A7744_PD_ALWAYS_ON>;
+ resets = < 809>;
+ status = "disabled";
+ };
+
rcar_sound: sound@ec50 {
/*
* #sound-dai-cells is required
--
2.7.4
[PATCH 0/5] Add more support to RZ/G1N
This patch series aims to add support for some more interfaces to RZ/G1N SoC (IPMMU, VSP, VIN, PWM and TPU). This patch series tested against renesas-dev. it depends on the the below patch series. https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=48065 Biju Das (5): ARM: dts: r8a7744: add VIN dt support ARM: dts: r8a7744: Add VSP support ARM: dts: r8a7744: Add IPMMU DT nodes ARM: dts: r8a7744: Add PWM SoC support ARM: dts: r8a7744: Add TPU support arch/arm/boot/dts/r8a7744.dtsi | 198 + 1 file changed, 198 insertions(+) -- 2.7.4
[PATCH v3 3/3] mmc: renesas_sdhi: disable HS400 on H3 ES1.x and M3-W ES1.[012]
The Renesas BSP confirms that H3 ES1.x and M3-W ES1.[012] do not
properly support HS400. Add a quirk to indicate this and disable HS400
in the MMC capabilities if the quirk is set.
Signed-off-by: Niklas Söderlund
Tested-by: Wolfram Sang
Reviewed-by: Wolfram Sang
Reviewed-by: Simon Horman
---
* Changes since v2
- s/M3-W ES1.x/M3-W ES1.[012]/ in commit message and topic as HS400 is
not disabled for M3-W ES1.3. Thanks Geert for pointing this out.
---
drivers/mmc/host/renesas_sdhi_core.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c
b/drivers/mmc/host/renesas_sdhi_core.c
index f20df18f49e0d7c5..d4df4e59d9f2a8ad 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -47,6 +47,7 @@
#define SDHI_VER_GEN3_SDMMC0xcd10
struct renesas_sdhi_quirks {
+ bool hs400_disabled;
bool hs400_4taps;
};
@@ -598,15 +599,21 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host
*host, bool enable)
renesas_sdhi_sdbuf_width(host, enable ? width : 16);
}
-static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+static const struct renesas_sdhi_quirks sdhi_quirks_h3_m3w_es1 = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_h3_es2 = {
+ .hs400_disabled = false,
.hs400_4taps = true,
};
static const struct soc_device_attribute sdhi_quirks_match[] = {
- { .soc_id = "r8a7795", .revision = "ES1.*", .data = _quirks_4tap },
- { .soc_id = "r8a7795", .revision = "ES2.0", .data = _quirks_4tap },
- { .soc_id = "r8a7796", .revision = "ES1.0", .data = _quirks_4tap },
- { .soc_id = "r8a7796", .revision = "ES1.1", .data = _quirks_4tap },
+ { .soc_id = "r8a7795", .revision = "ES1.*", .data =
_quirks_h3_m3w_es1 },
+ { .soc_id = "r8a7795", .revision = "ES2.0", .data = _quirks_h3_es2
},
+ { .soc_id = "r8a7796", .revision = "ES1.0", .data =
_quirks_h3_m3w_es1 },
+ { .soc_id = "r8a7796", .revision = "ES1.1", .data =
_quirks_h3_m3w_es1 },
{ /* Sentinel. */ },
};
@@ -695,6 +702,9 @@ int renesas_sdhi_probe(struct platform_device *pdev,
host->multi_io_quirk= renesas_sdhi_multi_io_quirk;
host->dma_ops = dma_ops;
+ if (quirks && quirks->hs400_disabled)
+ host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
+
if (quirks && quirks->hs400_4taps)
mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400;
--
2.19.1
[PATCH v3 2/3] mmc: renesas_sdhi: align compatibility properties for H3 and M3-W
It was though all ES revisions of H3 and M3-W SoCs required the
TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is
not true, only early ES revisions of the SoC do.
Since quirk matching based on ES revisions is now used to handle the
flag it's possible to align all Gen3 compatibility properties. This will
allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400
mode.
Signed-off-by: Niklas Söderlund
Tested-by: Wolfram Sang
Reviewed-by: Wolfram Sang
Reviewed-by: Simon Horman
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 20 ++-
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 20 +++
2 files changed, 5 insertions(+), 35 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 57e829223c40e0ee..332c5c60edb3d9c4 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -99,22 +99,6 @@ static const struct renesas_sdhi_of_data of_rza2_compatible
= {
.max_segs = 1,
};
-static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
- TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
- TMIO_MMC_HAVE_4TAP_HS400,
- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
- MMC_CAP_CMD23,
- .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
- .bus_shift = 2,
- .scc_offset = 0x1000,
- .taps = rcar_gen3_scc_taps,
- .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
- /* DMAC can handle 0x blk count but only 1 segment */
- .max_blk_count = 0x,
- .max_segs = 1,
-};
-
static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
@@ -133,8 +117,8 @@ static const struct renesas_sdhi_of_data
of_rcar_gen3_compatible = {
static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
{ .compatible = "renesas,sdhi-r7s9210", .data = _rza2_compatible, },
{ .compatible = "renesas,sdhi-mmc-r8a77470", .data =
_rcar_gen3_compatible, },
- { .compatible = "renesas,sdhi-r8a7795", .data =
_rcar_r8a7795_compatible, },
- { .compatible = "renesas,sdhi-r8a7796", .data =
_rcar_r8a7795_compatible, },
+ { .compatible = "renesas,sdhi-r8a7795", .data =
_rcar_gen3_compatible, },
+ { .compatible = "renesas,sdhi-r8a7796", .data =
_rcar_gen3_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data =
_rcar_gen3_compatible, },
{},
};
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 1a4016f635d398c2..8471160316e073c5 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -75,19 +75,6 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
},
};
-static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
- TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
- TMIO_MMC_HAVE_4TAP_HS400,
- .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
- MMC_CAP_CMD23,
- .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
- .bus_shift = 2,
- .scc_offset = 0x1000,
- .taps = rcar_gen3_scc_taps,
- .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
-};
-
static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
@@ -114,8 +101,8 @@ static const struct of_device_id
renesas_sdhi_sys_dmac_of_match[] = {
{ .compatible = "renesas,sdhi-r8a7792", .data =
_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7793", .data =
_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7794", .data =
_rcar_gen2_compatible, },
- { .compatible = "renesas,sdhi-r8a7795", .data =
_rcar_r8a7795_compatible, },
- { .compatible = "renesas,sdhi-r8a7796", .data =
_rcar_r8a7795_compatible, },
+ { .compatible = "renesas,sdhi-r8a7795", .data =
_rcar_gen3_compatible, },
+ { .compatible = "renesas,sdhi-r8a7796", .data =
_rcar_gen3_compatible, },
{ .compatible = "renesas,rcar-gen1-sdhi", .data =
_rcar_gen1_compatible, },
{ .compatible = "renesas,rcar-gen2-sdhi", .data =
_rcar_gen2_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data =
_rcar_gen3_compatible, },
@@ -493,8 +480,7 @@ static const struct soc_device_attribute
gen3_soc_whitelist[] = {
static int
[PATCH v3 1/3] mmc: renesas_sdhi: handle 4tap hs400 mode quirk based on SoC revision
Latest datasheet makes it clear that not all ES revisions of the H3 and
M3-W have the 4-tap HS400 mode quirk, currently the quirk is set
unconditionally for these two SoCs. Prepare to handle the quirk based on
SoC revision instead of compatibility value by using soc_device_match()
and set the TMIO_MMC_HAVE_4TAP_HS400 flag explicitly.
The reason for adding a new quirks struct instead of just a flag is that
looking ahead it seems more quirks needs to be handled in a SoC revision
basis.
Signed-off-by: Niklas Söderlund
Tested-by: Wolfram Sang
Reviewed-by: Wolfram Sang
Reviewed-by: Simon Horman
---
* Changes since v2
- Renamed sdhi_quirks_h3_m3w to sdhi_quirks_4tap. This have little
effect as the last patch in this series renames the variable once more
once more quirks are added which are more SoC specific. Suggested by
Geert, thanks.
---
drivers/mmc/host/renesas_sdhi_core.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c
b/drivers/mmc/host/renesas_sdhi_core.c
index 78bd117bbe65de46..f20df18f49e0d7c5 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include "renesas_sdhi.h"
#include "tmio_mmc.h"
@@ -45,6 +46,10 @@
#define SDHI_VER_GEN3_SD 0xcc10
#define SDHI_VER_GEN3_SDMMC0xcd10
+struct renesas_sdhi_quirks {
+ bool hs400_4taps;
+};
+
static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
{
u32 val;
@@ -593,11 +598,25 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host
*host, bool enable)
renesas_sdhi_sdbuf_width(host, enable ? width : 16);
}
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+ .hs400_4taps = true,
+};
+
+static const struct soc_device_attribute sdhi_quirks_match[] = {
+ { .soc_id = "r8a7795", .revision = "ES1.*", .data = _quirks_4tap },
+ { .soc_id = "r8a7795", .revision = "ES2.0", .data = _quirks_4tap },
+ { .soc_id = "r8a7796", .revision = "ES1.0", .data = _quirks_4tap },
+ { .soc_id = "r8a7796", .revision = "ES1.1", .data = _quirks_4tap },
+ { /* Sentinel. */ },
+};
+
int renesas_sdhi_probe(struct platform_device *pdev,
const struct tmio_mmc_dma_ops *dma_ops)
{
struct tmio_mmc_data *mmd = pdev->dev.platform_data;
+ const struct renesas_sdhi_quirks *quirks = NULL;
const struct renesas_sdhi_of_data *of_data;
+ const struct soc_device_attribute *attr;
struct tmio_mmc_data *mmc_data;
struct tmio_mmc_dma *dma_priv;
struct tmio_mmc_host *host;
@@ -607,6 +626,10 @@ int renesas_sdhi_probe(struct platform_device *pdev,
of_data = of_device_get_match_data(>dev);
+ attr = soc_device_match(sdhi_quirks_match);
+ if (attr)
+ quirks = attr->data;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
@@ -672,6 +695,9 @@ int renesas_sdhi_probe(struct platform_device *pdev,
host->multi_io_quirk= renesas_sdhi_multi_io_quirk;
host->dma_ops = dma_ops;
+ if (quirks && quirks->hs400_4taps)
+ mmc_data->flags |= TMIO_MMC_HAVE_4TAP_HS400;
+
/* For some SoC, we disable internal WP. GPIO may override this */
if (mmc_can_gpio_ro(host->mmc))
mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
--
2.19.1
[PATCH v3 0/3] mmc: renesas_sdhi: extend quirk selection to handle ES revisions
Hi, Recent datasheet updates have made it clear that some quirks are not SoC specific but SoC + ES version specific. Currently the quirks are selected using compatibility values but whit this new information that is not enough. Patch 1/3 adds support to select quirks based on SoC + ES revision using soc_device_match() and converts the only existing quirk. Patch 2/3 Removes the old method to select quirk based on compatibility string. While Patch 3/3 adds a new quirk from the BSP which blacklists some known problematic ES versions for HS400. HS400 is not yet enabled upstream so blacklisting these ES versions is not a regression of functionality. Based on mmc/next and tested on H3 and M3-N. Niklas Söderlund (3): mmc: renesas_sdhi: handle 4tap hs400 mode quirk based on SoC revision mmc: renesas_sdhi: align compatibility properties for H3 and M3-W mmc: renesas_sdhi: disable HS400 on H3 ES1.x and M3-W ES1.[012] drivers/mmc/host/renesas_sdhi_core.c | 36 +++ drivers/mmc/host/renesas_sdhi_internal_dmac.c | 20 ++- drivers/mmc/host/renesas_sdhi_sys_dmac.c | 20 ++- 3 files changed, 41 insertions(+), 35 deletions(-) -- 2.19.1
RE: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
> -Original Message- > From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman > Sent: 28 November 2018 13:24 > To: Biju Das > Cc: Sergei Shtylyov ; Rob Herring > ; Mark Rutland ; Magnus > Damm ; linux-renesas-soc@vger.kernel.org; > devicet...@vger.kernel.org; Geert Uytterhoeven > ; Chris Paterson > ; Fabrizio Castro > > Subject: Re: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 > > > > > > On 11/27/2018 02:56 PM, Biju Das wrote: > > > > > > > Enable the SDHI0 controller on iWave RZ/G1N Qseven System On > Module. > > > > > >Why your subject has SDHI10? > > > > It is a typo. > > > > Simon, Will you fix this while applying or do you want me to send V2? > > Please let me know. > > No need to repost for this. Thanks Simon. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Re: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 controller
On Tue, Nov 27, 2018 at 02:22:12PM +, Biju Das wrote: > Hello Sergei, > > Thanks for the feedback. > > > -Original Message- > > From: Sergei Shtylyov > > Sent: 27 November 2018 14:17 > > To: Biju Das ; Rob Herring > > ; Mark Rutland > > Cc: Simon Horman ; Magnus Damm > > ; linux-renesas-soc@vger.kernel.org; > > devicet...@vger.kernel.org; Geert Uytterhoeven > > ; Chris Paterson > > ; Fabrizio Castro > > > > Subject: Re: [PATCH 06/22] ARM: dts: r8a7744-iwg20m: Enable SDHI10 > > controller > > > > Hello! > > > > On 11/27/2018 02:56 PM, Biju Das wrote: > > > > > Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. > > > >Why your subject has SDHI10? > > It is a typo. > > Simon, Will you fix this while applying or do you want me to send V2? > Please let me know. No need to repost for this. > > > > Signed-off-by: Biju Das > > [...] > > > > MBR, Sergei > > > > Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, > Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered > No. 04586709.
Re: [PATCH v4 2/3] mmc: tmio: fix reset operation
On Mon, Nov 26, 2018 at 06:02:46PM +0100, Niklas Söderlund wrote: > SD / MMC did not operate properly when suspend transition failed. > Because the SCC was not reset at resume, issue of the command failed. > Call the host specific reset function and reset the hardware in order to > add reset of SCC. This change also fixes tuning on some stubborn cards > on Gen2. > > Based on work from Masaharu Hayakawa. > > Signed-off-by: Niklas Söderlund Reviewed-by: Simon Horman
Issue with enabling VSP source on rcar gen2 koelsch board
Hi all, On the past, I have tested vsp source on rcar gen2 koelsch board, using the patches series below(Apart from the below patch series, I have enabled "CONFIG_DRM_RCAR_VSP=y") https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels 1) [HACK] ARM: shmobile: r8a7791: Link the VSP1 and DU 2) [HACK] v4l: vsp1: Disable UAPI for VSP1D 3) [HACK] drm: rcar-du: Enable VSP source support for R8A7791 But on the latest renesas-dev branch looks like it is broken The issue is kernel doesn't boot, if I connect display panel. Looks like it is hanging in register_framebuffer. [5.344412] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [5.364250] [drm] No driver support for vblank timestamp query. Have any one noticed this issue? Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
[PATCH 12/16] ARM: dts: iwg23s-sbc: Enable cmt0
From: Biju Das
This patch enables cmt0 support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index ffd8216f28c3..18d22631e188 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -73,6 +73,10 @@
};
};
+ {
+ status = "okay";
+};
+
_clk {
clock-frequency = <2000>;
};
--
2.11.0
[PATCH 11/16] ARM: dts: r8a77470: Add CMT SoC specific support
From: Biju Das
Add CMT[01] support to r8a77470 SoC DT.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 0a7ca2ff4dc4..5c0e48d0449a 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -615,6 +615,38 @@
compatible = "renesas,prr";
reg = <0 0xff44 0 4>;
};
+
+ cmt0: timer@ffca {
+ compatible = "renesas,r8a77470-cmt0",
+"renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca 0 0x1004>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e613 {
+ compatible = "renesas,r8a77470-cmt1",
+"renesas,rcar-gen2-cmt1";
+ reg = <0 0xe613 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 329>;
+ status = "disabled";
+ };
};
timer {
--
2.11.0
[PATCH 14/16] ARM: dts: r8a77470: Add QSPI support
From: Fabrizio Castro
Add QSPI[01] support to the RZ/G1C SoC specific device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 5c0e48d0449a..f4e232bf9d03 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -460,6 +460,38 @@
status = "disabled";
};
+ qspi0: spi@e6b1 {
+ compatible = "renesas,qspi-r8a77470", "renesas,qspi";
+ reg = <0 0xe6b1 0 0x2c>;
+ interrupts = ;
+ clocks = < CPG_MOD 918>;
+ dmas = < 0x17>, < 0x18>,
+ < 0x17>, < 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 918>;
+ status = "disabled";
+ };
+
+ qspi1: spi@ee20 {
+ compatible = "renesas,qspi-r8a77470", "renesas,qspi";
+ reg = <0 0xee20 0 0x2c>;
+ interrupts = ;
+ clocks = < CPG_MOD 917>;
+ dmas = < 0xd1>, < 0xd2>,
+ < 0xd1>, < 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = < 917>;
+ status = "disabled";
+ };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
--
2.11.0
[PATCH 16/16] ARM: dts: r9a06g032: Correct the GIC DT node name
From: Phil Edworthy
Harmless mistake, but it's incorrect. The DT spec provides recommendations
for the node names:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model. If appropriate, the
name should be one of the following choices:
...
interrupt-controller"
Signed-off-by: Phil Edworthy
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 2322268bc862..4c1ab49c7d39 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -173,7 +173,7 @@
status = "okay";
};
- gic: gic@44101000 {
+ gic: interrupt-controller@44101000 {
compatible = "arm,cortex-a7-gic", "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
--
2.11.0
[PATCH 13/16] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB
From: Biju Das
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 18d22631e188..52f23b858885 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -60,6 +60,9 @@
};
{
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
phy-handle = <>;
phy-mode = "gmii";
renesas,no-ether-link;
@@ -82,6 +85,11 @@
};
{
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii_tx_rx";
+ function = "avb";
+ };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
--
2.11.0
[PATCH 09/16] ARM: dts: iwg23s-sbc: Enable watchdog support
From: Biju Das
This patch enables watchdog support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index e5cfb50ddce3..ffd8216f28c3 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -102,6 +102,11 @@
};
};
+ {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
--
2.11.0
[PATCH 10/16] ARM: dts: r8a77470: Add USB-DMAC device nodes
From: Biju Das
This patch adds USB DMAC nodes.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 56 +
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index a703b74cc1f9..0a7ca2ff4dc4 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -325,6 +325,62 @@
status = "disabled";
};
+ usb_dmac00: dma-controller@e65a {
+ compatible = "renesas,r8a77470-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65a 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 330>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac10: dma-controller@e65b {
+ compatible = "renesas,r8a77470-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65b 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 331>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac01: dma-controller@e65a8000 {
+ compatible = "renesas,r8a77470-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65a8000 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 326>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 326>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac11: dma-controller@e65b8000 {
+ compatible = "renesas,r8a77470-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65b8000 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 327>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 327>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
--
2.11.0
[PATCH 05/16] ARM: dts: iwg23s-sbc: Add uSD and eMMC support
From: Fabrizio Castro
Add uSD card and eMMC support to the iwg23s single board
computer powered by the RZ/G1C SoC (a.k.a. r8a77470).
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 76 +++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 22da819f186b..e5cfb50ddce3 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -6,6 +6,7 @@
*/
/dts-v1/;
+#include
#include "r8a77470.dtsi"
/ {
model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
@@ -25,6 +26,37 @@
device_type = "memory";
reg = <0 0x4000 0 0x2000>;
};
+
+ reg_1p8v: reg-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: reg-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+
+ gpios = < 24 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <330 1
+ 180 0>;
+ };
};
{
@@ -46,10 +78,28 @@
};
{
+ mmc_pins_uhs: mmc_uhs {
+ groups = "mmc_data8", "mmc_ctrl";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
scif1_pins: scif1 {
groups = "scif1_data_b";
function = "scif1";
};
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
};
{
@@ -58,3 +108,29 @@
status = "okay";
};
+
+ {
+ pinctrl-0 = <_pins_uhs>;
+ pinctrl-names = "state_uhs";
+
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-1 = <_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_sdhi2>;
+ bus-width = <4>;
+ cd-gpios = < 20 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
--
2.11.0
[PATCH 06/16] ARM: dts: r8a779[01]: Disable unconnected LVDS encoders
From: Laurent Pinchart
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
are enabled in DT but have no device connected to their output. This
result in spurious messages being printed to the kernel log such as
rcar-du feb0.display: no connector for encoder /soc/lvds@feb9, skipping
Fix it by disabling the encoders.
Fixes: 15a1ff30d8f9 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings")
Fixes: e5c3f4707f39 ("ARM: dts: r8a7791: Convert to new LVDS DT bindings")
Reported-by: Geert Uytterhoeven
Signed-off-by: Laurent Pinchart
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7790-lager.dts | 2 --
arch/arm/boot/dts/r8a7791-koelsch.dts | 2 --
arch/arm/boot/dts/r8a7791-porter.dts | 2 --
3 files changed, 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
b/arch/arm/boot/dts/r8a7790-lager.dts
index 50312e752e2f..7b9508e83d46 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -489,8 +489,6 @@
};
{
- status = "okay";
-
ports {
port@1 {
lvds_connector: endpoint {
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts
b/arch/arm/boot/dts/r8a7791-koelsch.dts
index ce22db01fbba..e6580aa0cea3 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -479,8 +479,6 @@
};
{
- status = "okay";
-
ports {
port@1 {
lvds_connector: endpoint {
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts
b/arch/arm/boot/dts/r8a7791-porter.dts
index f02036e5de01..fefdf8238bbe 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -482,8 +482,6 @@
};
{
- status = "okay";
-
ports {
port@1 {
lvds_connector: endpoint {
--
2.11.0
[PATCH 07/16] ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSI
From: Magnus Damm Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) DTSI to include product name. Signed-off-by: Magnus Damm [simon: squashed similar patches] Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 2 +- arch/arm/boot/dts/r8a7740.dtsi | 2 +- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 373ea8720769..67d86012a85c 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the EMEV2 SoC + * Device Tree Source for the Emma Mobile EV2 SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 383cba68dbba..12ffe73bf2bc 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the r8a7740 SoC + * Device Tree Source for the R-Mobile A1 (R8A77400) SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index e8f0a07c4564..33836990b102 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the SH73A0 SoC + * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ -- 2.11.0
[PATCH 15/16] ARM: dts: iwg23s-sbc: Add QSPI flash support
From: Fabrizio Castro
This commit adds QSPI flash support to the iwg23s board specific
device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 52f23b858885..40b7f98d6013 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -96,6 +96,11 @@
power-source = <1800>;
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data2";
+ function = "qspi0";
+ };
+
scif1_pins: scif1 {
groups = "scif1_data_b";
function = "scif1";
@@ -114,6 +119,27 @@
};
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ /* WARNING - This device contains the bootloader. Handle with care. */
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "issi,is25lp016d", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <13300>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
{
timeout-sec = <60>;
status = "okay";
--
2.11.0
[PATCH 08/16] ARM: dts: r8a77470: Add watchdog support to SoC dtsi
From: Biju Das
This patch adds watchdog support to the r8a77470 SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
[simon: moved node to preserve sort order]
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 6ac7f467065e..a703b74cc1f9 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -79,6 +79,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a77470-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = < CPG_MOD 402>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a77470",
"renesas,rcar-gen2-gpio";
--
2.11.0
[PATCH 01/16] ARM: dts: r9a06g032: Add pinctrl node
From: Phil Edworthy
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r9a06g032.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index eaf94976ed6d..2322268bc862 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -165,6 +165,14 @@
status = "disabled";
};
+ pinctrl: pin-controller@40067000 {
+ compatible = "renesas,r9a06g032-pinctrl",
"renesas,rzn1-pinctrl";
+ reg = <0x40067000 0x1000>, <0x5100 0x480>;
+ clocks = < R9A06G032_HCLK_PINCONFIG>;
+ clock-names = "bus";
+ status = "okay";
+ };
+
gic: gic@44101000 {
compatible = "arm,cortex-a7-gic", "arm,gic-400";
interrupt-controller;
--
2.11.0
[PATCH 02/16] ARM: dts: r8a77470: Add I2C[0123] support
From: Fabrizio Castro
Add device tree nodes for the I2C[0123] controllers. Also, add
the aliases node.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9ec78d3d0ca8..9611a936e1b8 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -14,6 +14,14 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -237,6 +245,62 @@
reg = <0 0xe630 0 0x2>;
};
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 931>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 930>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e653 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe653 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 929>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e654 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77470",
+"renesas,rcar-gen2-i2c";
+ reg = <0 0xe654 0 0x40>;
+ interrupts = ;
+ clocks = < CPG_MOD 928>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
i2c4: i2c@e652 {
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0
[PATCH 03/16] ARM: dts: r8a77470: Add SDHI0 support
From: Fabrizio Castro
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes the SDHI support of the R-Car Gen2
compatible IPs, including fixing the max-frequency
definition of SDHI2, as it turns out there is a bug in
Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev.
1.00 Oct. 2017).
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9611a936e1b8..ab2e0223f8a1 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -490,6 +490,21 @@
status = "disabled";
};
+ sdhi0: sd@ee10 {
+ compatible = "renesas,sdhi-r8a77470",
+"renesas,rcar-gen2-sdhi";
+ reg = <0 0xee10 0 0x328>;
+ interrupts = ;
+ clocks = < CPG_MOD 314>;
+ dmas = < 0xcd>, < 0xce>,
+ < 0xcd>, < 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <15600>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 314>;
+ status = "disabled";
+ };
+
sdhi2: sd@ee16 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
@@ -499,7 +514,7 @@
dmas = < 0xd3>, < 0xd4>,
< 0xd3>, < 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <9750>;
+ max-frequency = <7800>;
power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 312>;
status = "disabled";
--
2.11.0
[PATCH 04/16] ARM: dts: r8a77470: Add SDHI1 support
From: Fabrizio Castro
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most similarities with the R-Car
Gen2 family of SoCs, and there is a combination of R-Car
Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP
on this specific chip.
This patch adds the SoC specific part of SDHI1 support, and
since SDHI1 comes with internal DMA, its DT node looks fairly
different from SDHI0 and SDHI2.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index ab2e0223f8a1..6ac7f467065e 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -505,6 +505,17 @@
status = "disabled";
};
+ sdhi1: sd@ee30 {
+ compatible = "renesas,sdhi-mmc-r8a77470";
+ reg = <0 0xee30 0 0x2000>;
+ interrupts = ;
+ clocks = < CPG_MOD 313>;
+ max-frequency = <15600>;
+ power-domains = < R8A77470_PD_ALWAYS_ON>;
+ resets = < 313>;
+ status = "disabled";
+ };
+
sdhi2: sd@ee16 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
--
2.11.0
[GIT PULL v2] Renesas ARM Based SoC DT Updates for v4.21
Hi Olof, Hi Kevin, Hi Arnd, Please consider these Renesas ARM based SoC DT updates for v4.21. I am sending out this pull-request at this time as there are a number of patches queued up in my arm (32) DT branch and I hope that this will ease the burden later on in the development cycle. I expect to send a follow-up pull-request for this branch at the usual pre-rc6 timing. Changes since v1: * Correct garbled Reviewed-by tag in "[PATCH 01/16] ARM: dts: r9a06g032: Add pinctrl node" The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a: Linux 4.20-rc1 (2018-11-04 15:37:52 -0800) are available in the git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-dt-for-v4.21 for you to fetch changes up to 673df60a880f060e3e94920c7b5f7a9ed8aa65f2: ARM: dts: r9a06g032: Correct the GIC DT node name (2018-11-28 13:55:30 +0100) Renesas ARM Based SoC DT Updates for v4.21 * RZ/N1D (r9a06g032) SoC: - Correct GIC DT node name - Enable pin controller * RZ/G1C (r8a77470) iWave g23S single board computer - Add QSPI flash support - Add pinctl support for EtherAVB - Enable CMT0 (Renesas R-Car Compare Match Timer) - Enable RWDT (Renesas Watchdog Timer) - Enable uSD and eMMC support * RZ/G1C (r8a77470) SoC: - Describe USB-DMAC and I2C devices in DT * R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) SoCs: - Include SoC name in DTSI * R-Car H2 (r8a7790) based lager, and R-Car M2-W (r8a7791) based koelsch and porter boards: - Disable unconnected LVDS encoders Biju Das (6): ARM: dts: r8a77470: Add watchdog support to SoC dtsi ARM: dts: iwg23s-sbc: Enable watchdog support ARM: dts: r8a77470: Add USB-DMAC device nodes ARM: dts: r8a77470: Add CMT SoC specific support ARM: dts: iwg23s-sbc: Enable cmt0 ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB Fabrizio Castro (6): ARM: dts: r8a77470: Add I2C[0123] support ARM: dts: r8a77470: Add SDHI0 support ARM: dts: r8a77470: Add SDHI1 support ARM: dts: iwg23s-sbc: Add uSD and eMMC support ARM: dts: r8a77470: Add QSPI support ARM: dts: iwg23s-sbc: Add QSPI flash support Laurent Pinchart (1): ARM: dts: r8a779[01]: Disable unconnected LVDS encoders Magnus Damm (1): ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSI Phil Edworthy (2): ARM: dts: r9a06g032: Add pinctrl node ARM: dts: r9a06g032: Correct the GIC DT node name arch/arm/boot/dts/emev2.dtsi | 2 +- arch/arm/boot/dts/r8a7740.dtsi| 2 +- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 119 arch/arm/boot/dts/r8a77470.dtsi | 222 +- arch/arm/boot/dts/r8a7790-lager.dts | 2 - arch/arm/boot/dts/r8a7791-koelsch.dts | 2 - arch/arm/boot/dts/r8a7791-porter.dts | 2 - arch/arm/boot/dts/r9a06g032.dtsi | 10 +- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 9 files changed, 352 insertions(+), 11 deletions(-)
Re: [PATCH 01/16] ARM: dts: r9a06g032: Add pinctrl node
On Mon, Nov 26, 2018 at 01:54:03PM +0100, Simon Horman wrote:
> From: Phil Edworthy
>
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy
> Geert Uytterhoeven
The tag above is garbled. I will fix this and repost this pull-request.
> Signed-off-by: Simon Horman
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi
> b/arch/arm/boot/dts/r9a06g032.dtsi
> index eaf94976ed6d..2322268bc862 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -165,6 +165,14 @@
> status = "disabled";
> };
>
> + pinctrl: pin-controller@40067000 {
> + compatible = "renesas,r9a06g032-pinctrl",
> "renesas,rzn1-pinctrl";
> + reg = <0x40067000 0x1000>, <0x5100 0x480>;
> + clocks = < R9A06G032_HCLK_PINCONFIG>;
> + clock-names = "bus";
> + status = "okay";
> + };
> +
> gic: gic@44101000 {
> compatible = "arm,cortex-a7-gic", "arm,gic-400";
> interrupt-controller;
> --
> 2.11.0
>
