[PATCH/RFT] arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMIC

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds the regulator definition required for operation of
S2RAM.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 62bdddc..3eee419 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -425,6 +425,26 @@
};
 };
 
+_dvfs {
+   status = "okay";
+
+   clock-frequency = <40>;
+
+   pmic: pmic@30 {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   compatible = "rohm,bd9571mwv";
+   reg = <0x30>;
+   interrupt-parent = <_ex>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   };
+};
+
  {
status = "okay";
 
@@ -480,6 +500,11 @@
function = "du";
};
 
+   irq0_pins: irq0 {
+   groups = "intc_ex_irq0";
+   function = "intc_ex";
+   };
+
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
-- 
1.9.1

[PATCH/RFT v2] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.

v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
  - Fix the definition of the hscif3_data_d_pins
  - Update the size of the sh_pfc_pin_group.common and the
sh_pfc_function.common

 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 370 +-
 1 file changed, 368 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 5d6a13f..6868753 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1626,6 +1626,290 @@ enum {
DU_DISP_MARK,
 };
 
+/* - HSCIF0 --*/
+static const unsigned int hscif0_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int hscif0_data_a_mux[] = {
+   HRX0_A_MARK, HTX0_A_MARK,
+};
+
+static const unsigned int hscif0_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int hscif0_clk_a_mux[] = {
+   HSCK0_A_MARK,
+};
+
+static const unsigned int hscif0_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int hscif0_ctrl_a_mux[] = {
+   HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+
+static const unsigned int hscif0_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int hscif0_data_b_mux[] = {
+   HRX0_B_MARK, HTX0_B_MARK,
+};
+
+static const unsigned int hscif0_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 13),
+};
+
+static const unsigned int hscif0_clk_b_mux[] = {
+   HSCK0_B_MARK,
+};
+
+/* - HSCIF1 - */
+static const unsigned int hscif1_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int hscif1_data_a_mux[] = {
+   HRX1_A_MARK, HTX1_A_MARK,
+};
+
+static const unsigned int hscif1_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int hscif1_clk_a_mux[] = {
+   HSCK1_A_MARK,
+};
+
+static const unsigned int hscif1_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int hscif1_data_b_mux[] = {
+   HRX1_B_MARK, HTX1_B_MARK,
+};
+
+static const unsigned int hscif1_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int hscif1_clk_b_mux[] = {
+   HSCK1_B_MARK,
+};
+
+static const unsigned int hscif1_ctrl_b_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int hscif1_ctrl_b_mux[] = {
+   HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+
+/* - HSCIF2 - */
+static const unsigned int hscif2_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int hscif2_data_a_mux[] = {
+   HRX2_A_MARK, HTX2_A_MARK,
+};
+
+static const unsigned int hscif2_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 14),
+};
+
+static const unsigned int hscif2_clk_a_mux[] = {
+   HSCK2_A_MARK,
+};
+
+static const unsigned int hscif2_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int hscif2_ctrl_a_mux[] = {
+   HRTS2_N_A_MARK, HCTS2_N_A_MARK,
+};
+
+static const unsigned int hscif2_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int hscif2_data_b_mux[] = {
+   HRX2_B_MARK, HTX2_B_MARK,
+};
+
+/* - HSCIF3 */
+static const unsigned int hscif3_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+
+static const unsigned int hscif3_data_a_mux[] = {
+   HRX3_A_MARK, HTX3_A_MARK,
+};
+
+static const unsigned int hscif3_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int hscif3_data_b_mux[] = {
+   HRX3_B_MARK, HTX3_B_MARK,
+};
+
+static const unsigned int hscif3_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(0, 4),
+};
+
+static const unsigned int hscif3_clk_b_mux[] = {
+   HSCK3_B_MARK,
+};
+
+static const unsigned int hscif3_data_c_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int hscif3_data_c_mux[] = {
+   HRX3_C_MARK, HTX3_C_MARK,
+};
+
+static const unsigned int hscif3_clk_c_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int hscif3_clk_c_mux

Re: [PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions

[Yoshihiro Kaneko]

Hi Geert-san,

Thanks for your review!!

2018年11月6日(火) 0:30 Geert Uytterhoeven :
>
> Hi Kaneko-san,
>
> On Sat, Oct 20, 2018 at 11:31 PM Yoshihiro Kaneko  
> wrote:
> > From: Takeshi Kihara 
> >
> > This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
> > the R8A77990 SoC.
> >
> > Signed-off-by: Takeshi Kihara 
> > Signed-off-by: Yoshihiro Kaneko 
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
> > +static const unsigned int hscif3_data_d_pins[] = {
> > +   /* RX, TX */
> > +   RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),
>
> These two pins are exchanged.
> According to the datasheet, it should be:
>
> RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),

I will fix it in v2.

>
> > +};
> > +
> > +static const unsigned int hscif3_data_d_mux[] = {
> > +   HRX3_D_MARK, HTX3_D_MARK,
> > +};
>
> > @@ -2454,6 +2738,37 @@ enum {
> > SH_PFC_PIN_GROUP(du_disp_cde),
> > SH_PFC_PIN_GROUP(du_cde),
> > SH_PFC_PIN_GROUP(du_disp),
> > +   SH_PFC_PIN_GROUP(hscif0_data_a),
> > +   SH_PFC_PIN_GROUP(hscif0_clk_a),
> > +   SH_PFC_PIN_GROUP(hscif0_ctrl_a),
> > +   SH_PFC_PIN_GROUP(hscif0_data_b),
> > +   SH_PFC_PIN_GROUP(hscif0_clk_b),
> > +   SH_PFC_PIN_GROUP(hscif1_data_a),
> > +   SH_PFC_PIN_GROUP(hscif1_clk_a),
> > +   SH_PFC_PIN_GROUP(hscif1_data_b),
> > +   SH_PFC_PIN_GROUP(hscif1_clk_b),
> > +   SH_PFC_PIN_GROUP(hscif1_ctrl_b),
> > +   SH_PFC_PIN_GROUP(hscif2_data_a),
> > +   SH_PFC_PIN_GROUP(hscif2_clk_a),
> > +   SH_PFC_PIN_GROUP(hscif2_ctrl_a),
> > +   SH_PFC_PIN_GROUP(hscif2_data_b),
> > +   SH_PFC_PIN_GROUP(hscif3_data_a),
> > +   SH_PFC_PIN_GROUP(hscif3_data_b),
> > +   SH_PFC_PIN_GROUP(hscif3_clk_b),
> > +   SH_PFC_PIN_GROUP(hscif3_data_c),
> > +   SH_PFC_PIN_GROUP(hscif3_clk_c),
> > +   SH_PFC_PIN_GROUP(hscif3_ctrl_c),
> > +   SH_PFC_PIN_GROUP(hscif3_data_d),
> > +   SH_PFC_PIN_GROUP(hscif3_data_e),
> > +   SH_PFC_PIN_GROUP(hscif3_ctrl_e),
> > +   SH_PFC_PIN_GROUP(hscif4_data_a),
> > +   SH_PFC_PIN_GROUP(hscif4_clk_a),
> > +   SH_PFC_PIN_GROUP(hscif4_ctrl_a),
> > +   SH_PFC_PIN_GROUP(hscif4_data_b),
> > +   SH_PFC_PIN_GROUP(hscif4_clk_b),
> > +   SH_PFC_PIN_GROUP(hscif4_data_c),
> > +   SH_PFC_PIN_GROUP(hscif4_data_d),
> > +   SH_PFC_PIN_GROUP(hscif4_data_e),
> > SH_PFC_PIN_GROUP(i2c1_a),
> > SH_PFC_PIN_GROUP(i2c1_b),
> > SH_PFC_PIN_GROUP(i2c1_c),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_groups.common[] array.

I will fix it.

>
> > @@ -2781,6 +3142,11 @@ enum {
> > .common = {
> > SH_PFC_FUNCTION(avb),
> > SH_PFC_FUNCTION(du),
> > +   SH_PFC_FUNCTION(hscif0),
> > +   SH_PFC_FUNCTION(hscif1),
> > +   SH_PFC_FUNCTION(hscif2),
> > +   SH_PFC_FUNCTION(hscif3),
> > +   SH_PFC_FUNCTION(hscif4),
> > SH_PFC_FUNCTION(i2c1),
> > SH_PFC_FUNCTION(i2c2),
> > SH_PFC_FUNCTION(i2c4),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_functions.common[] array.

I will fix it.


Best regards,
Kaneko

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

[PATCH/RFT] arm64: dts: renesas: r8a77990-ebisu: Enable i2c

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch enables I2C3 channels for the r8a77990-ebisu.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 611f026..4a596ef 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -294,6 +294,10 @@
clock-names = "fck", "dclkin.0", "extal";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77990: Enable I2C DMA

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch enables I2C DMA.

NOTE: I2C7 DMA is not supported by R-Car Gen3 Hardware User's Manual
Rev.0.80E.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index a437862..9df0751 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -213,6 +213,9 @@
clocks = < CPG_MOD 931>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 931>;
+   dmas = < 0x91>, < 0x90>,
+  < 0x91>, < 0x90>;
+   dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@@ -227,6 +230,9 @@
clocks = < CPG_MOD 930>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 930>;
+   dmas = < 0x93>, < 0x92>,
+  < 0x93>, < 0x92>;
+   dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -241,6 +247,9 @@
clocks = < CPG_MOD 929>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 929>;
+   dmas = < 0x95>, < 0x94>,
+  < 0x95>, < 0x94>;
+   dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -255,6 +264,8 @@
clocks = < CPG_MOD 928>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 928>;
+   dmas = < 0x97>, < 0x96>;
+   dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@@ -269,6 +280,8 @@
clocks = < CPG_MOD 927>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 927>;
+   dmas = < 0x99>, < 0x98>;
+   dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -283,6 +296,8 @@
clocks = < CPG_MOD 919>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 919>;
+   dmas = < 0x9b>, < 0x9a>;
+   dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@@ -297,6 +312,8 @@
clocks = < CPG_MOD 918>;
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 918>;
+   dmas = < 0x9d>, < 0x9c>;
+   dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add I2C-DVFS device node

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds I2C-DVFS device node for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 9df0751..5d9905f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -22,7 +22,8 @@
i2c4 = 
i2c5 = 
i2c6 = 
-   i2c7 = 
+   i2c7 = _dvfs;
+   i2c8 = 
};
 
cpus {
@@ -337,6 +338,22 @@
reg = <0 0xe606 0 0x508>;
};
 
+   i2c_dvfs: i2c@e60b {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,iic-r8a77990",
+"renesas,rcar-gen3-iic",
+"renesas,rmobile-iic";
+   reg = <0 0xe60b 0 0x34>;
+   interrupts = ;
+   clocks = < CPG_MOD 926>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 926>;
+   dmas = < 0x11>, < 0x10>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77990-ebisu: Add serial console pins

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds pin control for SCIF2.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index f342dd8..611f026 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -321,6 +321,11 @@
function = "pwm5";
};
 
+   scif2_pins: scif2 {
+   groups = "scif2_data_a";
+   function = "scif2";
+   };
+
usb0_pins: usb {
groups = "usb0_b";
function = "usb0";
@@ -352,6 +357,9 @@
 };
 
  {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
status = "okay";
 };
 
-- 
1.9.1

[PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.

 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 366 ++
 1 file changed, 366 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fdafa4..0d0153a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1459,6 +1459,290 @@ enum {
DU_DISP_MARK,
 };
 
+/* - HSCIF0 --*/
+static const unsigned int hscif0_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int hscif0_data_a_mux[] = {
+   HRX0_A_MARK, HTX0_A_MARK,
+};
+
+static const unsigned int hscif0_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int hscif0_clk_a_mux[] = {
+   HSCK0_A_MARK,
+};
+
+static const unsigned int hscif0_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int hscif0_ctrl_a_mux[] = {
+   HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+
+static const unsigned int hscif0_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int hscif0_data_b_mux[] = {
+   HRX0_B_MARK, HTX0_B_MARK,
+};
+
+static const unsigned int hscif0_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 13),
+};
+
+static const unsigned int hscif0_clk_b_mux[] = {
+   HSCK0_B_MARK,
+};
+
+/* - HSCIF1 - */
+static const unsigned int hscif1_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int hscif1_data_a_mux[] = {
+   HRX1_A_MARK, HTX1_A_MARK,
+};
+
+static const unsigned int hscif1_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int hscif1_clk_a_mux[] = {
+   HSCK1_A_MARK,
+};
+
+static const unsigned int hscif1_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int hscif1_data_b_mux[] = {
+   HRX1_B_MARK, HTX1_B_MARK,
+};
+
+static const unsigned int hscif1_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int hscif1_clk_b_mux[] = {
+   HSCK1_B_MARK,
+};
+
+static const unsigned int hscif1_ctrl_b_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int hscif1_ctrl_b_mux[] = {
+   HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+
+/* - HSCIF2 - */
+static const unsigned int hscif2_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int hscif2_data_a_mux[] = {
+   HRX2_A_MARK, HTX2_A_MARK,
+};
+
+static const unsigned int hscif2_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 14),
+};
+
+static const unsigned int hscif2_clk_a_mux[] = {
+   HSCK2_A_MARK,
+};
+
+static const unsigned int hscif2_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int hscif2_ctrl_a_mux[] = {
+   HRTS2_N_A_MARK, HCTS2_N_A_MARK,
+};
+
+static const unsigned int hscif2_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int hscif2_data_b_mux[] = {
+   HRX2_B_MARK, HTX2_B_MARK,
+};
+
+/* - HSCIF3 */
+static const unsigned int hscif3_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+
+static const unsigned int hscif3_data_a_mux[] = {
+   HRX3_A_MARK, HTX3_A_MARK,
+};
+
+static const unsigned int hscif3_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int hscif3_data_b_mux[] = {
+   HRX3_B_MARK, HTX3_B_MARK,
+};
+
+static const unsigned int hscif3_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(0, 4),
+};
+
+static const unsigned int hscif3_clk_b_mux[] = {
+   HSCK3_B_MARK,
+};
+
+static const unsigned int hscif3_data_c_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int hscif3_data_c_mux[] = {
+   HRX3_C_MARK, HTX3_C_MARK,
+};
+
+static const unsigned int hscif3_clk_c_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int hscif3_clk_c_mux[] = {
+   HSCK3_C_MARK,
+};
+
+static const unsigned int hscif3_ctrl_c_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
+};
+
+static const unsigned int hscif3_ctrl_c_mux

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add SCIF-{0,1,3,4,5} device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 83 +++
 1 file changed, 83 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6d5efeb..f969e68 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -679,6 +679,40 @@
status = "disabled";
};
 
+   scif0: serial@e6e6 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e6 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 207>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x51>, < 0x50>,
+  < 0x51>, < 0x50>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 207>;
+   status = "disabled";
+   };
+
+   scif1: serial@e6e68000 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e68000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 206>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x53>, < 0x52>,
+  < 0x53>, < 0x52>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 206>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -694,6 +728,55 @@
status = "disabled";
};
 
+   scif3: serial@e6c5 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c5 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 204>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x57>, < 0x56>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 204>;
+   status = "disabled";
+   };
+
+   scif4: serial@e6c4 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c4 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 203>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x59>, < 0x58>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 203>;
+   status = "disabled";
+   };
+
+   scif5: serial@e6f3 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "rene

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add all HSCIF nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds the device nodes for all HSCIF serial ports to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 88 +++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index f969e68..a437862 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -357,6 +357,94 @@
resets = < 407>;
};
 
+   hscif0: serial@e654 {
+   compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe654 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 520>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x31>, < 0x30>,
+  < 0x31>, < 0x30>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 520>;
+   status = "disabled";
+   };
+
+   hscif1: serial@e655 {
+   compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe655 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 519>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x33>, < 0x32>,
+  < 0x33>, < 0x32>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 519>;
+   status = "disabled";
+   };
+
+   hscif2: serial@e656 {
+   compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe656 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 518>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x35>, < 0x34>,
+  < 0x35>, < 0x34>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 518>;
+   status = "disabled";
+   };
+
+   hscif3: serial@e66a {
+   compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe66a 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 517>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x37>, < 0x36>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 517>;
+   status = "disabled";
+   };
+
+   hscif4: serial@e66b {
+   compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";

[PATCH/RFT] arm64: dts: renesas: r8a77990: add thermal device support

[Yoshihiro Kaneko]

This patch adds the thermal device node and the thermal-zone for
the R8A77990 SoC.

Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 7278cd5..5381466 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -341,6 +341,18 @@
#power-domain-cells = <1>;
};
 
+   thermal: thermal@e619 {
+   compatible = "renesas,thermal-r8a77990";
+   reg = <0 0xe619 0 0x10>, <0 0xe6190100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+
intc_ex: interrupt-controller@e61c {
compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
#interrupt-cells = <2>;
@@ -1063,6 +1075,25 @@
};
};
 
+   thermal-zones {
+   cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   };
+   };
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
-- 
1.9.1

[PATCH/RFT 2/2] thermal: rcar_thermal: add R8A77990 support

[Yoshihiro Kaneko]

Add support for R-Car E3 (R8A77990) thermal support.

Signed-off-by: Yoshihiro Kaneko 
---
 drivers/thermal/rcar_thermal.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 78f9328..b1bc5c1 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -113,6 +113,10 @@ struct rcar_thermal_priv {
 .data = _gen2_thermal,
},
{
+   .compatible = "renesas,thermal-r8a77990",
+   .data = _gen3_thermal,
+   },
+   {
.compatible = "renesas,thermal-r8a77995",
.data = _gen3_thermal,
},
-- 
1.9.1

[PATCH/RFT 0/2] thermal: add suport for R8A77990

[Yoshihiro Kaneko]

This series adds thermal support for R-Car E3 (R8A77990).

This series is based on the next branch of Eduardo Valentin's linux-soc-thermal
tree.

Yoshihiro Kaneko (2):
  dt-bindings: thermal: rcar-thermal: add R8A77990 support
  thermal: rcar_thermal: add R8A77990 support

 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 5 +++--
 drivers/thermal/rcar_thermal.c | 4 
 2 files changed, 7 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH/RFT 1/2] dt-bindings: thermal: rcar-thermal: add R8A77990 support

[Yoshihiro Kaneko]

Document the R-Car E3 (R8A77990) SoC bindings.

Signed-off-by: Yoshihiro Kaneko 
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 67c563f..18353b9 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible   : "renesas,thermal-",
   "renesas,rcar-gen2-thermal" (with thermal-zone) or
   "renesas,rcar-thermal" (without thermal-zone) as
-   fallback except R-Car D3.
+   fallback except R-Car E3/D3.
  Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -13,6 +13,7 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77990" (R-Car E3)
- "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
@@ -21,7 +22,7 @@ Required properties:
 Option properties:
 
 - interrupts   : If present should contain 3 interrupts for
-  R-Car D3 or 1 interrupt otherwise.
+  R-Car E3/D3 or 1 interrupt otherwise.
 
 Example (non interrupt support):
 
-- 
1.9.1

[PATCH] arm64: dts: renesas: r8a77990: Add DMA properties to MSIOF nodes

[Yoshihiro Kaneko]

This patch adds DMA properties to the MSIOF device nodes of R8A77990 SoC.

Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 7278cd5..6d5efeb 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -700,6 +700,9 @@
reg = <0 0xe6e9 0 0x0064>;
interrupts = ;
clocks = < CPG_MOD 211>;
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 211>;
#address-cells = <1>;
@@ -713,6 +716,9 @@
reg = <0 0xe6ea 0 0x0064>;
interrupts = ;
clocks = < CPG_MOD 210>;
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 210>;
#address-cells = <1>;
@@ -726,6 +732,8 @@
reg = <0 0xe6c0 0 0x0064>;
interrupts = ;
clocks = < CPG_MOD 209>;
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 209>;
#address-cells = <1>;
@@ -739,6 +747,8 @@
reg = <0 0xe6c1 0 0x0064>;
interrupts = ;
clocks = < CPG_MOD 208>;
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 208>;
#address-cells = <1>;
-- 
1.9.1

[PATCH v2] ASoC: rsnd: Add device tree binding for r8a77990

[Yoshihiro Kaneko]

From: Hiroyuki Yokoyama 

This patch adds the device tree binding of the r8a77990 SoC.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

v2 [Yoshihiro Kaneko]
- Rebased

 Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt 
b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index 9e764270..58971a6 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -353,6 +353,7 @@ Required properties:
- "renesas,rcar_sound-r8a7795" (R-Car H3)
- "renesas,rcar_sound-r8a7796" (R-Car M3-W)
- "renesas,rcar_sound-r8a77965" (R-Car M3-N)
+   - "renesas,rcar_sound-r8a77990" (R-Car E3)
 - reg  : Should contain the register physical address.
  required register is
   SRU/ADG/SSI  if generation1
-- 
1.9.1

Re: [PATCH] ASoC: rsnd: Add device tree binding for r8a77990

[Yoshihiro Kaneko]

Hi Mark,

2018年8月29日(水) 5:21 Mark Brown :
>
> On Fri, Aug 17, 2018 at 04:53:55PM +0900, Yoshihiro Kaneko wrote:
> > From: Hiroyuki Yokoyama 
> >
> > This patch adds the device tree binding of the r8a77990 SoC.
>
> This doesn't apply against current code, please check and resend.

I will rebase this patch and resend.

Best regards,
Kaneko

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add all MSIOF device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds the device nodes for all MSIOF SPI controllers to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 80 +++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 09e7b2f..438dd3a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -14,6 +14,13 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   aliases {
+   spi0 = 
+   spi1 = 
+   spi2 = 
+   spi3 = 
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -70,6 +77,13 @@
clock-frequency = <0>;
};
 
+   /* MSIOF reference clock - to be overridden by boards that provide it */
+   msiof_ref_clk: msiof-ref-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -218,6 +232,72 @@
#power-domain-cells = <1>;
};
 
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>, <_ref_clk>;
+   clock-names = "msiof_clk", "msiof_ref_clk";
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>, <_ref_clk>;
+   clock-names = "msiof_clk", "msiof_ref_clk";
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>, <_ref_clk>;
+   clock-names = "msiof_clk", "msiof_ref_clk";
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>, <_ref_clk>;
+   clock-names = "msiof_clk", "msiof_ref_clk";
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a77990",
 "renesas,rcar-dmac";
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 102 ++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6198768..09e7b2f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -218,6 +218,108 @@
#power-domain-cells = <1>;
};
 
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 219>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac1: dma-controller@e730 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe730 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 218>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac2: dma-controller@e731 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe731 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 217>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 217>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
ipmmu_ds0: mmu@e674 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe674 0 0x1000>;
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77995-draak: Add MSIOF ch2 pins support

[Yoshihiro Kaneko]

From: Hiromitsu Yamasaki 

This patch adds support for MSIOF ch2 pinctrl to use the LVDS Control
Connector (CN41) for the Draak board on the R8A77995 SoC.

Signed-off-by: Hiromitsu Yamasaki 
Signed-off-by: Takeshi Kihara 
[ykaneko0...@gmail.com: deleted the unused reference to 'msiof_ref_clk']
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f26..e60b1e4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -135,6 +135,12 @@
function = "i2c1";
};
 
+   msiof2_pins: spi2 {
+   groups = "msiof2_clk", "msiof2_sync_b",
+"msiof2_rxd",  "msiof2_txd";
+   function = "msiof2";
+   };
+
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
@@ -371,3 +377,10 @@
};
};
 };
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   /* In case of using this node, please enable this property */
+   /* status = "okay"; */
+};
-- 
1.9.1

[PATCH] ASoC: rsnd: Add device tree binding for r8a77990

[Yoshihiro Kaneko]

From: Hiroyuki Yokoyama 

This patch adds the device tree binding of the r8a77990 SoC.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt 
b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index b86d790..07aba8d 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -352,6 +352,7 @@ Required properties:
- "renesas,rcar_sound-r8a7794" (R-Car E2)
- "renesas,rcar_sound-r8a7795" (R-Car H3)
- "renesas,rcar_sound-r8a7796" (R-Car M3-W)
+   - "renesas,rcar_sound-r8a77990" (R-Car E3)
 - reg  : Should contain the register physical address.
  required register is
   SRU/ADG/SSI  if generation1
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add Audio-DMAC and Sound device nodes

[Yoshihiro Kaneko]

This patch adds Audio-DMAC0 device node and Sound device node
for the R8A77990 SoC.

The following patches were squashed into this patch:
* Takeshi Kihara 
  arm64: dts: r8a77990: Add Audio-DMAC device nodes
  arm64: dts: r8a77990: Add Sound device node and SSI support
  arm64: dts: r8a77990: Add Sound SRC support
  arm64: dts: r8a77990: Add Sound DVC device nodes
  arm64: dts: r8a77990: Add Sound CTU support
  arm64: dts: r8a77990: Add Sound MIX support
* Hai Nguyen Pham 
  arm64: dts: r8a77990: Tie Audio-DMAC to IPMMU-MP

Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 273 +-
 1 file changed, 272 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 2ee0edf..bc64e0f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -5,7 +5,7 @@
  * Copyright (C) 2018 Renesas Electronics Corp.
  */
 
-#include 
+#include 
 #include 
 #include 
 
@@ -14,6 +14,29 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+   audio_clk_a: audio_clk_a {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_b: audio_clk_b {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_c: audio_clk_c {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -419,6 +442,254 @@
status = "disabled";
};
 
+   rcar_sound: sound@ec50 {
+   /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi  DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+   /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout   : #clock-cells = <0>;   <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>;   <_sound N>;
+*/
+   compatible =  "renesas,rcar_sound-r8a77990", 
"renesas,rcar_sound-gen3";
+   reg =   <0 0xec50 0 0x1000>, /* SCU */
+   <0 0xec5a 0 0x100>,  /* ADG */
+   <0 0xec54 0 0x1000>, /* SSIU */
+   <0 0xec541000 0 0x280>,  /* SSI */
+   <0 0xec76 0 0x200>;  /* Audio DMAC peri 
peri*/
+   reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+   clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE R8A77990_CLK_ZA2>;
+   clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4&qu

[PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

[Yoshihiro Kaneko]

From: Dien Pham 

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 52205be..c5fb35b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp@16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

[Yoshihiro Kaneko]

From: Dien Pham 

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0a64b72..28dcbb6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp@16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
1.9.1

[PATCH] ASoC: rsnd: Document R-Car M3-N support

[Yoshihiro Kaneko]

From: Hiroyuki Yokoyama 

Document support for the sound modules in the Renesas M3-N (r8a77965)
SoC.

No driver update is needed.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt 
b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index b86d790..9e764270 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -352,6 +352,7 @@ Required properties:
- "renesas,rcar_sound-r8a7794" (R-Car E2)
- "renesas,rcar_sound-r8a7795" (R-Car H3)
- "renesas,rcar_sound-r8a7796" (R-Car M3-W)
+   - "renesas,rcar_sound-r8a77965" (R-Car M3-N)
 - reg  : Should contain the register physical address.
  required register is
   SRU/ADG/SSI  if generation1
-- 
1.9.1

[PATCH/RFT] arm64: dts: renesas: r8a77965: Add Sound and Audio DMAC device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

The following patches were squashed into this patch:

  arm64: dts: r8a77965: Add Audio-DMAC device nodes
  arm64: dts: r8a77965: Add Sound device node and SSI support
  arm64: dts: r8a77965: Add Sound SRC support
  arm64: dts: r8a77965: Add Sound DVC device nodes
  arm64: dts: r8a77965: Add Sound CTU support
  arm64: dts: r8a77965: Add Sound MIX support

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 245 --
 1 file changed, 234 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd4446..0a64b72 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -12,7 +12,7 @@
 #include 
 #include 
 
-#define CPG_AUDIO_CLK_I10
+#define CPG_AUDIO_CLK_IR8A77965_CLK_S0D4
 
 / {
compatible = "renesas,r8a77965";
@@ -1324,46 +1324,269 @@
};
 
rcar_sound: sound@ec50 {
+   /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi  DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+   /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout   : #clock-cells = <0>;   <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>;   <_sound N>;
+*/
+   compatible =  "renesas,rcar_sound-r8a77965", 
"renesas,rcar_sound-gen3";
reg =   <0 0xec50 0 0x1000>, /* SCU */
<0 0xec5a 0 0x100>,  /* ADG */
<0 0xec54 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>,  /* SSI */
<0 0xec74 0 0x200>;  /* Audio DMAC peri 
peri*/
-   /* placeholder */
+   reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+   clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE R8A77965_CLK_S0D4>;
+   clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 1005>,
+

Re: [PATCH/RFT 0/7] rsnd: add support for r8a77965

[Yoshihiro Kaneko]

Hi Simon-san,

2018-07-24 1:21 GMT+09:00 Simon Horman :
> On Wed, Jul 18, 2018 at 04:47:56AM +0900, Yoshihiro Kaneko wrote:
>> This series adds sound support for r8a77965 (R-Car M3-N).
>> This series is based on the devel branch of Simon Horman's renesas tree.
>>
>> Hiroyuki Yokoyama (1):
>>   ASoC: rsnd: Document R-Car M3-N support
>>
>> Takeshi Kihara (6):
>>   arm64: dts: renesas: r8a77965: Add Audio-DMAC device nodes
>>   arm64: dts: renesas: r8a77965: Add Sound device node and SSI support
>>   arm64: dts: renesas: r8a77965: Add Sound SRC support
>>   arm64: dts: renesas: r8a77965: Add Sound DVC device nodes
>>   arm64: dts: renesas: r8a77965: Add Sound CTU support
>>   arm64: dts: renesas: r8a77965: Add Sound MIX support
>>
>>  .../devicetree/bindings/sound/renesas,rsnd.txt |   1 +
>>  arch/arm64/boot/dts/renesas/r8a77965.dtsi  | 245 
>> -
>
> Thanks Kaneko-san,
>
> in general this series looks good, however, I would like to ask you to
> squash all the dts patches (the patches by Kihara-san) into a single patch.
>
> For many years now we have split patches up as this series does.
> And no doubt that is why BPS team chose to split up the patches
> that you have based this patchset on. However, we were recently
> asked by the Olof Johansson to squash patches together to make
> the high-level intent of patches clearer to him in his position
> of ARM-SoC co-maintainer.
>
> So while what you have done is correct, it is now the "old way".
> Please squash the patches together as this is the "new way".

Thank you for the detailed explanation.
I will do it.

>
> Thanks!

Best regards,
Kaneko

Re: [PATCH/RFT 3/7] arm64: dts: renesas: r8a77965: Add Sound device node and SSI support

[Yoshihiro Kaneko]

Hi Morimoto-san,

Thank you for your review.

2018-07-20 8:23 GMT+09:00 Kuninori Morimoto :
>
> Hi
>
>> From: Takeshi Kihara 
>>
>> Based on several similar patches of the R8A7796 device tree
>> by Kuninori Morimoto .
>>
>> Signed-off-by: Takeshi Kihara 
>> Signed-off-by: Yoshihiro Kaneko 
>> ---
> (snip)
>>   rcar_sound: sound@ec50 {
>> + /*
>> +  * #sound-dai-cells is required
>> +  *
>> +  * Single DAI : #sound-dai-cells = <0>; <_sound>;
>> +  * Multi  DAI : #sound-dai-cells = <1>; <_sound 
>> N>;
>> +  */
>> + /*
>> +  * #clock-cells is required for audio_clkout0/1/2/3
>> +  *
>> +  * clkout   : #clock-cells = <0>;   <_sound>;
>> +  * clkout0/1/2/3: #clock-cells = <1>;   <_sound 
>> N>;
>> +  */
>> + compatible =  "renesas,rcar_sound-r8a7796", 
>> "renesas,rcar_sound-gen3";
>
> 77965 ?

Will fix.

>
> Acked-by: Kuninori Morimoto 

Best regards,
Kaneko

Re: [PATCH/RFT 2/7] ASoC: rsnd: Document R-Car M3-N support

[Yoshihiro Kaneko]

Hi Morimoto-san,

Thank you for your review.
I will exclude this patch from the series and repost this as a single
patch to ALSA SoC ML.

Best regards,
Kaneko

2018-07-20 8:12 GMT+09:00 Kuninori Morimoto :
>
> Hi
>
> Thnak you for your patch
>
>> From: Hiroyuki Yokoyama 
>>
>> Document support for the sound modules in the Renesas M3-N (r8a77965)
>> SoC.
>>
>> No driver update is needed.
>>
>> Signed-off-by: Hiroyuki Yokoyama 
>> Signed-off-by: Yoshihiro Kaneko 
>> ---
>
> Acked-by: Kuninori Morimoto 
>
> But, I think this patch should go to ALSA SoC ML.
>
>
>>  Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt 
>> b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
>> index b86d790..9e764270 100644
>> --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
>> +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
>> @@ -352,6 +352,7 @@ Required properties:
>>   - "renesas,rcar_sound-r8a7794" (R-Car E2)
>>   - "renesas,rcar_sound-r8a7795" (R-Car H3)
>>   - "renesas,rcar_sound-r8a7796" (R-Car M3-W)
>> + - "renesas,rcar_sound-r8a77965" (R-Car 
>> M3-N)
>>  - reg: Should contain the register physical 
>> address.
>> required register is
>>  SRU/ADG/SSI  if generation1
>> --
>> 1.9.1
>>

Re: [PATCH/RFT 1/7] arm64: dts: renesas: r8a77965: Add Audio-DMAC device nodes

[Yoshihiro Kaneko]

Hi Geert-san,

Thank you for your review.
I will correct the sort order of the audma nodes and  a typo of the commit log.

Best regards,
Kaneko

2018-07-18 18:06 GMT+09:00 Geert Uytterhoeven :
> On Tue, Jul 17, 2018 at 9:48 PM Yoshihiro Kaneko  
> wrote:
>> From: Takeshi Kihara 
>>
>> This patch adds Audio-DMAC{0,1} device nodes for the R8A77965 SoC.
>>
>> Based on a similar patch of the R8A7796 device tree
>> by uninori Morimoto .
>
> Kuninori
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

[PATCH/RFT 2/7] ASoC: rsnd: Document R-Car M3-N support

[Yoshihiro Kaneko]

From: Hiroyuki Yokoyama 

Document support for the sound modules in the Renesas M3-N (r8a77965)
SoC.

No driver update is needed.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---
 Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt 
b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index b86d790..9e764270 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -352,6 +352,7 @@ Required properties:
- "renesas,rcar_sound-r8a7794" (R-Car E2)
- "renesas,rcar_sound-r8a7795" (R-Car H3)
- "renesas,rcar_sound-r8a7796" (R-Car M3-W)
+   - "renesas,rcar_sound-r8a77965" (R-Car M3-N)
 - reg  : Should contain the register physical address.
  required register is
   SRU/ADG/SSI  if generation1
-- 
1.9.1

[PATCH/RFT 5/7] arm64: dts: renesas: r8a77965: Add Sound DVC device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 91cb50f..61140e1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1355,6 +1355,7 @@
 < CPG_MOD 1026>, < CPG_MOD 1027>,
 < CPG_MOD 1028>, < CPG_MOD 1029>,
 < CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
 <_clk_a>, <_clk_b>,
 <_clk_c>,
 < CPG_CORE R8A77965_CLK_S0D4>;
@@ -1365,6 +1366,7 @@
  "src.9", "src.8", "src.7", "src.6",
  "src.5", "src.4", "src.3", "src.2",
  "src.1", "src.0",
+ "dvc.0", "dvc.1",
  "clk_a", "clk_b", "clk_c", "clk_i";
power-domains = < R8A77965_PD_ALWAYS_ON>;
resets = < 1005>,
@@ -1379,6 +1381,17 @@
  "ssi.1", "ssi.0";
status = "disabled";
 
+   rcar_sound,dvc {
+   dvc0: dvc-0 {
+   dmas = < 0xbc>;
+   dma-names = "tx";
+   };
+   dvc1: dvc-1 {
+   dmas = < 0xbe>;
+   dma-names = "tx";
+   };
+   };
+
rcar_sound,src {
src0: src-0 {
interrupts = ;
-- 
1.9.1

[PATCH/RFT 3/7] arm64: dts: renesas: r8a77965: Add Sound device node and SSI support

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on several similar patches of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 109 +++---
 1 file changed, 85 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index c0dbabd..c5d6ab4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -12,7 +12,7 @@
 #include 
 #include 
 
-#define CPG_AUDIO_CLK_I10
+#define CPG_AUDIO_CLK_IR8A77965_CLK_S0D4
 
 / {
compatible = "renesas,r8a77965";
@@ -1324,42 +1324,103 @@
};
 
rcar_sound: sound@ec50 {
+   /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi  DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+   /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout   : #clock-cells = <0>;   <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>;   <_sound N>;
+*/
+   compatible =  "renesas,rcar_sound-r8a7796", 
"renesas,rcar_sound-gen3";
reg =   <0 0xec50 0 0x1000>, /* SCU */
<0 0xec5a 0 0x100>,  /* ADG */
<0 0xec54 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>,  /* SSI */
<0 0xec74 0 0x200>;  /* Audio DMAC peri 
peri*/
-   /* placeholder */
+   reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+   clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+<_clk_a>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE R8A77965_CLK_S0D4>;
+   clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 1005>,
+< 1006>, < 1007>,
+< 1008>, < 1009>,
+< 1010>, < 1011>,
+< 1012>, < 1013>,
+< 1014>, < 1015>;
+   reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+   status = "disabled";
 
-   rcar_sound,dvc {
-   dvc0: dvc-0 {
+   rcar_sound,ssi {
+   ssi0: ssi-0 {
+   interrupts = ;
+   dmas = < 0x01>, < 0x02>, 
< 0x15>, < 0x16>;
+   dma-names = "rx", "tx", "rxu", "txu";
};
-   dvc1: dvc-1 {
+   ssi1: ssi-1 {
+   interrupts = ;
+   dmas = < 0x03>, < 0x04>, 
< 0x49>, < 0x4a>;
+   dma-names = "rx", "tx", "rxu", "txu";
  

[PATCH/RFT 7/7] arm64: dts: renesas: r8a77965: Add Sound MIX support

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 2188ad2..56303ac 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1356,6 +1356,7 @@
 < CPG_MOD 1028>, < CPG_MOD 1029>,
 < CPG_MOD 1030>, < CPG_MOD 1031>,
 < CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
 < CPG_MOD 1019>, < CPG_MOD 1018>,
 <_clk_a>, <_clk_b>,
 <_clk_c>,
@@ -1367,6 +1368,7 @@
  "src.9", "src.8", "src.7", "src.6",
  "src.5", "src.4", "src.3", "src.2",
  "src.1", "src.0",
+ "mix.1", "mix.0",
  "ctu.1", "ctu.0",
  "dvc.0", "dvc.1",
  "clk_a", "clk_b", "clk_c", "clk_i";
@@ -1394,6 +1396,11 @@
};
};
 
+   rcar_sound,mix {
+   mix0: mix-0 { };
+   mix1: mix-1 { };
+   };
+
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
-- 
1.9.1

[PATCH/RFT 6/7] arm64: dts: renesas: r8a77965: Add Sound CTU support

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 61140e1..2188ad2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1355,6 +1355,7 @@
 < CPG_MOD 1026>, < CPG_MOD 1027>,
 < CPG_MOD 1028>, < CPG_MOD 1029>,
 < CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
 < CPG_MOD 1019>, < CPG_MOD 1018>,
 <_clk_a>, <_clk_b>,
 <_clk_c>,
@@ -1366,6 +1367,7 @@
  "src.9", "src.8", "src.7", "src.6",
  "src.5", "src.4", "src.3", "src.2",
  "src.1", "src.0",
+ "ctu.1", "ctu.0",
  "dvc.0", "dvc.1",
  "clk_a", "clk_b", "clk_c", "clk_i";
power-domains = < R8A77965_PD_ALWAYS_ON>;
@@ -1392,6 +1394,17 @@
};
};
 
+   rcar_sound,ctu {
+   ctu00: ctu-0 { };
+   ctu01: ctu-1 { };
+   ctu02: ctu-2 { };
+   ctu03: ctu-3 { };
+   ctu10: ctu-4 { };
+   ctu11: ctu-5 { };
+   ctu12: ctu-6 { };
+   ctu13: ctu-7 { };
+   };
+
rcar_sound,src {
src0: src-0 {
interrupts = ;
-- 
1.9.1

[PATCH/RFT 1/7] arm64: dts: renesas: r8a77965: Add Audio-DMAC device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds Audio-DMAC{0,1} device nodes for the R8A77965 SoC.

Based on a similar patch of the R8A7796 device tree
by uninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 +++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd4446..c0dbabd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1386,6 +1386,74 @@
status = "disabled";
};
 
+   audma0: dma-controller@ec70 {
+   compatible = "renesas,dmac-r8a77965",
+"renesas,rcar-dmac";
+   reg = <0 0xec70 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 502>;
+   clock-names = "fck";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 502>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   audma1: dma-controller@ec72 {
+   compatible = "renesas,dmac-r8a77965",
+"renesas,rcar-dmac";
+   reg = <0 0xec72 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 501>;
+   clock-names = "fck";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 501>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
ohci0: usb@ee08 {
compatible = "generic-ohci";
reg = <0 0xee08 0 0x100>;
-- 
1.9.1

[PATCH/RFT 0/7] rsnd: add support for r8a77965

[Yoshihiro Kaneko]

This series adds sound support for r8a77965 (R-Car M3-N).
This series is based on the devel branch of Simon Horman's renesas tree.

Hiroyuki Yokoyama (1):
  ASoC: rsnd: Document R-Car M3-N support

Takeshi Kihara (6):
  arm64: dts: renesas: r8a77965: Add Audio-DMAC device nodes
  arm64: dts: renesas: r8a77965: Add Sound device node and SSI support
  arm64: dts: renesas: r8a77965: Add Sound SRC support
  arm64: dts: renesas: r8a77965: Add Sound DVC device nodes
  arm64: dts: renesas: r8a77965: Add Sound CTU support
  arm64: dts: renesas: r8a77965: Add Sound MIX support

 .../devicetree/bindings/sound/renesas,rsnd.txt |   1 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi  | 245 -
 2 files changed, 235 insertions(+), 11 deletions(-)

-- 
1.9.1

[PATCH/RFT 4/7] arm64: dts: renesas: r8a77965: Add Sound SRC support

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 61 +++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index c5d6ab4..91cb50f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1350,6 +1350,11 @@
 < CPG_MOD 1010>, < CPG_MOD 1011>,
 < CPG_MOD 1012>, < CPG_MOD 1013>,
 < CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
 <_clk_a>, <_clk_b>,
 <_clk_c>,
 < CPG_CORE R8A77965_CLK_S0D4>;
@@ -1357,6 +1362,9 @@
  "ssi.9", "ssi.8", "ssi.7", "ssi.6",
  "ssi.5", "ssi.4", "ssi.3", "ssi.2",
  "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
  "clk_a", "clk_b", "clk_c", "clk_i";
power-domains = < R8A77965_PD_ALWAYS_ON>;
resets = < 1005>,
@@ -1371,6 +1379,59 @@
  "ssi.1", "ssi.0";
status = "disabled";
 
+   rcar_sound,src {
+   src0: src-0 {
+   interrupts = ;
+   dmas = < 0x85>, < 0x9a>;
+   dma-names = "rx", "tx";
+   };
+   src1: src-1 {
+   interrupts = ;
+   dmas = < 0x87>, < 0x9c>;
+   dma-names = "rx", "tx";
+   };
+   src2: src-2 {
+   interrupts = ;
+   dmas = < 0x89>, < 0x9e>;
+   dma-names = "rx", "tx";
+   };
+   src3: src-3 {
+   interrupts = ;
+   dmas = < 0x8b>, < 0xa0>;
+   dma-names = "rx", "tx";
+   };
+   src4: src-4 {
+   interrupts = ;
+   dmas = < 0x8d>, < 0xb0>;
+   dma-names = "rx", "tx";
+   };
+   src5: src-5 {
+   interrupts = ;
+   dmas = < 0x8f>, < 0xb2>;
+   dma-names = "rx", "tx";
+   };
+   src6: src-6 {
+   interrupts = ;
+   dmas = < 0x91>, < 0xb4>;
+   dma-names = "rx", "tx";
+   };
+   src7: src-7 {
+   interrupts = ;
+   dmas = < 0x93>, < 0xb6>;
+   dma-names = "rx", "tx";
+   };
+   src8: src-8 {
+   interrupts = ;
+   dmas = < 0x95>, < 0xb8>;
+   dma-names = "rx", "tx";
+   };
+   src9: src-9 {
+   interrupts = ;
+   dmas = < 0x97>, < 0xba>;
+   dma-names = "rx", "tx";
+   };
+   };
+
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = ;
-- 
1.9.1

[PATCH/RFT 2/2] arm64: dts: renesas: r8a77965: Add PCIe device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds PCIe{0,1} device nodes to R8A77965 SoC.

Based on a similar patches of the R8A7796 device tree
by Harunobu Kurokawa .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 48 +--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index d740c79..0d39a31 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1433,13 +1433,57 @@
};
 
pciec0: pcie@fe00 {
+   compatible = "renesas,pcie-r8a77965",
+"renesas,pcie-rcar-gen3";
reg = <0 0xfe00 0 0x8>;
-   /* placeholder */
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xfe10 0 
0x0010
+   0x0200 0 0xfe20 0 0xfe20 0 
0x0020
+   0x0200 0 0x3000 0 0x3000 0 
0x0800
+   0x4200 0 0x3800 0 0x3800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x8000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 116 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 319>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 319>;
+   status = "disabled";
};
 
pciec1: pcie@ee80 {
+   compatible = "renesas,pcie-r8a77965",
+"renesas,pcie-rcar-gen3";
reg = <0 0xee80 0 0x8>;
-   /* placeholder */
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xee90 0 
0x0010
+   0x0200 0 0xeea0 0 0xeea0 0 
0x0020
+   0x0200 0 0xc000 0 0xc000 0 
0x0800
+   0x4200 0 0xc800 0 0xc800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x8000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 148 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 318>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 318>;
+   status = "disabled";
};
 
fcpf0: fcp@fe95 {
-- 
1.9.1

[PATCH/RFT 1/2] PCI: rcar: Add compatible string for r8a77965

[Yoshihiro Kaneko]

This patch adds support for r8a77965 (R-Car M3-N)

Signed-off-by: Yoshihiro Kaneko 
---
 Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt 
b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index 1fb614e..dd71cfe 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -8,6 +8,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
"renesas,pcie-r8a7796" for the R8A7796 SoC;
+   "renesas,pcie-r8a77965" for the R8A77965 SoC;
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
 RZ/G1 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
-- 
1.9.1

[PATCH/RFT 0/2] Add PCIe support for r8a77965

[Yoshihiro Kaneko]

This series adds PCIe support for r8a77965 (R-Car M3-N).
It is not necessary to update driver and PFC.

This series is based on the devel branch of Simon Horman's renesas tree.

Takeshi Kihara (1):
  arm64: dts: renesas: r8a77965: Add PCIe device nodes

Yoshihiro Kaneko (1):
  PCI: rcar: Add compatible string for r8a77965

 Documentation/devicetree/bindings/pci/rcar-pci.txt |  1 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi  | 48 +-
 2 files changed, 47 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH] arm64: dts: renesas: r8a7796: Add PCIe device nodes

[Yoshihiro Kaneko]

From: Harunobu Kurokawa 

This patch adds PCIe{0,1} device nodes for R8A7796 SoC.

Signed-off-by: Harunobu Kurokawa 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 50 ++--
 1 file changed, 47 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 7c25be6..2a04635b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for the r8a7796 SoC
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
@@ -2108,13 +2108,57 @@
};
 
pciec0: pcie@fe00 {
+   compatible = "renesas,pcie-r8a7796",
+"renesas,pcie-rcar-gen3";
reg = <0 0xfe00 0 0x8>;
-   /* placeholder */
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xfe10 0 
0x0010
+   0x0200 0 0xfe20 0 0xfe20 0 
0x0020
+   0x0200 0 0x3000 0 0x3000 0 
0x0800
+   0x4200 0 0x3800 0 0x3800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x8000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 116 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 319>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 319>;
+   status = "disabled";
};
 
pciec1: pcie@ee80 {
+   compatible = "renesas,pcie-r8a7796",
+"renesas,pcie-rcar-gen3";
reg = <0 0xee80 0 0x8>;
-   /* placeholder */
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xee90 0 
0x0010
+   0x0200 0 0xeea0 0 0xeea0 0 
0x0020
+   0x0200 0 0xc000 0 0xc000 0 
0x0800
+   0x4200 0 0xc800 0 0xc800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x8000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 148 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 318>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   resets = < 318>;
+   status = "disabled";
};
 
imr-lx4@fe86 {
-- 
1.9.1

[PATCH v2] arm64: dts: renesas: r8a77965: Add Watchdog Timer controller node using RCLK Watchdog Timer

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3-N (R8A77965) SoC.

Based on a similar patch of the R8A7796 device tree
by Geert Uytterhoeven .

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
Reviewed-by: Simon Horman 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

v2 [Yoshihiro Kaneko]
- add tags
* As suggested by Geert Uytterhoeven
- fix the summary prefix of the subject
- fix the notation of the name of SoC

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 486aeca..fb7100f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -139,8 +139,13 @@
ranges;
 
wdt0: watchdog@e602 {
+   compatible = "renesas,r8a77965-wdt",
+"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
-   /* placeholder */
+   clocks = < CPG_MOD 402>;
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 402>;
+   status = "disabled";
};
 
gpio0: gpio@e605 {
-- 
1.9.1

Re: [PATCH] arm64: dts: r8a77965: Add Watchdog Timer controller node using RCLK Watchdog Timer

[Yoshihiro Kaneko]

Hi Geert-san,

Thanks for your review.
I will correct the commit message as per your instructions.

Thanks,
Kaneko

2018-05-28 22:07 GMT+09:00 Geert Uytterhoeven :
> Hi Kaneko-san,
>
> (after adding more coffee)
>
> The summary prefix should be "arm64: dts: renesas: r8a77965:"
>
> On Mon, May 28, 2018 at 11:32 AM, Geert Uytterhoeven
>  wrote:
>> On Wed, May 23, 2018 at 2:36 PM, Yoshihiro Kaneko  
>> wrote:
>>> From: Takeshi Kihara 
>>>
>>> Add a device node for the Watchdog Timer (WDT) controller on the Renesas
>>> R-Car M3N (R8A77965) SoC.
>
> M3-N
>
>>> Based on a similar patch of the R8A7796 device tree
>>> by Geert Uytterhoeven .
>>>
>>> Signed-off-by: Takeshi Kihara 
>>> Signed-off-by: Yoshihiro Kaneko 
>>
>> Reviewed-by: Geert Uytterhoeven 
>> Tested-by: Geert Uytterhoeven 
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

[PATCH] arm64: dts: r8a77965: Add Watchdog Timer controller node using RCLK Watchdog Timer

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3N (R8A77965) SoC.

Based on a similar patch of the R8A7796 device tree
by Geert Uytterhoeven <geert+rene...@glider.be>.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 486aeca..fb7100f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -139,8 +139,13 @@
ranges;
 
wdt0: watchdog@e602 {
+   compatible = "renesas,r8a77965-wdt",
+"renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
-   /* placeholder */
+   clocks = < CPG_MOD 402>;
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 402>;
+   status = "disabled";
};
 
gpio0: gpio@e605 {
-- 
1.9.1

[PATCH v4 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

This series adds thermal support for r8a77995.
R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
Therefore this series adds r8a77995 support to rcar_thermal driver not
rcar_gen3_thermal driver.

This series is based on the next branch of Zhang Rui's linux tree.

v4 [Yoshihiro Kaneko]
rcar_thermal.c:
- add Tested-by tag
* As suggested by Simon Horman
- add comment to ".nirqs = 2" of rcar_gen3_thermal

rcar-thermal.txt:
* As suggested by Simon Horman
- update the explanation of the interrupts

r8a77995.dtsi:
- repositioned the thermal subnode by bus address order


v3 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- make use_of_thermal in structure rcar_thermal_chip a single bit
- add feature bits to rcar_thermal_chip
- add the number of interrupts to rcar_thermal_chip
- remove rcar_thermal_type in rcar_thermal_cip
- make variable chip in rcar_thermal_probe() a const

rcar-thermal.txt:
* No change

r8a77995.dtsi:
* No change


v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- remove rcar_of_data macro
- store a pointer to rcar_thermal_chip in rcar_thermal_priv
- remove unnecessary cast in rcar_thermal_dt_ids

rcar-thermal.txt:
- drop the fallback for D3
- update the paragraph about interrupts

r8a77995.dtsi:
- fix the base address and the register addresses
- drop the fallback

Yoshihiro Kaneko (3):
  thermal: rcar_thermal: add r8a77995 support
  dt-bindings: thermal: rcar-thermal: add R8A77995 support
  arm64: dts: renesas: r8a77995: add thermal device support

 .../devicetree/bindings/thermal/rcar-thermal.txt   |   7 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  |  31 
 drivers/thermal/rcar_thermal.c | 158 -
 3 files changed, 162 insertions(+), 34 deletions(-)

-- 
1.9.1

[PATCH v4 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Add support for R-Car D3 (r8a77995) thermal sensor.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Tested-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/thermal/rcar_thermal.c | 158 -
 1 file changed, 126 insertions(+), 32 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 73e5fee..45fb284 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -58,10 +58,47 @@ struct rcar_thermal_common {
spinlock_t lock;
 };
 
+struct rcar_thermal_chip {
+   unsigned int use_of_thermal : 1;
+   unsigned int has_filonoff : 1;
+   unsigned int irq_per_ch : 1;
+   unsigned int needs_suspend_resume : 1;
+   unsigned int nirqs;
+};
+
+static const struct rcar_thermal_chip rcar_thermal = {
+   .use_of_thermal = 0,
+   .has_filonoff = 1,
+   .irq_per_ch = 0,
+   .needs_suspend_resume = 0,
+   .nirqs = 1,
+};
+
+static const struct rcar_thermal_chip rcar_gen2_thermal = {
+   .use_of_thermal = 1,
+   .has_filonoff = 1,
+   .irq_per_ch = 0,
+   .needs_suspend_resume = 0,
+   .nirqs = 1,
+};
+
+static const struct rcar_thermal_chip rcar_gen3_thermal = {
+   .use_of_thermal = 1,
+   .has_filonoff = 0,
+   .irq_per_ch = 1,
+   .needs_suspend_resume = 1,
+   /*
+* The Gen3 chip has 3 interrupts, but this driver uses only 2
+* interrupts to detect a temperature change, rise or fall.
+*/
+   .nirqs = 2,
+};
+
 struct rcar_thermal_priv {
void __iomem *base;
struct rcar_thermal_common *common;
struct thermal_zone_device *zone;
+   const struct rcar_thermal_chip *chip;
struct delayed_work work;
struct mutex lock;
struct list_head list;
@@ -77,13 +114,20 @@ struct rcar_thermal_priv {
 #define rcar_priv_to_dev(priv) ((priv)->common->dev)
 #define rcar_has_irq_support(priv) ((priv)->common->base)
 #define rcar_id_to_shift(priv) ((priv)->id * 8)
-#define rcar_of_data(dev)  ((unsigned 
long)of_device_get_match_data(dev))
-#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
 
-#define USE_OF_THERMAL 1
 static const struct of_device_id rcar_thermal_dt_ids[] = {
-   { .compatible = "renesas,rcar-thermal", },
-   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
*)USE_OF_THERMAL },
+   {
+   .compatible = "renesas,rcar-thermal",
+   .data = _thermal,
+   },
+   {
+   .compatible = "renesas,rcar-gen2-thermal",
+.data = _gen2_thermal,
+   },
+   {
+   .compatible = "renesas,thermal-r8a77995",
+   .data = _gen3_thermal,
+   },
{},
 };
 MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -190,7 +234,8 @@ static int rcar_thermal_update_temp(struct 
rcar_thermal_priv *priv)
 * enable IRQ
 */
if (rcar_has_irq_support(priv)) {
-   rcar_thermal_write(priv, FILONOFF, 0);
+   if (priv->chip->has_filonoff)
+   rcar_thermal_write(priv, FILONOFF, 0);
 
/* enable Rising/Falling edge interrupt */
rcar_thermal_write(priv, POSNEG,  0x1);
@@ -420,7 +465,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
 
rcar_thermal_for_each_priv(priv, common) {
rcar_thermal_irq_disable(priv);
-   if (rcar_use_of_thermal(dev))
+   if (priv->chip->use_of_thermal)
thermal_remove_hwmon_sysfs(priv->zone);
else
thermal_zone_device_unregister(priv->zone);
@@ -438,6 +483,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
struct device *dev = >dev;
struct resource *res, *irq;
+   const struct rcar_thermal_chip *chip = of_device_get_match_data(dev);
int mres = 0;
int i;
int ret = -ENODEV;
@@ -457,19 +503,35 @@ static int rcar_thermal_probe(struct platform_device 
*pdev)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-   if (irq) {
-   /*
-* platform has IRQ support.
-* Then, driver uses common registers
-* rcar_has_irq_support() will be enabled
-*/
-   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
-   common->base = devm_ioremap_resource(dev, res);
-   if (IS_ERR(common->base))
-   return PTR_ERR(common->base);
+   for (i = 0; i < chip->nirqs; i++) {
+   irq = platform_get_resource(pdev, 

[PATCH v4 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 82aed7e..d4884e3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -216,6 +216,18 @@
#power-domain-cells = <1>;
};
 
+   thermal: thermal@e619 {
+   compatible = "renesas,thermal-r8a77995";
+   reg = <0 0xe619 0 0x10>, <0 0xe6190100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+
intc_ex: interrupt-controller@e61c {
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
#interrupt-cells = <2>;
@@ -785,6 +797,25 @@
};
};
 
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   };
+   };
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) 
| IRQ_TYPE_LEVEL_LOW)>,
-- 
1.9.1

[PATCH v4 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 349e635..67c563f 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -3,7 +3,8 @@
 Required properties:
 - compatible   : "renesas,thermal-",
   "renesas,rcar-gen2-thermal" (with thermal-zone) or
-  "renesas,rcar-thermal" (without thermal-zone) as 
fallback.
+  "renesas,rcar-thermal" (without thermal-zone) as
+   fallback except R-Car D3.
  Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -12,13 +13,15 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
  if it has "interrupts".
 
 Option properties:
 
-- interrupts   : use interrupt
+- interrupts   : If present should contain 3 interrupts for
+  R-Car D3 or 1 interrupt otherwise.
 
 Example (non interrupt support):
 
-- 
1.9.1

Re: [PATCH/RFT v3 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

2018-05-15 16:26 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Mon, May 14, 2018 at 06:11:59AM +0900, Yoshihiro Kaneko wrote:
>> Hi Simon-san,
>>
>> 2018年5月10日(木) 3:11 Simon Horman <ho...@verge.net.au>:
>>
>> > On Tue, Apr 03, 2018 at 09:43:03PM +0900, Yoshihiro Kaneko wrote:
>> > > Add support for R-Car D3 (r8a77995) thermal sensor.
>> > >
>> > > Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>> > > ---
>> > >  drivers/thermal/rcar_thermal.c | 154
>> > -
>> > >  1 file changed, 122 insertions(+), 32 deletions(-)
>> > >
>> > > diff --git a/drivers/thermal/rcar_thermal.c
>> > b/drivers/thermal/rcar_thermal.c
>> > > index 73e5fee..5ec47a9 100644
>> > > --- a/drivers/thermal/rcar_thermal.c
>> > > +++ b/drivers/thermal/rcar_thermal.c
>> > > @@ -58,10 +58,43 @@ struct rcar_thermal_common {
>> > >   spinlock_t lock;
>> > >  };
>> > >
>> > > +struct rcar_thermal_chip {
>> > > + unsigned int use_of_thermal : 1;
>> > > + unsigned int has_filonoff : 1;
>> > > + unsigned int irq_per_ch : 1;
>> > > + unsigned int needs_suspend_resume : 1;
>> > > + unsigned int nirqs;
>> > > +};
>> > > +
>> > > +static const struct rcar_thermal_chip rcar_thermal = {
>> > > + .use_of_thermal = 0,
>> > > + .has_filonoff = 1,
>> > > + .irq_per_ch = 0,
>> > > + .needs_suspend_resume = 0,
>> > > + .nirqs = 1,
>> > > +};
>> > > +
>> > > +static const struct rcar_thermal_chip rcar_gen2_thermal = {
>> > > + .use_of_thermal = 1,
>> > > + .has_filonoff = 1,
>> > > + .irq_per_ch = 0,
>> > > + .needs_suspend_resume = 0,
>> > > + .nirqs = 1,
>> > > +};
>> > > +
>> > > +static const struct rcar_thermal_chip rcar_gen3_thermal = {
>> > > + .use_of_thermal = 1,
>> > > + .has_filonoff = 0,
>> > > + .irq_per_ch = 1,
>> > > + .needs_suspend_resume = 1,
>> > > + .nirqs = 2,
>> > > +};
>> >
>> > The binding and dts patches in this series describe 3 interrupts
>> > for R-Car D3. But the above specifies two. Am I missing something obvious?
>>
>>
>> R-Car D3 has 3 interrupts, but this driver uses only 2 interrupts to detect
>> a temperature change, rise or fall.
>
> Thanks, that makes perfect sense.
>
> Perhaps a comment above ".nirqs = 2" would make it more obvious to the casual
> observer?

I agree with you.
I will update this patch.

Re: [PATCH/RFT v2 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Hi Simon-san,

2018-05-07 21:43 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> Hi Kaneko-san,
>
> could you re-spin this series with Geerts concerns (below) addressed.
>
> When you repost I think you can add the tested tags and drop the RFT from
> the prefix. I think its likely it can then be merged.

I had posted V3 that was updated with Geert-san's suggestions.
Should I repost V4 with the tested tags and without the RFT prefix?

>
> On Tue, Apr 03, 2018 at 08:17:01PM +0900, Yoshihiro Kaneko wrote:
>> Hi Geert-san,
>>
>> 2018-03-30 18:25 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
>> > Hi Kaneko-san,
>> >
>> > On Fri, Mar 30, 2018 at 5:13 AM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
>> > wrote:
>> >> Add support for R-Car D3 (r8a77995) thermal sensor.
>> >>
>> >> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>> >
>> > Thanks for your patch!
>> >
>> >> --- a/drivers/thermal/rcar_thermal.c
>> >> +++ b/drivers/thermal/rcar_thermal.c
>> >> @@ -58,10 +58,35 @@ struct rcar_thermal_common {
>> >> spinlock_t lock;
>> >>  };
>> >>
>> >> +enum rcar_thermal_type {
>> >> +   RCAR_THERMAL,
>> >> +   RCAR_GEN2_THERMAL,
>> >> +   RCAR_GEN3_THERMAL,
>> >> +};
>> >> +
>> >> +struct rcar_thermal_chip {
>> >> +   int use_of_thermal;
>> >
>> > This can be a single bit:
>> >
>> > unsigned int use_of_thermal : 1;
>> >
>> >> +   enum rcar_thermal_type type;
>> >
>> > If you would add feature bits, you can get rid of rcar_thermal_type:
>> >
>> > unsigned int has_filonoff : 1;
>> > unsigned int has_enr : 1;
>> > unsigned int needs_suspend_resume : 1;
>> >
>> > The number of interrupts can be stored here, too.
>>
>> It's nice!
>>
>> >
>> >> +};
>> >> +
>> >> +static const struct rcar_thermal_chip rcar_thermal = {
>> >> +   .use_of_thermal = 0,
>> >> +   .type = RCAR_THERMAL,
>> >
>> > .has_filonoff = 1,
>> > .has_enr = 0,
>> > ...
>> > .nirqs = 1,
>> >
>> >> @@ -190,7 +222,8 @@ static int rcar_thermal_update_temp(struct 
>> >> rcar_thermal_priv *priv)
>> >>  * enable IRQ
>> >>  */
>> >> if (rcar_has_irq_support(priv)) {
>> >> -   rcar_thermal_write(priv, FILONOFF, 0);
>> >> +   if (priv->chip->type != RCAR_GEN3_THERMAL)
>> >
>> > if (priv->chip->has_filonoff)
>> >
>> >> @@ -438,6 +471,9 @@ static int rcar_thermal_probe(struct platform_device 
>> >> *pdev)
>> >> struct rcar_thermal_priv *priv;
>> >> struct device *dev = >dev;
>> >> struct resource *res, *irq;
>> >> +   struct rcar_thermal_chip *chip = ((struct rcar_thermal_chip *)
>> >
>> > I don't think the cast is needed.
>>
>> I will make 'chip' a const variable.
>>
>> >
>> >> @@ -457,19 +493,35 @@ static int rcar_thermal_probe(struct 
>> >> platform_device *pdev)
>> >> pm_runtime_enable(dev);
>> >> pm_runtime_get_sync(dev);
>> >>
>> >> -   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
>> >> -   if (irq) {
>> >> -   /*
>> >> -* platform has IRQ support.
>> >> -* Then, driver uses common registers
>> >> -* rcar_has_irq_support() will be enabled
>> >> -*/
>> >> -   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
>> >> -   common->base = devm_ioremap_resource(dev, res);
>> >> -   if (IS_ERR(common->base))
>> >> -   return PTR_ERR(common->base);
>> >> +   for (i = 0; i < nirq; i++) {
>> >
>> > for (i = 0; i < priv->nirqs; i++) {
>>
>>
>> Best regards,
>> Kaneko
>>
>> >
>> > Gr{oetje,eeting}s,
>> >
>> > Geert
>> >
>> > --
>> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
>> > ge...@linux-m68k.org
>> >
>> > In personal conversations with technical people, I call myself a hacker. 
>> > But
>> > when I'm talking to journalists I just say "programmer" or something like 
>> > that.
>> > -- Linus Torvalds
>>

[PATCH v2] mmc: renesas_sdhi: Add r8a77965 support

[Yoshihiro Kaneko]

From: Masaharu Hayakawa <masaharu.hayakawa...@renesas.com>

This patch adds r8a77965 support in SDHI.

Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Tested-by: Simon Horman <horms+rene...@verge.net.au>
Tested-by: Wolfram Sang <wsa+rene...@sang-engineering.com>
---

This patch is based on the next branch of Ulf Hansson's mmc tree.

v2 [Yoshihiro Kaneko]
renesas_sdhi_internal_dmac.c
* As suggested by Simon Horman
  Dropped .revision for r8a77965 in gen3_soc_whitelist.
* As suggested by Wolfram Sang
  Dropped "renesas,rcar-gen3-sdhi" line in renesas_sdhi_internal_dmac_of_match.

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt 
b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index ba38252..ee978c9 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -26,6 +26,7 @@ Required properties:
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+   "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c 
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index a6bf123..b6edb7a 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -276,6 +276,7 @@ static void 
renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
/* generic ones */
{ .soc_id = "r8a7795" },
{ .soc_id = "r8a7796" },
+   { .soc_id = "r8a77965" },
{ .soc_id = "r8a77980" },
{ .soc_id = "r8a77995" },
{ /* sentinel */ }
-- 
1.9.1

[PATCH v2] arm64: dts: r8a77965: Add SDHI device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

Add SDHI nodes to the DT of the r8a77965 SoC.

Based on several similar patches of the R8A7796 device tree
by Simon Horman <horms+rene...@verge.net.au>.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the devel branch of Simon Horman's renesas tree.

v2 [Yoshihiro Kaneko]
* As suggested by Simon Horman
Rebased on top of the devel branch of the renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 36 +++
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index ba0edda..510815e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -978,23 +978,51 @@
};
 
sdhi0: sd@ee10 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
reg = <0 0xee10 0 0x2000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = < CPG_MOD 314>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 314>;
+   status = "disabled";
};
 
sdhi1: sd@ee12 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
reg = <0 0xee12 0 0x2000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = < CPG_MOD 313>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 313>;
+   status = "disabled";
};
 
sdhi2: sd@ee14 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
reg = <0 0xee14 0 0x2000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = < CPG_MOD 312>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 312>;
+   status = "disabled";
};
 
sdhi3: sd@ee16 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
reg = <0 0xee16 0 0x2000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = < CPG_MOD 311>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 311>;
+   status = "disabled";
};
 
gic: interrupt-controller@f101 {
-- 
1.9.1

Re: [PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Yoshihiro Kaneko]

Hi Simon-san,

2018-05-02 0:30 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Mon, Apr 30, 2018 at 04:48:16AM +0900, Yoshihiro Kaneko wrote:
>> From: Takeshi Kihara <takeshi.kihara...@renesas.com>
>>
>> Add SDHI nodes to the DT of the r8a77965 SoC.
>>
>> Based on several similar patches of the R8A7796 device tree
>> by Simon Horman <horms+rene...@verge.net.au>.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> This patch needs to be rebased on top of the devel branch of the renesas
> tree. Otherwise it looks good to me.

Thanks for your review.
I will rebase this patch.

>
>> ---
>>  arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 
>> ++-
>>  1 file changed, 48 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
>> b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> index f0871fc..6860704 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
>> @@ -834,26 +834,6 @@
>>   };
>>   };
>>
>> - sdhi0: sd@ee10 {
>> - reg = <0 0xee10 0 0x2000>;
>> - /* placeholder */
>> - };
>> -
>> - sdhi1: sd@ee12 {
>> - reg = <0 0xee12 0 0x2000>;
>> - /* placeholder */
>> - };
>> -
>> - sdhi2: sd@ee14 {
>> - reg = <0 0xee14 0 0x2000>;
>> - /* placeholder */
>> - };
>> -
>> - sdhi3: sd@ee16 {
>> - reg = <0 0xee16 0 0x2000>;
>> - /* placeholder */
>> - };
>> -
>>   usb3_phy0: usb-phy@e65ee000 {
>>   reg = <0 0xe65ee000 0 0x90>;
>>   #phy-cells = <0>;
>> @@ -874,5 +854,53 @@
>>   reg = <0 0xe602 0 0x0c>;
>>   /* placeholder */
>>   };
>> +
>> + sdhi0: sd@ee10 {
>> + compatible = "renesas,sdhi-r8a77965",
>> +  "renesas,rcar-gen3-sdhi";
>> + reg = <0 0xee10 0 0x2000>;
>> + interrupts = ;
>> + clocks = < CPG_MOD 314>;
>> + max-frequency = <2>;
>> + power-domains = < 32>;
>> + resets = < 314>;
>> + status = "disabled";
>> + };
>> +
>> + sdhi1: sd@ee12 {
>> + compatible = "renesas,sdhi-r8a77965",
>> +  "renesas,rcar-gen3-sdhi";
>> + reg = <0 0xee12 0 0x2000>;
>> + interrupts = ;
>> + clocks = < CPG_MOD 313>;
>> + max-frequency = <2>;
>> + power-domains = < 32>;
>> + resets = < 313>;
>> + status = "disabled";
>> + };
>> +
>> + sdhi2: sd@ee14 {
>> + compatible = "renesas,sdhi-r8a77965",
>> +  "renesas,rcar-gen3-sdhi";
>> + reg = <0 0xee14 0 0x2000>;
>> + interrupts = ;
>> + clocks = < CPG_MOD 312>;
>> + max-frequency = <2>;
>> + power-domains = < 32>;
>> + resets = < 312>;
>> + status = "disabled";
>> + };
>> +
>> + sdhi3: sd@ee16 {
>> + compatible = "renesas,sdhi-r8a77965",
>> +  "renesas,rcar-gen3-sdhi";
>> + reg = <0 0xee16 0 0x2000>;
>> + interrupts = ;
>> + clocks = < CPG_MOD 311>;
>> + max-frequency = <2>;
>> + power-domains = < 32>;
>> + resets = < 311>;
>> + status = "disabled";
>> + };
>>   };
>>  };
>> --
>> 1.9.1
>>

Best regards,
Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

Hi Geert-san,

2018-05-04 17:30 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Fri, May 4, 2018 at 10:28 AM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> 2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
>>> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
>>> wrote:
>>>> From: Takeshi Kihara <takeshi.kihara...@renesas.com>
>>>>
>>>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>>>> SoC.
>>>>
>>>> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
>>>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>>>
>>> Thanks for your patch!
>>>
>>> The pins, groups, and functions are correct, so
>>> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>.
>>> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.
>>
>> Thanks for your review!
>> I will fix up the below in V2.
>
> There's no need to send a v2, as I have already fixed and applied your patch.

Okay, Thanks!

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Yoshihiro Kaneko]

Hello,

2018-05-02 17:14 GMT+09:00 Wolfram Sang :
>
>> With the current state of the driver this patch should be fine,
>> modulo the changes suggested above. But once HS400 support is merged
>> some logic will be required to disable that feature for the r8a77965
>> until HS400 support for that SoC is explicitly added.
>>
>> Or conversely, perhaps when HS400 is added it should only be enabled
>> in the driver for SoCs that are known to work: r8a7796 and r8a7795. In the
>> case of the latter perhaps only ES2.0.
>>
>> Wolfram, what do you think?
>
> M3-N (and future SoCs as it seems) has 8 taps while the others have 4.
> Maybe we should have something already in place to distinguish 8 taps
> and 4 taps and leave the 8 taps part for "to be added later"?
>

Thanks for your review.
I will drop .revision = "ES1.0" and renesas,sdhi-r8a77965 in V2.

Best regards,
Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

Hi Geert-san,

2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> From: Takeshi Kihara <takeshi.kihara...@renesas.com>
>>
>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>> SoC.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> Thanks for your patch!
>
> The pins, groups, and functions are correct, so
> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>.
> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.

Thanks for your review!
I will fix up the below in V2.

>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> @@ -1923,6 +1923,264 @@ enum {
>> RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>>  };
>>
>> +/* - SDHI0 
>> -- */
>> +static const unsigned int sdhi0_data1_pins[] = {
>
> [...]
>
>> +};
>
> This doesn't belong in the middle of the usb0 section ;-)
>
>> +
>>  static const unsigned int usb0_mux[] = {
>> USB0_PWEN_MARK, USB0_OVC_MARK,
>>  };
>> @@ -1997,6 +2255,32 @@ enum {
>> SH_PFC_PIN_GROUP(usb0),
>> SH_PFC_PIN_GROUP(usb1),
>> SH_PFC_PIN_GROUP(usb30),
>> +   SH_PFC_PIN_GROUP(sdhi0_data1),
>
> Alphabetical order, please.
>
>> @@ -2083,6 +2367,44 @@ enum {
>> "usb30",
>>  };
>>
>> +static const char * const sdhi0_groups[] = {
>
> Alphabetical order, please.
>
>> @@ -2096,6 +2418,10 @@ enum {
>> SH_PFC_FUNCTION(usb0),
>> SH_PFC_FUNCTION(usb1),
>> SH_PFC_FUNCTION(usb30),
>> +   SH_PFC_FUNCTION(sdhi0),
>> +   SH_PFC_FUNCTION(sdhi1),
>> +   SH_PFC_FUNCTION(sdhi2),
>> +   SH_PFC_FUNCTION(sdhi3),
>>  };
>
> Alphabetical order, please.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Best regards,
Kaneko

[PATCH/RFT 3/3] arm64: dts: r8a77965: Add SDHI device nodes

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

Add SDHI nodes to the DT of the r8a77965 SoC.

Based on several similar patches of the R8A7796 device tree
by Simon Horman <horms+rene...@verge.net.au>.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 68 ++-
 1 file changed, 48 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index f0871fc..6860704 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -834,26 +834,6 @@
};
};
 
-   sdhi0: sd@ee10 {
-   reg = <0 0xee10 0 0x2000>;
-   /* placeholder */
-   };
-
-   sdhi1: sd@ee12 {
-   reg = <0 0xee12 0 0x2000>;
-   /* placeholder */
-   };
-
-   sdhi2: sd@ee14 {
-   reg = <0 0xee14 0 0x2000>;
-   /* placeholder */
-   };
-
-   sdhi3: sd@ee16 {
-   reg = <0 0xee16 0 0x2000>;
-   /* placeholder */
-   };
-
usb3_phy0: usb-phy@e65ee000 {
reg = <0 0xe65ee000 0 0x90>;
#phy-cells = <0>;
@@ -874,5 +854,53 @@
reg = <0 0xe602 0 0x0c>;
/* placeholder */
};
+
+   sdhi0: sd@ee10 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee10 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 314>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 314>;
+   status = "disabled";
+   };
+
+   sdhi1: sd@ee12 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee12 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 313>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 313>;
+   status = "disabled";
+   };
+
+   sdhi2: sd@ee14 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee14 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 312>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 312>;
+   status = "disabled";
+   };
+
+   sdhi3: sd@ee16 {
+   compatible = "renesas,sdhi-r8a77965",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee16 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 311>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 311>;
+   status = "disabled";
+   };
};
 };
-- 
1.9.1

[PATCH/RFT 2/3] mmc: renesas_sdhi: Add r8a77965 support

[Yoshihiro Kaneko]

From: Masaharu Hayakawa <masaharu.hayakawa...@renesas.com>

This patch adds r8a77965 support in SDHI.

Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt 
b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index ba38252..ee978c9 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -26,6 +26,7 @@ Required properties:
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+   "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c 
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index a6bf123..733ea8e 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -99,6 +99,7 @@
 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
{ .compatible = "renesas,sdhi-r8a7795", .data = 
_rcar_gen3_compatible, },
{ .compatible = "renesas,sdhi-r8a7796", .data = 
_rcar_gen3_compatible, },
+   { .compatible = "renesas,sdhi-r8a77965", .data = 
_rcar_gen3_compatible, },
{ .compatible = "renesas,rcar-gen3-sdhi", .data = 
_rcar_gen3_compatible, },
{},
 };
@@ -276,6 +277,7 @@ static void 
renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
/* generic ones */
{ .soc_id = "r8a7795" },
{ .soc_id = "r8a7796" },
+   { .soc_id = "r8a77965", .revision = "ES1.0" },
{ .soc_id = "r8a77980" },
{ .soc_id = "r8a77995" },
{ /* sentinel */ }
-- 
1.9.1

[PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 ++
 1 file changed, 326 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index cea9d05..0350197 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1923,6 +1923,264 @@ enum {
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
 
+/* - SDHI0 -- 
*/
+static const unsigned int sdhi0_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int sdhi0_data1_mux[] = {
+   SD0_DAT0_MARK,
+};
+
+static const unsigned int sdhi0_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+   RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int sdhi0_data4_mux[] = {
+   SD0_DAT0_MARK, SD0_DAT1_MARK,
+   SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+
+static const unsigned int sdhi0_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+
+static const unsigned int sdhi0_ctrl_mux[] = {
+   SD0_CLK_MARK, SD0_CMD_MARK,
+};
+
+static const unsigned int sdhi0_cd_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi0_cd_mux[] = {
+   SD0_CD_MARK,
+};
+
+static const unsigned int sdhi0_wp_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi0_wp_mux[] = {
+   SD0_WP_MARK,
+};
+
+/* - SDHI1 -- 
*/
+static const unsigned int sdhi1_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(3, 8),
+};
+
+static const unsigned int sdhi1_data1_mux[] = {
+   SD1_DAT0_MARK,
+};
+
+static const unsigned int sdhi1_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi1_data4_mux[] = {
+   SD1_DAT0_MARK, SD1_DAT1_MARK,
+   SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+
+static const unsigned int sdhi1_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int sdhi1_ctrl_mux[] = {
+   SD1_CLK_MARK, SD1_CMD_MARK,
+};
+
+static const unsigned int sdhi1_cd_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int sdhi1_cd_mux[] = {
+   SD1_CD_MARK,
+};
+
+static const unsigned int sdhi1_wp_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int sdhi1_wp_mux[] = {
+   SD1_WP_MARK,
+};
+
+/* - SDHI2 -- 
*/
+static const unsigned int sdhi2_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(4, 2),
+};
+
+static const unsigned int sdhi2_data1_mux[] = {
+   SD2_DAT0_MARK,
+};
+
+static const unsigned int sdhi2_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+   RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+
+static const unsigned int sdhi2_data4_mux[] = {
+   SD2_DAT0_MARK, SD2_DAT1_MARK,
+   SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+
+static const unsigned int sdhi2_data8_pins[] = {
+   /* D[0:7] */
+   RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
+   RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
+   RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi2_data8_mux[] = {
+   SD2_DAT0_MARK, SD2_DAT1_MARK,
+   SD2_DAT2_MARK, SD2_DAT3_MARK,
+   SD2_DAT4_MARK, SD2_DAT5_MARK,
+   SD2_DAT6_MARK, SD2_DAT7_MARK,
+};
+
+static const unsigned int sdhi2_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+
+static const unsigned int sdhi2_ctrl_mux[] = {
+   SD2_CLK_MARK, SD2_CMD_MARK,
+};
+
+static const unsigned int sdhi2_cd_a_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(4, 13),
+};
+
+static const unsigned int sdhi2_cd_a_mux[] = {
+   SD2_CD_A_MARK,
+};
+
+static const unsigned int sdhi2_cd_b_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(5, 10),
+};
+
+static const unsigned int sdhi2_cd_b_mux[] = {
+   SD2_CD_B_MARK,
+};
+
+static const unsigned int sdhi2_wp_a_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(4, 14),
+};
+
+static const unsigned int sdhi2_wp_a_mux[] = {
+   SD2_WP_A_MARK,
+};
+
+static const unsigned int sdhi2_wp_b_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int sdhi2_wp_b_mux[] = {
+   SD2_WP_B_MARK,
+};
+
+static const unsigned int sdhi2_ds_pins[] = {
+   /* DS */
+   RCAR_GP_PIN(4, 6),
+};
+
+static const unsigne

[PATCH/RFT 0/3] mmc: renesas_sdhi: add support for r8a77965

[Yoshihiro Kaneko]

This series adds SDHI device support for r8a77965.

This series is based on the next branch of Ulf Hansson's mmc tree.

Masaharu Hayakawa (1):
  mmc: renesas_sdhi: Add r8a77965 support

Takeshi Kihara (2):
  pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions
  arm64: dts: r8a77965: Add SDHI device nodes

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt |   1 +
 arch/arm64/boot/dts/renesas/r8a77965.dtsi  |  68 +++--
 drivers/mmc/host/renesas_sdhi_internal_dmac.c  |   2 +
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c  | 326 +
 4 files changed, 377 insertions(+), 20 deletions(-)

-- 
1.9.1

Re: [PATCH 0/5] arm64: dts: renesas: r8a779xx: sort nodes

[Yoshihiro Kaneko]

Hi Simon-san,

2018-04-24 17:24 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Tue, Apr 24, 2018 at 02:31:40AM +0900, Yoshihiro Kaneko wrote:
>> Hi Simon-san,
>>
>> 2018-04-23 19:26 GMT+09:00 Simon Horman <ho...@verge.net.au>:
>> > On Thu, Apr 19, 2018 at 05:14:35AM +0900, Yoshihiro Kaneko wrote:
>> >> Sort nodes of the R-Car M3-N (r8a77965), V3M (r8a77970) and D3 (r8a77995) 
>> >> DTs.
>> >>
>> >> This is part of an ongoing effort to provide consistent node
>> >> order in the DT of Renesas SoCs to improve maintainability.
>> >>
>> >> This should not have any run-time effect.
>> >>
>> >> Based on the devel branch of Simon Horman's renesas tree.
>> >>
>> >> Yoshihiro Kaneko (5):
>> >>   arm64: dts: renesas: r8a77995: sort subnodes of the root node
>> >>   arm64: dts: renesas: r8a77995: sort subnodes of the soc node
>> >>   arm64: dts: renesas: r8a77965: sort subnodes of the root node
>> >>   arm64: dts: renesas: r8a77965: sort subnodes of the soc node
>> >>   arm64: dts: renesas: r8a77970: sort subnodes of the soc node
>> >
>> > Thanks, applied.
>> >
>> > There ware a few nodes added to r8a77970 between when you made
>> > this patchset and when I applied it. I think the r8a77970 is still
>> > sorted as desired. Could you double-check once I push a devel
>> > branch later today?
>>
>> Yes, will do.
>
> Thanks, you should now be able to check renesas-devel-20180423-v4.17-rc2

fcpvd0 should be after vspd0?
It seems good to me except the above.

Re: [PATCH 0/5] arm64: dts: renesas: r8a779xx: sort nodes

[Yoshihiro Kaneko]

Hi Simon-san,

2018-04-23 19:26 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Thu, Apr 19, 2018 at 05:14:35AM +0900, Yoshihiro Kaneko wrote:
>> Sort nodes of the R-Car M3-N (r8a77965), V3M (r8a77970) and D3 (r8a77995) 
>> DTs.
>>
>> This is part of an ongoing effort to provide consistent node
>> order in the DT of Renesas SoCs to improve maintainability.
>>
>> This should not have any run-time effect.
>>
>> Based on the devel branch of Simon Horman's renesas tree.
>>
>> Yoshihiro Kaneko (5):
>>   arm64: dts: renesas: r8a77995: sort subnodes of the root node
>>   arm64: dts: renesas: r8a77995: sort subnodes of the soc node
>>   arm64: dts: renesas: r8a77965: sort subnodes of the root node
>>   arm64: dts: renesas: r8a77965: sort subnodes of the soc node
>>   arm64: dts: renesas: r8a77970: sort subnodes of the soc node
>
> Thanks, applied.
>
> There ware a few nodes added to r8a77970 between when you made
> this patchset and when I applied it. I think the r8a77970 is still
> sorted as desired. Could you double-check once I push a devel
> branch later today?

Yes, will do.

[PATCH 5/5] arm64: dts: renesas: r8a77970: sort subnodes of the soc node

[Yoshihiro Kaneko]

Sort subnodes of the soc node.
- The primary key is the bus address.
- The secondary key is the IP block.
- The tertiary key is the node name.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77970.dtsi | 378 +++---
 1 file changed, 189 insertions(+), 189 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 71f466d..d8f6808 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -83,23 +83,6 @@
#size-cells = <2>;
ranges;
 
-   gic: interrupt-controller@f101 {
-   compatible = "arm,gic-400";
-   #interrupt-cells = <3>;
-   #address-cells = <0>;
-   interrupt-controller;
-   reg = <0 0xf101 0 0x1000>,
- <0 0xf102 0 0x2>,
- <0 0xf104 0 0x2>,
- <0 0xf106 0 0x2>;
-   interrupts = ;
-   clocks = < CPG_MOD 408>;
-   clock-names = "clk";
-   power-domains = < R8A77970_PD_ALWAYS_ON>;
-   resets = < 408>;
-   };
-
rwdt: watchdog@e602 {
compatible = "renesas,r8a77970-wdt",
 "renesas,rcar-gen3-wdt";
@@ -110,75 +93,6 @@
status = "disabled";
};
 
-   cpg: clock-controller@e615 {
-   compatible = "renesas,r8a77970-cpg-mssr";
-   reg = <0 0xe615 0 0x1000>;
-   clocks = <_clk>, <_clk>;
-   clock-names = "extal", "extalr";
-   #clock-cells = <2>;
-   #power-domain-cells = <0>;
-   #reset-cells = <1>;
-   };
-
-   rst: reset-controller@e616 {
-   compatible = "renesas,r8a77970-rst";
-   reg = <0 0xe616 0 0x200>;
-   };
-
-   sysc: system-controller@e618 {
-   compatible = "renesas,r8a77970-sysc";
-   reg = <0 0xe618 0 0x440>;
-   #power-domain-cells = <1>;
-   };
-
-   ipmmu_vi0: mmu@febd {
-   compatible = "renesas,ipmmu-r8a77970";
-   reg = <0 0xfebd 0 0x1000>;
-   renesas,ipmmu-main = <_mm 9>;
-   power-domains = < R8A77970_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   status = "disabled";
-   };
-
-   ipmmu_ir: mmu@ff8b {
-   compatible = "renesas,ipmmu-r8a77970";
-   reg = <0 0xff8b 0 0x1000>;
-   renesas,ipmmu-main = <_mm 3>;
-   power-domains = < R8A77970_PD_A3IR>;
-   #iommu-cells = <1>;
-   status = "disabled";
-   };
-
-   ipmmu_rt: mmu@ffc8 {
-   compatible = "renesas,ipmmu-r8a77970";
-   reg = <0 0xffc8 0 0x1000>;
-   renesas,ipmmu-main = <_mm 7>;
-   power-domains = < R8A77970_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_ds1: mmu@e774 {
-   compatible = "renesas,ipmmu-r8a77970";
-   reg = <0 0xe774 0 0x1000>;
-   renesas,ipmmu-main = <_mm 0>;
-   power-domains = < R8A77970_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_mm: mmu@e67b {
-   compatible = "renesas,ipmmu-r8a77970";
-   reg = <0 0xe67b 0 0x1000>;
-   interrupts = ,
-;
-   power-domains = < R8A77970_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   pfc: pin-controller@e606 {
-   compatible = "renesas,pfc-r8a77

[PATCH 3/5] arm64: dts: renesas: r8a77965: sort subnodes of the root node

[Yoshihiro Kaneko]

Sort subnodes of the root node alphanumerically.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 +++---
 1 file changed, 60 insertions(+), 60 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index a41f916..d110382 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -22,9 +22,34 @@
i2c7 = _dvfs;
};
 
-   psci {
-   compatible = "arm,psci-1.0", "arm,psci-0.2";
-   method = "smc";
+   /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+   audio_clk_a: audio_clk_a {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_b: audio_clk_b {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_c: audio_clk_c {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
};
 
cpus {
@@ -71,34 +96,24 @@
clock-frequency = <0>;
};
 
-   /*
-* The external audio clocks are configured as 0 Hz fixed frequency
-* clocks by default.
-* Boards that provide audio clocks should override them.
-*/
-   audio_clk_a: audio_clk_a {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   audio_clk_b: audio_clk_b {
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
 
-   audio_clk_c: audio_clk_c {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
+   pmu_a57 {
+   compatible = "arm,cortex-a57-pmu";
+   interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>,
+<_1>;
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
+   psci {
+   compatible = "arm,psci-1.0", "arm,psci-0.2";
+   method = "smc";
};
 
/* External SCIF clock - to be overridden by boards that provide it */
@@ -108,42 +123,6 @@
clock-frequency = <0>;
};
 
-   /* External PCIe clock - can be overridden by the board */
-   pcie_bus_clk: pcie_bus {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   /* External USB clocks - can be overridden by the board */
-   usb3s0_clk: usb3s0 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   usb_extal_clk: usb_extal {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
-   timer {
-   compatible = "arm,armv8-timer";
-   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>;
-   };
-
-   pmu_a57 {
-   compatible = "arm,cortex-a57-pmu";
-   

[PATCH 4/5] arm64: dts: renesas: r8a77965: sort subnodes of the soc node

[Yoshihiro Kaneko]

Sort subnodes of the soc node.
- The primary key is the bus address.
- The secondary key is the IP block.
- The tertiary key is the node name.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 912 +++---
 1 file changed, 456 insertions(+), 456 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index d110382..b12f417 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -130,52 +130,9 @@
#size-cells = <2>;
ranges;
 
-   gic: interrupt-controller@f101 {
-   compatible = "arm,gic-400";
-   #interrupt-cells = <3>;
-   #address-cells = <0>;
-   interrupt-controller;
-   reg = <0x0 0xf101 0 0x1000>,
- <0x0 0xf102 0 0x2>,
- <0x0 0xf104 0 0x2>,
- <0x0 0xf106 0 0x2>;
-   interrupts = ;
-   clocks = < CPG_MOD 408>;
-   clock-names = "clk";
-   power-domains = < 32>;
-   resets = < 408>;
-   };
-
-   pfc: pin-controller@e606 {
-   compatible = "renesas,pfc-r8a77965";
-   reg = <0 0xe606 0 0x50c>;
-   };
-
-   cpg: clock-controller@e615 {
-   compatible = "renesas,r8a77965-cpg-mssr";
-   reg = <0 0xe615 0 0x1000>;
-   clocks = <_clk>, <_clk>;
-   clock-names = "extal", "extalr";
-   #clock-cells = <2>;
-   #power-domain-cells = <0>;
-   #reset-cells = <1>;
-   };
-
-   rst: reset-controller@e616 {
-   compatible = "renesas,r8a77965-rst";
-   reg = <0 0xe616 0 0x0200>;
-   };
-
-   prr: chipid@fff00044 {
-   compatible = "renesas,prr";
-   reg = <0 0xfff00044 0 4>;
-   };
-
-   sysc: system-controller@e618 {
-   compatible = "renesas,r8a77965-sysc";
-   reg = <0 0xe618 0 0x0400>;
-   #power-domain-cells = <1>;
+   wdt0: watchdog@e602 {
+   reg = <0 0xe602 0 0x0c>;
+   /* placeholder */
};
 
gpio0: gpio@e605 {
@@ -298,6 +255,32 @@
resets = < 905>;
};
 
+   pfc: pin-controller@e606 {
+   compatible = "renesas,pfc-r8a77965";
+   reg = <0 0xe606 0 0x50c>;
+   };
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a77965-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>, <_clk>;
+   clock-names = "extal", "extalr";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a77965-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a77965-sysc";
+   reg = <0 0xe618 0 0x0400>;
+   #power-domain-cells = <1>;
+   };
+
intc_ex: interrupt-controller@e61c {
compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
#interrupt-cells = <2>;
@@ -314,6 +297,121 @@
resets = < 407>;
};
 
+   i2c0: i2c@e650 {
+   reg = <0 0xe650 0 0x40>;
+   /* placeholder */
+   };
+
+   i2c1: i2c@e6508000 {
+   reg = <0 0xe6508000 0 0x40>;
+   /* placeholde

[PATCH 2/5] arm64: dts: renesas: r8a77995: sort subnodes of the soc node

[Yoshihiro Kaneko]

Sort subnodes of the soc node.
- The primary key is the bus address.
- The secondary key is the IP block.
- The tertiary key is the node name.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 697 +++---
 1 file changed, 348 insertions(+), 349 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cf47655..a978305 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -76,23 +76,6 @@
#size-cells = <2>;
ranges;
 
-   gic: interrupt-controller@f101 {
-   compatible = "arm,gic-400";
-   #interrupt-cells = <3>;
-   #address-cells = <0>;
-   interrupt-controller;
-   reg = <0x0 0xf101 0 0x1000>,
- <0x0 0xf102 0 0x2>,
- <0x0 0xf104 0 0x2>,
- <0x0 0xf106 0 0x2>;
-   interrupts = ;
-   clocks = < CPG_MOD 408>;
-   clock-names = "clk";
-   power-domains = < R8A77995_PD_ALWAYS_ON>;
-   resets = < 408>;
-   };
-
rwdt: watchdog@e602 {
compatible = "renesas,r8a77995-wdt",
 "renesas,rcar-gen3-wdt";
@@ -103,88 +86,123 @@
status = "disabled";
};
 
-   ipmmu_vi0: mmu@febd {
-   compatible = "renesas,ipmmu-r8a77995";
-   reg = <0 0xfebd 0 0x1000>;
-   renesas,ipmmu-main = <_mm 14>;
-   #iommu-cells = <1>;
-   status = "disabled";
-   };
-
-   ipmmu_vp0: mmu@fe99 {
-   compatible = "renesas,ipmmu-r8a77995";
-   reg = <0 0xfe99 0 0x1000>;
-   renesas,ipmmu-main = <_mm 16>;
-   #iommu-cells = <1>;
-   status = "disabled";
-   };
-
-   ipmmu_vc0: mmu@fe6b {
-   compatible = "renesas,ipmmu-r8a77995";
-   reg = <0 0xfe6b 0 0x1000>;
-   renesas,ipmmu-main = <_mm 12>;
-   #iommu-cells = <1>;
-   status = "disabled";
+   gpio0: gpio@e605 {
+   compatible = "renesas,gpio-r8a77995",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe605 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 0 9>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 912>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 912>;
};
 
-   ipmmu_pv0: mmu@fd80 {
-   compatible = "renesas,ipmmu-r8a77995";
-   reg = <0 0xfd80 0 0x1000>;
-   renesas,ipmmu-main = <_mm 6>;
-   #iommu-cells = <1>;
-   status = "disabled";
+   gpio1: gpio@e6051000 {
+   compatible = "renesas,gpio-r8a77995",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6051000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 32 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 911>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 911>;
};
 
-   ipmmu_hc: mmu@e657 {
- 

[PATCH 0/5] arm64: dts: renesas: r8a779xx: sort nodes

[Yoshihiro Kaneko]

Sort nodes of the R-Car M3-N (r8a77965), V3M (r8a77970) and D3 (r8a77995) DTs.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Based on the devel branch of Simon Horman's renesas tree.

Yoshihiro Kaneko (5):
  arm64: dts: renesas: r8a77995: sort subnodes of the root node
  arm64: dts: renesas: r8a77995: sort subnodes of the soc node
  arm64: dts: renesas: r8a77965: sort subnodes of the root node
  arm64: dts: renesas: r8a77965: sort subnodes of the soc node
  arm64: dts: renesas: r8a77970: sort subnodes of the soc node

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1160 ++---
 arch/arm64/boot/dts/renesas/r8a77970.dtsi |  378 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi |  717 +-
 3 files changed, 1127 insertions(+), 1128 deletions(-)

-- 
1.9.1

[PATCH 1/5] arm64: dts: renesas: r8a77995: sort subnodes of the root node

[Yoshihiro Kaneko]

Sort subnodes of the root node alphanumerically.

This is part of an ongoing effort to provide consistent node
order in the DT of Renesas SoCs to improve maintainability.

This should not have any run-time effect.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 82aed7e..cf47655 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -18,9 +18,11 @@
#address-cells = <2>;
#size-cells = <2>;
 
-   psci {
-   compatible = "arm,psci-1.0", "arm,psci-0.2";
-   method = "smc";
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
};
 
cpus {
@@ -51,18 +53,16 @@
clock-frequency = <0>;
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
};
 
+   psci {
+   compatible = "arm,psci-1.0", "arm,psci-0.2";
+   method = "smc";
+   };
+
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
-- 
1.9.1

[PATCH/RFT v3 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 349e635..5ab5fcd 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -3,7 +3,8 @@
 Required properties:
 - compatible   : "renesas,thermal-",
   "renesas,rcar-gen2-thermal" (with thermal-zone) or
-  "renesas,rcar-thermal" (without thermal-zone) as 
fallback.
+  "renesas,rcar-thermal" (without thermal-zone) as
+   fallback except R-Car D3.
  Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -12,13 +13,15 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
  if it has "interrupts".
 
 Option properties:
 
-- interrupts   : use interrupt
+- interrupts   : use interrupt.
+  Should contain 3 interrupts for R-Car D3.
 
 Example (non interrupt support):
 
-- 
1.9.1

[PATCH/RFT v3 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd..9a52b41 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -636,5 +636,35 @@
#phy-cells = <0>;
status = "disabled";
};
+
+   thermal: thermal@e619 {
+   compatible = "renesas,thermal-r8a77995";
+   reg = <0 0xe619 0 0x10>, <0 0xe6190100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+   };
+
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   cooling-maps {
+   };
+   };
};
 };
-- 
1.9.1

[PATCH/RFT v3 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

This series adds thermal support for r8a77995.
R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
Therefore this series adds r8a77995 support to rcar_thermal driver not
rcar_gen3_thermal driver.

This series is based on the next branch of Zhang Rui's linux tree.

v3 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- make use_of_thermal in structure rcar_thermal_chip a single bit
- add feature bits to rcar_thermal_chip
- add the number of interrupts to rcar_thermal_chip
- remove rcar_thermal_type in rcar_thermal_cip
- make variable chip in rcar_thermal_probe() a const

rcar-thermal.txt:
* No change

r8a77995.dtsi:
* No change


v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- remove rcar_of_data macro
- store a pointer to rcar_thermal_chip in rcar_thermal_priv
- remove unnecessary cast in rcar_thermal_dt_ids

rcar-thermal.txt:
- drop the fallback for D3
- update the paragraph about interrupts

r8a77995.dtsi:
- fix the base address and the register addresses
- drop the fallback

Yoshihiro Kaneko (3):
  thermal: rcar_thermal: add r8a77995 support
  dt-bindings: thermal: rcar-thermal: add R8A77995 support
  arm64: dts: renesas: r8a77995: add thermal device support

 .../devicetree/bindings/thermal/rcar-thermal.txt   |   7 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  |  30 
 drivers/thermal/rcar_thermal.c | 154 -
 3 files changed, 157 insertions(+), 34 deletions(-)

-- 
1.9.1

[PATCH/RFT v3 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Add support for R-Car D3 (r8a77995) thermal sensor.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 drivers/thermal/rcar_thermal.c | 154 -
 1 file changed, 122 insertions(+), 32 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 73e5fee..5ec47a9 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -58,10 +58,43 @@ struct rcar_thermal_common {
spinlock_t lock;
 };
 
+struct rcar_thermal_chip {
+   unsigned int use_of_thermal : 1;
+   unsigned int has_filonoff : 1;
+   unsigned int irq_per_ch : 1;
+   unsigned int needs_suspend_resume : 1;
+   unsigned int nirqs;
+};
+
+static const struct rcar_thermal_chip rcar_thermal = {
+   .use_of_thermal = 0,
+   .has_filonoff = 1,
+   .irq_per_ch = 0,
+   .needs_suspend_resume = 0,
+   .nirqs = 1,
+};
+
+static const struct rcar_thermal_chip rcar_gen2_thermal = {
+   .use_of_thermal = 1,
+   .has_filonoff = 1,
+   .irq_per_ch = 0,
+   .needs_suspend_resume = 0,
+   .nirqs = 1,
+};
+
+static const struct rcar_thermal_chip rcar_gen3_thermal = {
+   .use_of_thermal = 1,
+   .has_filonoff = 0,
+   .irq_per_ch = 1,
+   .needs_suspend_resume = 1,
+   .nirqs = 2,
+};
+
 struct rcar_thermal_priv {
void __iomem *base;
struct rcar_thermal_common *common;
struct thermal_zone_device *zone;
+   const struct rcar_thermal_chip *chip;
struct delayed_work work;
struct mutex lock;
struct list_head list;
@@ -77,13 +110,20 @@ struct rcar_thermal_priv {
 #define rcar_priv_to_dev(priv) ((priv)->common->dev)
 #define rcar_has_irq_support(priv) ((priv)->common->base)
 #define rcar_id_to_shift(priv) ((priv)->id * 8)
-#define rcar_of_data(dev)  ((unsigned 
long)of_device_get_match_data(dev))
-#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
 
-#define USE_OF_THERMAL 1
 static const struct of_device_id rcar_thermal_dt_ids[] = {
-   { .compatible = "renesas,rcar-thermal", },
-   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
*)USE_OF_THERMAL },
+   {
+   .compatible = "renesas,rcar-thermal",
+   .data = _thermal,
+   },
+   {
+   .compatible = "renesas,rcar-gen2-thermal",
+.data = _gen2_thermal,
+   },
+   {
+   .compatible = "renesas,thermal-r8a77995",
+   .data = _gen3_thermal,
+   },
{},
 };
 MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -190,7 +230,8 @@ static int rcar_thermal_update_temp(struct 
rcar_thermal_priv *priv)
 * enable IRQ
 */
if (rcar_has_irq_support(priv)) {
-   rcar_thermal_write(priv, FILONOFF, 0);
+   if (priv->chip->has_filonoff)
+   rcar_thermal_write(priv, FILONOFF, 0);
 
/* enable Rising/Falling edge interrupt */
rcar_thermal_write(priv, POSNEG,  0x1);
@@ -420,7 +461,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
 
rcar_thermal_for_each_priv(priv, common) {
rcar_thermal_irq_disable(priv);
-   if (rcar_use_of_thermal(dev))
+   if (priv->chip->use_of_thermal)
thermal_remove_hwmon_sysfs(priv->zone);
else
thermal_zone_device_unregister(priv->zone);
@@ -438,6 +479,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
struct device *dev = >dev;
struct resource *res, *irq;
+   const struct rcar_thermal_chip *chip = of_device_get_match_data(dev);
int mres = 0;
int i;
int ret = -ENODEV;
@@ -457,19 +499,35 @@ static int rcar_thermal_probe(struct platform_device 
*pdev)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-   if (irq) {
-   /*
-* platform has IRQ support.
-* Then, driver uses common registers
-* rcar_has_irq_support() will be enabled
-*/
-   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
-   common->base = devm_ioremap_resource(dev, res);
-   if (IS_ERR(common->base))
-   return PTR_ERR(common->base);
+   for (i = 0; i < chip->nirqs; i++) {
+   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+   if (!irq)
+   continue;
+   if (!common->base) {
+   /*
+* platform has IRQ support.
+* Then, driver uses common registers
+  

Re: [PATCH/RFT v2 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Hi Geert-san,

2018-03-30 18:25 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Fri, Mar 30, 2018 at 5:13 AM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> Add support for R-Car D3 (r8a77995) thermal sensor.
>>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> Thanks for your patch!
>
>> --- a/drivers/thermal/rcar_thermal.c
>> +++ b/drivers/thermal/rcar_thermal.c
>> @@ -58,10 +58,35 @@ struct rcar_thermal_common {
>> spinlock_t lock;
>>  };
>>
>> +enum rcar_thermal_type {
>> +   RCAR_THERMAL,
>> +   RCAR_GEN2_THERMAL,
>> +   RCAR_GEN3_THERMAL,
>> +};
>> +
>> +struct rcar_thermal_chip {
>> +   int use_of_thermal;
>
> This can be a single bit:
>
> unsigned int use_of_thermal : 1;
>
>> +   enum rcar_thermal_type type;
>
> If you would add feature bits, you can get rid of rcar_thermal_type:
>
> unsigned int has_filonoff : 1;
> unsigned int has_enr : 1;
> unsigned int needs_suspend_resume : 1;
>
> The number of interrupts can be stored here, too.

It's nice!

>
>> +};
>> +
>> +static const struct rcar_thermal_chip rcar_thermal = {
>> +   .use_of_thermal = 0,
>> +   .type = RCAR_THERMAL,
>
> .has_filonoff = 1,
> .has_enr = 0,
> ...
> .nirqs = 1,
>
>> @@ -190,7 +222,8 @@ static int rcar_thermal_update_temp(struct 
>> rcar_thermal_priv *priv)
>>  * enable IRQ
>>  */
>> if (rcar_has_irq_support(priv)) {
>> -   rcar_thermal_write(priv, FILONOFF, 0);
>> +   if (priv->chip->type != RCAR_GEN3_THERMAL)
>
> if (priv->chip->has_filonoff)
>
>> @@ -438,6 +471,9 @@ static int rcar_thermal_probe(struct platform_device 
>> *pdev)
>> struct rcar_thermal_priv *priv;
>> struct device *dev = >dev;
>> struct resource *res, *irq;
>> +   struct rcar_thermal_chip *chip = ((struct rcar_thermal_chip *)
>
> I don't think the cast is needed.

I will make 'chip' a const variable.

>
>> @@ -457,19 +493,35 @@ static int rcar_thermal_probe(struct platform_device 
>> *pdev)
>> pm_runtime_enable(dev);
>> pm_runtime_get_sync(dev);
>>
>> -   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
>> -   if (irq) {
>> -   /*
>> -* platform has IRQ support.
>> -* Then, driver uses common registers
>> -* rcar_has_irq_support() will be enabled
>> -*/
>> -   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
>> -   common->base = devm_ioremap_resource(dev, res);
>> -   if (IS_ERR(common->base))
>> -   return PTR_ERR(common->base);
>> +   for (i = 0; i < nirq; i++) {
>
> for (i = 0; i < priv->nirqs; i++) {


Best regards,
Kaneko

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH/RFT v2 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

Hi Simon-san,

2018-03-30 22:49 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Fri, Mar 30, 2018 at 12:13:00PM +0900, Yoshihiro Kaneko wrote:
>> This series adds thermal support for r8a77995.
>> R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
>> Therefore this series adds r8a77995 support to rcar_thermal driver not
>> rcar_gen3_thermal driver.
>>
>> This series is based on the next branch of Zhang Rui's linux tree.
>
> I have very lightly tested this as follows after enabling
> CONFIG_RCAR_THERMAL in the kernel .config.
>
> # cat /sys/devices/virtual/thermal/thermal_zone0/temp
> 4

Thanks for the testing.
Probably 40C is reasonable, is not?


Best regards,
Kaneko

[PATCH/RFT v2 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

This series adds thermal support for r8a77995.
R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
Therefore this series adds r8a77995 support to rcar_thermal driver not
rcar_gen3_thermal driver.

This series is based on the next branch of Zhang Rui's linux tree.

v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- remove rcar_of_data macro
- store a pointer to rcar_thermal_chip in rcar_thermal_priv
- remove unnecessary cast in rcar_thermal_dt_ids

rcar-thermal.txt:
- drop the fallback for D3
- update the paragraph about interrupts

r8a77995.dtsi:
- fix the base address and the register addresses
- drop the fallback


Yoshihiro Kaneko (3):
  thermal: rcar_thermal: add r8a77995 support
  dt-bindings: thermal: rcar-thermal: add R8A77995 support
  arm64: dts: renesas: r8a77995: add thermal device support

 .../devicetree/bindings/thermal/rcar-thermal.txt   |   7 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  |  30 +
 drivers/thermal/rcar_thermal.c | 148 -
 3 files changed, 151 insertions(+), 34 deletions(-)

-- 
1.9.1

[PATCH/RFT v2 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Add support for R-Car D3 (r8a77995) thermal sensor.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 drivers/thermal/rcar_thermal.c | 148 -
 1 file changed, 116 insertions(+), 32 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 73e5fee..a631bff 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -58,10 +58,35 @@ struct rcar_thermal_common {
spinlock_t lock;
 };
 
+enum rcar_thermal_type {
+   RCAR_THERMAL,
+   RCAR_GEN2_THERMAL,
+   RCAR_GEN3_THERMAL,
+};
+
+struct rcar_thermal_chip {
+   int use_of_thermal;
+   enum rcar_thermal_type type;
+};
+
+static const struct rcar_thermal_chip rcar_thermal = {
+   .use_of_thermal = 0,
+   .type = RCAR_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen2_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN2_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen3_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN3_THERMAL,
+};
+
 struct rcar_thermal_priv {
void __iomem *base;
struct rcar_thermal_common *common;
struct thermal_zone_device *zone;
+   struct rcar_thermal_chip *chip;
struct delayed_work work;
struct mutex lock;
struct list_head list;
@@ -77,13 +102,20 @@ struct rcar_thermal_priv {
 #define rcar_priv_to_dev(priv) ((priv)->common->dev)
 #define rcar_has_irq_support(priv) ((priv)->common->base)
 #define rcar_id_to_shift(priv) ((priv)->id * 8)
-#define rcar_of_data(dev)  ((unsigned 
long)of_device_get_match_data(dev))
-#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
 
-#define USE_OF_THERMAL 1
 static const struct of_device_id rcar_thermal_dt_ids[] = {
-   { .compatible = "renesas,rcar-thermal", },
-   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
*)USE_OF_THERMAL },
+   {
+   .compatible = "renesas,rcar-thermal",
+   .data = _thermal,
+   },
+   {
+   .compatible = "renesas,rcar-gen2-thermal",
+.data = _gen2_thermal,
+   },
+   {
+   .compatible = "renesas,thermal-r8a77995",
+   .data = _gen3_thermal,
+   },
{},
 };
 MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -190,7 +222,8 @@ static int rcar_thermal_update_temp(struct 
rcar_thermal_priv *priv)
 * enable IRQ
 */
if (rcar_has_irq_support(priv)) {
-   rcar_thermal_write(priv, FILONOFF, 0);
+   if (priv->chip->type != RCAR_GEN3_THERMAL)
+   rcar_thermal_write(priv, FILONOFF, 0);
 
/* enable Rising/Falling edge interrupt */
rcar_thermal_write(priv, POSNEG,  0x1);
@@ -420,7 +453,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
 
rcar_thermal_for_each_priv(priv, common) {
rcar_thermal_irq_disable(priv);
-   if (rcar_use_of_thermal(dev))
+   if (priv->chip->use_of_thermal)
thermal_remove_hwmon_sysfs(priv->zone);
else
thermal_zone_device_unregister(priv->zone);
@@ -438,6 +471,9 @@ static int rcar_thermal_probe(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
struct device *dev = >dev;
struct resource *res, *irq;
+   struct rcar_thermal_chip *chip = ((struct rcar_thermal_chip *)
+ of_device_get_match_data(dev));
+   int nirq = chip->type == RCAR_GEN3_THERMAL ? 2 : 1;
int mres = 0;
int i;
int ret = -ENODEV;
@@ -457,19 +493,35 @@ static int rcar_thermal_probe(struct platform_device 
*pdev)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-   if (irq) {
-   /*
-* platform has IRQ support.
-* Then, driver uses common registers
-* rcar_has_irq_support() will be enabled
-*/
-   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
-   common->base = devm_ioremap_resource(dev, res);
-   if (IS_ERR(common->base))
-   return PTR_ERR(common->base);
+   for (i = 0; i < nirq; i++) {
+   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+   if (!irq)
+   continue;
+   if (!common->base) {
+   /*
+* platform has IRQ support.
+* Then, driver uses common registers
+* rcar_has_irq_support() will be enabled
+*/
+   

[PATCH/RFT v2 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd..9a52b41 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -636,5 +636,35 @@
#phy-cells = <0>;
status = "disabled";
};
+
+   thermal: thermal@e619 {
+   compatible = "renesas,thermal-r8a77995";
+   reg = <0 0xe619 0 0x10>, <0 0xe6190100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+   };
+
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   cooling-maps {
+   };
+   };
};
 };
-- 
1.9.1

[PATCH/RFT v2 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 349e635..5ab5fcd 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -3,7 +3,8 @@
 Required properties:
 - compatible   : "renesas,thermal-",
   "renesas,rcar-gen2-thermal" (with thermal-zone) or
-  "renesas,rcar-thermal" (without thermal-zone) as 
fallback.
+  "renesas,rcar-thermal" (without thermal-zone) as
+   fallback except R-Car D3.
  Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -12,13 +13,15 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
  if it has "interrupts".
 
 Option properties:
 
-- interrupts   : use interrupt
+- interrupts   : use interrupt.
+  Should contain 3 interrupts for R-Car D3.
 
 Example (non interrupt support):
 
-- 
1.9.1

Re: [PATCH/RFT 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Hi Geert-san,

Thanks for your review.

2018-03-12 20:02 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi  Kaneko-san,
>
> On Sun, Mar 11, 2018 at 9:26 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> Add support for R-Car D3 (r8a77995) thermal sensor.
>>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> Thanks for your patch!
>
>> --- a/drivers/thermal/rcar_thermal.c
>> +++ b/drivers/thermal/rcar_thermal.c
>
>> @@ -77,13 +101,23 @@ struct rcar_thermal_priv {
>>  #define rcar_priv_to_dev(priv) ((priv)->common->dev)
>>  #define rcar_has_irq_support(priv) ((priv)->common->base)
>>  #define rcar_id_to_shift(priv) ((priv)->id * 8)
>> -#define rcar_of_data(dev)  ((unsigned 
>> long)of_device_get_match_data(dev))
>> -#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
>> +#define rcar_of_data(dev) \
>> +   ((struct rcar_thermal_chip *)of_device_get_match_data(dev))
>
> I think it would be better to get rid of this macro, as
> of_device_get_match_data()
> walks the rcar_thermal_dt_ids[] over and over again.
>
> Instead, you can store a pointer to struct rcar_thermal_chip in struct
> rcar_thermal_priv in rcar_thermal_probe().

I understand.
I will work on this improvement.

>
>> +#define rcar_use_of_thermal(dev)   (rcar_of_data(dev)->use_of_thermal)
>> -#define USE_OF_THERMAL 1
>>  static const struct of_device_id rcar_thermal_dt_ids[] = {
>> -   { .compatible = "renesas,rcar-thermal", },
>> -   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
>> *)USE_OF_THERMAL },
>> +   {
>> +   .compatible = "renesas,rcar-thermal",
>> +   .data = (void *)_thermal,
>
> This cast not needed.

Yes.

>
>> @@ -438,6 +473,7 @@ static int rcar_thermal_probe(struct platform_device 
>> *pdev)
>> struct rcar_thermal_priv *priv;
>> struct device *dev = >dev;
>> struct resource *res, *irq;
>> +   int nirq = rcar_of_data(dev)->type == RCAR_GEN3_THERMAL ? 2 : 1;
>
> Why 2? Your DT patch has 3 interrupts, which matches the datasheet.

This driver uses INTDT0 and INTDT1. INTDT2 is not used.


Thanks,
Kaneko

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Hi Geert-san,

Thanks for your review.

2018-03-12 19:56 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Sun, Mar 11, 2018 at 9:26 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> Thanks for your patch!
>
>> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> @@ -402,5 +402,36 @@
>> #phy-cells = <0>;
>> status = "disabled";
>> };
>> +
>> +   thermal: thermal@e61f {
>
> According to the Hard User Manual rev. 0.80, the base address is e619?

You are correct.
I will update this patch to fix it.

>
>> +   compatible = "renesas,thermal-r8a77995",
>> +"renesas,rcar-thermal";
>
> I would drop the fallback property, cfr. my comments on the DT binding
> patch.

Yes. I will do it.

>
>> +   reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
>
> 0xe619... (twice)

I will fix it.


Thanks,
Kaneko

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Hi Geert-san,

Thank you for your review!

2018-03-12 19:13 GMT+09:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Kaneko-san,
>
> On Sun, Mar 11, 2018 at 9:26 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
> wrote:
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
>> +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
>> @@ -12,6 +12,7 @@ Required properties:
>> - "renesas,thermal-r8a7791" (R-Car M2-W)
>> - "renesas,thermal-r8a7792" (R-Car V2H)
>> - "renesas,thermal-r8a7793" (R-Car M2-N)
>> +   - "renesas,thermal-r8a77995" (R-Car D3)
>
> OK for this change.
>
> I think the paragraph above needs some clarification, too:
>
> Required properties:
> - compatible: "renesas,thermal-",
>"renesas,rcar-gen2-thermal" (with
> thermal-zone) or
>"renesas,rcar-thermal" (without
> thermal-zone) as fallback.
>
> Your DT update for D3 contains the thermal-zone, but it is not R-Car Gen2,
> while you declare it compatible with "renesas,rcar-thermal".
>
> Probably we can just drop the fallback for D3 (and V3M later)?

It sounds good.
I will update DT to drop the fallback for D3.

>
> And the paragraph about interrupts need an update, too, as D3 has more
> than one interrupt:
>
> Option properties:
> - interrupts: use interrupt

I will update this paragraph.


Thanks,
Kaneko

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

[PATCH/RFT 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

This series adds thermal support for r8a77995.
R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
Therefore this series adds r8a77995 support to rcar_thermal driver not
rcar_gen3_thermal driver.

This series is based on the next branch of Zhang Rui's linux tree.

Yoshihiro Kaneko (3):
  thermal: rcar_thermal: add r8a77995 support
  dt-bindings: thermal: rcar-thermal: add R8A77995 support
  arm64: dts: renesas: r8a77995: add thermal device support

 .../devicetree/bindings/thermal/rcar-thermal.txt   |   1 +
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  |  31 +
 drivers/thermal/rcar_thermal.c | 141 -
 3 files changed, 144 insertions(+), 29 deletions(-)

-- 
1.9.1

[PATCH 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 788e3af..d1a5197 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -402,5 +402,36 @@
#phy-cells = <0>;
status = "disabled";
};
+
+   thermal: thermal@e61f {
+   compatible = "renesas,thermal-r8a77995",
+"renesas,rcar-thermal";
+   reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+   };
+
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   cooling-maps {
+   };
+   };
};
 };
-- 
1.9.1

[PATCH 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 349e635..b2829cb 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -12,6 +12,7 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
  if it has "interrupts".
-- 
1.9.1

[PATCH/RFT 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Add support for R-Car D3 (r8a77995) thermal sensor.

Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 drivers/thermal/rcar_thermal.c | 141 -
 1 file changed, 112 insertions(+), 29 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 73e5fee..d517155 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -69,6 +69,30 @@ struct rcar_thermal_priv {
u32 ctemp;
 };
 
+enum rcar_thermal_type {
+   RCAR_THERMAL,
+   RCAR_GEN2_THERMAL,
+   RCAR_GEN3_THERMAL,
+};
+
+struct rcar_thermal_chip {
+   int use_of_thermal;
+   enum rcar_thermal_type type;
+};
+
+static const struct rcar_thermal_chip rcar_thermal = {
+   .use_of_thermal = 0,
+   .type = RCAR_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen2_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN2_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen3_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN3_THERMAL,
+};
+
 #define rcar_thermal_for_each_priv(pos, common)\
list_for_each_entry(pos, >head, list)
 
@@ -77,13 +101,23 @@ struct rcar_thermal_priv {
 #define rcar_priv_to_dev(priv) ((priv)->common->dev)
 #define rcar_has_irq_support(priv) ((priv)->common->base)
 #define rcar_id_to_shift(priv) ((priv)->id * 8)
-#define rcar_of_data(dev)  ((unsigned 
long)of_device_get_match_data(dev))
-#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
+#define rcar_of_data(dev) \
+   ((struct rcar_thermal_chip *)of_device_get_match_data(dev))
+#define rcar_use_of_thermal(dev)   (rcar_of_data(dev)->use_of_thermal)
 
-#define USE_OF_THERMAL 1
 static const struct of_device_id rcar_thermal_dt_ids[] = {
-   { .compatible = "renesas,rcar-thermal", },
-   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
*)USE_OF_THERMAL },
+   {
+   .compatible = "renesas,rcar-thermal",
+   .data = (void *)_thermal,
+   },
+   {
+   .compatible = "renesas,rcar-gen2-thermal",
+.data = (void *)_gen2_thermal,
+   },
+   {
+   .compatible = "renesas,thermal-r8a77995",
+   .data = (void *)_gen3_thermal,
+   },
{},
 };
 MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -190,7 +224,8 @@ static int rcar_thermal_update_temp(struct 
rcar_thermal_priv *priv)
 * enable IRQ
 */
if (rcar_has_irq_support(priv)) {
-   rcar_thermal_write(priv, FILONOFF, 0);
+   if (rcar_of_data(dev)->type != RCAR_GEN3_THERMAL)
+   rcar_thermal_write(priv, FILONOFF, 0);
 
/* enable Rising/Falling edge interrupt */
rcar_thermal_write(priv, POSNEG,  0x1);
@@ -438,6 +473,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
struct device *dev = >dev;
struct resource *res, *irq;
+   int nirq = rcar_of_data(dev)->type == RCAR_GEN3_THERMAL ? 2 : 1;
int mres = 0;
int i;
int ret = -ENODEV;
@@ -457,19 +493,35 @@ static int rcar_thermal_probe(struct platform_device 
*pdev)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-   if (irq) {
-   /*
-* platform has IRQ support.
-* Then, driver uses common registers
-* rcar_has_irq_support() will be enabled
-*/
-   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
-   common->base = devm_ioremap_resource(dev, res);
-   if (IS_ERR(common->base))
-   return PTR_ERR(common->base);
+   for (i = 0; i < nirq; i++) {
+   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+   if (!irq)
+   continue;
+   if (!common->base) {
+   /*
+* platform has IRQ support.
+* Then, driver uses common registers
+* rcar_has_irq_support() will be enabled
+*/
+   res = platform_get_resource(pdev, IORESOURCE_MEM,
+   mres++);
+   common->base = devm_ioremap_resource(dev, res);
+   if (IS_ERR(common->base))
+   return PTR_ERR(common->base);
 
-   idle = 0; /* polling delay is not needed */
+   idle = 0; /* polling delay is not needed */
+   }
+
+   ret = devm_request_irq(dev, irq->start, rcar_thermal_irq,
+

Re: [PATCH/RFT v3] sata_rcar: Reset SATA PHY when Salvator-X board resumes

[Yoshihiro Kaneko]

Hi Sergei,

2018-02-05 17:33 GMT+09:00 Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>:
> Hello!
>
> On 2/4/2018 10:18 PM, Yoshihiro Kaneko wrote:
>
>> From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
>>
>> Because power of Salvator-X board is cut off in suspend,
>> it needs to reset SATA PHY state in resume.
>> Otherwise, SATA partition could not be accessed anymore.
>>
>> Signed-off-by: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
>> Signed-off-by: Hien Dang <hien.dang...@rvc.renesas.com>
>> [reinit phy in sata_rcar_resume() function on R-Car Gen3 only]
>> [factor out SATA module init sequence]
>> [fixed the prefix for the subject]
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>
> [...]
>
>OK, this one seems better.

Thank you as always for your help.

Best regards,
Kaneko

>
> MBR, Sergei

[PATCH/RFT v3] sata_rcar: Reset SATA PHY when Salvator-X board resumes

[Yoshihiro Kaneko]

From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>

Because power of Salvator-X board is cut off in suspend,
it needs to reset SATA PHY state in resume.
Otherwise, SATA partition could not be accessed anymore.

Signed-off-by: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
Signed-off-by: Hien Dang <hien.dang...@rvc.renesas.com>
[reinit phy in sata_rcar_resume() function on R-Car Gen3 only]
[factor out SATA module init sequence]
[fixed the prefix for the subject]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
 drivers/ata/sata_rcar.c | 63 +++--
 1 file changed, 40 insertions(+), 23 deletions(-)

This patch is based on the for-next branch of libata tree.

v2 [Yoshihiro Kaneko]
* reinit phy on R-Car Gen3 only as suggested by Geert Uytterhoeven
* use "sata_rcar" prefix for the subject as suggested by Sergei Shtylyov

v3 [Yoshihiro Kaneko]
* As suggested by Sergei Shtylyov
  - factored out the common part of the initialising SATA module
  - remove the redundant "sata:" prefix from the subject

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 80ee2f2..6f47ca3 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -146,6 +146,7 @@
 enum sata_rcar_type {
RCAR_GEN1_SATA,
RCAR_GEN2_SATA,
+   RCAR_GEN3_SATA,
RCAR_R8A7790_ES1_SATA,
 };
 
@@ -784,26 +785,11 @@ static void sata_rcar_setup_port(struct ata_host *host)
ioaddr->command_addr= ioaddr->cmd_addr + (ATA_REG_CMD << 2);
 }
 
-static void sata_rcar_init_controller(struct ata_host *host)
+static void sata_rcar_init_module(struct sata_rcar_priv *priv)
 {
-   struct sata_rcar_priv *priv = host->private_data;
void __iomem *base = priv->base;
u32 val;
 
-   /* reset and setup phy */
-   switch (priv->type) {
-   case RCAR_GEN1_SATA:
-   sata_rcar_gen1_phy_init(priv);
-   break;
-   case RCAR_GEN2_SATA:
-   case RCAR_R8A7790_ES1_SATA:
-   sata_rcar_gen2_phy_init(priv);
-   break;
-   default:
-   dev_warn(host->dev, "SATA phy is not initialized\n");
-   break;
-   }
-
/* SATA-IP reset state */
val = ioread32(base + ATAPI_CONTROL1_REG);
val |= ATAPI_CONTROL1_RESET;
@@ -824,10 +810,34 @@ static void sata_rcar_init_controller(struct ata_host 
*host)
/* ack and mask */
iowrite32(0, base + SATAINTSTAT_REG);
iowrite32(0x7ff, base + SATAINTMASK_REG);
+
/* enable interrupts */
iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
 }
 
+static void sata_rcar_init_controller(struct ata_host *host)
+{
+   struct sata_rcar_priv *priv = host->private_data;
+   void __iomem *base = priv->base;
+
+   /* reset and setup phy */
+   switch (priv->type) {
+   case RCAR_GEN1_SATA:
+   sata_rcar_gen1_phy_init(priv);
+   break;
+   case RCAR_GEN2_SATA:
+   case RCAR_GEN3_SATA:
+   case RCAR_R8A7790_ES1_SATA:
+   sata_rcar_gen2_phy_init(priv);
+   break;
+   default:
+   dev_warn(host->dev, "SATA phy is not initialized\n");
+   break;
+   }
+
+   sata_rcar_init_module(priv);
+}
+
 static const struct of_device_id sata_rcar_match[] = {
{
/* Deprecated by "renesas,sata-r8a7779" */
@@ -856,7 +866,7 @@ static void sata_rcar_init_controller(struct ata_host *host)
},
{
.compatible = "renesas,sata-r8a7795",
-   .data = (void *)RCAR_GEN2_SATA
+   .data = (void *)RCAR_GEN3_SATA
},
{
.compatible = "renesas,rcar-gen2-sata",
@@ -864,7 +874,7 @@ static void sata_rcar_init_controller(struct ata_host *host)
},
{
.compatible = "renesas,rcar-gen3-sata",
-   .data = (void *)RCAR_GEN2_SATA
+   .data = (void *)RCAR_GEN3_SATA
},
{ },
 };
@@ -982,11 +992,18 @@ static int sata_rcar_resume(struct device *dev)
if (ret)
return ret;
 
-   /* ack and mask */
-   iowrite32(0, base + SATAINTSTAT_REG);
-   iowrite32(0x7ff, base + SATAINTMASK_REG);
-   /* enable interrupts */
-   iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
+   if (priv->type == RCAR_GEN3_SATA) {
+   sata_rcar_gen2_phy_init(priv);
+   sata_rcar_init_module(priv);
+   } else {
+   /* ack and mask */
+   iowrite32(0, base + SATAINTSTAT_REG);
+   iowrite32(0x7ff, base + SATAINTMASK_REG);
+
+   /* enable interrupts */
+   iowrite32(ATAPI_INT_ENABLE_SATAINT,
+ base + ATAPI_INT_ENABLE_REG);
+   }
 
ata_host_resume(host);
 
-- 
1.9.1

[PATCH/RFT v4] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

From: Hien Dang <hien.dang...@renesas.com>

This patch adds an implementation that saves and restores the state of
GPIO configuration on suspend and resume.

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[Modify structure of the bank info to simplify a saving registers]
[Remove DEV_PM_OPS macro]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-gpio tree.

v2 [Yoshihiro Kaneko]
* Modify structure of the bank info as suggested by Geert Uytterhoeven

v3 [Yoshihiro Kaneko]
* Remove DEV_PM_OPS macro as suggested by Vladimir Zapolskiy

v4 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
  - make the name of all members of gpio_rcar_bank_info accord with the
name of the registers
  - fix type of the 'offset' variable in unsigned int
  - fix the inverted logic in gpio_rcar_resume()

 drivers/gpio/gpio-rcar.c | 66 
 1 file changed, 66 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index e76de57..e5b0dbe 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -31,6 +31,16 @@
 #include 
 #include 
 
+struct gpio_rcar_bank_info {
+   u32 iointsel;
+   u32 inoutsel;
+   u32 outdt;
+   u32 posneg;
+   u32 edglevel;
+   u32 bothedge;
+   u32 intmsk;
+};
+
 struct gpio_rcar_priv {
void __iomem *base;
spinlock_t lock;
@@ -41,6 +51,7 @@ struct gpio_rcar_priv {
unsigned int irq_parent;
bool has_both_edge_trigger;
bool needs_clk;
+   struct gpio_rcar_bank_info bank_info;
 };
 
 #define IOINTSEL 0x00  /* General IO/Interrupt Switching Register */
@@ -531,11 +542,66 @@ static int gpio_rcar_remove(struct platform_device *pdev)
return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpio_rcar_suspend(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+
+   p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
+   p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
+   p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
+   p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
+   p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
+   p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
+   if (p->has_both_edge_trigger)
+   p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
+
+   return 0;
+}
+
+static int gpio_rcar_resume(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+   unsigned int offset;
+   u32 mask;
+
+   for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
+   mask = BIT(offset);
+   /* I/O pin */
+   if (!(p->bank_info.iointsel & mask)) {
+   if (p->bank_info.inoutsel & mask)
+   gpio_rcar_direction_output(
+   >gpio_chip, offset,
+   !!(p->bank_info.outdt & mask));
+   else
+   gpio_rcar_direction_input(>gpio_chip,
+ offset);
+   } else {
+   /* Interrupt pin */
+   gpio_rcar_config_interrupt_input_mode(
+   p,
+   offset,
+   !(p->bank_info.posneg & mask),
+   !(p->bank_info.edglevel & mask),
+   !!(p->bank_info.bothedge & mask));
+
+   if (p->bank_info.intmsk & mask)
+   gpio_rcar_write(p, MSKCLR, mask);
+   }
+   }
+
+   return 0;
+}
+#endif /* CONFIG_PM_SLEEP*/
+
+static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, 
gpio_rcar_resume);
+
 static struct platform_driver gpio_rcar_device_driver = {
.probe  = gpio_rcar_probe,
.remove = gpio_rcar_remove,
.driver = {
.name   = "gpio_rcar",
+   .pm = _rcar_pm_ops,
.of_match_table = of_match_ptr(gpio_rcar_of_table),
}
 };
-- 
1.9.1

[PATCH v2] sata: sata_rcar: Reset SATA PHY when Salvator-X board resumes

[Yoshihiro Kaneko]

From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>

Because power of Salvator-X board is cut off in suspend,
it needs to reset SATA PHY state in resume.
Otherwise, SATA partition could not be accessed anymore.

Signed-off-by: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
Signed-off-by: Hien Dang <hien.dang...@rvc.renesas.com>
[reinit phy in sata_rcar_resume() function on R-Car Gen3 only]
[fixed the prefix for the subject]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of libata tree.

v2 [Yoshihiro Kaneko]
* reinit phy on R-Car Gen3 only as suggested by Geert Uytterhoeven
* use "sata_rcar" prefix for the subject as suggested by Sergei Shtylyov

 drivers/ata/sata_rcar.c | 38 --
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 80ee2f2..4adc0d6 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -146,6 +146,7 @@
 enum sata_rcar_type {
RCAR_GEN1_SATA,
RCAR_GEN2_SATA,
+   RCAR_GEN3_SATA,
RCAR_R8A7790_ES1_SATA,
 };
 
@@ -796,6 +797,7 @@ static void sata_rcar_init_controller(struct ata_host *host)
sata_rcar_gen1_phy_init(priv);
break;
case RCAR_GEN2_SATA:
+   case RCAR_GEN3_SATA:
case RCAR_R8A7790_ES1_SATA:
sata_rcar_gen2_phy_init(priv);
break;
@@ -856,7 +858,7 @@ static void sata_rcar_init_controller(struct ata_host *host)
},
{
.compatible = "renesas,sata-r8a7795",
-   .data = (void *)RCAR_GEN2_SATA
+   .data = (void *)RCAR_GEN3_SATA
},
{
.compatible = "renesas,rcar-gen2-sata",
@@ -864,7 +866,7 @@ static void sata_rcar_init_controller(struct ata_host *host)
},
{
.compatible = "renesas,rcar-gen3-sata",
-   .data = (void *)RCAR_GEN2_SATA
+   .data = (void *)RCAR_GEN3_SATA
},
{ },
 };
@@ -977,11 +979,43 @@ static int sata_rcar_resume(struct device *dev)
struct sata_rcar_priv *priv = host->private_data;
void __iomem *base = priv->base;
int ret;
+   u32 val;
 
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
 
+   /* reinit phy on R-Car Gen3 only */
+   switch (priv->type) {
+   case RCAR_GEN1_SATA:
+   case RCAR_GEN2_SATA:
+   case RCAR_R8A7790_ES1_SATA:
+   break;
+   case RCAR_GEN3_SATA:
+   sata_rcar_gen2_phy_init(priv);
+   break;
+   default:
+   dev_warn(host->dev, "SATA phy is not initialized\n");
+   break;
+   }
+
+   /* SATA-IP reset state */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val |= ATAPI_CONTROL1_RESET;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+   /* ISM mode, PRD mode, DTEND flag at bit 0 */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val |= ATAPI_CONTROL1_ISM;
+   val |= ATAPI_CONTROL1_DESE;
+   val |= ATAPI_CONTROL1_DTA32M;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+   /* Release the SATA-IP from the reset state */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val &= ~ATAPI_CONTROL1_RESET;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
/* ack and mask */
iowrite32(0, base + SATAINTSTAT_REG);
iowrite32(0x7ff, base + SATAINTMASK_REG);
-- 
1.9.1

[PATCH/RFT v3] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

From: Hien Dang <hien.dang...@renesas.com>

This patch adds an implementation that saves and restores the state of
GPIO configuration on suspend and resume.

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[Modify structure of the bank info to simplify a saving registers]
[Remove DEV_PM_OPS macro]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-gpio tree.

v2 [Yoshihiro Kaneko]
* Modify structure of the bank info as suggested by Geert Uytterhoeven

v3 [Yoshihiro Kaneko]
* Remove DEV_PM_OPS macro as suggested by Vladimir Zapolskiy

 drivers/gpio/gpio-rcar.c | 65 
 1 file changed, 65 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index e76de57..88fbb3e 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -31,6 +31,16 @@
 #include 
 #include 
 
+struct gpio_rcar_bank_info {
+   u32 iointsel;
+   u32 inoutsel;
+   u32 outdt;
+   u32 active_high_rising_edge;
+   u32 level_trigger;
+   u32 both;
+   u32 intmsk;
+};
+
 struct gpio_rcar_priv {
void __iomem *base;
spinlock_t lock;
@@ -41,6 +51,7 @@ struct gpio_rcar_priv {
unsigned int irq_parent;
bool has_both_edge_trigger;
bool needs_clk;
+   struct gpio_rcar_bank_info bank_info;
 };
 
 #define IOINTSEL 0x00  /* General IO/Interrupt Switching Register */
@@ -531,11 +542,65 @@ static int gpio_rcar_remove(struct platform_device *pdev)
return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpio_rcar_suspend(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+
+   p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
+   p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
+   p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
+   p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
+   p->bank_info.active_high_rising_edge = gpio_rcar_read(p, POSNEG);
+   p->bank_info.level_trigger = gpio_rcar_read(p, EDGLEVEL);
+   p->bank_info.both = gpio_rcar_read(p, BOTHEDGE);
+
+   return 0;
+}
+
+static int gpio_rcar_resume(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+   int offset;
+   u32 mask;
+
+   for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
+   mask = BIT(offset);
+   /* I/O pin */
+   if (!(p->bank_info.iointsel & mask)) {
+   if (p->bank_info.inoutsel & mask)
+   gpio_rcar_direction_output(
+   >gpio_chip, offset,
+   !!(p->bank_info.outdt & mask));
+   else
+   gpio_rcar_direction_input(>gpio_chip,
+ offset);
+   /* Interrupt pin */
+   } else {
+   gpio_rcar_config_interrupt_input_mode(
+   p,
+   offset,
+   !(p->bank_info.active_high_rising_edge & mask),
+   !!(p->bank_info.level_trigger & mask),
+   !!(p->bank_info.both & mask));
+
+   if (p->bank_info.intmsk & mask)
+   gpio_rcar_write(p, MSKCLR, mask);
+   }
+   }
+
+   return 0;
+}
+#endif /* CONFIG_PM_SLEEP*/
+
+static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, 
gpio_rcar_resume);
+
 static struct platform_driver gpio_rcar_device_driver = {
.probe  = gpio_rcar_probe,
.remove = gpio_rcar_remove,
.driver = {
.name   = "gpio_rcar",
+   .pm = _rcar_pm_ops,
.of_match_table = of_match_ptr(gpio_rcar_of_table),
}
 };
-- 
1.9.1

Re: [PATCH/RFT v2] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

Hi Vladimir,

Thank you for your review.
I will re-spin this patch.

Thanks,
Kaneko

2017-12-25 17:35 GMT+09:00 Vladimir Zapolskiy <vladimir_zapols...@mentor.com>:
> On 12/24/2017 03:37 PM, Yoshihiro Kaneko wrote:
>> From: Hien Dang <hien.dang...@renesas.com>
>>
>> This patch adds an implementation that saves and restores the state of
>> GPIO configuration on suspend and resume.
>>
>> Signed-off-by: Hien Dang <hien.dang...@renesas.com>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
>> [Modify structure of the bank info to simplify a saving registers]
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
>> ---
>
> [snip]
>
>> +static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops,
>> + gpio_rcar_suspend, gpio_rcar_resume);
>> +#define DEV_PM_OPS (_rcar_pm_ops)
>> +#else
>> +#define DEV_PM_OPS NULL
>> +#endif /* CONFIG_PM_SLEEP*/
>> +
>>  static int gpio_rcar_probe(struct platform_device *pdev)
>>  {
>>   struct gpio_rcar_priv *p;
>> @@ -536,6 +604,7 @@ static int gpio_rcar_remove(struct platform_device *pdev)
>>   .remove = gpio_rcar_remove,
>>   .driver = {
>>   .name   = "gpio_rcar",
>> + .pm = DEV_PM_OPS,
>>   .of_match_table = of_match_ptr(gpio_rcar_of_table),
>>   }
>>  };
>>
>
> You can safely follow the next simpler pattern (add pm functions after
> gpio_rcar_remove() function and remove DEV_PM_OPS macro):
>
> #ifdef CONFIG_PM_SLEEP
> static int gpio_rcar_suspend(struct device *dev)
> {
> ...
> }
>
> static int gpio_rcar_resume(struct device *dev)
> {
> ...
> }
> #endif
>
> static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, 
> gpio_rcar_resume);
>
> static struct platform_driver gpio_rcar_device_driver = {
> .probe  = gpio_rcar_probe,
> .remove = gpio_rcar_remove,
> .driver = {
> .name   = "gpio_rcar",
> .pm = _rcar_pm_ops,
> .of_match_table = of_match_ptr(gpio_rcar_of_table),
> }
> };
>
> --
> With best wishes,
> Vladimir

Re: [PATCH] sata: rcar_sata: Reset SATA PHY when Salvator-X board resumes

[Yoshihiro Kaneko]

Hi Simon-san, Geert-san,

2017-12-19 17:26 GMT+09:00 Simon Horman <ho...@verge.net.au>:
> On Wed, Dec 06, 2017 at 07:56:09PM +0100, Geert Uytterhoeven wrote:
>> Hi Kaneko-san,
>>
>> On Wed, Dec 6, 2017 at 7:45 PM, Yoshihiro Kaneko <ykaneko0...@gmail.com> 
>> wrote:
>> > From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
>> >
>> > Because power of Salvator-X board is cut off in suspend,
>> > it needs to reset SATA PHY state in resume.
>> > Otherwise, SATA partition could not be accessed anymore.
>>
>> Thanks for your patch!
>>
>> So this is needed on R-Car Gen3 only.
>>
>> > --- a/drivers/ata/sata_rcar.c
>> > +++ b/drivers/ata/sata_rcar.c
>> > @@ -977,11 +977,43 @@ static int sata_rcar_resume(struct device *dev)
>> > struct sata_rcar_priv *priv = host->private_data;
>> > void __iomem *base = priv->base;
>> > int ret;
>> > +   u32 val;
>> >
>> > ret = clk_prepare_enable(priv->clk);
>> > if (ret)
>> > return ret;
>> >
>> > +   /* Re-use from sata_rcar_init_controller() */
>> > +   /* reset and setup phy */
>> > +   switch (priv->type) {
>> > +   case RCAR_GEN1_SATA:
>> > +   sata_rcar_gen1_phy_init(priv);
>>
>> Hence why do this (and the below) on R-Car Gen1, too?
>>
>> > +   break;
>> > +   case RCAR_GEN2_SATA:
>> > +   sata_rcar_gen2_phy_init(priv);
>>
>> And on both R-Car Gen2 and Gen3 (currently Gen3 is treated like Gen2
>> everywhere in the driver)?
>> What about introducing RCAR_GEN3_SATA, and doing the reinit on R-Car Gen3
>> only?
>
> Agreed, that seems to make sense.
> Kaneko-san, could you look into implementing this?

Yes, I will do it.

Kaneko

>
>>
>> > +   break;
>> > +   default:
>> > +   dev_warn(host->dev, "SATA phy is not initialized\n");
>> > +   break;
>> > +   }
>>
>> [...]
>>
>> Gr{oetje,eeting}s,
>>
>> Geert
>>
>> --
>> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
>> ge...@linux-m68k.org
>>
>> In personal conversations with technical people, I call myself a hacker. But
>> when I'm talking to journalists I just say "programmer" or something like 
>> that.
>> -- Linus Torvalds
>>

[PATCH/RFT v2] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

From: Hien Dang <hien.dang...@renesas.com>

This patch adds an implementation that saves and restores the state of
GPIO configuration on suspend and resume.

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[Modify structure of the bank info to simplify a saving registers]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-gpio tree.

v2 [Yoshihiro Kaneko]
* Modify structure of the bank info as suggested by Geert Uytterhoeven

 drivers/gpio/gpio-rcar.c | 69 
 1 file changed, 69 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index e76de57..7c7360b 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -31,6 +31,16 @@
 #include 
 #include 
 
+struct gpio_rcar_bank_info {
+   u32 iointsel;
+   u32 inoutsel;
+   u32 outdt;
+   u32 active_high_rising_edge;
+   u32 level_trigger;
+   u32 both;
+   u32 intmsk;
+};
+
 struct gpio_rcar_priv {
void __iomem *base;
spinlock_t lock;
@@ -41,6 +51,7 @@ struct gpio_rcar_priv {
unsigned int irq_parent;
bool has_both_edge_trigger;
bool needs_clk;
+   struct gpio_rcar_bank_info bank_info;
 };
 
 #define IOINTSEL 0x00  /* General IO/Interrupt Switching Register */
@@ -415,6 +426,63 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, 
unsigned int *npins)
return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpio_rcar_suspend(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+
+   p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
+   p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
+   p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
+   p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
+   p->bank_info.active_high_rising_edge = gpio_rcar_read(p, POSNEG);
+   p->bank_info.level_trigger = gpio_rcar_read(p, EDGLEVEL);
+   p->bank_info.both = gpio_rcar_read(p, BOTHEDGE);
+
+   return 0;
+}
+
+static int gpio_rcar_resume(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+   int offset;
+   u32 mask;
+
+   for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
+   mask = BIT(offset);
+   /* I/O pin */
+   if (!(p->bank_info.iointsel & mask)) {
+   if (p->bank_info.inoutsel & mask)
+   gpio_rcar_direction_output(
+   >gpio_chip, offset,
+   !!(p->bank_info.outdt & mask));
+   else
+   gpio_rcar_direction_input(>gpio_chip,
+ offset);
+   /* Interrupt pin */
+   } else {
+   gpio_rcar_config_interrupt_input_mode(
+   p,
+   offset,
+   !(p->bank_info.active_high_rising_edge & mask),
+   !!(p->bank_info.level_trigger & mask),
+   !!(p->bank_info.both & mask));
+
+   if (p->bank_info.intmsk & mask)
+   gpio_rcar_write(p, MSKCLR, mask);
+   }
+   }
+
+   return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops,
+   gpio_rcar_suspend, gpio_rcar_resume);
+#define DEV_PM_OPS (_rcar_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif /* CONFIG_PM_SLEEP*/
+
 static int gpio_rcar_probe(struct platform_device *pdev)
 {
struct gpio_rcar_priv *p;
@@ -536,6 +604,7 @@ static int gpio_rcar_remove(struct platform_device *pdev)
.remove = gpio_rcar_remove,
.driver = {
.name   = "gpio_rcar",
+   .pm = DEV_PM_OPS,
.of_match_table = of_match_ptr(gpio_rcar_of_table),
}
 };
-- 
1.9.1

Re: [PATCH] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

Hi Simon-san, Geert-san,

I am sorry for my late reply.

2017-12-07 19:27 GMT+09:00 Simon Horman :
> On Thu, Dec 07, 2017 at 10:26:53AM +0100, Geert Uytterhoeven wrote:
>> On Thu, Dec 7, 2017 at 10:21 AM, Geert Uytterhoeven
>>  wrote:
>> >>> >  struct gpio_rcar_priv {
>> >>> > void __iomem *base;
>> >>> > spinlock_t lock;
>> >>> > @@ -41,6 +51,7 @@ struct gpio_rcar_priv {
>> >>> > unsigned int irq_parent;
>> >>> > bool has_both_edge_trigger;
>> >>> > bool needs_clk;
>> >>> > +   struct gpio_rcar_bank_info bank_info[32];
>> >>>
>> >>> That's 32 x 7 = 224 bytes in total.
>> >>>
>> >>> What about just using 7 u32s instead, one for each register to save?
>> >>> That way you only need 7 x 4 = 28 bytes, and you can probably optimize
>> >>> the code to just save/restore the whole register at once.
>> >>
>> >> So the suggestion is to use a u32 instead of struct gpio_rcar_bank_info,
>> >> and for each field of struct gpio_rcar_bank_info use a bit in the u32?
>> >>
>> >> If so, probably one could go a step further and use a u8 as there are
>> >> currently only 7 fields, thus using 32 x 1 = 32 bytes rather than
>> >> 32 x 4 = 128 bytes.
>> >
>> > I think you misunderstood.
>> > The patch has one gpio_rcar_bank_info for each GPIO.
>> > Each bank has 7 bits (bools), one for each register.
>> > Indexing is done through bank_info[]..
>> > Saving/restoring bits requires converting from hardware register layout to
>> > stored layout ("transposing a 32 x 7 matrix to a 7 x 32 matrix").
>> >
>> > I proposed 7 u32s, one for each register, storing the similar bits for all
>> > 32 GPIOs.
>> > So indexing is reversed, becoming regs[] & BIT(), which is
>> > similar to how the data is stored in hardware registers.
>> > Storing all bits related to a single register in a single u32 may allow to
>> > save/restore all bits of the register in a single operation.
>>
>> More clarification: it's the difference between "int array[7][32]" and
>> "int array[32][7]".  Both store the same amount of data.
>> But if the hardware uses the former organization, you want to
>> save/restore using the same organization, else it requires an expensive
>> transformation.
>
> Thanks, you are correct that I misunderstood.
> I understand now.
>
> Kaneko-san, could you take a look at switching this around and posting an RFT?

Sure, will do.

Thanks,
Kaneko

[PATCH] gpio: gpio-rcar: Support S2RAM

[Yoshihiro Kaneko]

From: Hien Dang <hien.dang...@renesas.com>

This patch adds an implementation that saves and restores the state of
GPIO configuration on suspend and resume.

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-gpio tree.

 drivers/gpio/gpio-rcar.c | 89 
 1 file changed, 89 insertions(+)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index e76de57..c99a2c5 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -31,6 +31,16 @@
 #include 
 #include 
 
+struct gpio_rcar_bank_info {
+   bool iointsel;
+   bool inoutsel;
+   bool outdt;
+   bool active_high_rising_edge;
+   bool level_trigger;
+   bool both;
+   bool intmsk;
+};
+
 struct gpio_rcar_priv {
void __iomem *base;
spinlock_t lock;
@@ -41,6 +51,7 @@ struct gpio_rcar_priv {
unsigned int irq_parent;
bool has_both_edge_trigger;
bool needs_clk;
+   struct gpio_rcar_bank_info bank_info[32];
 };
 
 #define IOINTSEL 0x00  /* General IO/Interrupt Switching Register */
@@ -415,6 +426,83 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, 
unsigned int *npins)
return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpio_rcar_suspend(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+   int offset;
+   u32 bit_mask;
+   struct gpio_rcar_bank_info *bank_info;
+
+   for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
+   bank_info = >bank_info[offset];
+   bit_mask = BIT(offset);
+   bank_info->iointsel = !!(gpio_rcar_read(p, IOINTSEL) &
+bit_mask);
+
+   /* I/O pin  */
+   if (!bank_info->iointsel) {
+   bank_info->inoutsel = !!(gpio_rcar_read(p, INOUTSEL) &
+bit_mask);
+   bank_info->outdt = !!(gpio_rcar_read(p, OUTDT) &
+ bit_mask);
+   /* Interrupt pin  */
+   } else {
+   bank_info->intmsk = !!(gpio_rcar_read(p, INTMSK) &
+  bit_mask);
+   bank_info->active_high_rising_edge =
+   !(!!(gpio_rcar_read(p, POSNEG) & bit_mask));
+   bank_info->level_trigger =
+   !(!!(gpio_rcar_read(p, EDGLEVEL) & bit_mask));
+   bank_info->both = !!(gpio_rcar_read(p, BOTHEDGE) &
+bit_mask);
+   }
+   }
+
+   return 0;
+}
+
+static int gpio_rcar_resume(struct device *dev)
+{
+   struct gpio_rcar_priv *p = dev_get_drvdata(dev);
+   int offset;
+   struct gpio_rcar_bank_info *bank_info;
+
+   for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
+   bank_info = >bank_info[offset];
+   /* I/O pin  */
+   if (!bank_info->iointsel) {
+   if (bank_info->inoutsel)
+   gpio_rcar_direction_output(>gpio_chip,
+  offset,
+  bank_info->outdt);
+   else
+   gpio_rcar_direction_input(>gpio_chip,
+ offset);
+   /* Interrupt pin  */
+   } else {
+   gpio_rcar_config_interrupt_input_mode(
+   p,
+   offset,
+   bank_info->active_high_rising_edge,
+   bank_info->level_trigger,
+   bank_info->both);
+
+   if (bank_info->intmsk)
+   gpio_rcar_write(p, MSKCLR, BIT(offset));
+   }
+   }
+
+   return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops,
+   gpio_rcar_suspend, gpio_rcar_resume);
+#define DEV_PM_OPS (_rcar_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif /* CONFIG_PM_SLEEP*/
+
 static int gpio_rcar_probe(struct platform_device *pdev)
 {
struct gpio_rcar_priv *p;
@@ -536,6 +624,7 @@ static int gpio_rcar_remove(struct platform_device *pdev)
.remove = gpio_rcar_remove,
.driver = {
.name   = "gpio_rcar",
+   .pm = DEV_PM_OPS,
.of_match_table = of_match_ptr(gpio_rcar_of_table),
}
 };
-- 
1.9.1

[PATCH] sata: rcar_sata: Reset SATA PHY when Salvator-X board resumes

[Yoshihiro Kaneko]

From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>

Because power of Salvator-X board is cut off in suspend,
it needs to reset SATA PHY state in resume.
Otherwise, SATA partition could not be accessed anymore.

Signed-off-by: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
Signed-off-by: Hien Dang <hien.dang...@rvc.renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of libata tree.

 drivers/ata/sata_rcar.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 80ee2f2..aba6121 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -977,11 +977,43 @@ static int sata_rcar_resume(struct device *dev)
struct sata_rcar_priv *priv = host->private_data;
void __iomem *base = priv->base;
int ret;
+   u32 val;
 
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
 
+   /* Re-use from sata_rcar_init_controller() */
+   /* reset and setup phy */
+   switch (priv->type) {
+   case RCAR_GEN1_SATA:
+   sata_rcar_gen1_phy_init(priv);
+   break;
+   case RCAR_GEN2_SATA:
+   sata_rcar_gen2_phy_init(priv);
+   break;
+   default:
+   dev_warn(host->dev, "SATA phy is not initialized\n");
+   break;
+   }
+
+   /* SATA-IP reset state */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val |= ATAPI_CONTROL1_RESET;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+   /* ISM mode, PRD mode, DTEND flag at bit 0 */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val |= ATAPI_CONTROL1_ISM;
+   val |= ATAPI_CONTROL1_DESE;
+   val |= ATAPI_CONTROL1_DTA32M;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+   /* Release the SATA-IP from the reset state */
+   val = ioread32(base + ATAPI_CONTROL1_REG);
+   val &= ~ATAPI_CONTROL1_RESET;
+   iowrite32(val, base + ATAPI_CONTROL1_REG);
+
/* ack and mask */
iowrite32(0, base + SATAINTSTAT_REG);
iowrite32(0x7ff, base + SATAINTMASK_REG);
-- 
1.9.1

[PATCH] pinctrl: sh-pfc: r8a7796: Rename RTS{0,1,3,4}# pin function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch renames the pin function macro definitions of the GPSR5 and
IPSR{0,3,5,6,12} registers value for the RTS{0,1,3,4}# pin.

This is a correction because GPSR and IPSR register specification for
R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-pinctrl tree.

 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 48 ++--
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 954daae..e5807d1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -163,11 +163,11 @@
 #define GPSR5_11   F_(RX2_A,   IP13_7_4)
 #define GPSR5_10   F_(TX2_A,   IP13_3_0)
 #define GPSR5_9F_(SCK2,IP12_31_28)
-#define GPSR5_8F_(RTS1_N_TANS, IP12_27_24)
+#define GPSR5_8F_(RTS1_N,  IP12_27_24)
 #define GPSR5_7F_(CTS1_N,  IP12_23_20)
 #define GPSR5_6F_(TX1_A,   IP12_19_16)
 #define GPSR5_5F_(RX1_A,   IP12_15_12)
-#define GPSR5_4F_(RTS0_N_TANS, IP12_11_8)
+#define GPSR5_4F_(RTS0_N,  IP12_11_8)
 #define GPSR5_3F_(CTS0_N,  IP12_7_4)
 #define GPSR5_2F_(TX0, IP12_3_0)
 #define GPSR5_1F_(RX0, IP11_31_28)
@@ -220,7 +220,7 @@
 #define IP0_11_8   FM(AVB_PHY_INT) F_(0, 0)
FM(MSIOF2_SYNC_C)   FM(RX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,7 +240,7 @@
 #define IP2_27_24  FM(A7)  FM(LCDOUT23)
FM(MSIOF2_SS2_A)FM(TX4_B)   FM(VI4_DATA15)  
FM(VI5_DATA15)  FM(DU_DB7)  F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP2_31_28  FM(A8)  FM(RX3_B)   
FM(MSIOF2_SYNC_A)   FM(HRX4_B)  F_(0, 0)F_(0, 
0)F_(0, 0)FM(SDA6_A)  FM(AVB_AVTP_MATCH_B)
FM(PWM1_B)  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP3_3_0FM(A9)  F_(0, 0)
FM(MSIOF2_SCK_A)FM(CTS4_N_B)F_(0, 0)
FM(VI

[PATCH] pinctrl: sh-pfc: r8a7795: Rename RTS{0,1,3,4}# pin function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch renames the pin function macro definitions of the GPSR and
IPSR registers value for the RTS{0,1,3,4}# pin.

This is a correction because GPSR and IPSR register specification for
R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual
Rev.0.54E.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-pinctrl tree.

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 ++--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index b513010..df7cd0f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -158,11 +158,11 @@
 #define GPSR5_11   F_(RX2_A,   IP13_7_4)
 #define GPSR5_10   F_(TX2_A,   IP13_3_0)
 #define GPSR5_9F_(SCK2,IP12_31_28)
-#define GPSR5_8F_(RTS1_N_TANS, IP12_27_24)
+#define GPSR5_8F_(RTS1_N,  IP12_27_24)
 #define GPSR5_7F_(CTS1_N,  IP12_23_20)
 #define GPSR5_6F_(TX1_A,   IP12_19_16)
 #define GPSR5_5F_(RX1_A,   IP12_15_12)
-#define GPSR5_4F_(RTS0_N_TANS, IP12_11_8)
+#define GPSR5_4F_(RTS0_N,  IP12_11_8)
 #define GPSR5_3F_(CTS0_N,  IP12_7_4)
 #define GPSR5_2F_(TX0, IP12_3_0)
 #define GPSR5_1F_(RX0, IP11_31_28)
@@ -215,7 +215,7 @@
 #define IP0_11_8   FM(AVB_PHY_INT) F_(0, 0)
FM(MSIOF2_SYNC_C)   FM(RX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)
FM(FSCLKST2_N_A) F_(0, 0)   F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
-#define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -237,7 +237,7 @@
 #define IP2_27_24  FM(A7)  FM(LCDOUT23)
FM(MSIOF2_SS2_A)FM(TX4_B)   FM(VI4_DATA15)  
FM(VI5_DATA15)  FM(DU_DB7)  F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP2_31_28  FM(A8)  FM(RX3_B)   
FM(MSIOF2_SYNC_A)   FM(HRX4_B)  F_(0, 0)F_(0, 
0)F_(0, 0)FM(SDA6_A)  FM(AVB_AVTP_MATCH_B)
FM(PWM1_B)  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP3_3_0FM(A9)  F_(0, 0)
FM(MSIOF2_SCK_A)FM(CTS4_N_B)F_(0, 0)
FM(VI

[PATCH] pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25 pins function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch fixes the macro definitions of A20..A25 pins function deleted.

This is a correction because IPSR register specification for R8A7796 SoC
was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---

This patch is based on the for-next branch of linux-pinctrl tree.

 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 ++
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 73ed9c7..954daae 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -224,12 +224,12 @@
 #define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   FM(A25) 
FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)
F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)  
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)FM(A24) 
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_15_12  FM(IRQ5)FM(QSTB_QHE)FM(A23) 
FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_TXD_E) F_(0, 0)   FM(PWM6_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_19_16  FM(PWM0)FM(AVB_AVTP_PPS)FM(A22) 
F_(0, 0)FM(VI4_DATA6_B) F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)FM(IECLK_B) F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_23_20  FM(PWM1_A)  F_(0, 0)FM(A21) 
FM(HRX3_D)  FM(VI4_DATA7_B) F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)FM(IERX_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1_27_24  FM(PWM2_A)  F_(0, 0)FM(A20) 
FM(HTX3_D)  F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)FM(IETX_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   F_(0, 
0)FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)F_(0, 0)
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12  FM(IRQ5)FM(QSTB_QHE)F_(0, 0)
FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_TXD_E) F_(0, 0)   FM(PWM6_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16  FM(PWM0)FM(AVB_AVTP_PPS)F_(0, 0)
F_(0, 0)FM(VI4_DATA6_B) F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)FM(IECLK_B) F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20  FM(PWM1_A)  F_(0, 0)F_(0, 0)
FM(HRX3_D)  FM(VI4_DATA7