Re: [PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-08-27 Thread Simon Horman 
On Fri, Aug 24, 2018 at 10:23:28AM +0200, Simon Horman wrote:
> On Wed, Aug 22, 2018 at 04:41:18PM +0200, Simon Horman wrote:
> > On Tue, Aug 14, 2018 at 11:12:41PM +0900, Yoshihiro Kaneko wrote:
> > > From: Dien Pham 
> > > 
> > > This patch adds OPPs table for CA57{0,1} cpu devices
> > > 
> > > Signed-off-by: Dien Pham 
> > > Signed-off-by: Takeshi Kihara 
> > > Signed-off-by: Yoshihiro Kaneko 
> > 
> > Tested on r8a77965/Salvator-XS
> > 
> > I see that CPUFreq is activated, that sysfs reports 3 possible
> > CPU speeds; 1.5, 1.0 and 0.50GHz. That current CPU frequency can be 
> > manipulated
> > by setting the maximum CPU frequency in sysfs. And that the frequency
> > of Z clock changes accordingly.
> > 
> > Tested-by: Simon Horman 
> 
> I have applied this for v4.20.

I noticed that this patch included unit numbers for the opps nodes.
This is not correct as there is no bus that the nodes live on.
I fixed this using s/@/-/.
The result is below:

>From cd889b86ce3fba300ce82b0ec22bf310cd2f361d Mon Sep 17 00:00:00 2001
From: Dien Pham 
Date: Tue, 14 Aug 2018 23:12:41 +0900
Subject: [PATCH] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
Tested-by: Simon Horman 
[simon: do not give nodes unit names as they have no bus addresses]
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index e7128fb65e33..5ce978502ee9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp-15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp-16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp-17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp-18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
2.11.0

Re: [PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-08-24 Thread Simon Horman 
On Wed, Aug 22, 2018 at 04:41:18PM +0200, Simon Horman wrote:
> On Tue, Aug 14, 2018 at 11:12:41PM +0900, Yoshihiro Kaneko wrote:
> > From: Dien Pham 
> > 
> > This patch adds OPPs table for CA57{0,1} cpu devices
> > 
> > Signed-off-by: Dien Pham 
> > Signed-off-by: Takeshi Kihara 
> > Signed-off-by: Yoshihiro Kaneko 
> 
> Tested on r8a77965/Salvator-XS
> 
> I see that CPUFreq is activated, that sysfs reports 3 possible
> CPU speeds; 1.5, 1.0 and 0.50GHz. That current CPU frequency can be 
> manipulated
> by setting the maximum CPU frequency in sysfs. And that the frequency
> of Z clock changes accordingly.
> 
> Tested-by: Simon Horman 

I have applied this for v4.20.

Re: [PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-08-22 Thread Simon Horman 
On Tue, Aug 14, 2018 at 11:12:41PM +0900, Yoshihiro Kaneko wrote:
> From: Dien Pham 
> 
> This patch adds OPPs table for CA57{0,1} cpu devices
> 
> Signed-off-by: Dien Pham 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Tested on r8a77965/Salvator-XS

I see that CPUFreq is activated, that sysfs reports 3 possible
CPU speeds; 1.5, 1.0 and 0.50GHz. That current CPU frequency can be manipulated
by setting the maximum CPU frequency in sysfs. And that the frequency
of Z clock changes accordingly.

Tested-by: Simon Horman

[PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-08-14 Thread Yoshihiro Kaneko 
From: Dien Pham 

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 52205be..c5fb35b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp@16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
1.9.1

Re: [PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-07-30 Thread Geert Uytterhoeven 
Hi Kaneko-san,

On Wed, Jul 25, 2018 at 10:42 PM Yoshihiro Kaneko  wrote:
> From: Dien Pham 
>
> This patch adds OPPs table for CA57{0,1} cpu devices
>
> Signed-off-by: Dien Pham 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Syntax looks good, but I cannot review the actual values.
Acked-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH/RFT] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

2018-07-25 Thread Yoshihiro Kaneko 
From: Dien Pham 

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0a64b72..28dcbb6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp@15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp@16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp@18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
1.9.1