Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-05-04 Thread Yoshihiro Kaneko 
Hi Geert-san,

2018-05-04 17:30 GMT+09:00 Geert Uytterhoeven :
> Hi Kaneko-san,
>
> On Fri, May 4, 2018 at 10:28 AM, Yoshihiro Kaneko  
> wrote:
>> 2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven :
>>> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko  
>>> wrote:
 From: Takeshi Kihara 

 This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
 SoC.

 Signed-off-by: Takeshi Kihara 
 Signed-off-by: Yoshihiro Kaneko 
>>>
>>> Thanks for your patch!
>>>
>>> The pins, groups, and functions are correct, so
>>> Reviewed-by: Geert Uytterhoeven .
>>> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.
>>
>> Thanks for your review!
>> I will fix up the below in V2.
>
> There's no need to send a v2, as I have already fixed and applied your patch.

Okay, Thanks!

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-05-04 Thread Geert Uytterhoeven 
Hi Kaneko-san,

On Fri, May 4, 2018 at 10:28 AM, Yoshihiro Kaneko  wrote:
> 2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven :
>> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko  
>> wrote:
>>> From: Takeshi Kihara 
>>>
>>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>>> SoC.
>>>
>>> Signed-off-by: Takeshi Kihara 
>>> Signed-off-by: Yoshihiro Kaneko 
>>
>> Thanks for your patch!
>>
>> The pins, groups, and functions are correct, so
>> Reviewed-by: Geert Uytterhoeven .
>> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.
>
> Thanks for your review!
> I will fix up the below in V2.

There's no need to send a v2, as I have already fixed and applied your patch.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-05-04 Thread Yoshihiro Kaneko 
Hi Geert-san,

2018-05-02 18:16 GMT+09:00 Geert Uytterhoeven :
> Hi Kaneko-san,
>
> On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko  
> wrote:
>> From: Takeshi Kihara 
>>
>> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
>> SoC.
>>
>> Signed-off-by: Takeshi Kihara 
>> Signed-off-by: Yoshihiro Kaneko 
>
> Thanks for your patch!
>
> The pins, groups, and functions are correct, so
> Reviewed-by: Geert Uytterhoeven .
> i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.

Thanks for your review!
I will fix up the below in V2.

>
>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
>> @@ -1923,6 +1923,264 @@ enum {
>> RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>>  };
>>
>> +/* - SDHI0 
>> -- */
>> +static const unsigned int sdhi0_data1_pins[] = {
>
> [...]
>
>> +};
>
> This doesn't belong in the middle of the usb0 section ;-)
>
>> +
>>  static const unsigned int usb0_mux[] = {
>> USB0_PWEN_MARK, USB0_OVC_MARK,
>>  };
>> @@ -1997,6 +2255,32 @@ enum {
>> SH_PFC_PIN_GROUP(usb0),
>> SH_PFC_PIN_GROUP(usb1),
>> SH_PFC_PIN_GROUP(usb30),
>> +   SH_PFC_PIN_GROUP(sdhi0_data1),
>
> Alphabetical order, please.
>
>> @@ -2083,6 +2367,44 @@ enum {
>> "usb30",
>>  };
>>
>> +static const char * const sdhi0_groups[] = {
>
> Alphabetical order, please.
>
>> @@ -2096,6 +2418,10 @@ enum {
>> SH_PFC_FUNCTION(usb0),
>> SH_PFC_FUNCTION(usb1),
>> SH_PFC_FUNCTION(usb30),
>> +   SH_PFC_FUNCTION(sdhi0),
>> +   SH_PFC_FUNCTION(sdhi1),
>> +   SH_PFC_FUNCTION(sdhi2),
>> +   SH_PFC_FUNCTION(sdhi3),
>>  };
>
> Alphabetical order, please.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Best regards,
Kaneko

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-05-02 Thread Geert Uytterhoeven 
Hi Kaneko-san,

On Sun, Apr 29, 2018 at 9:48 PM, Yoshihiro Kaneko  wrote:
> From: Takeshi Kihara 
>
> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
> SoC.
>
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Thanks for your patch!

The pins, groups, and functions are correct, so
Reviewed-by: Geert Uytterhoeven .
i.e. queuing in sh-pfc-for-v4.18, after fixing up the below.

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1923,6 +1923,264 @@ enum {
> RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>  };
>
> +/* - SDHI0 
> -- */
> +static const unsigned int sdhi0_data1_pins[] = {

[...]

> +};

This doesn't belong in the middle of the usb0 section ;-)

> +
>  static const unsigned int usb0_mux[] = {
> USB0_PWEN_MARK, USB0_OVC_MARK,
>  };
> @@ -1997,6 +2255,32 @@ enum {
> SH_PFC_PIN_GROUP(usb0),
> SH_PFC_PIN_GROUP(usb1),
> SH_PFC_PIN_GROUP(usb30),
> +   SH_PFC_PIN_GROUP(sdhi0_data1),

Alphabetical order, please.

> @@ -2083,6 +2367,44 @@ enum {
> "usb30",
>  };
>
> +static const char * const sdhi0_groups[] = {

Alphabetical order, please.

> @@ -2096,6 +2418,10 @@ enum {
> SH_PFC_FUNCTION(usb0),
> SH_PFC_FUNCTION(usb1),
> SH_PFC_FUNCTION(usb30),
> +   SH_PFC_FUNCTION(sdhi0),
> +   SH_PFC_FUNCTION(sdhi1),
> +   SH_PFC_FUNCTION(sdhi2),
> +   SH_PFC_FUNCTION(sdhi3),
>  };

Alphabetical order, please.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-05-01 Thread Simon Horman 
On Mon, Apr 30, 2018 at 04:48:14AM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara 
> 
> This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
> SoC.
> 
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Reviewed-by: Simon Horman 

> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 
> ++
>  1 file changed, 326 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c 
> b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> index cea9d05..0350197 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
> @@ -1923,6 +1923,264 @@ enum {
>   RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
>  };
>  
> +/* - SDHI0 
> -- */
> +static const unsigned int sdhi0_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(3, 2),
> +};
> +
> +static const unsigned int sdhi0_data1_mux[] = {
> + SD0_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi0_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
> + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
> +};
> +
> +static const unsigned int sdhi0_data4_mux[] = {
> + SD0_DAT0_MARK, SD0_DAT1_MARK,
> + SD0_DAT2_MARK, SD0_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi0_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +};
> +
> +static const unsigned int sdhi0_ctrl_mux[] = {
> + SD0_CLK_MARK, SD0_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi0_cd_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(3, 12),
> +};
> +
> +static const unsigned int sdhi0_cd_mux[] = {
> + SD0_CD_MARK,
> +};
> +
> +static const unsigned int sdhi0_wp_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(3, 13),
> +};
> +
> +static const unsigned int sdhi0_wp_mux[] = {
> + SD0_WP_MARK,
> +};
> +
> +/* - SDHI1 
> -- */
> +static const unsigned int sdhi1_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(3, 8),
> +};
> +
> +static const unsigned int sdhi1_data1_mux[] = {
> + SD1_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi1_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi1_data4_mux[] = {
> + SD1_DAT0_MARK, SD1_DAT1_MARK,
> + SD1_DAT2_MARK, SD1_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi1_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +};
> +
> +static const unsigned int sdhi1_ctrl_mux[] = {
> + SD1_CLK_MARK, SD1_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi1_cd_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(3, 14),
> +};
> +
> +static const unsigned int sdhi1_cd_mux[] = {
> + SD1_CD_MARK,
> +};
> +
> +static const unsigned int sdhi1_wp_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(3, 15),
> +};
> +
> +static const unsigned int sdhi1_wp_mux[] = {
> + SD1_WP_MARK,
> +};
> +
> +/* - SDHI2 
> -- */
> +static const unsigned int sdhi2_data1_pins[] = {
> + /* D0 */
> + RCAR_GP_PIN(4, 2),
> +};
> +
> +static const unsigned int sdhi2_data1_mux[] = {
> + SD2_DAT0_MARK,
> +};
> +
> +static const unsigned int sdhi2_data4_pins[] = {
> + /* D[0:3] */
> + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
> + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
> +};
> +
> +static const unsigned int sdhi2_data4_mux[] = {
> + SD2_DAT0_MARK, SD2_DAT1_MARK,
> + SD2_DAT2_MARK, SD2_DAT3_MARK,
> +};
> +
> +static const unsigned int sdhi2_data8_pins[] = {
> + /* D[0:7] */
> + RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
> + RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
> + RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
> + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
> +};
> +
> +static const unsigned int sdhi2_data8_mux[] = {
> + SD2_DAT0_MARK, SD2_DAT1_MARK,
> + SD2_DAT2_MARK, SD2_DAT3_MARK,
> + SD2_DAT4_MARK, SD2_DAT5_MARK,
> + SD2_DAT6_MARK, SD2_DAT7_MARK,
> +};
> +
> +static const unsigned int sdhi2_ctrl_pins[] = {
> + /* CLK, CMD */
> + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
> +};
> +
> +static const unsigned int sdhi2_ctrl_mux[] = {
> + SD2_CLK_MARK, SD2_CMD_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_a_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(4, 13),
> +};
> +
> +static const unsigned int sdhi2_cd_a_mux[] = {
> + SD2_CD_A_MARK,
> +};
> +
> +static const unsigned int sdhi2_cd_b_pins[] = {
> + /* CD */
> + RCAR_GP_PIN(5, 10),
> +};
> +
> +static const unsigned int sdhi2_cd_b_mux[] = {
> + SD2_CD_B_MARK,
> +};
> +
> +static const unsigned int sdhi2_wp_a_pins[] = {
> + /* WP */
> + RCAR_GP_PIN(4, 14),
> +};
> +
> +static const

[PATCH/RFT 1/3] pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions

2018-04-29 Thread Yoshihiro Kaneko 
From: Takeshi Kihara 

This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 326 ++
 1 file changed, 326 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index cea9d05..0350197 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1923,6 +1923,264 @@ enum {
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
 };
 
+/* - SDHI0 -- 
*/
+static const unsigned int sdhi0_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int sdhi0_data1_mux[] = {
+   SD0_DAT0_MARK,
+};
+
+static const unsigned int sdhi0_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+   RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int sdhi0_data4_mux[] = {
+   SD0_DAT0_MARK, SD0_DAT1_MARK,
+   SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+
+static const unsigned int sdhi0_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+
+static const unsigned int sdhi0_ctrl_mux[] = {
+   SD0_CLK_MARK, SD0_CMD_MARK,
+};
+
+static const unsigned int sdhi0_cd_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi0_cd_mux[] = {
+   SD0_CD_MARK,
+};
+
+static const unsigned int sdhi0_wp_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi0_wp_mux[] = {
+   SD0_WP_MARK,
+};
+
+/* - SDHI1 -- 
*/
+static const unsigned int sdhi1_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(3, 8),
+};
+
+static const unsigned int sdhi1_data1_mux[] = {
+   SD1_DAT0_MARK,
+};
+
+static const unsigned int sdhi1_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi1_data4_mux[] = {
+   SD1_DAT0_MARK, SD1_DAT1_MARK,
+   SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+
+static const unsigned int sdhi1_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int sdhi1_ctrl_mux[] = {
+   SD1_CLK_MARK, SD1_CMD_MARK,
+};
+
+static const unsigned int sdhi1_cd_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int sdhi1_cd_mux[] = {
+   SD1_CD_MARK,
+};
+
+static const unsigned int sdhi1_wp_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int sdhi1_wp_mux[] = {
+   SD1_WP_MARK,
+};
+
+/* - SDHI2 -- 
*/
+static const unsigned int sdhi2_data1_pins[] = {
+   /* D0 */
+   RCAR_GP_PIN(4, 2),
+};
+
+static const unsigned int sdhi2_data1_mux[] = {
+   SD2_DAT0_MARK,
+};
+
+static const unsigned int sdhi2_data4_pins[] = {
+   /* D[0:3] */
+   RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+   RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+
+static const unsigned int sdhi2_data4_mux[] = {
+   SD2_DAT0_MARK, SD2_DAT1_MARK,
+   SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+
+static const unsigned int sdhi2_data8_pins[] = {
+   /* D[0:7] */
+   RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
+   RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
+   RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi2_data8_mux[] = {
+   SD2_DAT0_MARK, SD2_DAT1_MARK,
+   SD2_DAT2_MARK, SD2_DAT3_MARK,
+   SD2_DAT4_MARK, SD2_DAT5_MARK,
+   SD2_DAT6_MARK, SD2_DAT7_MARK,
+};
+
+static const unsigned int sdhi2_ctrl_pins[] = {
+   /* CLK, CMD */
+   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+
+static const unsigned int sdhi2_ctrl_mux[] = {
+   SD2_CLK_MARK, SD2_CMD_MARK,
+};
+
+static const unsigned int sdhi2_cd_a_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(4, 13),
+};
+
+static const unsigned int sdhi2_cd_a_mux[] = {
+   SD2_CD_A_MARK,
+};
+
+static const unsigned int sdhi2_cd_b_pins[] = {
+   /* CD */
+   RCAR_GP_PIN(5, 10),
+};
+
+static const unsigned int sdhi2_cd_b_mux[] = {
+   SD2_CD_B_MARK,
+};
+
+static const unsigned int sdhi2_wp_a_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(4, 14),
+};
+
+static const unsigned int sdhi2_wp_a_mux[] = {
+   SD2_WP_A_MARK,
+};
+
+static const unsigned int sdhi2_wp_b_pins[] = {
+   /* WP */
+   RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int sdhi2_wp_b_mux[] = {
+   SD2_WP_B_MARK,
+};
+
+static const unsigned int sdhi2_ds_pins[] = {
+   /* DS */
+   RCAR_GP_PIN(4, 6),
+};
+
+static const unsigned int sdhi2_ds_mux[]