[PATCH] ARM: shmobile: rcar-gen2: Add more register documentation

2017-01-26 Thread Simon Horman 
From: Geert Uytterhoeven 

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c 
b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd9ac366868f..0178da7ace82 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -20,14 +20,30 @@
 
 /* RST */
 #define RST0xe616
-#define CA15BAR0x0020
-#define CA7BAR 0x0030
-#define CA15RESCNT 0x0040
-#define CA7RESCNT  0x0044
+
+#define CA15BAR0x0020  /* CA15 Boot Address Register */
+#define CA7BAR 0x0030  /* CA7 Boot Address Register */
+#define CA15RESCNT 0x0040  /* CA15 Reset Control Register */
+#define CA7RESCNT  0x0044  /* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN BIT(4)  /* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE0xa5a5
+#define CA15RESCNT_CPUS0xf /* CPU0-3 */
+#define CA7RESCNT_CODE 0x5a5a
+#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
+
 
 /* On-chip RAM */
 #define ICRAM1 0xe63c  /* Inter Connect RAM1 (4 KiB) */
 
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+   return (addr >> 8) & 0xfc00;
+}
+
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
@@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void)
 
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
-   bar = (boot_vector_addr >> 8) & 0xfc00;
+   bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
-   writel_relaxed(bar | 0x10, p + CA15BAR);
+   writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
 
/* de-assert reset for CA15 CPUs */
-   writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
-   0xa5a5, p + CA15RESCNT);
+   writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+   ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+  p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
-   writel_relaxed(bar | 0x10, p + CA7BAR);
+   writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
 
/* de-assert reset for CA7 CPUs */
-   writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
-   0x5a5a, p + CA7RESCNT);
+   writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+   ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+  p + CA7RESCNT);
}
iounmap(p);
 
-- 
2.7.0.rc3.207.g0ac5344

Re: [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation

2017-01-23 Thread Simon Horman 
On Mon, Jan 23, 2017 at 10:11:20AM +0100, Geert Uytterhoeven wrote:
> Hi Sergei,
> 
> On Fri, Jan 20, 2017 at 5:21 PM, Sergei Shtylyov
>  wrote:
> > On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
> >
> >> Signed-off-by: Geert Uytterhoeven 
> >> ---
> >>  arch/arm/mach-shmobile/pm-rcar-gen2.c | 40
> >> +--
> >>  1 file changed, 29 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> index dd9ac366868f4336..6ed9aa19c4d34766 100644
> >> --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> @@ -20,14 +20,30 @@
> >
> > [...]
> >>
> >> +static inline u32 phys_to_sbar(phys_addr_t addr)
> >> +{
> >> +   return (((addr) >> 8) & 0xfc00);
> >
> >
> >   It's not a macro -- innermost parens not needed...
> 
> Thanks, outermost neither ;-)

Geert, I'm assuming you will respin this.
Let me know if that is not the case.

Re: [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation

2017-01-23 Thread Geert Uytterhoeven 
Hi Sergei,

On Fri, Jan 20, 2017 at 5:21 PM, Sergei Shtylyov
 wrote:
> On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
>
>> Signed-off-by: Geert Uytterhoeven 
>> ---
>>  arch/arm/mach-shmobile/pm-rcar-gen2.c | 40
>> +--
>>  1 file changed, 29 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> b/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> index dd9ac366868f4336..6ed9aa19c4d34766 100644
>> --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> @@ -20,14 +20,30 @@
>
> [...]
>>
>> +static inline u32 phys_to_sbar(phys_addr_t addr)
>> +{
>> +   return (((addr) >> 8) & 0xfc00);
>
>
>   It's not a macro -- innermost parens not needed...

Thanks, outermost neither ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation

2017-01-20 Thread Sergei Shtylyov 

On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:


Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c 
b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd9ac366868f4336..6ed9aa19c4d34766 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -20,14 +20,30 @@

[...]

+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+   return (((addr) >> 8) & 0xfc00);


  It's not a macro -- innermost parens not needed...

[...]

MBR, Sergei

[PATCH] ARM: shmobile: rcar-gen2: Add more register documentation

2017-01-20 Thread Geert Uytterhoeven 
Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +--
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c 
b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd9ac366868f4336..6ed9aa19c4d34766 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -20,14 +20,30 @@
 
 /* RST */
 #define RST0xe616
-#define CA15BAR0x0020
-#define CA7BAR 0x0030
-#define CA15RESCNT 0x0040
-#define CA7RESCNT  0x0044
+
+#define CA15BAR0x0020  /* CA15 Boot Address Register */
+#define CA7BAR 0x0030  /* CA7 Boot Address Register */
+#define CA15RESCNT 0x0040  /* CA15 Reset Control Register */
+#define CA7RESCNT  0x0044  /* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN BIT(4)  /* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE0xa5a5
+#define CA15RESCNT_CPUS0xf /* CPU0-3 */
+#define CA7RESCNT_CODE 0x5a5a
+#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
+
 
 /* On-chip RAM */
 #define ICRAM1 0xe63c  /* Inter Connect RAM1 (4 KiB) */
 
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+   return (((addr) >> 8) & 0xfc00);
+}
+
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
@@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void)
 
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
-   bar = (boot_vector_addr >> 8) & 0xfc00;
+   bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
-   writel_relaxed(bar | 0x10, p + CA15BAR);
+   writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
 
/* de-assert reset for CA15 CPUs */
-   writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
-   0xa5a5, p + CA15RESCNT);
+   writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+   ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+  p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
-   writel_relaxed(bar | 0x10, p + CA7BAR);
+   writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
 
/* de-assert reset for CA7 CPUs */
-   writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
-   0x5a5a, p + CA7RESCNT);
+   writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+   ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+  p + CA7RESCNT);
}
iounmap(p);
 
-- 
1.9.1