Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions

[Geert Uytterhoeven]

On Wed, Jan 31, 2018 at 9:27 PM, Sergei Shtylyov
 wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions

[Simon Horman]

On Wed, Jan 31, 2018 at 11:27:47PM +0300, Sergei Shtylyov wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
> 
> Based on the original (and large) patch by Vladimir Barinov.
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 

Reviewed-by: Simon Horman 

Re: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions

[Rob Herring]

On Wed, Jan 31, 2018 at 11:27:47PM +0300, Sergei Shtylyov wrote:
> Add macros usable by the device tree sources to reference the R8A77980
> CPG core clocks by index. The data come from the table 8.2e of the R-Car
> Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
> however I had to add the Z2 clock which is somehow present only on the
> figure 8.1e...
> 
> Based on the original (and large) patch by Vladimir Barinov.
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
>  include/dt-bindings/clock/r8a77980-cpg-mssr.h |   51 
> ++
>  1 file changed, 51 insertions(+)
> 
> Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
> ===
> --- /dev/null
> +++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0+

This should end with ' */' and be its own comment. Otherwise,

Reviewed-by: Rob Herring 

[PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions

[Sergei Shtylyov]

Add macros usable by the device tree sources to reference the R8A77980
CPG core clocks by index. The data come from the table 8.2e of the R-Car
Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017),
however I had to add the Z2 clock which is somehow present only on the
figure 8.1e...

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 include/dt-bindings/clock/r8a77980-cpg-mssr.h |   51 ++
 1 file changed, 51 insertions(+)

Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
===
--- /dev/null
+++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include 
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z20
+#define R8A77980_CLK_ZR1
+#define R8A77980_CLK_ZTR   2
+#define R8A77980_CLK_ZTRD2 3
+#define R8A77980_CLK_ZT4
+#define R8A77980_CLK_ZX5
+#define R8A77980_CLK_S0D1  6
+#define R8A77980_CLK_S0D2  7
+#define R8A77980_CLK_S0D3  8
+#define R8A77980_CLK_S0D4  9
+#define R8A77980_CLK_S0D6  10
+#define R8A77980_CLK_S0D12 11
+#define R8A77980_CLK_S0D24 12
+#define R8A77980_CLK_S1D1  13
+#define R8A77980_CLK_S1D2  14
+#define R8A77980_CLK_S1D4  15
+#define R8A77980_CLK_S2D1  16
+#define R8A77980_CLK_S2D2  17
+#define R8A77980_CLK_S2D4  18
+#define R8A77980_CLK_S3D1  19
+#define R8A77980_CLK_S3D2  20
+#define R8A77980_CLK_S3D4  21
+#define R8A77980_CLK_LB22
+#define R8A77980_CLK_CL23
+#define R8A77980_CLK_ZB3   24
+#define R8A77980_CLK_ZB3D2 25
+#define R8A77980_CLK_ZB3D4 26
+#define R8A77980_CLK_SD0H  27
+#define R8A77980_CLK_SD0   28
+#define R8A77980_CLK_RPC   29
+#define R8A77980_CLK_RPCD2 30
+#define R8A77980_CLK_MSO   31
+#define R8A77980_CLK_CANFD 32
+#define R8A77980_CLK_CSI0  33
+#define R8A77980_CLK_CP34
+#define R8A77980_CLK_CPEX  35
+#define R8A77980_CLK_R 36
+#define R8A77980_CLK_OSC   37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */