Re: [PATCH 4/4] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups

[Geert Uytterhoeven]

On Mon, Oct 8, 2018 at 11:30 AM Fabrizio Castro
 wrote:
> Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
> pinctrl driver.
>
> Signed-off-by: Fabrizio Castro 
> Reviewed-by: Fabrizio Castro 

Reviewed-by: Geert Uytterhoeven 
i.e. will queue in sh-pfc-for-v4.21.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 4/4] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups

[Simon Horman]

On Mon, Oct 08, 2018 at 10:30:19AM +0100, Fabrizio Castro wrote:
> Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
> pinctrl driver.
> 
> Signed-off-by: Fabrizio Castro 
> Reviewed-by: Fabrizio Castro 

Reviewed-by: Simon Horman 

[PATCH 4/4] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups

[Fabrizio Castro]

Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
pinctrl driver.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Fabrizio Castro 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 726e3da..d9c6a03 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1635,6 +1635,29 @@ static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
 };
+static const unsigned int qspi1_ctrl_pins[] = {
+   /* SPCLK, SSL */
+   RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+   QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+   /* MOSI_IO0, MISO_IO1 */
+   RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int qspi1_data2_mux[] = {
+   QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+   /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+   RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
+   RCAR_GP_PIN(4, 8),
+};
+static const unsigned int qspi1_data4_mux[] = {
+   QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
+   QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
 /* - SCIF0 -- 
*/
 static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -2207,6 +2230,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
+   SH_PFC_PIN_GROUP(qspi1_ctrl),
+   SH_PFC_PIN_GROUP(qspi1_data2),
+   SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@@ -2369,6 +2395,12 @@ static const char * const qspi0_groups[] = {
"qspi0_data4",
 };
 
+static const char * const qspi1_groups[] = {
+   "qspi1_ctrl",
+   "qspi1_data2",
+   "qspi1_data4",
+};
+
 static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_data_b",
@@ -2490,6 +2522,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(qspi0),
+   SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
-- 
2.7.4