Re: [PATCH v2 1/2] arm64: renesas: r8a7795: Add PCIe nodes

[Geert Uytterhoeven]

Hi Phil,

On Tue, Apr 5, 2016 at 12:25 PM, Phil Edworthy
 wrote:
> Signed-off-by: Phil Edworthy 
> ---
> v2:
>  Dropped the "_clk" suffix from the PCIe bus device node's name.
>  Removed "clock-output-names" property from the PCIe bus node.
>  Use GIC_SPI  for all interrupts.

Thanks for the update, but you forgot two of them:

> +   interrupt-map = <0 0 0 0  0 116 
> IRQ_TYPE_LEVEL_HIGH>;

...  GIC_SPI ...

> +   interrupt-map = <0 0 0 0  0 148 
> IRQ_TYPE_LEVEL_HIGH>;

...  GIC_SPI ...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 1/2] arm64: renesas: r8a7795: Add PCIe nodes

[Phil Edworthy]

Signed-off-by: Phil Edworthy 
---
v2:
 Dropped the "_clk" suffix from the PCIe bus device node's name.
 Removed "clock-output-names" property from the PCIe bus node.
 Use GIC_SPI  for all interrupts.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 57 
 1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 868c10e..b2edc0b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -131,6 +131,14 @@
status = "disabled";
};
 
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   status = "disabled";
+   };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -1156,5 +1164,54 @@
power-domains = <>;
status = "disabled";
};
+   pciec0: pcie@fe00 {
+   compatible = "renesas,pcie-r8a7795";
+   reg = <0 0xfe00 0 0x8>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xfe10 0 
0x0010
+   0x0200 0 0xfe20 0 0xfe20 0 
0x0020
+   0x0200 0 0x3000 0 0x3000 0 
0x0800
+   0x4200 0 0x3800 0 0x3800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x4000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  0 116 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 319>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = <>;
+   status = "disabled";
+   };
+
+   pciec1: pcie@ee80 {
+   compatible = "renesas,pcie-r8a7795";
+   reg = <0 0xee80 0 0x8>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xee90 0 
0x0010
+   0x0200 0 0xeea0 0 0xeea0 0 
0x0020
+   0x0200 0 0xc000 0 0xc000 0 
0x0800
+   0x4200 0 0xc800 0 0xc800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x4000>;
+   interrupts = ,
+   ,
+   ;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  0 148 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 318>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = <>;
+   status = "disabled";
+   };
};
 };
-- 
2.5.0