Re: [PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
> Manual.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> Reviewed-by: Geert Uytterhoeven 
> ---
> V1->V2:
> * incorporated geert's review comment
>
>  include/dt-bindings/clock/r8a77470-cpg-mssr.h | 36 
> +++
>  1 file changed, 36 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a77470-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h 
> b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
> new file mode 100644
> index 000..ffc123c
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
> +
> +#include 
> +
> +/* r8a77470 CPG Core Clocks */
> +#define R8A77470_CLK_Z20
> +#define R8A77470_CLK_ZTR   2

These should be numbered consecutively, unless there is a good reason not
to do so.

Sorry for not noticing before, fixing up while applying...

> +#define R8A77470_CLK_ZTRD2 3
> +#define R8A77470_CLK_ZT4
> +#define R8A77470_CLK_ZX5
> +#define R8A77470_CLK_ZS6
> +#define R8A77470_CLK_HP7
> +#define R8A77470_CLK_B 9
> +#define R8A77470_CLK_LB10
> +#define R8A77470_CLK_P 11
> +#define R8A77470_CLK_CL12
> +#define R8A77470_CLK_CP13
> +#define R8A77470_CLK_M214
> +#define R8A77470_CLK_ZB3   16
> +#define R8A77470_CLK_SDH   19
> +#define R8A77470_CLK_SD0   20
> +#define R8A77470_CLK_SD1   21
> +#define R8A77470_CLK_SD2   22
> +#define R8A77470_CLK_MP24
> +#define R8A77470_CLK_QSPI  25
> +#define R8A77470_CLK_CPEX  26
> +#define R8A77470_CLK_RCAN  27
> +#define R8A77470_CLK_R 28
> +#define R8A77470_CLK_OSC   29

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
> Manual.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> Reviewed-by: Geert Uytterhoeven 
> ---
> V1->V2:
> * incorporated geert's review comment

Thanks for the update, will queue in clk-renesas-for v4.18.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Biju Das]

Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
---
V1->V2:
* incorporated geert's review comment

 include/dt-bindings/clock/r8a77470-cpg-mssr.h | 36 +++
 1 file changed, 36 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a77470-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h 
b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 000..ffc123c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+
+#include 
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z20
+#define R8A77470_CLK_ZTR   2
+#define R8A77470_CLK_ZTRD2 3
+#define R8A77470_CLK_ZT4
+#define R8A77470_CLK_ZX5
+#define R8A77470_CLK_ZS6
+#define R8A77470_CLK_HP7
+#define R8A77470_CLK_B 9
+#define R8A77470_CLK_LB10
+#define R8A77470_CLK_P 11
+#define R8A77470_CLK_CL12
+#define R8A77470_CLK_CP13
+#define R8A77470_CLK_M214
+#define R8A77470_CLK_ZB3   16
+#define R8A77470_CLK_SDH   19
+#define R8A77470_CLK_SD0   20
+#define R8A77470_CLK_SD1   21
+#define R8A77470_CLK_SD2   22
+#define R8A77470_CLK_MP24
+#define R8A77470_CLK_QSPI  25
+#define R8A77470_CLK_CPEX  26
+#define R8A77470_CLK_RCAN  27
+#define R8A77470_CLK_R 28
+#define R8A77470_CLK_OSC   29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
-- 
2.7.4