Re: [PATCH v3 2/7] dt-bindings: pinctrl: Add RZ/A1 bindings doc

[jacopo]

Hi Rob,
   thanks for the ack

On Thu, Mar 30, 2017 at 05:39:03PM -0500, Rob Herring wrote:
> On Fri, Mar 24, 2017 at 04:22:09PM +0100, Jacopo Mondi wrote:
> > Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
> > controller.
> > 
> > Signed-off-by: Jacopo Mondi 
> > ---
> >  .../bindings/pinctrl/renesas,rza1-pinctrl.txt  | 143 
> > +
> >  1 file changed, 143 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
> 
> Acked-by: Rob Herring 

Just an heads-up: in v4 dt bindings will change considerably to meet a
format more close to standard pin controller bindings.

I cannot take you ack here and apply to next iteration as it will
require you or other dt guardians to have a look at it again. Sorry
about this.

Thanks
   j

Re: [PATCH v3 2/7] dt-bindings: pinctrl: Add RZ/A1 bindings doc

[Rob Herring]

On Fri, Mar 24, 2017 at 04:22:09PM +0100, Jacopo Mondi wrote:
> Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
> controller.
> 
> Signed-off-by: Jacopo Mondi 
> ---
>  .../bindings/pinctrl/renesas,rza1-pinctrl.txt  | 143 
> +
>  1 file changed, 143 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt

Acked-by: Rob Herring 

[PATCH v3 2/7] dt-bindings: pinctrl: Add RZ/A1 bindings doc

[Jacopo Mondi]

Add device tree bindings documentation for Renesas RZ/A1 gpio and pin
controller.

Signed-off-by: Jacopo Mondi 
---
 .../bindings/pinctrl/renesas,rza1-pinctrl.txt  | 143 +
 1 file changed, 143 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
new file mode 100644
index 000..69aafd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -0,0 +1,143 @@
+Renesas RZ/A1 combined Pin and GPIO controller
+
+The Renesas SoCs of RZ/A1 family feature a combined Pin and GPIO controller
+hardware controller, named "Ports" in the hardware reference manual.
+Pin multiplexing and GPIO configuration is performed on a per-pin basis
+writing configuration values to per-port register sets.
+Each "port" features up to 16 pins, each of them configurable for GPIO
+function (port mode) or in alternate function mode.
+Up to 8 different alternate function modes exist for each single pin.
+
+Pin controller node
+---
+
+Required properties:
+  - compatible
+this shall be "renesas,r7s72100-ports".
+
+  - #pinctrl-cells
+as defined by pinctrl-bindings.txt, this is the number
+of cells (in addition to pin index) required to configure a single pin.
+Shall be set to 1.
+
+  - reg
+address base and length of the memory area where pin controller
+hardware is mapped to.
+
+Example:
+Pin controller node for RZ/A1H SoC (r7s72100)
+
+pinctrl: pinctrl@fcfe3000 {
+   compatible = "renesas,r7s72100-ports";
+
+   #pinctrl-cells = <1>;
+
+   reg = <0xfcfe3000 0x4230>;
+};
+
+Sub-nodes
+-
+
+The child nodes of the pin controller node describe a pin multiplexing
+function or a gpio controller alternatively.
+
+- Pin multiplexing sub-nodes:
+  A pin multiplexing sub-node describes how to configure a set of
+  (or a single) pin in some desired alternate function mode.
+  A single sub-node may define several pin configurations groups.
+
+  Required properties:
+- renesas,pins
+  describes an array of pin multiplexing configurations.
+  When a pin has to be configured in alternate function mode, use this
+  property to identify the pin by its global index, and provide its
+  alternate function configuration description along with it.
+  When multiple pins are required to be configured as part of the same
+  alternate function (odds are single-pin alternate functions exist) they
+  shall be specified as members of the same argument list of a single
+  "renesas-pins" property.
+  Helper macros to ease calculating the pin index from its position
+  (port where it sits on and pin offset), and alternate function
+  configuration options are provided in the pin controller header file at:
+  include/dt-bindings/pinctrl/r7s72100-pinctrl.h
+
+  Example:
+  A serial communication interface with a TX output pin and an RX input pin.
+
+   {
+   scif2_pins: serial2 {
+   renesas,pins = , ;
+   };
+  }
+
+  Pin #0 on port #3 is configured as alternate function #6.
+  Pin #2 on port #3 is configured as alternate function #4.
+
+  Example 2:
+  I2c master: both SDA and SCL pins need bi-directional operations
+
+   {
+   i2c2_pins: i2c2 {
+   renesas,pins = ,
+  ;
+   };
+  }
+
+  Pin #4 on port #1 is configured as alternate function #1.
+  Pin #5 on port #1 is configured as alternate function #1.
+  Both need to work in bi-directional mode.
+
+  Example 3:
+  Multi-function timer input and output compare pins.
+  The hardware manual prescribes this pins to have input/output direction
+  specified by software. Configure TIOC0A as input and TIOC0B as output.
+
+   {
+   tioc0_pins: tioc0 {
+   renesas,pins = ,
+  ;
+   };
+  }
+
+  Pin #0 on port #4 is configured as alternate function #2 with IO direction
+  specified by software as input.
+  Pin #1 on port #4 is configured as alternate function #1 with IO direction
+  specified by software as output.
+
+- GPIO controller sub-nodes:
+  Each port of the r7s72100 pin controller hardware is itself a gpio 
controller.
+  Different SoCs have different number of available pins per port, but
+  generally speaking, each of them can be configured in GPIO ("port") mode
+  on this hardware.
+  Describe gpio-controllers using sub-nodes with the following properties.
+
+  Required properties:
+- gpio-controller
+  empty property as defined by the gpio bindings documentation.
+- #gpio-cells
+  number of cells required to identify and configure a GPIO.
+  Shall be 2.
+-