RE: [PATCH v2 6/8] ARM: dts: r8a77470: Initial SoC device tree

[Biju Das]

Hi Simon & Geert,

Thanks for feedback.

> On Wed, Mar 28, 2018 at 08:26:14PM +0100, Biju Das wrote:
> > The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC,
> > RST, CPG, and the required clock descriptions.
> >
> > Signed-off-by: Biju Das 
> > Reviewed-by: Fabrizio Castro 
> > Reviewed-by: Geert Uytterhoeven 
> > ---
> > V1->V2:
> > * Incorporated geert's review comment
> > * Moved prr node inside soc node.
> >
> >  arch/arm/boot/dts/r8a77470.dtsi | 155
> > 
> >  1 file changed, 155 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/r8a77470.dtsi
> >
> > diff --git a/arch/arm/boot/dts/r8a77470.dtsi
> > b/arch/arm/boot/dts/r8a77470.dtsi new file mode 100644 index
> > 000..f096419
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -0,0 +1,155 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the r8a77470 SoC
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
>
> As requested by Geert in his review of v1, please use numerical values for the
> initial submission as the dt-bindings headers and the DTS files go upstream
> through different maintainer paths.
>
> In other words, please do not include r8a77470-cpg-mssr.h or r8a77470-sysc.h
> in the initial submission of this file as those header files will not be 
> present and
> there will be a build failure.
> Rather, please use numeric values for now and, as a follow-up in the v4.19
> development cycle, provide a patch to use the headers.
>

I got your point now. Will send V3 for this patch with numerical values.





Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v2 6/8] ARM: dts: r8a77470: Initial SoC device tree

[Simon Horman]

On Wed, Mar 28, 2018 at 08:26:14PM +0100, Biju Das wrote:
> The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
> CPG, and the required clock descriptions.
> 
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> Reviewed-by: Geert Uytterhoeven 
> ---
> V1->V2:
> * Incorporated geert's review comment
> * Moved prr node inside soc node.
> 
>  arch/arm/boot/dts/r8a77470.dtsi | 155 
> 
>  1 file changed, 155 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r8a77470.dtsi
> 
> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> new file mode 100644
> index 000..f096419
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -0,0 +1,155 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the r8a77470 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 

As requested by Geert in his review of v1, please use numerical values for
the initial submission as the dt-bindings headers and the DTS files go
upstream through different maintainer paths.

In other words, please do not include r8a77470-cpg-mssr.h or
r8a77470-sysc.h in the initial submission of this file as those header
files will not be present and there will be a build failure.
Rather, please use numeric values for now and, as a follow-up in the v4.19
development cycle, provide a patch to use the headers.

> +/ {
> + compatible = "renesas,r8a77470";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0>;
> + clock-frequency = <10>;
> + clocks = < CPG_CORE R8A77470_CLK_Z2>;
> + power-domains = < R8A77470_PD_CA7_CPU0>;
> + next-level-cache = <_CA7>;
> + };
> +
> +
> + L2_CA7: cache-controller-0 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + power-domains = < R8A77470_PD_CA7_SCU>;
> + };
> + };
> +
> + /* External root clock */
> + extal_clk: extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board. */
> + clock-frequency = <0>;
> + };
> +
> + /* External SCIF clock */
> + scif_clk: scif {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board. */
> + clock-frequency = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + cpg: clock-controller@e615 {
> + compatible = "renesas,r8a77470-cpg-mssr";
> + reg = <0 0xe615 0 0x1000>;
> + clocks = <_clk>, <_extal_clk>;
> + clock-names = "extal", "usb_extal";
> + #clock-cells = <2>;
> + #power-domain-cells = <0>;
> + #reset-cells = <1>;
> + };
> +
> + rst: reset-controller@e616 {
> + compatible = "renesas,r8a77470-rst";
> + reg = <0 0xe616 0 0x100>;
> + };
> +
> + sysc: system-controller@e618 {
> + compatible = "renesas,r8a77470-sysc";
> + reg = <0 0xe618 0 0x200>;
> + #power-domain-cells = <1>;
> + };
> +
> + icram0: sram@e63a {
> + compatible = "mmio-sram";
> + reg = <0 0xe63a 0 0x12000>;
> + };
> +
> + icram1: sram@e63c {
> + compatible = "mmio-sram";
> + reg = <0 0xe63c 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0xe63c 0x1000>;
> +
> + smp-sram@0 {
> + compatible = "renesas,smp-sram";
> + reg = <0 0x100>;
> + };
> + };
> +
> + icram2: sram@e630 {
> + compatible = "mmio-sram";
> + reg = <0 0xe630 0 0x2>;
> + };
> +
> + scif1: serial@e6e68000 {
> + compatible = "renesas,scif-r8a77470",
>