Re: [PATCH v6 1/2] pinctrl: Add RZ/A2 pin and gpio controller
Hi Chris,
On Thu, Nov 15, 2018 at 09:00:44AM -0500, Chris Brandt wrote:
> Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Jacopo Mondi
> ---
> v5:
> * Specify number of ports using of_device_id.data and save as priv->npins
> * Use priv->npins everywhere instead of hard coded RZA2_NPINS
> * Check gpio-ranges to make sure args matches SOC
Sorry about this, I didn't want to ask you to do this now, it might
have had post-poned to when a new SoC will have to be supported, but..
[snip]
> +
> +static const struct of_device_id rza2_pinctrl_of_match[] = {
> + { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
... I really don't like this, I'm sorry.
I would rather make a 'struct rza_pinctrl_info' or similar which
contains all the fields you now hardcode (number of ports, pins per
port etc) and which is easily extensible in case you need to do so.
I'm sorry this is more work, and again, it might be post-poned imo,
provided you drop this change you have introduced here.
Thanks
j
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver rza2_pinctrl_driver = {
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = rza2_pinctrl_of_match,
> + },
> + .probe = rza2_pinctrl_probe,
> +};
> +
> +static int __init rza2_pinctrl_init(void)
> +{
> + return platform_driver_register(_pinctrl_driver);
> +}
> +core_initcall(rza2_pinctrl_init);
> +
> +MODULE_AUTHOR("Chris Brandt ");
> +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
> +MODULE_LICENSE("GPL v2");
> --
> 2.16.1
>
signature.asc
Description: PGP signature
Re: [PATCH v4 2/4] pinctrl: sh-pfc: Fix VIN versioned groups name
Hi Simon, On Wed, Nov 07, 2018 at 11:41:34AM +0100, Simon Horman wrote: > On Tue, Nov 06, 2018 at 11:35:31AM +0100, Jacopo Mondi wrote: > > Versioned VIN groups can appear on different sets of pins. Using the > > VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through > > an optional 'version' argument. > > > > Use the 'version' argument for said macro to fix naming of versioned > > groups for R-Car SoCs that defines them. > > > > Signed-off-by: Jacopo Mondi > > Reviewed-by: Simon Horman > I'm going to split this patch for each SoC to ease backporting, as Geert suggested. Provided the single patches content is the same as here, can I retain your R-b tag? signature.asc Description: PGP signature
Re: [PATCH v4 4/4] pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Hi Simon,
On Wed, Nov 07, 2018 at 11:34:50AM +0100, Simon Horman wrote:
> On Tue, Nov 06, 2018 at 11:35:33AM +0100, Jacopo Mondi wrote:
> > Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
> >
> > Signed-off-by: Jacopo Mondi
> >
> > ---
> > v3 -> v4:
> > - Use new variadic version of VIN_DATA_PIN_GROUP macro
>
> I may be missing something but this patch seems to be the same as v3,
> using the VIN_DATA_PIN_GROUP_VER macro.
>
Oooops, I forgot to add the changes and lost them while rebasing.
Sorry about this, I'll resend.
Thanks
j
> >
> > v2 -> v3:
> > - Rebased on v4.20-rc1
> > - Use the newly introduced VIN_DATA_PIN_GROUP_VER macro
> >
> > Incorporate Geert's comments:
> > - vin5_data8_b is only used with 8 pins: use regular SH_PFC_PIN_GROUP()
> > - remove stf groups for vin4/vin5
> > - confirmed that pins [23-8] of vin4's groups 'a' and 'b' are shared
> > - confirmed with HW team the synchronism pins in vin5 are only for group 'a'
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244
> > ++
> > 1 file changed, 244 insertions(+)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > index 1fdafa4..16fd139 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > @@ -2433,6 +2433,190 @@ static const unsigned int usb30_id_mux[] = {
> > USB3HS0_ID_MARK,
> > };
> >
> > +/* - VIN4
> > --- */
> > +static const union vin_data vin4_data_a_pins = {
> > + .data24 = {
> > + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
> > + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
> > + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
> > + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
> > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> > + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> > + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> > + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> > + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
> > + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> > + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_a_mux = {
> > + .data24 = {
> > + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
> > + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
> > + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
> > + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
> > + VI4_DATA8_MARK, VI4_DATA9_MARK,
> > + VI4_DATA10_MARK, VI4_DATA11_MARK,
> > + VI4_DATA12_MARK, VI4_DATA13_MARK,
> > + VI4_DATA14_MARK, VI4_DATA15_MARK,
> > + VI4_DATA16_MARK, VI4_DATA17_MARK,
> > + VI4_DATA18_MARK, VI4_DATA19_MARK,
> > + VI4_DATA20_MARK, VI4_DATA21_MARK,
> > + VI4_DATA22_MARK, VI4_DATA23_MARK,
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_b_pins = {
> > + .data24 = {
> > + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
> > + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
> > + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
> > + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
> > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> > + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> > + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> > + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> > + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15),
> > + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> > + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> > + },
> > +};
> > +
> > +static const union vin_data vin4_data_b_mux = {
> > + .data24 = {
> > + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
> > + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
> > + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
> > + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
> > + VI4_DATA8_MARK, VI4_DATA9_MARK,
> > + VI4_DATA10_MARK, VI4_DATA11_MARK,
> > + VI4_DATA12_MARK, VI4_DATA13_MARK,
> > + VI4_DATA14_MARK, VI4_DATA15_MARK,
> > + VI4_DATA16_MARK, VI4_DATA17_MARK,
> > + VI4_DATA18_MARK, VI4_DATA19_MARK,
> > +
[PATCH v4 1/4] pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP
VIN data groups may appear on different sets of pins, usually named
"vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support
appending the '_a' or '_b' suffix, leading to the definition of groups
names not consistent with the ones defined using SH_PFC_PIN_GROUP() macro.
Fix this by adding making the VIN_DATA_PIN_GROUP macro a variadic one,
which accepts an optional 'version' argument.
Signed-off-by: Jacopo Mondi
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 458ae0a..0e0b4cc 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -54,15 +54,16 @@ struct sh_pfc_pin_group {
/*
* Using union vin_data saves memory occupied by the VIN data pins.
- * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
- * in this case.
+ * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
+ * in this case. It accepts an optional 'version' argument used when the
+ * same group can appear on a different set of pins.
*/
-#define VIN_DATA_PIN_GROUP(n, s) \
- { \
- .name = #n#s, \
- .pins = n##_pins.data##s, \
- .mux = n##_mux.data##s, \
- .nr_pins = ARRAY_SIZE(n##_pins.data##s),\
+#define VIN_DATA_PIN_GROUP(n, s, ...) \
+ { \
+ .name = #n#s#__VA_ARGS__, \
+ .pins = n##__VA_ARGS__##_pins.data##s, \
+ .mux = n##__VA_ARGS__##_mux.data##s,\
+ .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
}
union vin_data {
--
2.7.4
[PATCH v4 0/4] sh-pfc: Variadic VIN_DATA_PIN_GROUP macro + updates
Hi Geert, thanks to your suggestion I made a variadic macro out of the VIN_DATA_PIN_GROUP one. The macro accepts an optional third argument 'version' and creates properly formatted names in the form of 'vin4_data8_a' in place of the previous 'vin4_data_a8' ones. I included in this series the refactoring of existing users of versioned VIN_DATA_PIN_GROUP macro and upstreaming of VIN4 and VIN5 enablement for both R-Car M3-N and E3, both of them users of versioned VIN groups. Thanks j v3 -> v4: - The series gathers different patch series previously sent separately: [PATCH 0/2] pinctrl: sh-pfc: r8a77965: Add VIN4 and VIN5 [PATCH] pinctrl: sh-pfc: r8a77990: Add VIN pins, groups and functions As E3 patch depends on the M3-N series, I made a single one out of those. Changelog for the E3 patch (which was actually at v3) is included in the single patch commit message. Jacopo Mondi (4): pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP pinctrl: sh-pfc: Fix VIN versioned groups name pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 6 +- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 ++-- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24 ++-- drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 254 ++ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244 drivers/pinctrl/sh-pfc/sh_pfc.h | 17 +-- 6 files changed, 534 insertions(+), 35 deletions(-) -- 2.7.4
[PATCH v4 4/4] pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
Signed-off-by: Jacopo Mondi
---
v3 -> v4:
- Use new variadic version of VIN_DATA_PIN_GROUP macro
v2 -> v3:
- Rebased on v4.20-rc1
- Use the newly introduced VIN_DATA_PIN_GROUP_VER macro
Incorporate Geert's comments:
- vin5_data8_b is only used with 8 pins: use regular SH_PFC_PIN_GROUP()
- remove stf groups for vin4/vin5
- confirmed that pins [23-8] of vin4's groups 'a' and 'b' are shared
- confirmed with HW team the synchronism pins in vin5 are only for group 'a'
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244 ++
1 file changed, 244 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fdafa4..16fd139 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2433,6 +2433,190 @@ static const unsigned int usb30_id_mux[] = {
USB3HS0_ID_MARK,
};
+/* - VIN4 ---
*/
+static const union vin_data vin4_data_a_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
+ },
+};
+
+static const union vin_data vin4_data_a_mux = {
+ .data24 = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+
+static const union vin_data vin4_data_b_pins = {
+ .data24 = {
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
+ },
+};
+
+static const union vin_data vin4_data_b_mux = {
+ .data24 = {
+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+
+static const unsigned int vin4_sync_pins[] = {
+ /* HSYNC, VSYNC */
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int vin4_sync_mux[] = {
+ VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
+};
+
+static const unsigned int vin4_field_pins[] = {
+ RCAR_GP_PIN(2, 23),
+};
+
+static const unsigned int vin4_field_mux[] = {
+ VI4_FIELD_MARK,
+};
+
+static const unsigned int vin4_clkenb_pins[] = {
+ RCAR_GP_PIN(1, 2),
+};
+
+static const unsigned int vin4_clkenb_mux[] = {
+ VI4_CLKENB_MARK,
+};
+
+static const unsigned int vin4_clk_pins[] = {
+ RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int vin4_clk_mux[] = {
+ VI4_CLK_MARK,
+};
+
+/* - VIN5 ---
*/
+static const union vin_data vin5_data_a_pins = {
+ .data16 = {
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN
[PATCH v4 2/4] pinctrl: sh-pfc: Fix VIN versioned groups name
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through
an optional 'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for R-Car SoCs that defines them.
Signed-off-by: Jacopo Mondi
---
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 6 +++---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
index bf0681b..a8a110d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -1744,10 +1744,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
- VIN_DATA_PIN_GROUP(vin1_data_b, 24),
- VIN_DATA_PIN_GROUP(vin1_data_b, 20),
+ VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
- VIN_DATA_PIN_GROUP(vin1_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 0af737d..20fac0f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -4474,20 +4474,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data_a, 8),
- VIN_DATA_PIN_GROUP(vin4_data_a, 10),
- VIN_DATA_PIN_GROUP(vin4_data_a, 12),
- VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data_a, 20),
- VIN_DATA_PIN_GROUP(vin4_data_a, 24),
- VIN_DATA_PIN_GROUP(vin4_data_b, 8),
- VIN_DATA_PIN_GROUP(vin4_data_b, 10),
- VIN_DATA_PIN_GROUP(vin4_data_b, 12),
- VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data_b, 20),
- VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3a6d21d..b003abd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -4409,20 +4409,20 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data_a, 8),
- VIN_DATA_PIN_GROUP(vin4_data_a, 10),
- VIN_DATA_PIN_GROUP(vin4_data_a, 12),
- VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data_a, 20),
- VIN_DATA_PIN_GROUP(vin4_data_a, 24),
- VIN_DATA_PIN_GROUP(vin4_data_b, 8),
- VIN_DATA_PIN_GROUP(vin4_data_b, 10),
- VIN_DATA_PIN_GROUP(vin4_data_b, 12),
- VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data_b, 20),
- VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb
[PATCH v5 2/6] pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions
The VIN4 and VIN5 interfaces supports parallel video input.
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N.
Reviewed-by: Ulrich Hecht
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Add definitions for 10, 12 and 20 pin groups for VIN4 as suggested by Geert
- Add definitions for 10 and 12 pin groups for VIN5 as suggested by Geert
- s/union vin_data/union vin_data16/ for VIN5 pins and mux as suggested by Geert
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 270 ++
1 file changed, 270 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index dfdd982984d4..0159e80d29c3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -3725,6 +3725,216 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
+/* - VIN4 ---
*/
+static const unsigned int vin4_data18_a_pins[] = {
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+
+static const unsigned int vin4_data18_a_mux[] = {
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+
+static const union vin_data vin4_data_a_pins = {
+ .data24 = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ },
+};
+
+static const union vin_data vin4_data_a_mux = {
+ .data24 = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+
+static const unsigned int vin4_data18_b_pins[] = {
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+
+static const unsigned int vin4_data18_b_mux[] = {
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+
+static const union vin_data vin4_data_b_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0
[PATCH v5 0/6] sh-pfc: Variadic VIN_DATA_PIN_GROUP macro + VIN updates
Hi Geert, Simon, this version uses the new variadic macro VIN_DATA_PIN_GROUP as v4 (this for real in [3/6]. Refactoring of users of the macro old version have broken out to single patches, comments on M3-N and E3 VIN PFC groups have been incorporated. Quite a few changes in M3-N and E3 VIN support in PFC, so the single patches changelog is in commit messages. Thanks j Jacopo Mondi (6): pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions pinctrl: sh-pfc: r8a7792: Fix VIN versioned groups pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 6 +- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 +-- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24 +-- drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 270 ++ drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 244 ++ drivers/pinctrl/sh-pfc/sh_pfc.h | 15 +- 6 files changed, 549 insertions(+), 34 deletions(-) -- 2.7.4
[PATCH v5 6/6] pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through
an optional 'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for R-Car M3-W R8A7796 SoC.
Fixes: a5c2949ff7bd ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin
definitions")
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Broke out r8a7796 from single patch
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3a6d21d87107..b003abdd1a74 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -4409,20 +4409,20 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data_a, 8),
- VIN_DATA_PIN_GROUP(vin4_data_a, 10),
- VIN_DATA_PIN_GROUP(vin4_data_a, 12),
- VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data_a, 20),
- VIN_DATA_PIN_GROUP(vin4_data_a, 24),
- VIN_DATA_PIN_GROUP(vin4_data_b, 8),
- VIN_DATA_PIN_GROUP(vin4_data_b, 10),
- VIN_DATA_PIN_GROUP(vin4_data_b, 12),
- VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data_b, 20),
- VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
--
2.7.4
[PATCH v5 1/6] pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP
VIN data groups may appear on different sets of pins, usually named
"vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support
appending the '_a' or '_b' suffix, leading to the definition of group
names not consistent with the ones defined using the SH_PFC_PIN_GROUP()
macro.
Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one,
which accepts an optional 'version' argument.
Fixes: 423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to
shared header file")
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Rebased on sh-pfc-for-v4.21
- Add fixes tag
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 1fc13366869a..4ef485cfe08d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -55,14 +55,15 @@ struct sh_pfc_pin_group {
/*
* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
- * in this case.
+ * in this case. It accepts an optional 'version' argument used when the
+ * same group can appear on a different set of pins.
*/
-#define VIN_DATA_PIN_GROUP(n, s) \
- { \
- .name = #n#s, \
- .pins = n##_pins.data##s, \
- .mux = n##_mux.data##s, \
- .nr_pins = ARRAY_SIZE(n##_pins.data##s),\
+#define VIN_DATA_PIN_GROUP(n, s, ...) \
+ { \
+ .name = #n#s#__VA_ARGS__, \
+ .pins = n##__VA_ARGS__##_pins.data##s, \
+ .mux = n##__VA_ARGS__##_mux.data##s,\
+ .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
}
union vin_data12 {
--
2.7.4
[PATCH v5 3/6] pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Use new variadic macro: this time for real as reported by Simon
- s/union vin_data/union vin_data16/ for VIN5 pins and mux as suggested by Geert
- add vin4_data18_[a|b] pins
- fix VIN4_DATA19 pin number in vin4_data_b group
v3 -> v4:
- Use new variadic version of VIN_DATA_PIN_GROUP macro
v2 -> v3:
- Rebased on v4.20-rc1
- Use the newly introduced VIN_DATA_PIN_GROUP_VER macro
Incorporate Geert's comments:
- vin5_data8_b is only used with 8 pins: use regular SH_PFC_PIN_GROUP()
- remove stf groups for vin4/vin5
- confirmed that pins [23-8] of vin4's groups 'a' and 'b' are shared
- confirmed with HW team the synchronism pins in vin5 are only for group 'a'
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 300 +-
1 file changed, 298 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 923261687a75..1a2cf73a84ad 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2786,8 +2786,240 @@ static const unsigned int usb30_id_mux[] = {
USB3HS0_ID_MARK,
};
+/* - VIN4 ---
*/
+static const unsigned int vin4_data18_a_pins[] = {
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
+};
+
+static const unsigned int vin4_data18_a_mux[] = {
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+
+static const union vin_data vin4_data_a_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
+ },
+};
+
+static const union vin_data vin4_data_a_mux = {
+ .data24 = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+ },
+};
+
+static const unsigned int vin4_data18_b_pins[] = {
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+ RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
+};
+
+static const unsigned int vin4_data18_b_mux[] = {
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
+};
+
+static const union vin_data vin4_data_b_pins = {
+ .data24 = {
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
+ RCAR_GP_PIN(1, 4), RCAR_GP
[PATCH v5 4/6] pinctrl: sh-pfc: r8a7792: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Use of the
VIN_DATA_PIN_GROUP macro fix naming of said groups through an optional
'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for R-Car V2H R8A7792 SoC.
Fixes: 7dd74bb1f058 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups")
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Broke out r8a7792 from single patch
---
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
index e977121b433b..a623459b234e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -1744,10 +1744,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
- VIN_DATA_PIN_GROUP(vin1_data_b, 24),
- VIN_DATA_PIN_GROUP(vin1_data_b, 20),
+ VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
+ VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
- VIN_DATA_PIN_GROUP(vin1_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
--
2.7.4
[PATCH v5 5/6] pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Use of the
VIN_DATA_PIN_GROUP macro fix naming of said groups through an optional
'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for R-Car H3 R8A7795 SoC.
Fixes: 9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin
definitions")
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Jacopo Mondi
---
v4 -> v5:
- Broke out r8a7795 from single patch
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 0af737d11403..20fac0fde91a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -4474,20 +4474,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data_a, 8),
- VIN_DATA_PIN_GROUP(vin4_data_a, 10),
- VIN_DATA_PIN_GROUP(vin4_data_a, 12),
- VIN_DATA_PIN_GROUP(vin4_data_a, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data_a, 20),
- VIN_DATA_PIN_GROUP(vin4_data_a, 24),
- VIN_DATA_PIN_GROUP(vin4_data_b, 8),
- VIN_DATA_PIN_GROUP(vin4_data_b, 10),
- VIN_DATA_PIN_GROUP(vin4_data_b, 12),
- VIN_DATA_PIN_GROUP(vin4_data_b, 16),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data_b, 20),
- VIN_DATA_PIN_GROUP(vin4_data_b, 24),
+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
--
2.7.4
Re: [PATCH v4 1/2] pinctrl: Add RZ/A2 pin and gpio controller
ret = of_property_read_u32_index(np, "pinmux", i, );
> + if (ret)
> + return ret;
> + pins[i] = value & MUX_PIN_ID_MASK;
> + psel_val[i] = MUX_FUNC(value);
> + }
> +
> + /* Register a single pin group listing all the pins we read from DT */
> + gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
> + if (gsel < 0)
> + return gsel;
> +
> + /*
> + * Register a single group function where the 'data' is an array PSEL
> + * register values read from DT.
> + */
> + pin_fn[0] = np->name;
> + fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
> +psel_val);
> + if (fsel < 0) {
> + ret = fsel;
> + goto remove_group;
> + }
> +
> + dev_dbg(priv->dev, "Parsed %s with %d pins\n", np->name, npins);
> +
> + /* Create map where to retrieve function and mux settings from */
> + *num_maps = 0;
> + *map = kzalloc(sizeof(**map), GFP_KERNEL);
> + if (!*map) {
> + ret = -ENOMEM;
> + goto remove_function;
> + }
> +
> + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
> + (*map)->data.mux.group = np->name;
> + (*map)->data.mux.function = np->name;
> + *num_maps = 1;
> +
> + return 0;
> +
> +remove_function:
> + pinmux_generic_remove_function(pctldev, fsel);
> +
> +remove_group:
> + pinctrl_generic_remove_group(pctldev, gsel);
> +
> + dev_info(priv->dev, "Unable to parse DT node %s\n", np->name);
> +
> + return ret;
> +}
> +
> +static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map, unsigned int num_maps)
> +{
> + kfree(map);
> +}
> +
> +static const struct pinctrl_ops rza2_pinctrl_ops = {
> + .get_groups_count = pinctrl_generic_get_group_count,
> + .get_group_name = pinctrl_generic_get_group_name,
> + .get_group_pins = pinctrl_generic_get_group_pins,
> + .dt_node_to_map = rza2_dt_node_to_map,
> + .dt_free_map= rza2_dt_free_map,
> +};
> +
> +static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
> +unsigned int group)
> +{
> + struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
> + struct function_desc *func;
> + struct group_desc *grp;
> + int i;
> + unsigned int *psel_val;
> +
> + grp = pinctrl_generic_get_group(pctldev, group);
> + if (!grp)
> + return -EINVAL;
> +
> + func = pinmux_generic_get_function(pctldev, selector);
> + if (!func)
> + return -EINVAL;
> +
> + psel_val = func->data;
> +
> + for (i = 0; i < grp->num_pins; ++i) {
> + dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
> + port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
> + RZA2_PIN_ID_TO_PIN(grp->pins[i]),
> + psel_val[i]);
> + rza2_set_pin_function(
> + priv->base,
> + RZA2_PIN_ID_TO_PORT(grp->pins[i]),
> + RZA2_PIN_ID_TO_PIN(grp->pins[i]),
> + psel_val[i]);
> + }
> +
> + return 0;
> +}
> +
> +static const struct pinmux_ops rza2_pinmux_ops = {
> + .get_functions_count= pinmux_generic_get_function_count,
> + .get_function_name = pinmux_generic_get_function_name,
> + .get_function_groups= pinmux_generic_get_function_groups,
> + .set_mux= rza2_set_mux,
> + .strict = true,
> +};
> +
> +static int rza2_pinctrl_probe(struct platform_device *pdev)
> +{
> + struct rza2_pinctrl_priv *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(>dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = >dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->base = devm_ioremap_resource(>dev, res);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + priv->desc.name = DRIVER_NAME;
> + priv->desc.pctlops = _pinctrl_ops;
> + priv->desc.pmxops = _pinmux_ops;
> + priv->desc.owner= THIS_MODULE;
> +
> + ret = rza2_pinctrl_register(priv);
> + if (ret)
> + return ret;
> +
> + pr_info("RZ/A2 pin controller registered\n");
nit: dev_info
> +
> + return 0;
> +}
> +
> +static const struct of_device_id rza2_pinctrl_of_match[] = {
> + {
> + .compatible = "renesas,r7s9210-pinctrl",
> + },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver rza2_pinctrl_driver = {
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = rza2_pinctrl_of_match,
> + },
> + .probe = rza2_pinctrl_probe,
> +};
> +
> +static int __init rza2_pinctrl_init(void)
> +{
> + return platform_driver_register(_pinctrl_driver);
> +}
> +core_initcall(rza2_pinctrl_init);
> +
> +
nit: multiple empty lines
With this minor fixed, please add my
Reviewed-by: Jacopo Mondi
Thanks
j
> +MODULE_AUTHOR("Chris Brandt ");
> +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
> +MODULE_LICENSE("GPL v2");
> --
> 2.16.1
>
signature.asc
Description: PGP signature
Re: [PATCH v4 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Hi Chris,
thanks for the patch
Just two minor things, so please add my
Reviewed-by: Jacopo Mondi
On Wed, Nov 07, 2018 at 01:27:33PM -0500, Chris Brandt wrote:
> Add device tree binding documentation and header file for Renesas R7S9210
> (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Rob Herring
> ---
> v3:
> - Added Reviewed-by
> v2:
> * Moved gpio-controller to required
> * Wrote a better description of what the sub-nodes are for
> * Added pinmux property description
> * Changed macro RZA2_PIN_ID to RZA2_PIN
> ---
> .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 88
> ++
> include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47
> 2 files changed, 135 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
>
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> new file mode 100644
> index ..622d37a7225b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> @@ -0,0 +1,88 @@
> +Renesas RZ/A2 combined Pin and GPIO controller
> +
> +The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
> controller.
> +Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> +Each port features up to 8 pins, each of them configurable for GPIO
> +function (port mode) or in alternate function mode.
> +Up to 8 different alternate function modes exist for each single pin.
> +
> +Pin controller node
> +---
> +
> +Required properties:
> + - compatible: should be:
s/should/shall ?
> +- "renesas,r7s9210-pinctrl": for RZ/A2M
> + - reg
> +Address base and length of the memory area where the pin controller
> +hardware is mapped to.
> + - gpio-controller
> +This pin controller also controls pins as GPIO
> + - #gpio-cells
> +Must be 2
> + - gpio-ranges
> +Expresses the total number GPIO ports/pins in this SoC
> +
> +
Two empty lines.
Thanks
j
> +Example: Pin controller node for RZ/A2M SoC (r7s9210)
> +
> + pinctrl: pin-controller@fcffe000 {
> + compatible = "renesas,r7s9210-pinctrl";
> + reg = <0xfcffe000 0x9D1>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = < 0 0 176>;
> + };
> +
> +Sub-nodes
> +-
> +
> +The child nodes of the pin controller designate pins to be used for
> +specific peripheral functions or as GPIO.
> +
> +- Pin multiplexing sub-nodes:
> + A pin multiplexing sub-node describes how to configure a set of
> + (or a single) pin in some desired alternate function mode.
> + The values for the pinmux properties are a combination of port name, pin
> + number and the desired function index. Use the RZA2_PINMUX macro located
> + in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
> + For assigning GPIO pins, use the macro RZA2_PIN_ID also in
> r7s9210-pinctrl.h
> + to express the desired port pin.
> +
> + Required properties:
> +- pinmux:
> + integer array representing pin number and pin multiplexing
> configuration.
> + When a pin has to be configured in alternate function mode, use this
> + property to identify the pin by its global index, and provide its
> + alternate function configuration number along with it.
> + When multiple pins are required to be configured as part of the same
> + alternate function they shall be specified as members of the same
> + argument list of a single "pinmux" property.
> + Helper macros to ease assembling the pin index from its position
> + (port where it sits on and pin number) and alternate function
> identifier
> + are provided by the pin controller header file at:
> +
> + Integers values in "pinmux" argument list are assembled as:
> + ((PORT * 8 + PIN) | MUX_FUNC << 16)
> +
> + Example: Board specific pins configuration
> +
> + {
> + /* Serial Console */
> + scif4_pins: serial4 {
> + pinmux = , /* TxD4 */
> + ; /* RxD4 */
> + };
> + };
> +
> + Example: Assigning a GPIO:
> +
> + leds {
> + status = "okay";
> + compatible = "gpio-leds";
> +
> + led0 {
> + /* P6_0 */
> +
Re: [PATCH v2 5/8] pinctrl: sh-pfc: r8a77990: Add VIN pins, groups and functions
Hi again,
thanks to Morimoto-san, we got answers from the HW team.
I'm pasting them here below.
On Tue, Sep 11, 2018 at 11:44:30AM +0200, jacopo mondi wrote:
> Hi again,
>I actually noticed I'm handling VIN4 and VIN5 un-consistently
> here...
>
> On Tue, Sep 11, 2018 at 09:44:48AM +0200, jacopo mondi wrote:
> > Hi Simon,
> >thanks for looking into this patch
> >
> > On Mon, Sep 10, 2018 at 03:01:15PM +0200, Simon Horman wrote:
> > > On Wed, Sep 05, 2018 at 05:29:42PM +0200, Jacopo Mondi wrote:
> > > > This patch adds VIN{4,5} pins, groups and functions to the R8A77990 SoC.
> > > >
> > > > Signed-off-by: Jacopo Mondi
> > > > ---
> > > > drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 250
> > > > ++
> > > > 1 file changed, 250 insertions(+)
> > > >
> > > > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > > > b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > > > index b81c807..0797940 100644
> > > > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > > > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > > > @@ -1831,6 +1831,194 @@ static const unsigned int usb30_id_mux[] = {
> > > > USB3HS0_ID_MARK,
> > > > };
> > > >
> > > > +/* - VIN4
> > > > --- */
> > > > +static const union vin_data vin4_data_a_pins = {
> > > > + .data24 = {
> > > > + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
> > > > + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
> > > > + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
> > > > + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
> > > > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
> > > > + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> > > > + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
> > > > + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
> > > > + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
> > > > + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
> > > > + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
> > > > + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
> > > > + },
> > > > +};
> > > > +
> > > > +static const union vin_data vin4_data_a_mux = {
> > > > + .data24 = {
> > > > + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
> > > > + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
> > > > + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
> > > > + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
> > > > + VI4_DATA8_MARK, VI4_DATA9_MARK,
> > > > + VI4_DATA10_MARK, VI4_DATA11_MARK,
> > > > + VI4_DATA12_MARK, VI4_DATA13_MARK,
> > > > + VI4_DATA14_MARK, VI4_DATA15_MARK,
> > > > + VI4_DATA16_MARK, VI4_DATA17_MARK,
> > > > + VI4_DATA18_MARK, VI4_DATA19_MARK,
> > > > + VI4_DATA20_MARK, VI4_DATA21_MARK,
> > > > + VI4_DATA22_MARK, VI4_DATA23_MARK,
> > > > + },
> > > > +};
> > > > +
> > > > +static const union vin_data vin4_data_b_pins = {
> > > > + .data24 = {
> > > > + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
> > > > + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
> > > > + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
> > > > + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
> > >
> > > I am curious to know why the data B pins below (8 - 23)
> > > are duplicates of the corresponding data A pins in vin4_data_a_pins.
> > >
> >
> > On R-Car E3 only pins [0-7] of VIN4 interface have an '_a' and '_b'
> > options. Pins from [8-23] are "shared".
> >
> > We can discuss how we want this to be handled, but according to Table
> > 6D.5 (pag. 383 of R-Car chip manual revision 1.00) this table is
> > correct.
> >
> > Currently there are two open questions on this PFC patch:
> > 1) This one here you reported
>
> It does not end here, I'm sorry.
>
> VIN4 and VIN5 are described differently, it seems to me that we have
>
> vin4_data[0-7]_[a|b]
> vin4_data[8-23]
> vin4_sync
>
> vin5_data[0-7]_[a|b]
> vin5_data[8-15]_a
> vin5_sync_a
&g
Re: [PATCH 07/30] media: entity: Add has_route entity operation
Hello,
thank you all for the patches!
On Thu, Aug 23, 2018 at 03:25:21PM +0200, Niklas Söderlund wrote:
> From: Laurent Pinchart
>
> The optional operation can be used by entities to report whether two
> pads are internally connected.
>
> Signed-off-by: Laurent Pinchart
> Signed-off-by: Michal Simek
> Signed-off-by: Sakari Ailus
> ---
> include/media/media-entity.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/media/media-entity.h b/include/media/media-entity.h
> index 532c438b9eb862c5..07df1b8d85a3c1ba 100644
> --- a/include/media/media-entity.h
> +++ b/include/media/media-entity.h
> @@ -193,6 +193,9 @@ struct media_pad {
> * @link_validate: Return whether a link is valid from the entity point of
> * view. The media_pipeline_start() function
> * validates all links by calling this operation. Optional.
> + * @has_route: Return whether a route exists inside the entity
> between
> + * two given pads. Optional. If the operation isn't
> + * implemented all pads will be considered as connected.
> *
> * .. note::
> *
> @@ -205,6 +208,8 @@ struct media_entity_operations {
> const struct media_pad *local,
> const struct media_pad *remote, u32 flags);
> int (*link_validate)(struct media_link *link);
> + bool (*has_route)(struct media_entity *entity, unsigned int pad0,
> + unsigned int pad1);
In one next patch in the series:
[PATCH 09/30] media: entity: Swap pads if route is checked from source to sink
the media_entity_has_route() operations ensures the sink pad is always
the first one. Could we make it explicit in the paramters name and
documentation to ease understanding when driver will have to implement this?
Thanks
j
> };
>
> /**
> --
> 2.18.0
>
signature.asc
Description: PGP signature
Re: [PATCH v2 8/8] arm64: dts: renesas: ebisu: Add HDMI and CVBS input
Hi Simon, On Wed, Sep 12, 2018 at 11:29:51AM +0200, Simon Horman wrote: > On Mon, Sep 10, 2018 at 05:21:08PM +0300, Laurent Pinchart wrote: > > Hi Jacopo, > > > > Thank you for the patch. > > > > On Wednesday, 5 September 2018 18:29:45 EEST Jacopo Mondi wrote: > > > Add HDMI and CVBS inputs device nodes to R-Car E3 Ebisu board. > > > > > > Both HDMI and CVBS inputs are connected to an ADV7482 video decoder hooked > > > to the SoC CSI-2 receiver port. > > > > > > Signed-off-by: Jacopo Mondi > > > > Reviewed-by: Laurent Pinchart > > Jacopo, > > I assume that this patch depends on 7/8. > Please repost this patch when you repost that one, > addressing Laurent's feedback. Sorry, I'm now confused :) I don't see any pending comment on [7/8] nor on this one ([8/8]). [7/8] has been applied to your "arm64-dt-for-v4.20" branch already (just checked). I have a small comment on [6/8] and one open question on [5/8]. All the other patches have been reviewed/acked already. To sum up: do you want me to repost [7/8] when re-sending this series? Thanks j signature.asc Description: PGP signature
