[PATCH] mmc: core: Fix setting power notify state variable for non eMMC
This patch skips the setting of the power notify state variable for non eMMC 4.5 devices. Also fixes the problem of omap_hsmmc noisy/broken for suspend resume reported by kevin Hilman. cc: Chris Ball c...@laptop.org Signed-off-by: Girish K S girish.shivananja...@linaro.org --- drivers/mmc/core/mmc.c | 10 +++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 3627044..4db73a9 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -882,10 +882,14 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, card-ext_csd.generic_cmd6_time); if (err err != -EBADMSG) goto free_card; - } - if (!err) - card-poweroff_notify_state = MMC_POWERED_ON; + /* +* The err can be -EBADMSG or 0, +* so check for success and update the flag +*/ + if (!err) + card-poweroff_notify_state = MMC_POWERED_ON; + } /* * Activate high speed (if supported) -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/6] ARM: S3C64XX: Modified according to SPI consolidation work.
On Fri, Nov 04, 2011 at 08:43:54AM -0400, Padmavathi Venna wrote:
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+static struct s3c64xx_spi_info crag6410_spi0_pdata __initdata = {
+ .cfg_gpio = s3c64xx_spi0_cfg_gpio,
+ .fifo_lvl_mask = 0x7f,
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+};
+#endif
It seems like a step backwards to have all this stuff in the individual
machines - most of this (everything except cfg_gpio pretty much) is a
property of the SoC silicon so should be somewhere central for the SoC.
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Re: [PATCH] mmc: core: Fix setting power notify state variable for non eMMC
On 4 November 2011 06:52, Girish K S girish.shivananja...@linaro.org wrote: This patch skips the setting of the power notify state variable for non eMMC 4.5 devices. Also fixes the problem of omap_hsmmc noisy/broken for suspend resume reported by kevin Hilman. cc: Chris Ball c...@laptop.org Signed-off-by: Girish K S girish.shivananja...@linaro.org --- drivers/mmc/core/mmc.c | 10 +++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 3627044..4db73a9 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -882,10 +882,14 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, card-ext_csd.generic_cmd6_time); if (err err != -EBADMSG) goto free_card; - } - if (!err) - card-poweroff_notify_state = MMC_POWERED_ON; + /* + * The err can be -EBADMSG or 0, + * so check for success and update the flag + */ + if (!err) + card-poweroff_notify_state = MMC_POWERED_ON; + } /* * Activate high speed (if supported) -- 1.7.4.1 Hi Chris, this patch is based on for-linus branch. Regards Girish K S -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH] Consolidate Samsung MAINTAINERS
Am Sonntag 23 Oktober 2011, 00:12:14 schrieb Heiko Stübner: These days most Samsung stuff gets in the kernel through Kukjin Kim. This patch changes MAINTAINERS to reflect this. By adding Kukjin Kim to the maintainers for S3C2410, S3C244x and S3C64xx alongside Ben Dooks the extra entries become identical to the base ARM/SAMSUNG entry and can move into it. Also the S3C2416 gets a maintainer through the s3c24* wildcard - as it did not have one until now. Signed-off-by: Heiko Stuebner he...@sntech.de --- ping? Thanks Heiko -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] ARM: S5P64X0: Add SDMMC support
This patchset adds support for sdhci controller on S5P6440 and S5P6450. Since this patchset is based on mmc: sdhci-s3c: Rework platform data and add device tree support clk_type member has been removed from platform data. This patchset depends on the patchs: ARM: S5P64X0: Modified files for SPI consolidation work. mmc: sdhci-s3c: Rework platform data and add device tree support. Rajeshwari Shinde (3): ARM: S5P64X0: Add HSMMC setup for host Controller ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names ARM: S5P64X0: Enable SDHCI support arch/arm/mach-s5p64x0/Kconfig | 24 +++ arch/arm/mach-s5p64x0/Makefile |1 + arch/arm/mach-s5p64x0/clock-s5p6440.c | 72 +++ arch/arm/mach-s5p64x0/clock-s5p6450.c | 72 +++ arch/arm/mach-s5p64x0/cpu.c|9 +++ arch/arm/mach-s5p64x0/mach-smdk6440.c | 25 +++ arch/arm/mach-s5p64x0/mach-smdk6450.c | 26 +++- arch/arm/mach-s5p64x0/setup-sdhci-gpio.c | 104 arch/arm/plat-samsung/include/plat/sdhci.h | 42 +++ 9 files changed, 314 insertions(+), 61 deletions(-) create mode 100644 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: S5P64X0: Add HSMMC setup for host Controller
Adds support for HSMMC for S5P64X0 platform, performs
setup for host controller and related GPIO.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/mach-s5p64x0/Kconfig | 24 +++
arch/arm/mach-s5p64x0/Makefile |1 +
arch/arm/mach-s5p64x0/cpu.c|9 +++
arch/arm/mach-s5p64x0/setup-sdhci-gpio.c | 104
arch/arm/plat-samsung/include/plat/sdhci.h | 42 +++
5 files changed, 180 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 4de625a..4d6154e 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -41,6 +41,11 @@ config S5P64X0_SETUP_SPI
help
Common setup code for SPI GPIO configurations
+config S5P64X0_SETUP_SDHCI_GPIO
+ bool
+ help
+ Common setup code for SDHCI gpio.
+
# machine support
config MACH_SMDK6440
@@ -50,12 +55,16 @@ config MACH_SMDK6440
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_FB_24BPP
select S5P64X0_SETUP_I2C1
+ select S5P64X0_SETUP_SDHCI_GPIO
help
Machine support for the Samsung SMDK6440
@@ -66,13 +75,28 @@ config MACH_SMDK6450
select S3C_DEV_I2C1
select S3C_DEV_RTC
select S3C_DEV_WDT
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_FB_24BPP
select S5P64X0_SETUP_I2C1
+ select S5P64X0_SETUP_SDHCI_GPIO
help
Machine support for the Samsung SMDK6450
+menu Use 8-bit SDHCI bus width
+
+config S5P64X0_SD_CH1_8BIT
+ bool SDHCI Channel 1 (Slot 1)
+ depends on MACH_SMDK6450 || MACH_SMDK6440
+ help
+ Support SDHCI Channel 1 8-bit bus.
+ If selected, Channel 2 is disabled.
+
+endmenu
+
endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f473de..084f436 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5P64X0_SETUP_SPI)+= setup-spi.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index ecab40c..f6e24f3 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -40,6 +40,7 @@
#include plat/s5p6450.h
#include plat/adc-core.h
#include plat/fb-core.h
+#include plat/sdhci.h
/* Initial IO mappings */
@@ -112,6 +113,10 @@ void __init s5p6440_map_io(void)
s3c_adc_setname(s3c64xx-adc);
s3c_fb_setname(s5p64x0-fb);
+ s5p64x0_default_sdhci0();
+ s5p64x0_default_sdhci1();
+ s5p6440_default_sdhci2();
+
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
init_consistent_dma_size(SZ_8M);
@@ -123,6 +128,10 @@ void __init s5p6450_map_io(void)
s3c_adc_setname(s3c64xx-adc);
s3c_fb_setname(s5p64x0-fb);
+ s5p64x0_default_sdhci0();
+ s5p64x0_default_sdhci1();
+ s5p6450_default_sdhci2();
+
iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
init_consistent_dma_size(SZ_8M);
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 000..8410af0
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
+/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/platform_device.h
+#include linux/io.h
+#include linux/gpio.h
+
+#include mach/regs-gpio.h
+#include mach/regs-clock.h
+
+#include plat/gpio-cfg.h
+#include plat/sdhci.h
+#include plat/cpu.h
+
+void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+ struct s3c_sdhci_platdata *pdata = dev-dev.platform_data;
+
+ /* Set all the necessary GPG pins
[PATCH 3/3] ARM: S5P64X0: Enable SDHCI support
Enables SDHCI supports for SMDK6440 and SMDK6450.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/mach-s5p64x0/mach-smdk6440.c | 25 +
arch/arm/mach-s5p64x0/mach-smdk6450.c | 26 +-
2 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c
b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index d828fd3..79967d1 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,6 +24,7 @@
#include linux/gpio.h
#include linux/pwm_backlight.h
#include linux/fb.h
+#include linux/mmc/host.h
#include video/platform_lcd.h
@@ -53,6 +54,7 @@
#include plat/fb.h
#include plat/regs-fb.h
#include plat/s3c64xx-spi.h
+#include plat/sdhci.h
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
S3C2410_UCON_RXILEVEL | \
@@ -162,6 +164,25 @@ static struct platform_device *smdk6440_devices[]
__initdata = {
s5p6440_device_iis,
s3c_device_fb,
smdk6440_lcd_lte480wv,
+ s3c_device_hsmmc0,
+ s3c_device_hsmmc1,
+ s3c_device_hsmmc2,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_INTERNAL,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_NONE,
};
static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -253,6 +274,10 @@ static void __init smdk6440_machine_init(void)
s5p6440_set_lcd_interface();
s3c_fb_set_platdata(smdk6440_lcd_pdata);
+ s3c_sdhci0_set_platdata(smdk6440_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(smdk6440_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(smdk6440_hsmmc2_pdata);
+
platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
}
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c
b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 73224b2..6a4d41c 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,6 +24,7 @@
#include linux/gpio.h
#include linux/pwm_backlight.h
#include linux/fb.h
+#include linux/mmc/host.h
#include video/platform_lcd.h
@@ -53,6 +54,7 @@
#include plat/fb.h
#include plat/regs-fb.h
#include plat/s3c64xx-spi.h
+#include plat/sdhci.h
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
S3C2410_UCON_RXILEVEL | \
@@ -180,10 +182,28 @@ static struct platform_device *smdk6450_devices[]
__initdata = {
s5p6450_device_iis0,
s3c_device_fb,
smdk6450_lcd_lte480wv,
-
+ s3c_device_hsmmc0,
+ s3c_device_hsmmc1,
+ s3c_device_hsmmc2,
/* s5p6450_device_spi0 will be added */
};
+static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_NONE,
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_NONE,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
+ .cd_type= S3C_SDHCI_CD_NONE,
+};
+
static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
.flags = 0,
.slave_addr = 0x10,
@@ -273,6 +293,10 @@ static void __init smdk6450_machine_init(void)
s5p6450_set_lcd_interface();
s3c_fb_set_platdata(smdk6450_lcd_pdata);
+ s3c_sdhci0_set_platdata(smdk6450_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(smdk6450_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(smdk6450_hsmmc2_pdata);
+
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
}
--
1.7.4.4
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[PATCH 2/3] ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names
Add support for lookup of sdhci-s3c controller clocks using generic
names for s5p64x0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 72 +++--
arch/arm/mach-s5p64x0/clock-s5p6450.c | 72 +++--
2 files changed, 84 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c
b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 73c7cc9..c041ad7 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -379,36 +379,6 @@ static struct clksrc_sources clkset_audio = {
static struct clksrc_clk clksrcs[] = {
{
.clk= {
- .name = sclk_mmc,
- .devname= s3c-sdhci.0,
- .ctrlbit= (1 24),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
- }, {
- .clk= {
- .name = sclk_mmc,
- .devname= s3c-sdhci.1,
- .ctrlbit= (1 25),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
- }, {
- .clk= {
- .name = sclk_mmc,
- .devname= s3c-sdhci.2,
- .ctrlbit= (1 26),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
- }, {
- .clk= {
.name = sclk_post,
.ctrlbit= (1 10),
.enable = s5p64x0_sclk_ctrl,
@@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk= {
+ .name = sclk_mmc,
+ .devname= s3c-sdhci.0,
+ .ctrlbit= (1 24),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk= {
+ .name = sclk_mmc,
+ .devname= s3c-sdhci.1,
+ .ctrlbit= (1 25),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk= {
+ .name = sclk_mmc,
+ .devname= s3c-sdhci.2,
+ .ctrlbit= (1 26),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
static struct clksrc_clk clk_sclk_uclk = {
.clk= {
.name = uclk1,
@@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
clk_sclk_uclk,
clk_sclk_spi0,
clk_sclk_spi1,
+ clk_sclk_mmc0,
+ clk_sclk_mmc1,
+ clk_sclk_mmc2
};
static struct clk_lookup s5p6440_clk_lookup[] = {
@@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, spi_busclk0, clk_p),
CLKDEV_INIT(s3c64xx-spi.0, spi_busclk1, clk_sclk_spi0.clk),
CLKDEV_INIT(s3c64xx-spi.1, spi_busclk1, clk_sclk_spi1.clk),
+ CLKDEV_INIT(s3c-sdhci.0, mmc_busclk.2, clk_sclk_mmc0.clk),
+ CLKDEV_INIT(s3c-sdhci.1, mmc_busclk.2, clk_sclk_mmc1.clk),
+ CLKDEV_INIT(s3c-sdhci.2, mmc_busclk.2, clk_sclk_mmc2.clk),
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c
b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 50f90cb..b5087cb 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -413,36 +413,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
static struct clksrc_clk clksrcs[] = {
{
.clk= {
- .name
Re: [PATCH 2/2] mmc: core: Support packed command for eMMC4.5 device
On Thu, Nov 3, 2011 at 7:23 AM, Seungwon Jeon tgih@samsung.com wrote:
S, Venkatraman svenk...@ti.com wrote:
On Wed, Nov 2, 2011 at 1:33 PM, Seungwon Jeon tgih@samsung.com wrote:
This patch supports packed command of eMMC4.5 device.
Several reads(or writes) can be grouped in packed command
and all data of the individual commands can be sent in a
single transfer on the bus.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/card/block.c | 355
--
drivers/mmc/card/queue.c | 48 ++-
drivers/mmc/card/queue.h | 12 ++
include/linux/mmc/core.h | 3 +
4 files changed, 404 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index a1cb21f..6c49656 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -59,6 +59,13 @@ MODULE_ALIAS(mmc:block);
#define INAND_CMD38_ARG_SECTRIM1 0x81
#define INAND_CMD38_ARG_SECTRIM2 0x88
+#define mmc_req_rel_wr(req) (((req-cmd_flags REQ_FUA) || \
+ (req-cmd_flags REQ_META)) \
+ (rq_data_dir(req) == WRITE))
+#define PACKED_CMD_VER 0x01
+#define PACKED_CMD_RD 0x01
+#define PACKED_CMD_WR 0x02
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -943,7 +950,8 @@ static int mmc_blk_err_check(struct mmc_card *card,
* kind. If it was a write, we may have transitioned to
* program mode, which we have to wait for it to complete.
*/
- if (!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) {
+ if ((!mmc_host_is_spi(card-host) rq_data_dir(req) != READ) ||
+ (mq_mrq-packed_cmd == MMC_PACKED_WR_HDR)) {
u32 status;
do {
int err = get_card_status(card, status, 5);
@@ -980,12 +988,67 @@ static int mmc_blk_err_check(struct mmc_card *card,
if (!brq-data.bytes_xfered)
return MMC_BLK_RETRY;
+ if (mq_mrq-packed_cmd != MMC_PACKED_NONE) {
+ if (unlikely(brq-data.blocks 9 !=
brq-data.bytes_xfered))
+ return MMC_BLK_PARTIAL;
+ else
+ return MMC_BLK_SUCCESS;
+ }
+
if (blk_rq_bytes(req) != brq-data.bytes_xfered)
return MMC_BLK_PARTIAL;
return MMC_BLK_SUCCESS;
}
+static int mmc_blk_packed_err_check(struct mmc_card *card,
+ struct mmc_async_req *areq)
+{
+ struct mmc_queue_req *mq_mrq = container_of(areq, struct
mmc_queue_req,
+ mmc_active);
+ int err, check, status;
+ u8 ext_csd[512];
+
+ check = mmc_blk_err_check(card, areq);
+
+ if (check == MMC_BLK_SUCCESS)
+ return check;
+
+ if (check == MMC_BLK_PARTIAL) {
+ err = get_card_status(card, status, 0);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if (status R1_EXP_EVENT) {
+ err = mmc_send_ext_csd(card, ext_csd);
+ if (err)
+ return MMC_BLK_ABORT;
+
+ if ((ext_csd[EXT_CSD_EXP_EVENTS_STATUS + 0]
+ EXT_CSD_PACKED_FAILURE)
+
(ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+ EXT_CSD_PACKED_GENERIC_ERROR)) {
+ if (ext_csd[EXT_CSD_PACKED_CMD_STATUS]
+
EXT_CSD_PACKED_INDEXED_ERROR) {
+ /* Make be 0-based */
+ mq_mrq-packed_fail_idx =
+
ext_csd[EXT_CSD_PACKED_FAILURE_INDEX] - 1;
+ return MMC_BLK_PARTIAL;
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+ } else {
+ return MMC_BLK_RETRY;
+ }
+ }
+
+ if (check != MMC_BLK_ABORT)
+ return MMC_BLK_RETRY;
+ else
+ return MMC_BLK_ABORT;
+}
+
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
struct mmc_card *card,
int disable_multi,
@@ -1129,6 +1192,211 @@ static void mmc_blk_rw_rq_prep(struct
mmc_queue_req *mqrq,
mmc_queue_bounce_pre(mqrq);
}
+static u8 mmc_blk_chk_packable(struct mmc_queue *mq, struct request *req)
+{
+ struct request_queue *q = mq-queue;
+ struct mmc_card *card = mq-card;
+ struct
[PATCH 0/4]ARM: exynos4: Add l2 retention mode cpuidle state
From: Amit Daniel Kachhap amit.kach...@linaro.org This Patch series adds support for AFTR mode cpuidle state based on patch (http://www.spinics.net/lists/arm-kernel/msg132243.html) earlier submitted by Jaecheol Lee jc@samsung.com. This patch uses CPU PM notifiers , common l2 save/restore and new cpu_suspend/resume interfaces and is based on the tip of linus tree(git://github.com/torvalds/linux.git). Amit Daniel Kachhap (3): ARM: exynos4: Add support for AFTR mode cpuidle state ARM: exynos4: add L2 early resume code ARM: exynos4: remove useless code to save/restore L2 and GIC state Lorenzo Pieralisi (1): ARM: exynos4: remove useless churn in sleep.S arch/arm/mach-exynos4/cpu.c | 43 ++-- arch/arm/mach-exynos4/cpuidle.c | 152 +- arch/arm/mach-exynos4/include/mach/pmu.h |2 + arch/arm/mach-exynos4/pm.c | 86 - arch/arm/mach-exynos4/sleep.S| 29 +- 5 files changed, 210 insertions(+), 102 deletions(-) -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: exynos4: Add support for AFTR mode cpuidle state
From: Amit Daniel Kachhap amit.kach...@linaro.org
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in
cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode.
This patch ports the code to the latest interfaces to
save/restore CPU state inclusive of CPU PM notifiers, l2
resume and cpu_suspend/resume.
Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Amit Daniel Kachhap amit.kach...@linaro.org
---
arch/arm/mach-exynos4/cpuidle.c | 152 +-
arch/arm/mach-exynos4/include/mach/pmu.h |2 +
2 files changed, 151 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpuidle.c b/arch/arm/mach-exynos4/cpuidle.c
index bf7e96f..111ccc3 100644
--- a/arch/arm/mach-exynos4/cpuidle.c
+++ b/arch/arm/mach-exynos4/cpuidle.c
@@ -11,22 +11,48 @@
#include linux/kernel.h
#include linux/init.h
#include linux/cpuidle.h
+#include linux/cpu_pm.h
#include linux/io.h
-
+#include linux/suspend.h
+#include linux/err.h
#include asm/proc-fns.h
+#include asm/smp_scu.h
+#include asm/suspend.h
+#include asm/unified.h
+#include mach/regs-pmu.h
+#include mach/pmu.h
+
+#include plat/exynos4.h
+#include plat/cpu.h
+
+#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM7 : (S5P_VA_SYSRAM + 0x24))
+#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM6 : (S5P_VA_SYSRAM + 0x20))
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state);
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+ struct cpuidle_state *state);
+
static struct cpuidle_state exynos4_cpuidle_set[] = {
[0] = {
.enter = exynos4_enter_idle,
.exit_latency = 1,
.target_residency = 10,
.flags = CPUIDLE_FLAG_TIME_VALID,
- .name = IDLE,
+ .name = C0,
.desc = ARM clock gating(WFI),
},
+ [1] = {
+ .enter = exynos4_enter_lowpower,
+ .exit_latency = 300,
+ .target_residency = 10,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = C1,
+ .desc = ARM power down,
+ },
};
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -36,6 +62,96 @@ static struct cpuidle_driver exynos4_idle_driver = {
.owner = THIS_MODULE,
};
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos4_set_wakeupmask(void)
+{
+ __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+}
+
+static unsigned int g_pwr_ctrl, g_diag_reg;
+
+static void save_cpu_arch_register(void)
+{
+ /*read power control register*/
+ asm(mrc p15, 0, %0, c15, c0, 0 : =r(g_pwr_ctrl) : : cc);
+ /*read diagnostic register*/
+ asm(mrc p15, 0, %0, c15, c0, 1 : =r(g_diag_reg) : : cc);
+ return;
+}
+
+static void restore_cpu_arch_register(void)
+{
+ /*write power control register*/
+ asm(mcr p15, 0, %0, c15, c0, 0 : : r(g_pwr_ctrl) : cc);
+ /*write diagnostic register*/
+ asm(mcr p15, 0, %0, c15, c0, 1 : : r(g_diag_reg) : cc);
+ return;
+}
+
+static int idle_finisher(unsigned long flags)
+{
+ cpu_do_idle();
+ return 1;
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct timeval before, after;
+ int idle_time;
+ unsigned long tmp;
+
+ local_irq_disable();
+ do_gettimeofday(before);
+
+ exynos4_set_wakeupmask();
+
+ /* Set value of power down register for aftr mode */
+ exynos4_sys_powerdown_conf(SYS_AFTR);
+
+ save_cpu_arch_register();
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ cpu_pm_enter();
+ cpu_cluster_pm_enter();
+
+ cpu_suspend(0, idle_finisher);
+
+ scu_enable(S5P_VA_SCU);
+
+ cpu_cluster_pm_exit();
+ cpu_pm_exit();
+
+ restore_cpu_arch_register();
+
+ /*
+* If PMU failed while entering sleep mode, WFI will be
+* ignored by PMU and then exiting cpu_do_idle().
+* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+* in this situation.
+*/
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+
[PATCH 2/4] ARM: exynos4: remove useless churn in sleep.S
From: Lorenzo Pieralisi lorenzo.pieral...@arm.com This patch cleans up sleep code in preparation for L2 resume code and hotplug functions Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com --- arch/arm/mach-exynos4/sleep.S |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index 0984078..c19527b 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -27,8 +27,6 @@ */ #include linux/linkage.h -#include asm/assembler.h -#include asm/memory.h .text @@ -52,3 +50,4 @@ ENTRY(s3c_cpu_resume) b cpu_resume +ENDPROC(s3c_cpu_resume) -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] ARM: exynos4: add L2 early resume code
From: Amit Daniel Kachhap amit.kach...@linaro.org
This patch adds code to save L2 register configuration at boot, and to
resume L2 before MMU is enabled in suspend and cpuidle resume paths.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Amit Daniel Kachhap amit.kach...@linaro.org
---
arch/arm/mach-exynos4/cpu.c | 43 ++--
arch/arm/mach-exynos4/sleep.S | 26
2 files changed, 58 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index a348434..53c6cd3 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -11,6 +11,7 @@
#include linux/sched.h
#include linux/sysdev.h
+#include asm/cacheflush.h
#include asm/mach/map.h
#include asm/mach/irq.h
@@ -31,6 +32,7 @@
#include mach/regs-irq.h
#include mach/regs-pmu.h
+#include mach/pmu.h
unsigned int gic_bank_offset __read_mostly;
@@ -254,20 +256,39 @@ core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
- /* TAG, Data Latency Control: 2cycle */
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+ if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) 0x1)) {
- if (soc_is_exynos4210())
- __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
- else if (soc_is_exynos4212() || soc_is_exynos4412())
- __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+ l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
+ /* TAG, Data Latency Control: 2 cycles */
+ l2x0_saved_regs.tag_latency = 0x110;
+
+ if (soc_is_exynos4212() || soc_is_exynos4412())
+ l2x0_saved_regs.data_latency = 0x120;
+ else
+ l2x0_saved_regs.data_latency = 0x110;
+
+ l2x0_saved_regs.prefetch_ctrl = 0x3007;
+ l2x0_saved_regs.pwr_ctrl =
+ (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
- /* L2X0 Prefetch Control */
- __raw_writel(0x3007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+ l2x0_regs_phys = virt_to_phys(l2x0_saved_regs);
- /* L2X0 Power Control */
- __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
-S5P_VA_L2CC + L2X0_POWER_CTRL);
+ __raw_writel(l2x0_saved_regs.tag_latency,
+ S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+ __raw_writel(l2x0_saved_regs.data_latency,
+ S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+ /* L2X0 Prefetch Control */
+ __raw_writel(l2x0_saved_regs.prefetch_ctrl,
+ S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+ /* L2X0 Power Control */
+ __raw_writel(l2x0_saved_regs.pwr_ctrl,
+ S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+ clean_dcache_area(l2x0_regs_phys, sizeof(unsigned long));
+ clean_dcache_area(l2x0_saved_regs, sizeof(struct l2x0_regs));
+ }
l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200);
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index c19527b..3284213 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -27,6 +27,8 @@
*/
#include linux/linkage.h
+#include asm/asm-offsets.h
+#include asm/hardware/cache-l2x0.h
.text
@@ -47,7 +49,31 @@
* other way of restoring the stack pointer after sleep, and we
* must not write to the code segment (code is read-only)
*/
+ .align
+ .data
ENTRY(s3c_cpu_resume)
+ adr r0, l2x0_regs_phys
+ ldr r0, [r0]
+ ldr r1, [r0, #L2X0_R_PHY_BASE]
+ ldr r2, [r1, #L2X0_CTRL]
+ tst r2, #0x1
+ bne resume_l2on
+ ldr r2, [r0, #L2X0_R_AUX_CTRL]
+ str r2, [r1, #L2X0_AUX_CTRL]
+ ldr r2, [r0, #L2X0_R_TAG_LATENCY]
+ str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+ ldr r2, [r0, #L2X0_R_DATA_LATENCY]
+ str r2, [r1, #L2X0_DATA_LATENCY_CTRL]
+ ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
+ str r2, [r1, #L2X0_PREFETCH_CTRL]
+ ldr r2, [r0, #L2X0_R_PWR_CTRL]
+ str r2, [r1, #L2X0_POWER_CTRL]
+ mov r2, #1
+ str r2, [r1, #L2X0_CTRL]
+resume_l2on:
b cpu_resume
ENDPROC(s3c_cpu_resume)
+ .globl l2x0_regs_phys
+l2x0_regs_phys:
+ .long 0
--
1.7.5.4
--
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[PATCH 4/4] ARM: exynos4: remove useless code to save/restore L2 and GIC state
From: Amit Daniel Kachhap amit.kach...@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch
removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated
CPU PM notifiers and new sleep code that allows to resume L2 before MMU
is turned on.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Amit Daniel Kachhap amit.kach...@linaro.org
---
arch/arm/mach-exynos4/pm.c | 86
1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 62e4f43..7499f14 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
};
static struct sleep_save exynos4_core_save[] = {
- /* GIC side */
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
-
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
-
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
@@ -154,13 +83,6 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_SROM_BC3),
};
-static struct sleep_save exynos4_l2cc_save[] = {
- SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
- SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
@@ -181,7 +103,6 @@ static void exynos4_pm_prepare(void)
u32 tmp;
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
- s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
@@ -397,13 +318,6 @@ static void exynos4_pm_resume(void)
Re: [PATCH 4/4] ARM: exynos4: remove useless code to save/restore L2 and GIC state
On 11/04/2011 06:03 PM, amit.kach...@linaro.org wrote:
From: Amit Daniel Kachhap amit.kach...@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch
removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated
CPU PM notifiers and new sleep code that allows to resume L2 before MMU
is turned on.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Amit Daniel Kachhap amit.kach...@linaro.org
---
arch/arm/mach-exynos4/pm.c | 86
1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 62e4f43..7499f14 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
};
static struct sleep_save exynos4_core_save[] = {
- /* GIC side */
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
-
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
-
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
This list is not complete anyway, some peripheral devices interrupts do not
work after resume from system suspend to RAM.
Is there any code already handling GIC state during system suspend/resume
cycles?
Or you refer to some upcoming patches ?
--
Thanks,
Sylwester
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Re: [PATCH 5/6] mmc: Add OF bindings support for mmc host controller capabilities
On Thu, Nov 03, 2011 at 02:06:02AM +0530, Thomas Abraham wrote: Device nodes representing sd/mmc controllers in a device tree would include mmc host controller capabilities. Add support for parsing of mmc host controller capabilities included in device nodes. Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- .../devicetree/bindings/mmc/linux-mmc-host.txt | 13 drivers/mmc/core/host.c| 31 include/linux/mmc/host.h |1 + 3 files changed, 45 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/linux-mmc-host.txt diff --git a/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt b/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt new file mode 100644 index 000..714b2b1 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/linux-mmc-host.txt @@ -0,0 +1,13 @@ +* Linux MMC Host Controller Capabilities + +The following bindings can be used in a device node to specify any board +specific mmc host controller capabilities. + +- linux,mmc_cap_4_bit_data - Host can do 4-bit transfers +- linux,mmc_cap_mmc_highspeed - Host can do MMC high-speed timing +- linux,mmc_cap_sd_highspeed - Host can do SD high-speed timing +- linux,mmc_cap_needs_poll - Host needs polling for card detection +- linux,mmc_cap_8_bit_data - Host can do 8-bit transfer +- linux,mmc_cap_disable - Host can be disabled and re-enabled to save power +- linux,mmc_cap_nonremovable - Host is connected to nonremovable media +- linux,mmc_cap_erase - Host allows erase/trim commands linux-prefixed properties are a big red flag. The device tree should describe the hardware, not what linux does with the hardware. See previous comments about support-8bit for encoding exactly the same hardware capability in a linux-agnostic way. What the sdhci driver chooses to do with it is up to the driver, and in some cases it means it will set the capabilities flag. Same goes for the other properties. It should not go in as it is implemented in this patch, it needs to be fixed up. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] Samsung devel-4 for v3.2
On Friday 04 November 2011, Kukjin Kim wrote: As we talked in Prague, I'm sending 'pull request for v3.2' Samsung-devel4 which includes supporting EXYNOS4 DT, SPI clkdev and reorganization arch/arm/mach-exynos and small things. Please pull from: git://github.com/kgene/linux-samsung.git next-samsung-devel-4 As a note, the branch includes arm-soc/next/cleanup3 and arm-soc/next/devel2 based on mainline commit 994c0e99 (Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc) because it is needed for this and they include all of Samsung stuff for v3.2. And I will be back to kernel.org after this merge window. If any problems, please let me know. I've looked through it, and I think I'll hold off for this merge window, especially given that I had enough trouble with the the other commits and that the submission is really late. Please realize that I have to push back on stuff that comes during the merge window. Please send the contents split up into separate branches (dt, spi, clkdev, rename, devel) for 3.3. I think it's ok if you want to send just the rename patch for 3.2 the way we had discussed earlier, because this kind of patch really makes sense at the end of the merge window. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL] Samsung devel-4 for v3.2
Arnd Bergmann wrote: On Friday 04 November 2011, Kukjin Kim wrote: As we talked in Prague, I'm sending 'pull request for v3.2' Samsung-devel4 which includes supporting EXYNOS4 DT, SPI clkdev and reorganization arch/arm/mach-exynos and small things. Please pull from: git://github.com/kgene/linux-samsung.git next-samsung-devel-4 As a note, the branch includes arm-soc/next/cleanup3 and arm-soc/next/devel2 based on mainline commit 994c0e99 (Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc) because it is needed for this and they include all of Samsung stuff for v3.2. And I will be back to kernel.org after this merge window. If any problems, please let me know. I've looked through it, and I think I'll hold off for this merge window, especially given that I had enough trouble with the the other commits and that the submission is really late. Please realize that I have to push back on stuff that comes during the merge window. Please send the contents split up into separate branches (dt, spi, clkdev, rename, devel) for 3.3. I think it's ok if you want to send just the rename patch for 3.2 the way we had discussed earlier, because this kind of patch really makes sense at the end of the merge window. Hi Arnd, OK, I will send the rename branch in a half an hour and make separate branches for others which will be merged next time. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] Samsung devel-4 for v3.2
On Saturday 05 November 2011, Kukjin Kim wrote: Arnd Bergmann wrote: Please send the contents split up into separate branches (dt, spi, clkdev, rename, devel) for 3.3. I think it's ok if you want to send just the rename patch for 3.2 the way we had discussed earlier, because this kind of patch really makes sense at the end of the merge window. Hi Arnd, OK, I will send the rename branch in a half an hour and make separate branches for others which will be merged next time. Ok, very good. I'm sending the pull requests for the other two branches right now, I assume Linus will take them quickly (or not at all if he has unexpected objections), so you could base your pull request on top of his merge. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung Exynos for v3.2
Hi Arnd,
As you suggested, I made reorganization mach-exynos branch,
next-samsung-exynos in my tree and it has been tested on some boards.
Please pull from:
git://github.com/kgene/linux-samsung.git next-samsung-exynos
As a note, will finish other separate branch today.
If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
The following changes since commit 2ef9270f2481543e49bfbdc0d125f0bf3068d246:
Merge remote branch 'arm-soc/next/devel2' into next-samsung-dt (2011-11-02
19:12:59 +0900)
are available in the git repository at:
git://github.com/kgene/linux-samsung.git next-samsung-exynos
Jonghwan Choi (1):
ARM: SAMSUNG: Fix compile error due to kfree
Joonyoung Shim (1):
ARM: SAMSUNG: Add clk enable/disable of pwm
Kukjin Kim (1):
ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
Marc Zyngier (1):
ARM: EXYNOS4: convert MCT to percpu interrupt API
arch/arm/Kconfig |8 +-
arch/arm/Makefile |2 +-
arch/arm/configs/exynos4_defconfig |9 +--
arch/arm/{mach-exynos4 = mach-exynos}/Kconfig | 41 +---
arch/arm/{mach-exynos4 = mach-exynos}/Makefile| 11 ++--
.../{mach-exynos4 = mach-exynos}/Makefile.boot|0
.../clock-exynos4210.c |0
.../clock-exynos4212.c |0
arch/arm/{mach-exynos4 = mach-exynos}/clock.c |0
arch/arm/{mach-exynos4 = mach-exynos}/cpu.c | 69
+++-
arch/arm/{mach-exynos4 = mach-exynos}/cpuidle.c |0
arch/arm/{mach-exynos4 = mach-exynos}/dev-ahci.c |0
arch/arm/{mach-exynos4 = mach-exynos}/dev-audio.c |0
arch/arm/{mach-exynos4 = mach-exynos}/dev-dwmci.c |0
arch/arm/{mach-exynos4 = mach-exynos}/dev-pd.c|0
.../arm/{mach-exynos4 = mach-exynos}/dev-sysmmu.c |0
arch/arm/{mach-exynos4 = mach-exynos}/dma.c |0
arch/arm/{mach-exynos4 = mach-exynos}/headsmp.S |0
arch/arm/{mach-exynos4 = mach-exynos}/hotplug.c |0
.../include/mach/debug-macro.S |0
.../include/mach/dma.h |0
.../include/mach/dwmci.h |0
.../include/mach/entry-macro.S |0
.../include/mach/exynos4-clock.h |0
.../include/mach/gpio.h|0
.../include/mach/hardware.h|0
.../include/mach/io.h |0
.../include/mach/irqs.h|0
.../include/mach/map.h | 32 ++
.../include/mach/memory.h |0
.../include/mach/pm-core.h |0
.../include/mach/pmu.h |0
.../include/mach/regs-audss.h |0
.../include/mach/regs-clock.h |0
.../include/mach/regs-gpio.h |0
.../include/mach/regs-irq.h|0
.../include/mach/regs-mct.h|0
.../include/mach/regs-mem.h|0
.../include/mach/regs-pmu.h|0
.../include/mach/regs-sysmmu.h |0
.../include/mach/regs-usb-phy.h|0
.../include/mach/sysmmu.h |0
.../include/mach/system.h |0
.../include/mach/timex.h |0
.../include/mach/uncompress.h |0
.../include/mach/vmalloc.h |0
arch/arm/{mach-exynos4 = mach-exynos}/init.c |0
.../{mach-exynos4 = mach-exynos}/irq-combiner.c |0
arch/arm/{mach-exynos4 = mach-exynos}/irq-eint.c |0
.../mach-armlex4210.c |0
arch/arm/{mach-exynos4 = mach-exynos}/mach-nuri.c |0
.../{mach-exynos4 = mach-exynos}/mach-origen.c|0
.../{mach-exynos4 = mach-exynos}/mach-smdk4x12.c |0
.../{mach-exynos4 = mach-exynos}/mach-smdkv310.c |0
.../mach-universal_c210.c |0
arch/arm/{mach-exynos4 = mach-exynos}/mct.c | 40
arch/arm/{mach-exynos4 = mach-exynos}/platsmp.c |0
arch/arm/{mach-exynos4 = mach-exynos}/pm.c|0
arch/arm/{mach-exynos4 = mach-exynos}/pmu.c |0
.../arm/{mach-exynos4 = mach-exynos}/setup-fimc.c |0
.../{mach-exynos4 = mach-exynos}/setup-fimd0.c|0
.../arm/{mach-exynos4 = mach-exynos}/setup-i2c0.c |0
.../arm/{mach-exynos4 = mach-exynos}/setup-i2c1.c |0
.../arm/{mach-exynos4 = mach-exynos}/setup-i2c2.c |0
.../arm/{mach-exynos4 = mach-exynos}/setup-i2c3.c |0
.../arm/{mach-exynos4 = mach-exynos}/setup-i2c4.c |0
.../arm/{mach-exynos4
RE: [RFC][PATCH] Consolidate Samsung MAINTAINERS
Heiko Stübner wrote: Am Sonntag 23 Oktober 2011, 00:12:14 schrieb Heiko Stübner: These days most Samsung stuff gets in the kernel through Kukjin Kim. This patch changes MAINTAINERS to reflect this. By adding Kukjin Kim to the maintainers for S3C2410, S3C244x and S3C64xx alongside Ben Dooks the extra entries become identical to the base ARM/SAMSUNG entry and can move into it. Also the S3C2416 gets a maintainer through the s3c24* wildcard - as it did not have one until now. Signed-off-by: Heiko Stuebner he...@sntech.de --- ping? Hi Heiko, Basically I'm ok on this but need to get the agreement from Ben Dooks. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 5/5] [CPUFREQ] EXYNOS4210: Add support ASV feature
MyungJoo Ham wrote:
Hello,
Hi,
I got the comments from Jaecheol Lee but his mail client has some problem so
I'm sending instead.
On Wed, Nov 2, 2011 at 9:43 PM, Kukjin Kim kgene@samsung.com wrote:
[]
+static void __init set_volt_table(void)
+{
+ unsigned int tmp, i, asv_group = 0;
+
+ tmp = __raw_readl(S5P_INFORM2);
As I've mentioned in the ASV patch thread, do we really need to use an
INFORM register simply to save the id of supported voltage ranges?
Why aren't we using an extern variable here? For example, extern int
asv_group_id; and define it at asv.h or somewhere else.
At reboot, we are going to init ASV driver and will get the ASV value
again; thus, we don't need to use such a preserving register anyway.
At suspend/resume, the value in RAM does not disappear and the IPL
does not care this value; thus, it is meaningless to use INFORM2 for
this value.
ASV feature had been implemented in bootloader hence inform register was
used to return the result value to cpufreq driver. If there is no problem to
use the inform register why don't you keep this manner.
(snip)
Thanks.
Best regards,
Kgene.
--
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SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH 4/5] [CPUFREQ] EXYNOS4210: Add DVS lock feature for other driver
MyungJoo Ham wrote: On Wed, Nov 2, 2011 at 9:43 PM, Kukjin Kim kgene@samsung.com wrote: From: Jongpill Lee boyko@samsung.com This patch adds DVS lock feature for other driver and pm/ reboot notifier to enhance stability. (snip) Same, following is from Jaecheol Lee. Except for the case of PM (suspend/reset), it appears that this feature is something that is meant to be supported by qos (linux/pm_qos.h). Couldn't we simply use the QoS feature to support locking frequency above some specific levels? With QoS, I guess the implementation becomes more general and straightforward. Although we will probably need to use CPU_DMA_LATENCY for this case, I think it isn't awefully difficult to use DMA-Latency as the metric. Our goal is removal of using this cpufreq lock, but now some device driver which is not fully optimized need to use this lock temporary. If there is no request of this API from device driver, we will remove this feature or support this feature with different manner as you mentioned. One concern about this is that we are hereby enforcing all the related device drivers stuck with Exynos4210 only unless others also use cpufreq_lock_ID and its friends. We recommend this feature in only rare instances (performance issue). After resolving that problem, the device driver which is using lock should be modified with removing lock. Actually, there is no device driver that using lock now. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/5] [CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq
MyungJoo Ham wrote: On Wed, Nov 2, 2011 at 9:42 PM, Kukjin Kim kgene@samsung.com wrote: From: Jongpill Lee boyko@samsung.com This patch removes code for bus on cpufreq because the code for bus frequency changing moves to busfreq driver. So code about bus on cpufreq is not necessary. Signed-off-by: Jongpill Lee boyko@samsung.com Signed-off-by: SangWook Ju sw...@samsung.com Signed-off-by: Jaecheol Lee jc@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com --- drivers/cpufreq/exynos4210-cpufreq.c | 174 +- 1 files changed, 1 insertions(+), 173 deletions(-) Cool! Now, it's compatible with the Exynos4210 bus devfreq driver. Are you going to upstream the busfreq in the devfreq framework (at /drivers/devfreq/) or do you want me to submit the Exynos4210 bus devfreq driver that is currently on http://git.infradead.org/users/kmpark/linux-2.6- samsung/shortlog/refs/heads/devfreq (drivers/devfreq/exynos4210_memorybus.c) Devfreq is a framework to support DVFS feature for non-CPU devices, which is at 3.2-next tree. I think, we need to talk about above so would be better to us if we could have a meeting. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 0/6] SPI platform device consolidation
Padmavathi Venna wrote: SPI platform devices are defined in respective machine folder of Samsung S3C64XX and S5P series SoCs.This patchset moves S3C64XX and S5P series of SPI platform devices to a common place plat-samsung. This patchset also creates SPI setup files for GPIO configurations and initializes the platform specific data in the corresponding machine file. Padmavathi Venna (6): ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung ARM: S3C64XX: Modified files for SPI consolidation work ARM: S5PC100: Modified files for SPI consolidation work. ARM: S5P64X0: Modified files for SPI consolidation work ARM: S5PV210: Modified files for SPI consolidation work The following patch make the corresponding SPI changes required for Wolfson Cragganmore S3C6410 variant. This patch is only build tested. ARM: S3C64XX: Modified according to SPI consolidation work. arch/arm/mach-s3c64xx/Kconfig|8 +- arch/arm/mach-s3c64xx/Makefile |2 +- arch/arm/mach-s3c64xx/dev-spi.c | 172 - arch/arm/mach-s3c64xx/include/mach/map.h |2 + arch/arm/mach-s3c64xx/mach-crag6410.c|9 + arch/arm/mach-s3c64xx/mach-smdk6410.c| 19 ++ arch/arm/mach-s3c64xx/setup-spi.c| 32 +++ arch/arm/mach-s5p64x0/Kconfig|7 +- arch/arm/mach-s5p64x0/Makefile |2 +- arch/arm/mach-s5p64x0/dev-spi.c | 218 - arch/arm/mach-s5p64x0/include/mach/map.h |3 + arch/arm/mach-s5p64x0/mach-smdk6440.c| 19 ++ arch/arm/mach-s5p64x0/mach-smdk6450.c| 19 ++ arch/arm/mach-s5p64x0/setup-spi.c| 42 arch/arm/mach-s5pc100/Kconfig|5 + arch/arm/mach-s5pc100/Makefile |2 +- arch/arm/mach-s5pc100/dev-spi.c | 220 -- arch/arm/mach-s5pc100/include/mach/map.h |3 + arch/arm/mach-s5pc100/mach-smdkc100.c| 31 +++ arch/arm/mach-s5pc100/setup-spi.c| 43 + arch/arm/mach-s5pv210/Kconfig|5 + arch/arm/mach-s5pv210/Makefile |2 +- arch/arm/mach-s5pv210/dev-spi.c | 169 - arch/arm/mach-s5pv210/include/mach/map.h |2 + arch/arm/mach-s5pv210/mach-smdkv210.c| 21 ++ arch/arm/mach-s5pv210/setup-spi.c| 36 arch/arm/plat-samsung/Kconfig| 14 ++- arch/arm/plat-samsung/devs.c | 112 +++ arch/arm/plat-samsung/include/plat/devs.h|8 +- arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 16 +- 30 files changed, 444 insertions(+), 799 deletions(-) delete mode 100644 arch/arm/mach-s3c64xx/dev-spi.c create mode 100644 arch/arm/mach-s3c64xx/setup-spi.c delete mode 100644 arch/arm/mach-s5p64x0/dev-spi.c create mode 100644 arch/arm/mach-s5p64x0/setup-spi.c delete mode 100644 arch/arm/mach-s5pc100/dev-spi.c create mode 100644 arch/arm/mach-s5pc100/setup-spi.c delete mode 100644 arch/arm/mach-s5pv210/dev-spi.c create mode 100644 arch/arm/mach-s5pv210/setup-spi.c Looks good to consolidate work, but it's merge window so will be back on this after that. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] ARM: EXYNOS4: Add SPI support
Padmavathi Venna wrote: Add SPI setup files for GPIO configurations. Add SPI clkdev support. Initialize SPI platform specific code in the machine file. Signed-off-by: Padmavathi Venna padm...@samsung.com --- arch/arm/mach-exynos4/Kconfig |5 ++ arch/arm/mach-exynos4/Makefile |1 + arch/arm/mach-exynos4/clock.c | 72 +- arch/arm/mach-exynos4/include/mach/irqs.h |3 + arch/arm/mach-exynos4/include/mach/map.h|6 ++ arch/arm/mach-exynos4/include/mach/spi-clocks.h | 16 + arch/arm/mach-exynos4/mach-smdkv310.c | 35 +++ arch/arm/mach-exynos4/setup-spi.c | 47 +++ 8 files changed, 155 insertions(+), 30 deletions(-) create mode 100644 arch/arm/mach-exynos4/include/mach/spi-clocks.h create mode 100644 arch/arm/mach-exynos4/setup-spi.c The mach-exynos4 directory will be re-organized in this merge window. So maybe you need to wait for v3.2-rc1. And I will be on this after that :) Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 0/3] ARM: S5P64X0: Add SDMMC support
Rajeshwari Shinde wrote: This patchset adds support for sdhci controller on S5P6440 and S5P6450. Since this patchset is based on mmc: sdhci-s3c: Rework platform data and add device tree support clk_type member has been removed from platform data. This patchset depends on the patchs: ARM: S5P64X0: Modified files for SPI consolidation work. mmc: sdhci-s3c: Rework platform data and add device tree support. Rajeshwari Shinde (3): ARM: S5P64X0: Add HSMMC setup for host Controller ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names ARM: S5P64X0: Enable SDHCI support arch/arm/mach-s5p64x0/Kconfig | 24 +++ arch/arm/mach-s5p64x0/Makefile |1 + arch/arm/mach-s5p64x0/clock-s5p6440.c | 72 +++ arch/arm/mach-s5p64x0/clock-s5p6450.c | 72 +++ arch/arm/mach-s5p64x0/cpu.c|9 +++ arch/arm/mach-s5p64x0/mach-smdk6440.c | 25 +++ arch/arm/mach-s5p64x0/mach-smdk6450.c | 26 +++- arch/arm/mach-s5p64x0/setup-sdhci-gpio.c | 104 arch/arm/plat-samsung/include/plat/sdhci.h | 42 +++ 9 files changed, 314 insertions(+), 61 deletions(-) create mode 100644 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c -- 1.7.4.4 Hi Rajeshwari, I need to sort out your this patches and Thomas' sdhci dt patches. And it's merge window, so will be back on this after that. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
