Re: [PATCH 2/2] ARM: Exynos: Register JPEG on nuri
Hi Andrzej,
Tried applying this patch on the for-next branch of Kukjin Kim's tree [1].
It fails to apply
error: patch failed: arch/arm/mach-exynos/Kconfig:274
[Patch 1/2] applies cleanly though.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
Regards
Sachin
On 21/02/2012, Andrzej Pietrasiewicz andrze...@samsung.com wrote:
ARM: Exynos: Register JPEG on nuri
Signed-off-by: Andrzej Pietrasiewicz andrze...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/mach-nuri.c |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 23b6971..189a212 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -274,6 +274,7 @@ config MACH_NURI
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_CSIS0
+ select S5P_DEV_JPEG
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
diff --git a/arch/arm/mach-exynos/mach-nuri.c
b/arch/arm/mach-exynos/mach-nuri.c
index b62e02b..be7bfd2 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1260,6 +1260,7 @@ static struct platform_device *nuri_devices[]
__initdata = {
i2c9_gpio,
s3c_device_adc,
s5p_device_g2d,
+ s5p_device_jpeg,
s3c_device_rtc,
s5p_device_mfc,
s5p_device_mfc_l,
--
1.7.0.4
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--
With warm regards,
Sachin
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Re: [PATCH V6 1/5] ARM: exynos: Add support AFTR mode on EXYNOS4210
On 23 February 2012 11:54, Rob Lee rob@linaro.org wrote:
static struct cpuidle_state exynos4_cpuidle_set[] = {
[0] = {
@@ -27,9 +47,17 @@ static struct cpuidle_state exynos4_cpuidle_set[] = {
.exit_latency = 1,
.target_residency = 10,
.flags = CPUIDLE_FLAG_TIME_VALID,
- .name = IDLE,
+ .name = C0,
.desc = ARM clock gating(WFI),
},
+ [1] = {
+ .enter = exynos4_enter_lowpower,
+ .exit_latency = 300,
+ .target_residency = 10,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = C1,
+ .desc = ARM power down,
+ },
};
It looks like you could make this __initdata because your are copying
this state data over to the cpuidle_driver object during
initialization.
Hi Rob,
This is a good suggestion. I tested it and this works fine.
Hi Mr kim,
Can this change be accommodated in the current patch series as below
or should i send a new patchset?
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -41,7 +41,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index);
-static struct cpuidle_state exynos4_cpuidle_set[] = {
+static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
[0] = {
.enter = exynos4_enter_idle,
.exit_latency = 1,
Thanks,
Amit Daniel
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -39,9 +67,100 @@ static struct cpuidle_driver exynos4_idle_driver = {
.owner = THIS_MODULE,
};
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos4_set_wakeupmask(void)
+{
+ __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+}
+
+static unsigned int g_pwr_ctrl, g_diag_reg;
+
+static void save_cpu_arch_register(void)
+{
+ /*read power control register*/
+ asm(mrc p15, 0, %0, c15, c0, 0 : =r(g_pwr_ctrl) : : cc);
+ /*read diagnostic register*/
+ asm(mrc p15, 0, %0, c15, c0, 1 : =r(g_diag_reg) : : cc);
+ return;
+}
+
+static void restore_cpu_arch_register(void)
+{
+ /*write power control register*/
+ asm(mcr p15, 0, %0, c15, c0, 0 : : r(g_pwr_ctrl) : cc);
+ /*write diagnostic register*/
+ asm(mcr p15, 0, %0, c15, c0, 1 : : r(g_diag_reg) : cc);
+ return;
+}
+
+static int idle_finisher(unsigned long flags)
+{
+ cpu_do_idle();
+ return 1;
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct timeval before, after;
+ int idle_time;
+ unsigned long tmp;
+
+ local_irq_disable();
+ do_gettimeofday(before);
+
+ exynos4_set_wakeupmask();
+
+ /* Set value of power down register for aftr mode */
+ exynos4_sys_powerdown_conf(SYS_AFTR);
+
+ __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+ __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+ save_cpu_arch_register();
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ cpu_pm_enter();
+ cpu_suspend(0, idle_finisher);
+
+ scu_enable(S5P_VA_SCU);
+ cpu_pm_exit();
+
+ restore_cpu_arch_register();
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ }
+
+ /* Clear wakeup state register */
+ __raw_writel(0x0, S5P_WAKEUP_STAT);
+
+ do_gettimeofday(after);
+
+ local_irq_enable();
+ idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+ (after.tv_usec - before.tv_usec);
+
+ dev-last_residency = idle_time;
+ return index;
+}
+
static int exynos4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
- int index)
+ int index)
{
struct timeval before, after;
[PATCH v3 0/2] regulator: add irq domain and device tree support for MAX8997
Changes since v2: - Atleast one voltage level has to be specfied for Buck 1/2/5 even if GPIO DVS option is not used (suggested by MyungJoo Ham). - Reworked the irq_domain support based the v5 of irq_domain generalization patches. MAX8997 is a multi-function device which includes support for regulators, rtc, battery charger and other sub-blocks. This patchset adds device tree support for the pmic (regulators) sub-block. The first patch adds irq domain support for the interrupts supported by max8997 mainly for removing the need to pass a irq_base from the platform code. The irq_base could not anyway be passed in case of device tree based instantiation. The reverse mapping method used is linear since the sub-drivers of max8997 has access to the max8997 irq_domain from which the linux irq number can be obtained. The second patch adds device tree support for max8997. This patch modifies both mfd and regulator portions of the max8997 code. This patchset is based on the following tree. http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next] with all patches merged from http://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git [for-next] http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next] and depends on the following patchset. [PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts. This patchset has been tested on Origen board. Thomas Abraham (2): mfd: add irq domain support for max8997 interrupts regulator: add device tree support for max8997 .../devicetree/bindings/regulator/max8997-pmic.txt | 134 +++ arch/arm/mach-exynos/mach-nuri.c |4 - arch/arm/mach-exynos/mach-origen.c |1 - drivers/mfd/max8997-irq.c | 60 + drivers/mfd/max8997.c | 73 ++- drivers/regulator/max8997.c| 139 +++- include/linux/mfd/max8997-private.h|4 +- include/linux/mfd/max8997.h|2 +- 8 files changed, 382 insertions(+), 35 deletions(-) create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/2] mfd: add irq domain support for max8997 interrupts
Add irq domain support for max8997 interrupts. The reverse mapping method
used is linear mapping since the sub-drivers of max8997 such as regulator
and charger drivers can use the max8997 irq_domain to get the linux irq
number for max8997 interrupts. All uses of irq_base in platform data and
max8997 driver private data are removed.
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/mach-nuri.c|4 --
arch/arm/mach-exynos/mach-origen.c |1 -
drivers/mfd/max8997-irq.c | 60 --
drivers/mfd/max8997.c |1 -
include/linux/mfd/max8997-private.h |4 ++-
include/linux/mfd/max8997.h |1 -
6 files changed, 38 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index a6b9162..1e9ba12 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1078,12 +1078,8 @@ static struct platform_device nuri_max8903_device = {
static void __init nuri_power_init(void)
{
int gpio;
- int irq_base = IRQ_GPIO_END + 1;
int ta_en = 0;
- nuri_max8997_pdata.irq_base = irq_base;
- irq_base += MAX8997_IRQ_NR;
-
gpio = EXYNOS4_GPX0(7);
gpio_request(gpio, AP_PMIC_IRQ);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
diff --git a/arch/arm/mach-exynos/mach-origen.c
b/arch/arm/mach-exynos/mach-origen.c
index 02c242e..328dadb 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata
origen_max8997_pdata = {
.buck1_gpiodvs = false,
.buck2_gpiodvs = false,
.buck5_gpiodvs = false,
- .irq_base = IRQ_GPIO_END + 1,
.ignore_gpiodvs_side_effect = true,
.buck125_default_idx = 0x0,
diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
index 09274cf..3d8c9d1 100644
--- a/drivers/mfd/max8997-irq.c
+++ b/drivers/mfd/max8997-irq.c
@@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
static const inline struct max8997_irq_data *
irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
{
- return max8997_irqs[irq - max8997-irq_base];
+ struct irq_data *data = irq_get_irq_data(irq);
+ return max8997_irqs[data-hwirq];
}
static void max8997_irq_mask(struct irq_data *data)
@@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
- int i;
+ int i, cur_irq;
ret = max8997_read_reg(max8997-i2c, MAX8997_REG_INTSRC, irq_src);
if (ret 0) {
@@ -269,8 +270,10 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
/* Report */
for (i = 0; i MAX8997_IRQ_NR; i++) {
- if (irq_reg[max8997_irqs[i].group] max8997_irqs[i].mask)
- handle_nested_irq(max8997-irq_base + i);
+ if (irq_reg[max8997_irqs[i].group] max8997_irqs[i].mask) {
+ cur_irq = irq_find_mapping(max8997-irq_domain, i);
+ handle_nested_irq(cur_irq);
+ }
}
return IRQ_HANDLED;
@@ -278,26 +281,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
int max8997_irq_resume(struct max8997_dev *max8997)
{
- if (max8997-irq max8997-irq_base)
- max8997_irq_thread(max8997-irq_base, max8997);
+ if (max8997-irq max8997-irq_domain)
+ max8997_irq_thread(0, max8997);
+ return 0;
+}
+
+static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ struct max8997_dev *max8997 = d-host_data;
+
+ irq_set_chip_data(irq, max8997);
+ irq_set_chip_and_handler(irq, max8997_irq_chip, handle_edge_irq);
+ irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+ set_irq_flags(irq, IRQF_VALID);
+#else
+ irq_set_noprobe(irq);
+#endif
return 0;
}
+static struct irq_domain_ops max8997_irq_domain_ops = {
+ .map = max8997_irq_domain_map,
+};
+
int max8997_irq_init(struct max8997_dev *max8997)
{
+ struct irq_domain *domain;
int i;
- int cur_irq;
int ret;
u8 val;
if (!max8997-irq) {
dev_warn(max8997-dev, No interrupt specified.\n);
- max8997-irq_base = 0;
- return 0;
- }
-
- if (!max8997-irq_base) {
- dev_err(max8997-dev, No interrupt base specified.\n);
return 0;
}
@@ -327,18 +344,11 @@ int max8997_irq_init(struct max8997_dev *max8997)
true : false;
}
- /* Register with genirq */
- for (i = 0; i MAX8997_IRQ_NR; i++) {
-
[PATCH v3 2/2] regulator: add device tree support for max8997
Add device tree based discovery support for max8997.
Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Grant Likely grant.lik...@secretlab.ca
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/regulator/max8997-pmic.txt | 134 +++
drivers/mfd/max8997.c | 72 ++-
drivers/regulator/max8997.c| 139 +++-
include/linux/mfd/max8997.h|1 +
4 files changed, 344 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
diff --git a/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
new file mode 100644
index 000..d282635
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
@@ -0,0 +1,134 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be maxim,max8997-pmic.
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+ units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+ for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+ units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+ for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+ units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+ for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+property should specify atleast one voltage level (which would be a
+safe operating voltage).
+
+If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+property is specified, then all the eigth voltage values for the
+'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+ the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+ - First interrupt specifier is for 'irq1' interrupt.
+ - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+ multiple bucks, changing the voltage value of one of the bucks may affect
+ that of another buck, which is the side effect of the change (set_voltage).
+ Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+ the possible 8 options selectable by the dvs gpios. The value of this
+ property should be between 0 and 7. If not specified or if out of range, the
+ default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+ for dvs. The format of the gpio specifier depends in the gpio controller.
+
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as below. Note: The 'n' in LDOn and BUCKn
+represents the LDO or BUCK number as per the datasheet of max8997.
+
+For LDO's:
+ LDOn {
+ standard regulator bindings here
+ };
+
+For BUCK's:
+ BUCKn {
+ standard regulator bindings here
+ };
+
+The bindings inside the regulator nodes use the standard regulator bindings
+which are documented elsewhere.
+
+Example:
+
+ max8997_pmic@66 {
+ compatible = maxim,max8997-pmic;
+ interrupt-parent = wakeup_eint;
+ reg = 0x66;
+ interrupts = 4 0, 3 0;
+
+ max8997,pmic-buck1-uses-gpio-dvs;
+ max8997,pmic-buck2-uses-gpio-dvs;
+ max8997,pmic-buck5-uses-gpio-dvs;
+
+
[PATCH v2] ARM: S3C24XX: Move s3c2443-clock.c to mach-s3c24xx
S3C-SoCs starting with the S3C2443 can share a lot of functionality.
The file can collect more common code of these SocS later on and
therefore gets a new name to reflect this future purpose.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
for completenes sake, the patch with -M format
arch/arm/mach-s3c24xx/Kconfig | 14 --
arch/arm/mach-s3c24xx/Makefile |4
.../common-s3c2443.c} | 17 +
arch/arm/plat-s3c24xx/Kconfig |6 --
arch/arm/plat-s3c24xx/Makefile |1 -
5 files changed, 29 insertions(+), 13 deletions(-)
rename arch/arm/{plat-s3c24xx/s3c2443-clock.c =
mach-s3c24xx/common-s3c2443.c} (95%)
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e537577..506d55b 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -41,7 +41,7 @@ config CPU_S3C2416
select CPU_ARM926T
select CPU_LLSERIAL_S3C2440
select SAMSUNG_CLKSRC
- select S3C2443_CLOCK
+ select S3C2443_COMMON
select S3C2416_DMA if S3C24XX_DMA
select S3C2416_PM if PM
help
@@ -76,7 +76,7 @@ config CPU_S3C2443
select CPU_ARM920T
select CPU_LLSERIAL_S3C2440
select SAMSUNG_CLKSRC
- select S3C2443_CLOCK
+ select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
help
Support for the S3C2443 SoC from the S3C24XX line
@@ -470,6 +470,16 @@ config SMDK2440_CPU2442
endif # CPU_S3C2440
+if CPU_S3C2443 || CPU_S3C2416
+
+config S3C2443_COMMON
+ bool
+ help
+ Common code for the S3C2443 and similar processors, which includes
+ the S3C2416 and S3C2450.
+
+endif # CPU_S3C2443 || CPU_S3C2416
+
if CPU_S3C2443
config S3C2443_DMA
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 08b44a3..876e5e5 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -34,6 +34,10 @@ obj-$(CONFIG_S3C2440_DMA)+= dma-s3c2440.o
obj-$(CONFIG_CPU_S3C2443) += s3c2443.o irq-s3c2443.o clock-s3c2443.o
obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
+# common code
+
+obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
+
#
# machine support
# following is ordered alphabetically by option text.
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c
b/arch/arm/mach-s3c24xx/common-s3c2443.c
similarity index 95%
rename from arch/arm/plat-s3c24xx/s3c2443-clock.c
rename to arch/arm/mach-s3c24xx/common-s3c2443.c
index 3633060..2745616 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -1,9 +1,18 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
+/*
+ * Common code for SoCs starting with the S3C2443
*
* Copyright (c) 2007, 2010 Simtec Electronics
* Ben Dooks b...@simtec.co.uk
*
- * S3C2443 Clock control suport - common code
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*/
#include linux/init.h
@@ -552,7 +561,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn
get_mpll)
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk(CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld
MHz, pclk %ld.%03ld MHz\n,
- (mpllcon S3C2443_PLLCON_OFF) ? off:on,
+ (mpllcon S3C2443_PLLCON_OFF) ? off : on,
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
@@ -567,7 +576,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn
get_mpll)
}
printk(CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n,
- (epllcon S3C2443_PLLCON_OFF) ? off:on,
+ (epllcon S3C2443_PLLCON_OFF) ? off : on,
print_mhz(clk_get_rate(clk_epll)),
print_mhz(clk_get_rate(clk_usb_bus)));
}
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 0c183fd..74f76e0 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -44,12 +44,6 @@ config S3C2410_CLOCK
Clock code for the S3C2410, and similar processors which
is currently includes the S3C2410, S3C2440, S3C2442.
-config S3C2443_CLOCK
- bool
- help
- Clock code for the S3C2443 and similar processors, which includes
- the S3C2416 and S3C2450.
-
config S3C24XX_DCLK
bool
help
diff --git a/arch/arm/plat-s3c24xx/Makefile
RE: S5P-TV: Warning for regulator unbalanced disables
Hi Tushar, On Thursday, February 23, 2012 5:43 AM You wrote: After implementing genpd framework for EXYNOS4, (Ref commit 91cfbd4 ARM: EXYNOS: Hook up power domains to generic power domain infrastructure in Kukjin's for-next branch), we are getting following warning from s5p-hdmi driver. The test was done on Origen board with code based on 3.3-rc4 and Kukjin's for-next branch. [1] [ cut here ] WARNING: at drivers/regulator/core.c:1503 _regulator_disable+0xf8/0x164() (snipped) Thanks for the report. We know about this issue. It is not really related to regulators nor s5p-tv driver. There is something broken (or misused) in the gen_pd driver and its implementation for Exysno4 hw. If you dig a bit into the problem You can observe the following call sequence on device probe: exynos4_genpd_enable() s5p_tv_runtime_disable() exynos4_genpd_disable() So the call to s5p_tv_runtime_disable is not balanced with s5p_tv_runtime_resume() what causes the error you have posted. It looks that runtime pw framework makes some wrong assumptions about the state of the device once power domain has been registered. The same problem appears for s5p-fimc and s5p-mfc, although it is not observed as kernel error, but these devices also suffers from it - their clocks get disabled one time too much so they do not operate correctly. We are investigating this issue further. Best regards -- Marek Szyprowski Samsung Poland RD Center The above message is intended solely for the named addressee and may contain trade secret, industrial technology or privileged and confidential information otherwise protected under applicable law. Any unauthorized dissemination, distribution, copying or use of the information contained in this communication is strictly prohibited. If you have received this communication in error, please notify sender by email and delete this communication immediately. Powyższa wiadomość przeznaczona jest wyłącznie dla adresata niniejszej wiadomości i może zawierać informacje będące tajemnicą handlową, tajemnicą przedsiębiorstwa oraz informacje o charakterze poufnym chronione obowiązującymi przepisami prawa. Jakiekolwiek nieuprawnione ich rozpowszechnianie, dystrybucja, kopiowanie lub użycie informacji zawartych w powyższej wiadomości jest zabronione. Jeśli otrzymałeś powyższą wiadomość omyłkowo, uprzejmie proszę poinformuj o tym fakcie drogą mailową nadawcę tej wiadomości oraz niezwłocznie usuń powyższą wiadomość ze swojego komputera.
[PATCH v2 0/5] [SCSI] ufshcd: UFS Host Controller Driver
From: Santosh Yaraganavi santos...@gmail.com UFS: Universal Flash Storage is a storage specification for flash devices. It is aimed to provide a universal storage interface for both embedded and removable flash memory based storage in mobile devices such as smart phones and tablet computers. The specification is defined by JEDEC Solid State Technology Association. UFS is based on MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the physical layer and MIPI Unipro as the link layer. The main goals of UFS is to provide, - Optimized performance: For UFS version 1.0 and 1.1 the target performance is as follows, Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps) Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps) Future version of the standard, Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps) - Low power consumption - High random IOPs and low latency UFS Architecture Overview: UFS has a layered communication architecture which is based on SCSI SAM-5 architectural model. UFS communication architecture consists of following layers, * Application Layer: It is composed of UFS command set layer(UCS), Task Manager and Device manager. The UFS interface is designed to be protocol agnostic, however SCSI has been selected as a baseline protocol for versions 1.0 and 1.1 of UFS protocol layer. UFS supports subset of SCSI commands defined by SPC-4 and SBC-3. - UCS: It handles SCSI commands supported by UFS specification. - Task manager: It handles task management functions defined by the UFS which are meant for command queue control. - Device manager: It handles device level operations and device configuration operations. Device level operations mainly involve device power management operations and commands to Interconnect layers. Device level configurations involve handling of query requests which are used to modify and retrieve configuration information of the device. * UFS Transport Protocol(UTP) layer: UTP layer provides services for the higher layers through Service Access Points. UTP defines 3 service access points for higher layers. - UDM_SAP: Device manager service access point is exposed to device manager for device level operations. These device level operations are done through query requests. - UTP_CMD_SAP: Command service access point is exposed to UFS command set layer(UCS) to transport commands. - UTP_TM_SAP: Task management service access point is exposed to task manager to transport task management functions. UTP transports messages through UFS protocol information unit(UPIU). * UFS Interconnect Layer(UIC): This is the lowest layer of UFS layered architecture. It handles connection between UFS host and UFS device. UIC consists of MIPI UniPro and MIPI M-PHY. UIC provides 2 service access points to upper layer, - UIC_SAP: To transport UPIU between UFS host and UFS device. - UIO_SAP: To issue commands to Unipro layers. UFSHCD: The UFS host controller driver is based on Linux SCSI Framework. UFSHCD is a low level device driver which acts as an interface between SCSI Midlayer and PCIe based UFS host controllers. The current UFSHCD implementation supports following functionality, - UFS controller initialization: The initialization module brings UFS host controller to active state and prepares the controller to transfer commands/response between UFSHCD and UFS device. - UTP Transfer requests: Transfer request handling module of UFSHCD receives SCSI commands from SCSI Midlayer, forms UPIUs and issues the UPIUs to UFS Host controller. Also, the module decodes responses received from UFS host controller in the form of UPIUs and intimates the SCSI Midlayer of the status of the command. - UFS error handling: Error handling module handles Host controller fatal errors, Device fatal errors and UIC interconnect layer related errors. - SCSI Error handling: This is done through UFSHCD SCSI error handling routines registered with SCSI Midlayer. Examples of some of the error handling commands issues by SCSI Midlayer are Abort task, Lun reset and host reset. UFSHCD Routines to perform these tasks are registered with SCSI Midlayer through .eh_abort_handler, .eh_device_reset_handler and .eh_host_reset_handler. In this version of UFSHCD Query requests and power management functionality are not implemented. This patchset is successfully applied on 3.3-rc4 UFS Specifications can be found at, UFS - http://www.jedec.org/sites/default/files/docs/JESD220.pdf UFSHCI - http://www.jedec.org/sites/default/files/docs/JESD223.pdf Santosh Yaraganavi (5): [SCSI] ufshcd: UFS Host controller driver [SCSI] ufshcd: UFS UTP Transfer requests handling [SCSI] ufshcd: UFSHCI error handling [SCSI] ufshcd: SCSI error handling Documentation: UFS Host Controller Driver Documentation/scsi/00-INDEX |2 + Documentation/scsi/ufs.txt | 89 ++
[PATCH v2 1/5] [SCSI] ufshcd: UFS Host controller driver
From: Santosh Yaraganavi santos...@gmail.com This patch adds support for Universal Flash Storage(UFS) host controllers. The UFS host controller driver includes host controller initialization method. The Initialization process involves following steps: - Initiate UFS Host Controller initialization process by writing to Host controller enable register - Configure UFS Host controller registers with host memory space datastructure offsets. - Unipro link startup procedure - Check for connected device - Configure UFS host controller to process requests - Enable required interrupts - Configure interrupt aggregation Signed-off-by: Santosh Yaraganavi santos...@gmail.com Signed-off-by: Vinayak Holikatti vinholika...@gmail.com Reviewed-by: Arnd Bergmann a...@linaro.org Reviewed-by: Vishak G visha...@samsung.com Reviewed-by: Girish K S girish.shivananja...@linaro.org --- v1 - v2: - ufshcd_memory_alloc(): remove explicit memory alignment. - Re-use ufshcd_free_hba_memory() in ufshcd_memory_alloc - ufshcd_make_hba_operational(): Remove -EINVAL and use -ENXIO, -EIO - Remove NULL macro definition. - Remove macros BYTES_TO_DWORDS and UFSHCD_MMIO_BASE. - ufshcd_controller_enable(): send controller to reset state only if the controller is active. - ufshcd_intr(): Use spin_lock() instead of spin_lock_irqsave(). - ufshcd_suspend/ufshcd_resume: add TODO comments. - ufshcd_set_dma_mask(): Change DMA mask setting to 64/32 based on controller capability. - Change conditional statement to match kernel coding style, Ex: if (constant == variable) to if (variable == constant) if (NULL != pointer) to if (pointer) drivers/scsi/Kconfig |1 + drivers/scsi/Makefile |1 + drivers/scsi/ufs/Kconfig | 49 ++ drivers/scsi/ufs/Makefile |2 + drivers/scsi/ufs/ufs.h| 207 + drivers/scsi/ufs/ufshcd.c | 1092 + drivers/scsi/ufs/ufshci.h | 376 7 files changed, 1728 insertions(+), 0 deletions(-) create mode 100644 drivers/scsi/ufs/Kconfig create mode 100644 drivers/scsi/ufs/Makefile create mode 100644 drivers/scsi/ufs/ufs.h create mode 100644 drivers/scsi/ufs/ufshcd.c create mode 100644 drivers/scsi/ufs/ufshci.h diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 16570aa..477a91a 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -619,6 +619,7 @@ config SCSI_ARCMSR source drivers/scsi/megaraid/Kconfig.megaraid source drivers/scsi/mpt2sas/Kconfig +source drivers/scsi/ufs/Kconfig config SCSI_HPTIOP tristate HighPoint RocketRAID 3xxx/4xxx Controller support diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 2b88749..c832974 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -108,6 +108,7 @@ obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/ obj-$(CONFIG_MEGARAID_SAS) += megaraid/ obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas/ +obj-$(CONFIG_SCSI_UFSHCD) += ufs/ obj-$(CONFIG_SCSI_ACARD) += atp870u.o obj-$(CONFIG_SCSI_SUNESP) += esp_scsi.o sun_esp.o obj-$(CONFIG_SCSI_GDTH)+= gdth.o diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig new file mode 100644 index 000..8f27f9d --- /dev/null +++ b/drivers/scsi/ufs/Kconfig @@ -0,0 +1,49 @@ +# +# Kernel configuration file for the UFS Host Controller +# +# This code is based on drivers/scsi/ufs/Kconfig +# Copyright (C) 2011 Samsung Samsung India Software Operations +# +# Santosh Yaraganavi santosh...@samsung.com +# Vinayak Holikatti h.vina...@samsung.com + +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 +# of the License, or (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# NO WARRANTY +# THE PROGRAM IS PROVIDED ON AN AS IS BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT +# LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, +# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is +# solely responsible for determining the appropriateness of using and +# distributing the Program and assumes all risks associated with its +# exercise of rights under this Agreement, including but not limited to +# the risks and costs of program errors, damage to or loss of data, +# programs or equipment, and unavailability or interruption of operations. + +# DISCLAIMER OF LIABILITY +# NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY +#
[PATCH v2 2/5] [SCSI] ufshcd: UFS UTP Transfer requests handling
From: Santosh Yaraganavi santos...@gmail.com
This patch adds support for Transfer request handling.
ufshcd includes following implementations:
- SCSI queuecommand
- Compose UPIU(UFS Protocol information unit)
- Issue commands to UFS host controller
- Handle completed commands
Signed-off-by: Santosh Yaraganavi santos...@gmail.com
Signed-off-by: Vinayak Holikatti vinholika...@gmail.com
Reviewed-by: Arnd Bergmann a...@linaro.org
Reviewed-by: Vishak G visha...@samsung.com
Reviewed-by: Girish K S girish.shivananja...@linaro.org
---
v1 - v2:
- Use bitops.h defined functions to perform bit operations.
Ex: set_bit(), __set_bit, clear_bit...
- ufshcd_map_sg(): remove BUG_ON on scsi_dma_map() failure
and return error value.
- ufshcd_compose_upiu(): add missing break in switch case,
remove unused parameter hba.
- ufshcd_slave_alloc(): set sdev-use_10_for_ms = 1, since UFS
does not support MODE_SENSE_6.
- ufshcd_scsi_cmd_status(): add missing break in switch case.
Add ufshcd_adjust_lun_qdepth to adjust LUN queue depth
if SAM_STAT_TASK_SET_FULL is received from the device.
- ufshcd_transfer_rsp_status(): combine cases with same error code.
drivers/scsi/ufs/ufshcd.c | 500 +
1 files changed, 500 insertions(+), 0 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index abf617e..e4335f5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -63,6 +63,7 @@
#include scsi/scsi.h
#include scsi/scsi_cmnd.h
#include scsi/scsi_host.h
+#include scsi/scsi_tcq.h
#include scsi/scsi_dbg.h
#include ufs.h
@@ -75,6 +76,8 @@ enum {
UFSHCD_MAX_CHANNEL = 0,
UFSHCD_MAX_ID = 1,
UFSHCD_MAX_LUNS = 8,
+ UFSHCD_CMD_PER_LUN = 32,
+ UFSHCD_CAN_QUEUE= 32,
};
/* UFSHCD states */
@@ -128,6 +131,7 @@ struct uic_command {
* @host: Scsi_Host instance of the driver
* @pdev: PCI device handle
* @lrb: local reference block
+ * @outstanding_reqs: Bits representing outstanding transfer requests
* @capabilities: UFS Controller Capabilities
* @nutrs: Transfer Request Queue depth supported by controller
* @nutmrs: Task Management Queue depth supported by controller
@@ -154,6 +158,8 @@ struct ufs_hba {
struct ufshcd_lrb *lrb;
+ unsigned long outstanding_reqs;
+
u32 capabilities;
int nutrs;
int nutmrs;
@@ -174,12 +180,28 @@ struct ufs_hba {
* @ucd_cmd_ptr: UCD address of the command
* @ucd_rsp_ptr: Response UPIU address for this command
* @ucd_prdt_ptr: PRDT address of the command
+ * @cmd: pointer to SCSI command
+ * @sense_buffer: pointer sense buffer address of the SCSI command
+ * @sense_bufflen: Length of the sense buffer
+ * @scsi_status: SCSI status of the command
+ * @command_type: SCSI, UFS, Query.
+ * @task_tag: Task tag of the command
+ * @lun: LUN of the command
*/
struct ufshcd_lrb {
struct utp_transfer_req_desc *utr_descriptor_ptr;
struct utp_upiu_cmd *ucd_cmd_ptr;
struct utp_upiu_rsp *ucd_rsp_ptr;
struct ufshcd_sg_entry *ucd_prdt_ptr;
+
+ struct scsi_cmnd *cmd;
+ u8 *sense_buffer;
+ unsigned int sense_bufflen;
+ int scsi_status;
+
+ int command_type;
+ int task_tag;
+ unsigned int lun;
};
/**
@@ -206,6 +228,18 @@ static inline int ufshcd_is_device_present(u32 reg_hcs)
}
/**
+ * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
+ * @lrb: pointer to local command reference block
+ *
+ * This function is used to get the OCS field from UTRD
+ * Returns the OCS field in the UTRD
+ */
+static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
+{
+ return lrbp-utr_descriptor_ptr-header.dword_2 MASK_OCS;
+}
+
+/**
* ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
* @reg: Register value of host controller status
*
@@ -273,6 +307,36 @@ static inline void ufshcd_free_hba_memory(struct ufs_hba
*hba)
}
/**
+ * ufshcd_is_valid_req_rsp - checks if controller TR response is valid
+ * @ucd_rsp_ptr: pointer to response UPIU
+ *
+ * This function checks the response UPIU for valid transaction type in
+ * response field
+ * Returns 0 on success, non-zero on failure
+ */
+static inline int
+ufshcd_is_valid_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
+{
+ return ((be32_to_cpu(ucd_rsp_ptr-header.dword_0) 24) ==
+UPIU_TRANSACTION_RESPONSE) ? 0 :
+ (DID_ERROR 16 |
+ COMMAND_COMPLETE 8);
+}
+
+/**
+ * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
+ * @ucd_rsp_ptr: pointer to response UPIU
+ *
+ * This function gets the response status and scsi_status from response UPIU
+ * Returns the response result code.
+ */
+static inline int
+ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp
[PATCH v2 4/5] [SCSI] ufshcd: SCSI error handling
From: Santosh Yaraganavi santos...@gmail.com
UFSHCD SCSI error handling includes following implementations,
- Abort task
- Device reset
- Host reset
Signed-off-by: Santosh Yaraganavi santos...@gmail.com
Signed-off-by: Vinayak Holikatti vinholika...@gmail.com
Reviewed-by: Arnd Bergmann a...@linaro.org
Reviewed-by: Vishak G visha...@samsung.com
Reviewed-by: Girish K S girish.shivananja...@linaro.org
---
v1 - v2:
- Change task management function return value to SUCCESS/FAILED,
SCSI midlayer expects SUCCESS/FAILED return value for
error handling routines.
Ex: .eh_host_reset_handler, eh_abort_handler...
- ufshcd_tmc_handler(): use wake_up_interruptible() outside for loop
to wake up all the waiting threads at once.
Change hba-tm_condition[] to hba-tm_condition bitmask.
- ufshcd_abort(): add missing spin_unlock_irqrestore().
drivers/scsi/ufs/ufshcd.c | 298 -
1 files changed, 297 insertions(+), 1 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 1c6a9ed..856dbc1 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -65,6 +65,7 @@
#include scsi/scsi_host.h
#include scsi/scsi_tcq.h
#include scsi/scsi_dbg.h
+#include scsi/scsi_eh.h
#include ufs.h
#include ufshci.h
@@ -131,11 +132,14 @@ struct uic_command {
* @host: Scsi_Host instance of the driver
* @pdev: PCI device handle
* @lrb: local reference block
+ * @outstanding_tasks: Bits representing outstanding task requests
* @outstanding_reqs: Bits representing outstanding transfer requests
* @capabilities: UFS Controller Capabilities
* @nutrs: Transfer Request Queue depth supported by controller
* @nutmrs: Task Management Queue depth supported by controller
* @active_uic_cmd: handle of active UIC command
+ * @ufshcd_tm_wait_queue: wait queue for task management
+ * @tm_condition: condition variable for task management
* @ufshcd_state: UFSHCD states
* @int_enable_mask: Interrupt Mask Bits
* @uic_workq: Work queue for UIC completion handling
@@ -160,6 +164,7 @@ struct ufs_hba {
struct ufshcd_lrb *lrb;
+ unsigned long outstanding_tasks;
unsigned long outstanding_reqs;
u32 capabilities;
@@ -168,6 +173,8 @@ struct ufs_hba {
u32 ufs_version;
struct uic_command active_uic_cmd;
+ wait_queue_head_t ufshcd_tm_wait_queue;
+ unsigned long tm_condition;
u32 ufshcd_state;
u32 int_enable_mask;
@@ -246,6 +253,42 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb
*lrbp)
}
/**
+ * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
+ * @task_req_descp: pointer to utp_task_req_desc structure
+ *
+ * This function is used to get the OCS field from UTMRD
+ * Returns the OCS field in the UTMRD
+ */
+static inline int
+ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
+{
+ return task_req_descp-header.dword_2 MASK_OCS;
+}
+
+/**
+ * ufshcd_is_tmq_full - checks if the task management slots are full
+ * @hba: per adapter instance
+ *
+ * Returns maximum number of task management request slots in case of
+ * task management queue full or returns the free slot number
+ */
+static inline int ufshcd_is_tmq_full(struct ufs_hba *hba)
+{
+ return find_first_zero_bit(hba-outstanding_tasks, hba-nutmrs);
+}
+
+/**
+ * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ writel(~(1 pos),
+ (hba-mmio_base + REG_UTP_TRANSFER_REQ_LIST_CLEAR));
+}
+
+/**
* ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
* @reg: Register value of host controller status
*
@@ -1038,8 +1081,9 @@ static int ufshcd_do_reset(struct ufs_hba *hba)
}
}
- /* clear outstanding request bit maps */
+ /* clear outstanding request/task bit maps */
hba-outstanding_reqs = 0;
+ hba-outstanding_tasks = 0;
/* start the initialization process */
if (ufshcd_initialize_hba(hba)) {
@@ -1091,6 +1135,47 @@ static void ufshcd_slave_destroy(struct scsi_device
*sdev)
}
/**
+ * ufshcd_task_req_compl - handle task management request completion
+ * @hba: per adapter instance
+ * @index: index of the completed request
+ *
+ * Returns SUCCESS/FAILED
+ */
+static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index)
+{
+ struct utp_task_req_desc *task_req_descp;
+ struct utp_upiu_task_rsp *task_rsp_upiup;
+ unsigned long flags;
+ int ocs_value;
+ int task_result;
+
+ spin_lock_irqsave(hba-host-host_lock, flags);
+
+ /* Clear completed tasks from outstanding_tasks */
+ __clear_bit(index, hba-outstanding_tasks);
+
+ task_req_descp = hba-utmrdl_base_addr;
+ ocs_value =
[PATCH v2 5/5] Documentation: UFS Host Controller Driver
From: Santosh Yaraganavi santos...@gmail.com The document provides Universal Flash Storage(UFS) and UFS host controller driver overview. Signed-off-by: Santosh Yaraganavi santos...@gmail.com Reviewed-by: Vishak G visha...@samsung.com --- Documentation/scsi/00-INDEX |2 + Documentation/scsi/ufs.txt | 89 +++ 2 files changed, 91 insertions(+), 0 deletions(-) create mode 100644 Documentation/scsi/ufs.txt diff --git a/Documentation/scsi/00-INDEX b/Documentation/scsi/00-INDEX index b48ded5..b7dd650 100644 --- a/Documentation/scsi/00-INDEX +++ b/Documentation/scsi/00-INDEX @@ -94,3 +94,5 @@ sym53c8xx_2.txt - info on second generation driver for sym53c8xx based adapters tmscsim.txt - info on driver for AM53c974 based adapters +ufs.txt + - info on Universal Flash Storage(UFS) and UFS host controller driver. diff --git a/Documentation/scsi/ufs.txt b/Documentation/scsi/ufs.txt new file mode 100644 index 000..bd797b9 --- /dev/null +++ b/Documentation/scsi/ufs.txt @@ -0,0 +1,89 @@ +UFS: +Universal Flash Storage is a storage specification for flash devices. +It is aimed to provide a universal storage interface for both +embedded and removable flash memory based storage in mobile +devices such as smart phones and tablet computers. The specification +is defined by JEDEC Solid State Technology Association. UFS is based +on MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the +physical layer and MIPI Unipro as the link layer. + +The main goals of UFS is to provide, +- Optimized performance: + For UFS version 1.0 and 1.1 the target performance is as follows, + Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps) + Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps) + Future version of the standard, + Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps) +- Low power consumption +- High random IOPs and low latency + +UFS Architecture Overview: +UFS has a layered communication architecture which is based on SCSI +SAM-5 architectural model. + +UFS communication architecture consists of following layers, + +* Application Layer: It is composed of UFS command set layer(UCS), + Task Manager and Device manager. The UFS interface is designed to be + protocol agnostic, however SCSI has been selected as a baseline + protocol for versions 1.0 and 1.1 of UFS protocol layer. + UFS supports subset of SCSI commands defined by SPC-4 and SBC-3. + - UCS: It handles SCSI commands supported by UFS specification. + - Task manager: It handles task management functions defined by the +UFS which are meant for command queue control. + - Device manager: It handles device level operations and device +configuration operations. Device level operations mainly involve +device power management operations and commands to Interconnect +layers. Device level configurations involve handling of query +requests which are used to modify and retrieve configuration +information of the device. + +* UFS Transport Protocol(UTP) layer: UTP layer provides services for + the higher layers through Service Access Points. UTP defines 3 + service access points for higher layers. + - UDM_SAP: Device manager service access point is exposed to device +manager for device level operations. These device level operations +are done through query requests. + - UTP_CMD_SAP: Command service access point is exposed to UFS command +set layer(UCS) to transport commands. + - UTP_TM_SAP: Task management service access point is exposed to task +manager to transport task management functions. + UTP transports messages through UFS protocol information unit(UPIU). + +* UFS Interconnect Layer(UIC): This is the lowest layer of UFS layered + architecture. It handles connection between UFS host and UFS device. + UIC consists of MIPI UniPro and MIPI M-PHY. UIC provides 2 service + access points to upper layer, + - UIC_SAP: To transport UPIU between UFS host and UFS device. + - UIO_SAP: To issue commands to Unipro layers. + +UFSHCD: +The UFS host controller driver is based on Linux SCSI Framework. +UFSHCD is a low level device driver which acts as an interface between +SCSI Midlayer and PCIe based UFS host controllers. + +The current UFSHCD implementation supports following functionality, +- UFS controller initialization: The initialization module brings UFS + host controller to active state and prepares the controller to + transfer commands/response between UFSHCD and UFS device. +- UTP Transfer requests: Transfer request handling module of UFSHCD + receives SCSI commands from SCSI Midlayer, forms UPIUs and issues + the UPIUs to UFS Host controller. Also, the module decodes responses + received from UFS host controller in the form of UPIUs and intimates + the SCSI Midlayer of the status of the command. +- UFS error handling: Error handling module handles Host controller + fatal errors, Device fatal errors and UIC
[PATCH v2 3/5] [SCSI] ufshcd: UFSHCI error handling
From: Santosh Yaraganavi santos...@gmail.com
UFSHCI error handling includes support for:
- UFS host controller errors
- System bus errors
- Unipro errors
Signed-off-by: Santosh Yaraganavi santos...@gmail.com
Signed-off-by: Vinayak Holikatti vinholika...@gmail.com
Reviewed-by: Arnd Bergmann a...@linaro.org
Reviewed-by: Vishak G visha...@samsung.com
Reviewed-by: Girish K S girish.shivananja...@linaro.org
---
v1 - v2:
- ufshcd_do_reset(): change return value to SUCCESS/FAILED,
since the function can also be called from UFSHCD registered
SCSI midlayer error handling routines.
Ex: .eh_host_reset_handler which expects return value
SUCCESS/FAILED
- ufshcd_do_reset(): aquire spin_lock_irqsave only for
instructions which share common data structure.
drivers/scsi/ufs/ufshcd.c | 97 +
1 files changed, 97 insertions(+), 0 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e4335f5..1c6a9ed 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -139,6 +139,8 @@ struct uic_command {
* @ufshcd_state: UFSHCD states
* @int_enable_mask: Interrupt Mask Bits
* @uic_workq: Work queue for UIC completion handling
+ * @feh_workq: Work queue for fatal controller error handling
+ * @errors: HBA errors
*/
struct ufs_hba {
void __iomem *mmio_base;
@@ -172,6 +174,10 @@ struct ufs_hba {
/* Work Queues */
struct work_struct uic_workq;
+ struct work_struct feh_workq;
+
+ /* HBA Errors */
+ u32 errors;
};
/**
@@ -896,6 +902,9 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba)
/* Configure interrupt aggregation */
ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
+ if (hba-ufshcd_state == UFSHCD_STATE_RESET)
+ scsi_unblock_requests(hba-host);
+
hba-ufshcd_state = UFSHCD_STATE_OPERATIONAL;
scsi_scan_host(hba-host);
out:
@@ -997,6 +1006,51 @@ static int ufshcd_initialize_hba(struct ufs_hba *hba)
}
/**
+ * ufshcd_do_reset - reset the host controller
+ * @hba: per adapter instance
+ *
+ * Returns SUCCESS/FAILED
+ */
+static int ufshcd_do_reset(struct ufs_hba *hba)
+{
+ struct ufshcd_lrb *lrbp;
+ unsigned long flags;
+ int tag;
+
+ /* block commands from midlayer */
+ scsi_block_requests(hba-host);
+
+ spin_lock_irqsave(hba-host-host_lock, flags);
+ hba-ufshcd_state = UFSHCD_STATE_RESET;
+
+ /* send controller to reset state */
+ ufshcd_hba_stop(hba);
+ spin_unlock_irqrestore(hba-host-host_lock, flags);
+
+ /* abort outstanding commands */
+ for (tag = 0; tag hba-nutrs; tag++) {
+ if (test_bit(tag, hba-outstanding_reqs)) {
+ lrbp = hba-lrb[tag];
+ scsi_dma_unmap(lrbp-cmd);
+ lrbp-cmd-result = DID_RESET 16;
+ lrbp-cmd-scsi_done(lrbp-cmd);
+ lrbp-cmd = NULL;
+ }
+ }
+
+ /* clear outstanding request bit maps */
+ hba-outstanding_reqs = 0;
+
+ /* start the initialization process */
+ if (ufshcd_initialize_hba(hba)) {
+ dev_err(hba-pdev-dev,
+ Reset: Controller initialization failed\n);
+ return FAILED;
+ }
+ return SUCCESS;
+}
+
+/**
* ufshcd_slave_alloc - handle initial SCSI device configurations
* @sdev: pointer to SCSI device
*
@@ -1248,12 +1302,54 @@ static void ufshcd_uic_cc_handler (struct work_struct
*work)
}
/**
+ * ufshcd_fatal_err_handler - handle fatal errors
+ * @hba: per adapter instance
+ */
+static void ufshcd_fatal_err_handler(struct work_struct *work)
+{
+ struct ufs_hba *hba;
+ hba = container_of(work, struct ufs_hba, feh_workq);
+
+ /* check if reset is already in progress */
+ if (hba-ufshcd_state != UFSHCD_STATE_RESET)
+ ufshcd_do_reset(hba);
+}
+
+/**
+ * ufshcd_err_handler - Check for fatal errors
+ * @work: pointer to a work queue structure
+ */
+static void ufshcd_err_handler(struct ufs_hba *hba)
+{
+ u32 reg;
+
+ if (hba-errors INT_FATAL_ERRORS)
+ goto fatal_eh;
+
+ if (hba-errors UIC_ERROR) {
+
+ reg = readl(hba-mmio_base +
+ REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
+ if (reg UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
+ goto fatal_eh;
+ }
+ return;
+fatal_eh:
+ hba-ufshcd_state = UFSHCD_STATE_ERROR;
+ schedule_work(hba-feh_workq);
+}
+
+/**
* ufshcd_sl_intr - Interrupt service routine
* @hba: per adapter instance
* @intr_status: contains interrupts generated by the controller
*/
static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
{
+ hba-errors = UFSHCD_ERROR_MASK intr_status;
+ if (hba-errors)
+
