Re: [PATCH 3/7] mmc: dw_mmc: add device tree support
Hi,
On 5/2/12, Thomas Abraham thomas.abra...@linaro.org wrote:
Add device tree based discovery support.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 85 +
drivers/mmc/host/dw_mmc-pltfm.c| 24 +++
drivers/mmc/host/dw_mmc.c | 181
+++-
drivers/mmc/host/dw_mmc.h | 10 +
include/linux/mmc/dw_mmc.h |2 +
5 files changed, 296 insertions(+), 6 deletions(-)
create mode 100644
Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
new file mode 100644
index 000..c1ed70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
@@ -0,0 +1,85 @@
+* Synopsis Designware Mobile Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to
interface
+a SoC with storage medium such as eMMC or SD/MMC cards.
+
+Required Properties:
+
+* compatible: should be one of the following
+ - synopsis,dw-mshc: for controllers compliant with synopsis dw-mshc.
I googled the Synopsis Designware Mobile Storage Host Controller and
Synopsis released it as this name. but still I like the 'dw-mmc'
instead of'dw-mshc'.
+
+* reg: physical base address of the dw-mshc controller and size of its
memory
+ region.
+
+* interrupts: interrupt specifier for the controller. The format and value
of
+ the interrupt specifier depends on the interrupt parent for the
controller.
+
+# Slots: The slot specific information are contained within child-nodes
with
+ each child-node representing a supported slot. There should be atleast
one
+ child node representing a card slot. The name of the slot child node
should
+ be 'slot{n}' where n is the unique number of the slot connnected to the
+ controller. The following are optional properties which can be included
in
+ the slot child node.
+
+ * bus-width: specifies the width of the data bus connected from the
+ controller to the card slot. The value should be 1, 4 or 8. In case
+ this property is not specified, a default value of 1 is assumed for
+ this property.
+
+ * cd-gpios: specifies the card detect gpio line. The format of the
+ gpio specifier depends on the gpio controller.
+
+ * wp-gpios: specifies the write protect gpio line. The format of the
+ gpio specifier depends on the gpio controller.
+
+ * gpios: specifies a list of gpios used for command, clock and data
+ bus. The first gpio is the command line and the second gpio is the
+ clock line. The rest of the gpios (depending on the bus-width
+ property) are the data lines in no particular order. The format of
+ the gpio specifier depends on the gpio controller.
+
+Optional properties:
+
+* fifo-depth: The maximum size of the tx/rx fifo's. If this property is
not
+ specified, the default value of the fifo size is determined from the
+ controller registers.
+
+* card-detect-delay: Delay in milli-seconds before detecting card after
card
+ insert event. The default value is 0.
+
+* supports-highspeed: Enables support for high speed cards (upto 50MHz)
+
+* card-detection-broken: The card detection functionality is not available
on
+ any of the slots.
+
+* no-write-protect: The write protect pad of the controller is not
connected
+ to the write protect pin on the slot.
+
+Example:
+
+ The MSHC controller node can be split into two portions, SoC specific
and
+ board specific portions as listed below.
+
+ dwmmc0@1220 {
+ compatible = synopsis,dw-mshc;
+ reg = 0x1220 0x1000;
+ interrupts = 0 75 0;
+ };
+
+ dwmmc0@1220 {
+ supports-highspeed;
+ card-detection-broken;
+ no-write-protect;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+
+ slot0 {
+ bus-width = 8;
+ cd-gpios = gpc0 2 2 3 3;
+ gpios = gpc0 0 2 0 3, gpc0 1 2 0 3,
+ gpc1 0 2 3 3, gpc1 1 2 3 3,
+ gpc1 2 2 3 3, gpc1 3 2 3 3,
+ gpc0 3 2 3 3, gpc0 4 2 3 3,
+ gpc0 5 2 3 3, gpc0 6 2 3 3;
+ };
+ };
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c
b/drivers/mmc/host/dw_mmc-pltfm.c
index 92ec3eb..2b2c9bd 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -19,8 +19,24 @@
#include linux/mmc/host.h
#include linux/mmc/mmc.h
#include linux/mmc/dw_mmc.h
+#include linux/of.h
#include dw_mmc.h
+#ifdef CONFIG_OF
+static struct dw_mci_drv_data synopsis_drv_data = {
+
Re: [PATCH 4/7] mmc: dw_mmc: add samsung exynos5250 specific extentions
Hi,
On 5/2/12, Thomas Abraham thomas.abra...@linaro.org wrote:
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 33
+++-
drivers/mmc/host/dw_mmc-pltfm.c|8 +
drivers/mmc/host/dw_mmc.c | 32
++-
drivers/mmc/host/dw_mmc.h | 13
include/linux/mmc/dw_mmc.h |6 +++
5 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
index c1ed70e..465fc31 100644
--- a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
@@ -7,6 +7,8 @@ Required Properties:
* compatible: should be one of the following
- synopsis,dw-mshc: for controllers compliant with synopsis dw-mshc.
+ - synopsis,dw-mshc-exynos5250: for controllers with Samsung
+ Exynos5250 specific extentions.
* reg: physical base address of the dw-mshc controller and size of its
memory
region.
@@ -55,13 +57,40 @@ Optional properties:
* no-write-protect: The write protect pad of the controller is not
connected
to the write protect pin on the slot.
+Samsung Exynos5250 specific properties:
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider,
CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value
in
+ receive mode for single data rate mode operation. Refer notes of the
valid
+ values below.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider,
CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value
in
+ receive mode for double data rate mode operation. Refer notes of the
valid
+ values below. The order of the cells should be
+
+- First Cell:CIU clock divider value.
+- Second Cell: CIU clock phase shift value for tx mode.
+- Third Cell:CIU clock phase shift value for rx mode.
+
+ Valid values for SDR and DDR CIU clock timing:
+
+- valid values for CIU clock divider, tx phase shift and rx phase
shift
+ is 0 to 7.
+
+- When CIU clock divider value is set to 3, all possible 8 phase shift
+ values can be used.
+
+- If CIU clock divider value is 0 (that is divide by 1), both tx and
rx
+ phase shift clocks should be 0.
+
Example:
The MSHC controller node can be split into two portions, SoC specific
and
board specific portions as listed below.
dwmmc0@1220 {
- compatible = synopsis,dw-mshc;
+ compatible = synopsis,dw-mshc-exynos5250;
reg = 0x1220 0x1000;
interrupts = 0 75 0;
};
@@ -72,6 +101,8 @@ Example:
no-write-protect;
fifo-depth = 0x80;
card-detect-delay = 200;
+ samsung,dw-mshc-sdr-timing = 2 3 3;
+ samsung,dw-mshc-ddr-timing = 1 2 3;
slot0 {
bus-width = 8;
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c
b/drivers/mmc/host/dw_mmc-pltfm.c
index 2b2c9bd..35056fd 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -27,9 +27,17 @@ static struct dw_mci_drv_data synopsis_drv_data = {
.ctrl_type = DW_MCI_TYPE_SYNOPSIS,
};
+static struct dw_mci_drv_data exynos5250_drv_data = {
+ .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
+ .caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+ MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
These caps should be board specific. So it's not proper place. Esp.,
MMC_CAP_8_BIT_DATA.
+};
+
static const struct of_device_id dw_mci_pltfm_match[] = {
{ .compatible = synopsis,dw-mshc,
.data = (void *)synopsis_drv_data, },
+ { .compatible = synopsis,dw-mshc-exynos5250,
+ .data = (void *)exynos5250_drv_data, },
{},
};
MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index bcf66d7..9174a69 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -236,6 +236,7 @@ static void dw_mci_set_timeout(struct dw_mci *host)
static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command
*cmd)
{
struct mmc_data *data;
+ struct dw_mci_slot *slot = mmc_priv(mmc);
u32 cmdr;
cmd-error = -EINPROGRESS;
@@
Re: [PATCH 5/7] ARM: Samsung: Add support for MSHC controller clocks
Hi Thomas,
I suggest to split the patches into mmc part and samsung specific
part. As you know previous time there's mismatch between mmc and
samsung. So split the patches and send it separately to avoid merge
conflict and mismatch.
I think regardless mmc changes, it can be merged into samsung tree directly.
Thank you,
Kyungmin Park
On 5/2/12, Thomas Abraham thomas.abra...@linaro.org wrote:
Add clock instances for bus interface unit clock and card interface unit
clock of the all four MSHC controller instances.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/clock-exynos5.c | 45
--
1 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 7c0f810..4e17131 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -524,35 +524,30 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit= (1 19),
}, {
- .name = hsmmc,
- .devname= exynos4-sdhci.0,
+ .name = biu,
+ .devname= dw_mmc.0,
.parent = exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 12),
}, {
- .name = hsmmc,
- .devname= exynos4-sdhci.1,
+ .name = biu,
+ .devname= dw_mmc.1,
.parent = exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 13),
}, {
- .name = hsmmc,
- .devname= exynos4-sdhci.2,
+ .name = biu,
+ .devname= dw_mmc.2,
.parent = exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 14),
}, {
- .name = hsmmc,
- .devname= exynos4-sdhci.3,
+ .name = biu,
+ .devname= dw_mmc.3,
.parent = exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit= (1 15),
}, {
- .name = dwmci,
- .parent = exynos5_clk_aclk_200.clk,
- .enable = exynos5_clk_ip_fsys_ctrl,
- .ctrlbit= (1 16),
- }, {
.name = sata,
.devname= ahci,
.enable = exynos5_clk_ip_fsys_ctrl,
@@ -882,8 +877,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk= {
- .name = sclk_mmc,
- .devname= exynos4-sdhci.0,
+ .name = ciu,
+ .devname= dw_mmc.0,
.parent = exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 0),
@@ -893,8 +888,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk= {
- .name = sclk_mmc,
- .devname= exynos4-sdhci.1,
+ .name = ciu,
+ .devname= dw_mmc.1,
.parent = exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 4),
@@ -904,8 +899,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk= {
- .name = sclk_mmc,
- .devname= exynos4-sdhci.2,
+ .name = ciu,
+ .devname= dw_mmc.2,
.parent = exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 8),
@@ -915,8 +910,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk= {
- .name = sclk_mmc,
- .devname= exynos4-sdhci.3,
+ .name = ciu,
+ .devname= dw_mmc.3,
.parent = exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 12),
@@ -927,14 +922,6 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk= {
-
Re: [PATCH 4/7] mmc: dw_mmc: add samsung exynos5250 specific extentions
On 05/02/2012 04:01 PM, Kyungmin Park wrote:
Hi,
On 5/2/12, Thomas Abraham thomas.abra...@linaro.org wrote:
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 33
+++-
drivers/mmc/host/dw_mmc-pltfm.c|8 +
drivers/mmc/host/dw_mmc.c | 32
++-
drivers/mmc/host/dw_mmc.h | 13
include/linux/mmc/dw_mmc.h |6 +++
5 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
index c1ed70e..465fc31 100644
--- a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
@@ -7,6 +7,8 @@ Required Properties:
* compatible: should be one of the following
- synopsis,dw-mshc: for controllers compliant with synopsis dw-mshc.
+- synopsis,dw-mshc-exynos5250: for controllers with Samsung
+ Exynos5250 specific extentions.
* reg: physical base address of the dw-mshc controller and size of its
memory
region.
@@ -55,13 +57,40 @@ Optional properties:
* no-write-protect: The write protect pad of the controller is not
connected
to the write protect pin on the slot.
+Samsung Exynos5250 specific properties:
+
+* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider,
CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value
in
+ receive mode for single data rate mode operation. Refer notes of the
valid
+ values below.
+
+* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider,
CIU
+ clock phase shift value in transmit mode and CIU clock phase shift value
in
+ receive mode for double data rate mode operation. Refer notes of the
valid
+ values below. The order of the cells should be
+
+- First Cell: CIU clock divider value.
+- Second Cell: CIU clock phase shift value for tx mode.
+- Third Cell: CIU clock phase shift value for rx mode.
+
+ Valid values for SDR and DDR CIU clock timing:
+
+- valid values for CIU clock divider, tx phase shift and rx phase
shift
+ is 0 to 7.
+
+- When CIU clock divider value is set to 3, all possible 8 phase shift
+ values can be used.
+
+- If CIU clock divider value is 0 (that is divide by 1), both tx and
rx
+ phase shift clocks should be 0.
+
Example:
The MSHC controller node can be split into two portions, SoC specific
and
board specific portions as listed below.
dwmmc0@1220 {
-compatible = synopsis,dw-mshc;
+compatible = synopsis,dw-mshc-exynos5250;
reg = 0x1220 0x1000;
interrupts = 0 75 0;
};
@@ -72,6 +101,8 @@ Example:
no-write-protect;
fifo-depth = 0x80;
card-detect-delay = 200;
+samsung,dw-mshc-sdr-timing = 2 3 3;
+samsung,dw-mshc-ddr-timing = 1 2 3;
slot0 {
bus-width = 8;
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c
b/drivers/mmc/host/dw_mmc-pltfm.c
index 2b2c9bd..35056fd 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -27,9 +27,17 @@ static struct dw_mci_drv_data synopsis_drv_data = {
.ctrl_type = DW_MCI_TYPE_SYNOPSIS,
};
+static struct dw_mci_drv_data exynos5250_drv_data = {
+.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
+.caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
These caps should be board specific. So it's not proper place. Esp.,
MMC_CAP_8_BIT_DATA.
+};
+
static const struct of_device_id dw_mci_pltfm_match[] = {
{ .compatible = synopsis,dw-mshc,
.data = (void *)synopsis_drv_data, },
+{ .compatible = synopsis,dw-mshc-exynos5250,
+.data = (void *)exynos5250_drv_data, },
{},
};
MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index bcf66d7..9174a69 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -236,6 +236,7 @@ static void dw_mci_set_timeout(struct dw_mci *host)
static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command
*cmd)
{
struct mmc_data *data;
+struct dw_mci_slot *slot = mmc_priv(mmc);
u32 cmdr;
cmd-error =
Re: [PATCH] mmc: dw_mmc: make multiple instances of dw_mci_card_workqueue
On Tue, May 1, 2012 at 10:57 PM, Thomas Abraham thomas.abra...@linaro.org wrote: The variable 'dw_mci_card_workqueue' is a global variable shared between multiple instances of the dw_mmc host controller. Due to this, data corruption has been noticed when multiple instances of dw_mmc controllers are actively reading/writing the media. Fix this by adding a instance of 'struct workqueue_struct' for each host instance and removing the global 'dw_mci_card_workqueue' instance. Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- drivers/mmc/host/dw_mmc.c | 14 ++ include/linux/mmc/dw_mmc.h | 1 + 2 files changed, 7 insertions(+), 8 deletions(-) Looks good. Acked-by: Will Newton will.new...@imgtec.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/7] mmc: dw_mmc: add quirk to indicate missing write protect line
On Wed, May 2, 2012 at 6:07 AM, Thomas Abraham thomas.abra...@linaro.org wrote: If the write protect pad of the controller is not connected to the write protect pin of the slot, the driver should be notified of this condition so that incorrect check for write protection by reading the WRTORT register can avoided. The get_ro platform callback can be used for in such cases, but with device tree support enabled, such platform callbacks cannot be supported. Add a new quirk for notifying the driver about the missing write protect line so the driver can assume that the card write protection is disabled. Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- drivers/mmc/host/dw_mmc.c | 4 +++- include/linux/mmc/dw_mmc.h | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) Acked-by: Will Newton will.new...@imgtec.com -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/7] mmc: dw_mmc: lookup for optional biu and ciu clocks
On Tue, May 01, 2012 at 10:07:40PM -0700, Thomas Abraham wrote: Some platforms allow for clock gating and control of bus interface unit clock and card interface unit clock. Add support for clock lookup of optional biu and ciu clocks for clock gating and clock speed determination. As we're moving progressively towards the common clk API, which requires the new clk_prepare/clk_unprepare calls, new code should be using the dated API. Please update this to do so (eg, by using clk_prepare_enable() instead of clk_enable() for the simple solution.) Better solutions involve decoupling the two and only using clk_enable()/clk_disable() where you really need the clock to be on. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/7] mmc: dw_mmc: lookup for optional biu and ciu clocks
Hi
On 2 May 2012 06:07, Thomas Abraham thomas.abra...@linaro.org wrote:
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/mmc/host/dw_mmc.c | 35 +++
include/linux/mmc/dw_mmc.h | 4
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1532357..036846f 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1938,19 +1938,35 @@ int dw_mci_probe(struct dw_mci *host)
return -ENODEV;
}
- if (!host-pdata-bus_hz) {
+ host-biu_clk = clk_get(host-dev, biu);
These clock names sound quite platform specific (what if they're
called something else on another platform, or another platform has
separate ones for different instantiations of the block?). Perhaps the
clk names should get passed in through platform data. I haven't looked
how other drivers handle that though.
+ if (IS_ERR(host-biu_clk))
+ dev_info(host-dev, biu clock not available\n);
In this case, should it set host-biu_clk to NULL or are clk_disable
and clk_put guaranteed to handle an IS_ERR value?
+ else
+ clk_enable(host-biu_clk);
+
+ host-ciu_clk = clk_get(host-dev, ciu);
+ if (IS_ERR(host-ciu_clk))
+ dev_info(host-dev, ciu clock not available\n);
same here
+ else
+ clk_enable(host-ciu_clk);
+
+ if (IS_ERR(host-ciu_clk))
+ host-bus_hz = host-pdata-bus_hz;
+ else
+ host-bus_hz = clk_get_rate(host-ciu_clk);
+
+ if (!host-bus_hz) {
dev_err(host-dev,
Platform data must supply bus speed\n);
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk;
}
- host-bus_hz = host-pdata-bus_hz;
host-quirks = host-pdata-quirks;
spin_lock_init(host-lock);
INIT_LIST_HEAD(host-queue);
-
host-dma_ops = host-pdata-dma_ops;
dw_mci_init_dma(host);
@@ -2095,6 +2111,13 @@ err_dmaunmap:
regulator_disable(host-vmmc);
regulator_put(host-vmmc);
}
+ kfree(host);
what's this about?
+
+err_clk:
+ clk_disable(host-ciu_clk);
+ clk_disable(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
return ret;
}
EXPORT_SYMBOL(dw_mci_probe);
@@ -2128,6 +2151,10 @@ void dw_mci_remove(struct dw_mci *host)
regulator_put(host-vmmc);
}
+ clk_disable(host-ciu_clk);
+ clk_disable(host-biu_clk);
+ clk_put(host-ciu_clk);
+ clk_put(host-biu_clk);
}
EXPORT_SYMBOL(dw_mci_remove);
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 7a7ebd3..fa9a139 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -78,6 +78,8 @@ struct mmc_data;
* @data_offset: Set the offset of DATA register according to VERID.
* @dev: Device associated with the MMC controller.
* @pdata: Platform data associated with the MMC controller.
+ * @biu_clk: Pointer to bus interface unit clock instance.
+ * @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_shift: log2 of FIFO item size.
@@ -158,6 +160,8 @@ struct dw_mci {
u16 data_offset;
struct device dev;
struct dw_mci_board *pdata;
+ struct clk *biu_clk;
+ struct clk *ciu_clk;
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
/* FIFO push and pull */
--
1.7.5.4
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
--
James Hogan
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 19/20] ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes
Hi,
[adding devicetree-discuss]
On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
And interrupt combiner, external interrupt wakeup interrupt controller
and smsc9215 lan controller nodes.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 11 ++
arch/arm/boot/dts/exynos5250.dtsi | 55
+
2 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index bcc4b89..dbc4bdb 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -24,6 +24,17 @@
bootargs = root=/dev/ram0 rw ramdisk=8192
console=ttySAC1,115200;
};
+ lan9215@0x0500 {
+ compatible = smsc,lan9215, smsc,lan9115;
+ reg = 0x0500 0x2;
+ interrupts = 5 0;
+ interrupt-parent = wakeup_eint;
+ phy-mode = mii;
+ smsc,irq-push-pull;
+ smsc,force-internal-phy;
+ local-mac-address = [00 80 00 23 45 67];
+ };
+
since the 911x sits on a chipselect bus, you should instead add that
bus to the dtsi and define this on that bus.
Something like this in the dtsi:
sromc-bus {
#address-cells = 2;
#size-cells = 1;
ranges = 0 0 0x0400 0x2
1 0 0x0500 0x2
2 0 0x0600 0x2
3 0 0x0700 0x2;
};
and in the dts:
sromc-bus {
lan9215@1,0 {
compatible = smsc,lan9215, smsc,lan9115;
reg = 1 0 0x2;
interrupts = 5 0;
interrupt-parent = wakeup_eint;
phy-mode = mii;
smsc,irq-push-pull;
smsc,force-internal-phy;
local-mac-address = [00 80 00 23 45 67];
};
};
(You might be able to do just fine with one address cell, I'm not 100%
sure why Grant's example uses two, but I used the same above for
consistency).
Also, I don't think it's a good idea to hardcode the mac address in
the dts like this; have u-boot fill it in from the environment
variable there instead, if needed.
-Olof
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/7] mmc: dw_mmc: add device tree support
Hi,
On Tue, May 1, 2012 at 10:07 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
Add device tree based discovery support.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 85 +
drivers/mmc/host/dw_mmc-pltfm.c | 24 +++
drivers/mmc/host/dw_mmc.c | 181
+++-
drivers/mmc/host/dw_mmc.h | 10 +
include/linux/mmc/dw_mmc.h | 2 +
5 files changed, 296 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
new file mode 100644
index 000..c1ed70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
@@ -0,0 +1,85 @@
+* Synopsis Designware Mobile Storage Host Controller
+
+The Synopsis designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards.
+
+Required Properties:
+
+* compatible: should be one of the following
+ - synopsis,dw-mshc: for controllers compliant with synopsis dw-mshc.
+
+* reg: physical base address of the dw-mshc controller and size of its memory
+ region.
+
+* interrupts: interrupt specifier for the controller. The format and value of
+ the interrupt specifier depends on the interrupt parent for the controller.
+
+# Slots: The slot specific information are contained within child-nodes with
+ each child-node representing a supported slot. There should be atleast one
+ child node representing a card slot. The name of the slot child node should
+ be 'slot{n}' where n is the unique number of the slot connnected to the
+ controller. The following are optional properties which can be included in
+ the slot child node.
Since we're talking slots / cards on a bus, I think the addressing
model would be useful here. So in the main controller node:
#address-cells = 1;
#size-cells = 0;
And then each slot would need a reg property and possibly unit address:
slot {
reg = 0;
...
};
(unit addresses on the slots are only needed if they can't be
disambiguated by name, so not needed if you only have one slot).
-Olof
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/7] mmc: dw_mmc: add samsung exynos5250 specific extentions
Hi, On Tue, May 1, 2012 at 10:07 PM, Thomas Abraham thomas.abra...@linaro.org wrote: The instantiation of the Synopsis Designware controller on Exynos5250 include extension for SDR and DDR specific tx/rx phase shift timing and CIU internal divider. In addition to that, the option to skip the command hold stage is also introduced. Add support for these Exynos5250 specfic extenstions. Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- .../devicetree/bindings/mmc/synposis-dw-mshc.txt | 33 +++- drivers/mmc/host/dw_mmc-pltfm.c | 8 + drivers/mmc/host/dw_mmc.c | 32 ++- drivers/mmc/host/dw_mmc.h | 13 include/linux/mmc/dw_mmc.h | 6 +++ 5 files changed, 89 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt index c1ed70e..465fc31 100644 --- a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt @@ -7,6 +7,8 @@ Required Properties: * compatible: should be one of the following - synopsis,dw-mshc: for controllers compliant with synopsis dw-mshc. + - synopsis,dw-mshc-exynos5250: for controllers with Samsung + Exynos5250 specific extentions. It makes more sense to use your own manufacturer prefix here: samsung,exynos5250-dw-mshc -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 18/20] ARM: dts: Update device tree source files for EXYNOS5250
Hi,
On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
Updated EXYNOS5 device tree source files to reflect changes in rev1
of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and
SMDK5250 dts files and few minor fixes.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 52
+
arch/arm/boot/dts/exynos5250.dtsi | 44 +++-
2 files changed, 65 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b..bcc4b89 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,56 @@
chosen {
bootargs = root=/dev/ram0 rw ramdisk=8192
console=ttySAC1,115200;
};
+
+ i2c@12C6 {
+ #address-cells = 1;
+ #size-cells = 0;
Two nits:
#a-c and #s-c is likely to always be 1/0, so you might as well move
these to the dtsi file for the SoC.
Also, we tend to use non-caps here and in other locations (so it
should be 12c6 here).
-Olof
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] ARM: EXYNOS: Add DRM device to Origen and SMDKV310
Hi Kukjin, Can you please review these patches and let me know your comments. On 11/04/2012, Sachin Kamat sachin.ka...@linaro.org wrote: ping... On 27/03/2012, Sachin Kamat sachin.ka...@linaro.org wrote: This patch series adds DRM core device and FIMD DRM platform device support to Origen and SMDKV310 boards. This series depends on the following patch: http://www.spinics.net/lists/arm-kernel/msg164762.html Sachin Kamat (2): ARM: EXYNOS: Add DRM device to Origen ARM: EXYNOS: Add DRM device to SMDKV310 arch/arm/mach-exynos/Kconfig |2 ++ arch/arm/mach-exynos/mach-origen.c | 31 +++ arch/arm/mach-exynos/mach-smdkv310.c | 30 ++ 3 files changed, 63 insertions(+), 0 deletions(-) -- 1.7.4.1 -- With warm regards, Sachin -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
