[PATCH v3 1/5] ARM: Exynos: add a register base address variable in mct controller driver
All the MCT register read/writes use a fixed remapped address S5P_VA_SYSTIMER. With device tree support for MCT controller, it is possible to remove the static remap of the MCT controller address space and do the remap during the initialization of the MCT controller with the physical address obtained from the device tree. So in preparation of adding device tree support for MCT controller, add a new register base address variable that will hold the remapped MCT controller base address and convert all MCT register read/writes to use this new variable as the base address instead of the fixed S5P_VA_SYSTIMER. While at it, the MCT register offset and bit mask definitions are moved into the MCT controller driver file since there are no other consumers of these definitions. Cc: Changhwan Youn chaos.y...@samsung.com Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- arch/arm/mach-exynos/include/mach/regs-mct.h | 53 -- arch/arm/mach-exynos/mct.c | 97 - 2 files changed, 62 insertions(+), 88 deletions(-) delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h deleted file mode 100644 index 80dd02a..000 --- a/arch/arm/mach-exynos/include/mach/regs-mct.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-exynos4/include/mach/regs-mct.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 MCT configutation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_MCT_H -#define __ASM_ARCH_REGS_MCT_H __FILE__ - -#include mach/map.h - -#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x)) - -#define EXYNOS4_MCT_G_CNT_LEXYNOS4_MCTREG(0x100) -#define EXYNOS4_MCT_G_CNT_UEXYNOS4_MCTREG(0x104) -#define EXYNOS4_MCT_G_CNT_WSTATEXYNOS4_MCTREG(0x110) - -#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) -#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) -#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) - -#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) - -#define EXYNOS4_MCT_G_INT_CSTATEXYNOS4_MCTREG(0x244) -#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) -#define EXYNOS4_MCT_G_WSTATEXYNOS4_MCTREG(0x24C) - -#define _EXYNOS4_MCT_L_BASEEXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) -#define EXYNOS4_MCT_L_MASK (0xff00) - -#define MCT_L_TCNTB_OFFSET (0x00) -#define MCT_L_ICNTB_OFFSET (0x08) -#define MCT_L_TCON_OFFSET (0x20) -#define MCT_L_INT_CSTAT_OFFSET (0x30) -#define MCT_L_INT_ENB_OFFSET (0x34) -#define MCT_L_WSTAT_OFFSET (0x40) - -#define MCT_G_TCON_START (1 8) -#define MCT_G_TCON_COMP0_AUTO_INC (1 1) -#define MCT_G_TCON_COMP0_ENABLE(1 0) - -#define MCT_L_TCON_INTERVAL_MODE (1 2) -#define MCT_L_TCON_INT_START (1 1) -#define MCT_L_TCON_TIMER_START (1 0) - -#endif /* __ASM_ARCH_REGS_MCT_H */ diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index 57668eb..a9fd001 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -29,9 +29,36 @@ #include mach/map.h #include mach/irqs.h -#include mach/regs-mct.h #include asm/mach/time.h +#define EXYNOS4_MCTREG(x) (x) +#define EXYNOS4_MCT_G_CNT_LEXYNOS4_MCTREG(0x100) +#define EXYNOS4_MCT_G_CNT_UEXYNOS4_MCTREG(0x104) +#define EXYNOS4_MCT_G_CNT_WSTATEXYNOS4_MCTREG(0x110) +#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) +#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) +#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) +#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) +#define EXYNOS4_MCT_G_INT_CSTATEXYNOS4_MCTREG(0x244) +#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) +#define EXYNOS4_MCT_G_WSTATEXYNOS4_MCTREG(0x24C) +#define _EXYNOS4_MCT_L_BASEEXYNOS4_MCTREG(0x300) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_MASK (0xff00) + +#define MCT_L_TCNTB_OFFSET (0x00) +#define MCT_L_ICNTB_OFFSET (0x08) +#define MCT_L_TCON_OFFSET (0x20) +#define MCT_L_INT_CSTAT_OFFSET (0x30) +#define MCT_L_INT_ENB_OFFSET (0x34) +#define MCT_L_WSTAT_OFFSET (0x40) +#define MCT_G_TCON_START (1 8) +#define MCT_G_TCON_COMP0_AUTO_INC (1 1) +#define MCT_G_TCON_COMP0_ENABLE(1 0) +#define MCT_L_TCON_INTERVAL_MODE
[PATCH v3 2/5] ARM: Exynos: prepare an array of MCT interrupt numbers and use it
Instead of using soc_is_xxx macro at more than one place in the MCT
controller driver to decide the MCT interrpt number to be setup, populate
a table of known MCT global and local timer interrupts and use the values
in table to setup the MCT interrupts.
This also helps in adding device tree support for MCT controller driver by
allowing the driver to retrieve interrupt numbers from device tree and
populating them into this table, thereby supporting both legacy and dt
functionality to co-exist.
Cc: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/mct.c | 57 +++
1 files changed, 36 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index a9fd001..2f4ea16 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -66,9 +66,22 @@ enum {
MCT_INT_PPI
};
+enum {
+ MCT_G0_IRQ,
+ MCT_G1_IRQ,
+ MCT_G2_IRQ,
+ MCT_G3_IRQ,
+ MCT_L0_IRQ,
+ MCT_L1_IRQ,
+ MCT_L2_IRQ,
+ MCT_L3_IRQ,
+ MCT_NR_IRQS,
+};
+
static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
struct mct_clock_event_device {
struct clock_event_device *evt;
@@ -287,11 +300,7 @@ static void exynos4_clockevent_init(void)
clockevent_delta2ns(0xf, mct_comp_device);
mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(mct_comp_device);
-
- if (soc_is_exynos5250())
- setup_irq(EXYNOS5_IRQ_MCT_G0, mct_comp_event_irq);
- else
- setup_irq(EXYNOS4_IRQ_MCT_G0, mct_comp_event_irq);
+ setup_irq(mct_irqs[MCT_G0_IRQ], mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
@@ -415,7 +424,6 @@ static int __cpuinit exynos4_local_timer_setup(struct
clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
- int mct_lx_irq;
mevt = this_cpu_ptr(percpu_mct_tick);
mevt-evt = evt;
@@ -442,21 +450,17 @@ static int __cpuinit exynos4_local_timer_setup(struct
clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
- EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
- evt-irq = mct_lx_irq;
- setup_irq(mct_lx_irq, mct_tick0_event_irq);
+ evt-irq = mct_irqs[MCT_L0_IRQ];
+ setup_irq(evt-irq, mct_tick0_event_irq);
} else {
- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
- EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
- evt-irq = mct_lx_irq;
- setup_irq(mct_lx_irq, mct_tick1_event_irq);
- irq_set_affinity(mct_lx_irq, cpumask_of(1));
+ evt-irq = mct_irqs[MCT_L1_IRQ];
+ setup_irq(evt-irq, mct_tick1_event_irq);
+ irq_set_affinity(evt-irq, cpumask_of(1));
}
} else {
- enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
+ enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
return 0;
@@ -472,7 +476,7 @@ static void exynos4_local_timer_stop(struct
clock_event_device *evt)
else
remove_irq(evt-irq, mct_tick1_event_irq);
else
- disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
+ disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}
static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -494,11 +498,11 @@ static void __init exynos4_timer_resources(void)
if (mct_int_type == MCT_INT_PPI) {
int err;
- err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
+ err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
exynos4_mct_tick_isr, MCT,
percpu_mct_tick);
WARN(err, MCT: can't request IRQ %d (%d)\n,
-EXYNOS_IRQ_MCT_LOCALTIMER, err);
+mct_irqs[MCT_L0_IRQ], err);
}
local_timer_register(exynos4_mct_tick_ops);
@@ -512,10 +516,21 @@ static void __init exynos_timer_init(void)
return;
}
- if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
+ if (soc_is_exynos4210()) {
+ mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+ mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
+ mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
mct_int_type = MCT_INT_SPI;
-
[PATCH v3 3/5] ARM: Exynos: add device tree support for MCT controller driver
Allow the MCT controller base address and interrupts to be obtained from
device tree and remove unused static definitions of these. The non-dt support
for Exynos5250 is removed but retained for Exynos4210 based platforms.
Cc: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
.../bindings/timer/samsung,exynos4210-mct.txt | 69
arch/arm/mach-exynos/include/mach/irqs.h |6 --
arch/arm/mach-exynos/mct.c | 41
3 files changed, 97 insertions(+), 19 deletions(-)
create mode 100644
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000..c1b0a3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,69 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generate an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be samsung,exynos4210-mct.
+- reg: base address of the mct controller and length of the address space
+ it occupies.
+- interrupts: the list of interrupts generated by the controller. The following
+ should be the order of the interrupts specified. The local timer interrupts
+ should be specified after the four global timer interrupts have been
+ specified.
+
+ 0: Global Timer Interrupt 0
+ 1: Global Timer Interrupt 1
+ 2: Global Timer Interrupt 2
+ 3: Global Timer Interrupt 3
+ 4: Local Timer Interrupt 0
+ 5: Local Timer Interrupt 1
+ 6: ..
+ 7: ..
+ i: Local Timer Interrupt n
+
+- samsung,mct-nr-local-irqs: The number of local timer interrupts supported
+ by the MCT controller.
+
+Example 1: In this example, the system uses only the first global timer
+ interrupt generated by MCT and the remaining three global timer
+ interrupts are unused. Two local timer interrupts have been
+ specified.
+
+ mct@1005 {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x1005 0x800;
+ interrupts = 0 57 0, 0 0 0, 0 0 0, 0 0 0,
+0 42 0, 0 48 0;
+ samsung,mct-nr-local-irqs = 2;
+ };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+ connected to two seperate interrupt controllers. Hence, an
+ interrupt-map is created to map the interrupts to the respective
+ interrupt controllers.
+
+ mct@101C {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x101C 0x800;
+ interrupt-controller;
+ #interrups-cells = 2;
+ interrupt-parent = mct_map;
+ interrupts = 0 0, 1 0, 2 0, 3 0,
+4 0, 5 0;
+ samsung,mct-nr-local-irqs = 2;
+
+ mct_map: mct-map {
+ #interrupt-cells = 2;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0x0 0 combiner 23 3,
+ 0x4 0 gic 0 120 0,
+ 0x5 0 gic 0 121 0;
+ };
+ };
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 6794292..35fe6d5 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
/* For EXYNOS4 and EXYNOS5 */
-#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
-
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
/* For EXYNOS4 SoCs */
@@ -330,8 +328,6 @@
#define EXYNOS5_IRQ_CECIRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
-#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -426,8 +422,6 @@
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
diff --git
[PATCH v3 4/5] ARM: Exynos: remove static io-remapping of mct registers for Exynos5
With device tree support enabled for MCT controller, the static io-remapping
of the MCT controller address space is removed for Exynos5 platforms (which
supports only device tree based boot).
Cc: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/common.c |5 -
arch/arm/mach-exynos/include/mach/map.h |1 -
2 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 578a610..30592f0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -284,11 +284,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual= (unsigned long)S5P_VA_SYSTIMER,
- .pfn= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
.virtual= (unsigned long)S5P_VA_SYSRAM,
.pfn= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
.length = SZ_4K,
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index b8ea67e..99e0a79 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -68,7 +68,6 @@
#define EXYNOS5_PA_CMU 0x1001
#define EXYNOS4_PA_SYSTIMER0x1005
-#define EXYNOS5_PA_SYSTIMER0x101C
#define EXYNOS4_PA_WATCHDOG0x1006
#define EXYNOS5_PA_WATCHDOG0x101D
--
1.7.5.4
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[PATCH v3 5/5] ARM: dts: add mct device tree node for all supported Exynos SoC's
Add MCT device tree node for Exynos4210, Exynos4212, Exynos4412 and Exynos5250.
Cc: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210.dtsi |8
arch/arm/boot/dts/exynos4212.dtsi | 10 ++
arch/arm/boot/dts/exynos4412.dtsi |8
arch/arm/boot/dts/exynos5250.dtsi | 21 +
4 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 89c7dd0..1542d86 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,14 @@
0 12 0, 0 13 0, 0 14 0, 0 15 0;
};
+ mct@1005 {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x1005 0x800;
+ interrupts = 0 57 0, 0 0 0, 0 0 0, 0 0 0,
+0 42 0, 0 48 0;
+ samsung,mct-nr-local-irqs = 4;
+ };
+
pmu {
compatible = arm,cortex-a9-pmu;
interrupt-parent = combiner;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae200..87c6da4 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,14 @@
gic:interrupt-controller@1049 {
cpu-offset = 0x8000;
};
+
+ mct@1005 {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x1005 0x800;
+ interrupts = 0 57 0, 0 0 0, 0 0 0, 0 0 0,
+1 12 0, 1 12 0;
+ samsung,mct-nr-local-irqs = 2;
+ };
+
+
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe31..ccf020a 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,12 @@
gic:interrupt-controller@1049 {
cpu-offset = 0x4000;
};
+
+ mct@1005 {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x1005 0x800;
+ interrupts = 0 57 0, 0 0 0, 0 0 0, 0 0 0,
+1 12 0, 1 12 0, 1 12 0, 1 12 0;
+ samsung,mct-nr-local-irqs = 4;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 45799e8..7e9600d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -69,6 +69,27 @@
0 28 0, 0 29 0, 0 30 0, 0 31 0;
};
+ mct@101C {
+ compatible = samsung,exynos4210-mct;
+ reg = 0x101C 0x800;
+ interrupt-controller;
+ #interrups-cells = 2;
+ interrupt-parent = mct_map;
+ interrupts = 0 0, 1 0, 2 0, 3 0,
+4 0, 5 0;
+ samsung,mct-nr-local-irqs = 2;
+
+ mct_map: mct-map {
+ compatible = samsung,mct-map;
+ #interrupt-cells = 2;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0x0 0 combiner 23 3,
+ 0x4 0 gic 0 120 0,
+ 0x5 0 gic 0 121 0;
+ };
+ };
+
pmu {
compatible = arm,cortex-a15-pmu;
interrupt-parent = combiner;
--
1.7.5.4
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[PATCH v3 0/5] ARM: Exynos: Enable device tree support for MCT controller
Changes since v2: - Rebased to linux 3.8-rc1 Changes since v1: - Includes changes suggested by Sylwester Nawrocki sylvester.nawro...@gmail.com This patch series adds device tree support for Exynos4/5 MCT controller. This patch series has been tested on Exynos4210 based Origen board, Exynos4412 based Origen board and Exynos5250 based SMDK board. Thomas Abraham (5): ARM: Exynos: add a register base address variable in mct controller driver ARM: Exynos: prepare an array of MCT interrupt numbers and use it ARM: Exynos: add device tree support for MCT controller driver ARM: Exynos: remove static io-remapping of mct registers for Exynos5 ARM: dts: add mct device tree node for all supported Exynos SoC's .../bindings/timer/samsung,exynos4210-mct.txt | 69 arch/arm/boot/dts/exynos4210.dtsi |8 + arch/arm/boot/dts/exynos4212.dtsi | 10 + arch/arm/boot/dts/exynos4412.dtsi |8 + arch/arm/boot/dts/exynos5250.dtsi | 21 +++ arch/arm/mach-exynos/common.c |5 - arch/arm/mach-exynos/include/mach/irqs.h |6 - arch/arm/mach-exynos/include/mach/map.h|1 - arch/arm/mach-exynos/include/mach/regs-mct.h | 53 -- arch/arm/mach-exynos/mct.c | 175 +--- 10 files changed, 232 insertions(+), 124 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: add board dts file for EXYNOS4412 based Origen board
Add a minimal board dts file for EXYNOS4412 based Insignal Origen board.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos4412-origen.dts | 45 +++
2 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4412-origen.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e44da40..c84f9f7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4412-smdk4412.dtb \
+ exynos4412-origen.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000..df880c4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,45 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ exynos4412.dtsi
+
+/ {
+ model = Insignal Origen evaluation board based on Exynos4412;
+ compatible = insignal,origen4412, samsung,exynos4412;
+
+ memory {
+ reg = 0x4000 0x4000;
+ };
+
+ chosen {
+ bootargs =console=ttySAC2,115200;
+ };
+
+ serial@1380 {
+ status = okay;
+ };
+
+ serial@1381 {
+ status = okay;
+ };
+
+ serial@1382 {
+ status = okay;
+ };
+
+ serial@1383 {
+ status = okay;
+ };
+};
--
1.7.5.4
--
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[PATCH v5 00/12] clk: exynos4: migrate to common clock framework
Changes since v4: - Rebased to linux-3.8-rc1. Changes since v3: - Includes changes suggested by Tomasz Figa tomasz.f...@gmail.com This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms. This patch series depends on this series: http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14471.html and this patch http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14472.html Thomas Abraham (12): clk: samsung: add common clock framework helper functions for Samsung platforms clk: samsung: add pll clock registration helper functions clk: exynos4: register clocks using common clock framework ARM: Exynos: Rework timer initialization sequence ARM: Exynos4: Migrate clock support to common clock framework ARM: dts: add exynos4 clock controller nodes ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed ARM: dts: add clock provider information for all controllers in Exynos4 SoC ARM: Exynos4: remove auxdata table from machine file ARM: Exynos: use fin_pll clock as the tick clock source for mct ARM: Exynos: add support for mct clock setup .../devicetree/bindings/clock/exynos4-clock.txt| 215 +++ arch/arm/boot/dts/exynos4.dtsi | 50 ++ arch/arm/boot/dts/exynos4210-origen.dts| 12 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 + arch/arm/boot/dts/exynos4210.dtsi |6 + arch/arm/boot/dts/exynos4412-origen.dts| 12 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 + arch/arm/boot/dts/exynos4x12.dtsi |6 + arch/arm/mach-exynos/Kconfig |1 + arch/arm/mach-exynos/Makefile |3 - arch/arm/mach-exynos/clock-exynos4.h | 35 - arch/arm/mach-exynos/clock-exynos4210.c| 188 -- arch/arm/mach-exynos/clock-exynos4212.c| 192 -- arch/arm/mach-exynos/common.c | 57 ++- arch/arm/mach-exynos/common.h | 21 +- arch/arm/mach-exynos/mach-armlex4210.c |3 +- arch/arm/mach-exynos/mach-exynos4-dt.c | 72 +-- arch/arm/mach-exynos/mach-exynos5-dt.c |2 +- arch/arm/mach-exynos/mach-nuri.c |5 +- arch/arm/mach-exynos/mach-origen.c |5 +- arch/arm/mach-exynos/mach-smdk4x12.c |5 +- arch/arm/mach-exynos/mach-smdkv310.c |7 +- arch/arm/mach-exynos/mach-universal_c210.c |3 +- arch/arm/mach-exynos/mct.c | 32 +- arch/arm/plat-samsung/Kconfig |4 +- drivers/clk/Makefile |1 + drivers/clk/samsung/Makefile |6 + drivers/clk/samsung/clk-exynos4.c | 655 drivers/clk/samsung/clk-pll.c | 400 drivers/clk/samsung/clk-pll.h | 38 ++ drivers/clk/samsung/clk.c | 180 ++ drivers/clk/samsung/clk.h | 216 +++ 32 files changed, 1919 insertions(+), 537 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt delete mode 100644 arch/arm/mach-exynos/clock-exynos4.h delete mode 100644 arch/arm/mach-exynos/clock-exynos4210.c delete mode 100644 arch/arm/mach-exynos/clock-exynos4212.c create mode 100644 drivers/clk/samsung/Makefile create mode 100644 drivers/clk/samsung/clk-exynos4.c create mode 100644 drivers/clk/samsung/clk-pll.c create mode 100644 drivers/clk/samsung/clk-pll.h create mode 100644 drivers/clk/samsung/clk.c create mode 100644 drivers/clk/samsung/clk.h -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 01/12] clk: samsung: add common clock framework helper functions for Samsung platforms
All Samsung platforms include different types of clock including fixed-rate,
mux, divider and gate clock types. There are typically hundreds of such clocks
on each of the Samsung platforms. To enable Samsung platforms to register these
clocks using the common clock framework, a bunch of utility functions are
introduced here which simplify the clock registration process. The clocks are
usually statically instantiated and registered with common clock framework.
Cc: Mike Turquette mturque...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/clk/Makefile |1 +
drivers/clk/samsung/Makefile |5 +
drivers/clk/samsung/clk.c| 180 +++
drivers/clk/samsung/clk.h| 216 ++
4 files changed, 402 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/samsung/Makefile
create mode 100644 drivers/clk/samsung/clk.c
create mode 100644 drivers/clk/samsung/clk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ee90e87..aa14ab3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
obj-$(CONFIG_ARCH_ZYNQ)+= clk-zynq.o
+obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000..bd920b4
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,5 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_COMMON_CLK) += clk.o
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000..af000fb
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+#ifdef CONFIG_OF
+static struct clk_onecell_data clk_data;
+#endif
+
+/* setup the essentials required to support clock lookup using ccf */
+void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+ unsigned long nr_clks)
+{
+ reg_base = base;
+ if (!np)
+ return;
+
+#ifdef CONFIG_OF
+ clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+ if (!clk_table)
+ panic(could not allocate clock lookup table\n);
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = nr_clks;
+ of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+#endif
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+{
+ if (clk_table id)
+ clk_table[id] = clk;
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(
+ struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx nr_clk; idx++, list++) {
+ clk = clk_register_fixed_rate(NULL, list-name,
+ list-parent_name, list-flags, list-fixed_rate);
+ if (IS_ERR(clk)) {
+ pr_err(%s: failed to register clock %s\n, __func__,
+ list-name);
+ continue;
+ }
+
+ samsung_clk_add_lookup(clk, list-id);
+
+ /*
+* Unconditionally add a clock lookup for the fixed rate clocks.
+* There are not many of these on any of Samsung platforms.
+*/
+ ret = clk_register_clkdev(clk, list-name, NULL);
+ if (ret)
+ pr_err(%s: failed to register clock lookup for %s,
+ __func__, list-name);
+ }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
+ unsigned int nr_clk)
+{
+ struct clk *clk;
+ unsigned int idx, ret;
+
+ for (idx = 0; idx nr_clk; idx++, list++) {
+ clk = clk_register_mux(NULL, list-name, list-parent_names,
+ list-num_parents, list-flags, reg_base + list-offset,
+ list-shift, list-width, list-mux_flags, lock);
+
[PATCH v5 02/12] clk: samsung: add pll clock registration helper functions
There are several types of pll clocks used in Samsung SoC's and these pll
clocks can be represented as Samsung specific pll clock types and registered
with the common clock framework. Add support for pll35xx, pll36xx, pll45xx and
pll46xx clock types and helper functions to register them.
Cc: Mike Turquette mturque...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-pll.c | 400 +
drivers/clk/samsung/clk-pll.h | 38
3 files changed, 439 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-pll.c
create mode 100644 drivers/clk/samsung/clk-pll.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index bd920b4..78e5aaa 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,4 +2,4 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000..9073cd6
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include linux/errno.h
+#include clk.h
+#include clk-pll.h
+
+/*
+ * PLL35xx Clock Type
+ */
+
+#define PLL35XX_MDIV_MASK (0x3FF)
+#define PLL35XX_PDIV_MASK (0x3F)
+#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_MDIV_SHIFT (16)
+#define PLL35XX_PDIV_SHIFT (8)
+#define PLL35XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll35xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL35XX_MDIV_SHIFT) PLL35XX_MDIV_MASK;
+ pdiv = (pll_con PLL35XX_PDIV_SHIFT) PLL35XX_PDIV_MASK;
+ sdiv = (pll_con PLL35XX_SDIV_SHIFT) PLL35XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv sdiv));
+
+ return (unsigned long)fvco;
+}
+
+/* todo: implement pl35xx clock round rate operation */
+static long samsung_pll35xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ return -ENOTSUPP;
+}
+
+/* todo: implement pl35xx clock set rate */
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+ .recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll35xx_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll35xx(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll35xx *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err(%s: could not allocate pll clk %s\n, __func__, name);
+ return NULL;
+ }
+
+ init.name = name;
+ init.ops = samsung_pll35xx_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg = con_reg;
+
+ clk = clk_register(NULL, pll-hw);
+ if (IS_ERR(clk)) {
+ pr_err(%s: failed to register pll clock %s\n, __func__,
+ name);
+ kfree(pll);
+ }
+
+ if (clk_register_clkdev(clk, name, NULL))
+ pr_err(%s: failed to register lookup for %s, __func__, name);
+
+ return clk;
+}
+
+/*
+ * PLL36xx Clock Type
+ */
+
+#define PLL36XX_KDIV_MASK (0x)
+#define PLL36XX_MDIV_MASK (0x1FF)
+#define PLL36XX_PDIV_MASK (0x3F)
+#define PLL36XX_SDIV_MASK (0x7)
+#define PLL36XX_MDIV_SHIFT (16)
+#define PLL36XX_PDIV_SHIFT (8)
+#define PLL36XX_SDIV_SHIFT (0)
+
+struct samsung_clk_pll36xx {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
+
+static unsigned long
[PATCH v5 03/12] clk: exynos4: register clocks using common clock framework
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Cc: Mike Turquette mturque...@linaro.org Cc: Kukjin Kim kgene@samsung.com Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- .../devicetree/bindings/clock/exynos4-clock.txt| 215 +++ drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4.c | 655 3 files changed, 871 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos4.c diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt new file mode 100644 index 000..e874add --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -0,0 +1,215 @@ +* Samsung Exynos4 Clock Controller + +The Exynos4 clock controller generates and supplies clock to various controllers +within the Exynos4 SoC. The clock binding described here is applicable to all +SoC's in the Exynos4 family. + +Required Properties: + +- comptible: should be one of the following. + - samsung,exynos4210-clock - controller compatible with Exynos4210 SoC. + - samsung,exynos4412-clock - controller compatible with Exynos4412 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + + +[Core Clocks] + + Clock ID SoC (if specific) + --- + + xxti1 + xusbxti 2 + fin_pll 3 + fout_apll 4 + fout_mpll 5 + fout_epll 6 + fout_vpll 7 + sclk_apll 8 + sclk_mpll 9 + sclk_epll 10 + sclk_vpll 11 + arm_clk 12 + aclk200 13 + aclk100 14 + aclk160 15 + aclk133 16 + + +[Clock Gate for Special Clocks] + + Clock ID SoC (if specific) + --- + + sclk_fimc0 128 + sclk_fimc1 129 + sclk_fimc2 130 + sclk_fimc3 131 + sclk_cam0 132 + sclk_cam1 133 + sclk_csis0 134 + sclk_csis1 135 + sclk_hdmi 136 + sclk_mixer 137 + sclk_dac138 + sclk_pixel 139 + sclk_fimd0 140 + sclk_mdnie0 141 Exynos4412 + sclk_mdnie_pwm0 12 142 Exynos4412 + sclk_mipi0 143 + sclk_audio0 144 + sclk_mmc0 145 + sclk_mmc1 146 + sclk_mmc2 147 + sclk_mmc3 148 + sclk_mmc4 149 + sclk_sata 150 Exynos4210 + sclk_uart0 151 + sclk_uart1 152 + sclk_uart2 153 + sclk_uart3 154 + sclk_uart4 155 + sclk_audio1 156 + sclk_audio2 157 + sclk_spdif 158 + sclk_spi0 159 + sclk_spi1 160 + sclk_spi2 161 + sclk_slimbus162 + sclk_fimd1 163 Exynos4210 + sclk_mipi1 164 Exynos4210 + sclk_pcm1 165 + sclk_pcm2 166 + sclk_i2s1 167 + sclk_i2s2 168 + sclk_mipihsi169 Exynos4412 + + + [Peripheral Clock Gates] + + Clock ID SoC (if specific) + --- + + fimc0 256 + fimc1 257 + fimc2 258 + fimc3 259 + csis0 260 + csis1 261 + jpeg262 + smmu_fimc0 263 + smmu_fimc1 264 + smmu_fimc2 265 + smmu_fimc3 266 + smmu_jpeg 267 + vp 268 + mixer 269 + tvenc 270 Exynos4210 + hdmi271 + smmu_tv 272 + mfc 273 + smmu_mfcl 274 + smmu_mfcr 275 + g3d 276 + g2d 277 Exynos4210 + rotator 278 Exynos4210 + mdma279 Exynos4210 + smmu_g2d280 Exynos4210 + smmu_rotator281 Exynos4210 + smmu_mdma 282 Exynos4210 + fimd0 283 + mie0284 + mdnie0 285 Exynos4412 + dsim0 286 + smmu_fimd0 287 + fimd1 288 Exynos4210 + mie1289
[PATCH v5 04/12] ARM: Exynos: Rework timer initialization sequence
A seperate timer initialization function for all exynos based platforms is
created. This new initialization function will help to identify the type of
timer used and call their corresponding initialization function. Since the
clock initialization should be completed prior to the mct timer initialization,
the clock initialization can be initiated from this new timer initialization
function.
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/common.c | 27 +++
arch/arm/mach-exynos/common.h |3 ++-
arch/arm/mach-exynos/mach-armlex4210.c |2 +-
arch/arm/mach-exynos/mach-exynos4-dt.c |2 +-
arch/arm/mach-exynos/mach-exynos5-dt.c |2 +-
arch/arm/mach-exynos/mach-nuri.c |2 +-
arch/arm/mach-exynos/mach-origen.c |2 +-
arch/arm/mach-exynos/mach-smdk4x12.c |4 ++--
arch/arm/mach-exynos/mach-smdkv310.c |4 ++--
arch/arm/mach-exynos/mct.c | 13 +
10 files changed, 39 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 30592f0..535a7ed 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -24,6 +24,8 @@
#include linux/irqdomain.h
#include linux/of_address.h
+#include asm/mach/time.h
+#include asm/arch_timer.h
#include asm/proc-fns.h
#include asm/exception.h
#include asm/hardware/cache-l2x0.h
@@ -462,6 +464,31 @@ static void __init exynos5_init_clocks(int xtal)
exynos5_setup_clocks();
}
+void __init exynos_timer_init(void)
+{
+ /*
+* Temporary support for Exynos4 based non-dt platforms. This should
+* go away soon.
+*/
+ if (!of_have_populated_dt() (soc_is_exynos4210() ||
+ soc_is_exynos4212() || soc_is_exynos4412())) {
+ exynos_mct_init();
+ return;
+ }
+
+ /* quick check to see if this machine uses arch timer */
+ if (of_machine_is_compatible(samsung,exynos5440)) {
+ if (arch_timer_of_register())
+ panic(%s: could not initialize timer\n, __func__);
+ } else {
+ exynos_mct_init();
+ }
+}
+
+struct sys_timer exynos_timer = {
+ .init = exynos_timer_init,
+};
+
#define COMBINER_ENABLE_SET0x0
#define COMBINER_ENABLE_CLEAR 0x4
#define COMBINER_INT_STATUS0xC
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 7733b61..687b6f0 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,7 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
-extern struct sys_timer exynos4_timer;
+extern struct sys_timer exynos_timer;
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -21,6 +21,7 @@ void exynos5_init_irq(void);
void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
+extern void exynos_mct_init(void);
void exynos_firmware_init(void);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c
b/arch/arm/mach-exynos/mach-armlex4210.c
index b938f9f..4d0ea70 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -204,6 +204,6 @@ MACHINE_START(ARMLEX4210, ARMLEX4210)
.handle_irq = gic_handle_irq,
.init_machine = armlex4210_machine_init,
.init_late = exynos_init_late,
- .timer = exynos4_timer,
+ .timer = exynos_timer,
.restart= exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index ab1dacc..86d914c 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -111,7 +111,7 @@ DT_MACHINE_START(EXYNOS4210_DT, Samsung Exynos4 (Flattened
Device Tree))
.init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
- .timer = exynos4_timer,
+ .timer = exynos_timer,
.dt_compat = exynos4_dt_compat,
.restart= exynos4_restart,
MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e99d3d8..4ea3543 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -182,7 +182,7 @@ DT_MACHINE_START(EXYNOS5_DT, SAMSUNG EXYNOS5 (Flattened
Device Tree))
.handle_irq = gic_handle_irq,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
- .timer = exynos4_timer,
+ .timer = exynos_timer,
.dt_compat = exynos5_dt_compat,
.restart= exynos5_restart,
.reserve= exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c
[PATCH v5 06/12] ARM: dts: add exynos4 clock controller nodes
Add clock controller nodes for Exynos4210 and Exynos4x12 SoC's.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210.dtsi |6 ++
arch/arm/boot/dts/exynos4x12.dtsi |6 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 1542d86..a47d7fc 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -55,6 +55,12 @@
samsung,mct-nr-local-irqs = 4;
};
+ clock: clock-controller@0x1003 {
+ compatible = samsung,exynos4210-clock;
+ reg = 0x1003 0x2;
+ #clock-cells = 1;
+ };
+
pmu {
compatible = arm,cortex-a9-pmu;
interrupt-parent = combiner;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 0c6d001..00138d3 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
0 16 0, 0 17 0, 0 18 0, 0 19 0;
};
+ clock: clock-controller@0x1003 {
+ compatible = samsung,exynos4412-clock;
+ reg = 0x1003 0x2;
+ #clock-cells = 1;
+ };
+
pinctrl_0: pinctrl@1140 {
compatible = samsung,pinctrl-exynos4x12;
reg = 0x1140 0x1000;
--
1.7.5.4
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[PATCH v5 07/12] ARM: dts: add xxti and xusbxti fixed rate clock nodes for exynos4 based platforms
The clock frequency of xxti and xusbxti clocks is dependent on the frequency of
the
on-board oscillator that is used to generate these clocks. So allow the
frequency
of these clocks to be specfied from device tree.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-origen.dts | 12
arch/arm/boot/dts/exynos4210-smdkv310.dts | 12
arch/arm/boot/dts/exynos4412-origen.dts | 12
arch/arm/boot/dts/exynos4412-smdk4412.dts | 12
4 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f271001..d892ccc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -121,4 +121,16 @@
linux,default-trigger = heartbeat;
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = samsung,clock-xxti, fixed-clock;
+ clock-frequency = 0;
+ };
+
+ xusbxti {
+ compatible = samsung,clock-xusbxti, fixed-clock;
+ clock-frequency = 2400;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9b23a82..9a379eb 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -189,4 +189,16 @@
};
};
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = samsung,clock-xxti, fixed-clock;
+ clock-frequency = 1200;
+ };
+
+ xusbxti {
+ compatible = samsung,clock-xusbxti, fixed-clock;
+ clock-frequency = 2400;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index df880c4..7870bee 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -42,4 +42,16 @@
serial@1383 {
status = okay;
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = samsung,clock-xxti, fixed-clock;
+ clock-frequency = 0;
+ };
+
+ xusbxti {
+ compatible = samsung,clock-xusbxti, fixed-clock;
+ clock-frequency = 2400;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf57..8f422fc 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -42,4 +42,16 @@
serial@1383 {
status = okay;
};
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = samsung,clock-xxti, fixed-clock;
+ clock-frequency = 0;
+ };
+
+ xusbxti {
+ compatible = samsung,clock-xusbxti, fixed-clock;
+ clock-frequency = 2400;
+ };
+ };
};
--
1.7.5.4
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[PATCH v5 08/12] ARM: Exynos4: allow legacy board support to specify xxti and xusbxti clock speed
The clock speed of xxti and xusbxti clocks depends on the oscillator used on the
board to generate these clocks. For non-dt platforms, allow the board support
for those platforms to set the clock frequency of xxti and xusbxti clocks.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/common.c |3 +++
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/mach-nuri.c |2 ++
arch/arm/mach-exynos/mach-origen.c |2 ++
arch/arm/mach-exynos/mach-smdkv310.c |2 ++
arch/arm/mach-exynos/mach-universal_c210.c |2 ++
6 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 2b1b225..6349432 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -71,6 +71,8 @@ static void exynos5_init_clocks(int xtal);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
@@ -455,6 +457,7 @@ void __init exynos_timer_init(void)
if (!of_have_populated_dt() (soc_is_exynos4210() ||
soc_is_exynos4212() || soc_is_exynos4412())) {
exynos4_clk_init();
+ exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
exynos_mct_init();
return;
}
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index e3ed6bb..6636002 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -24,6 +24,7 @@ void exynos_init_late(void);
extern void exynos_mct_init(void);
#ifdef CONFIG_COMMON_CLK
+extern unsigned long xxti_f, xusbxti_f;
extern void exynos4_clk_init(void);
extern void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
#else
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 8695d33..afe068f 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1332,6 +1332,8 @@ static void __init nuri_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void __init nuri_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-origen.c
b/arch/arm/mach-exynos/mach-origen.c
index 5d9479d..bb72168 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -756,6 +756,8 @@ static void __init origen_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void __init origen_power_init(void)
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c
b/arch/arm/mach-exynos/mach-smdkv310.c
index a1be874..7d4e72d 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -373,6 +373,8 @@ static void __init smdkv310_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+ xxti_f = 1200;
+ xusbxti_f = 2400;
}
static void __init smdkv310_reserve(void)
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
b/arch/arm/mach-exynos/mach-universal_c210.c
index 3999c16..3de63cb 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1095,6 +1095,8 @@ static void __init universal_map_io(void)
exynos_init_io(NULL, 0);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+ xxti_f = 0;
+ xusbxti_f = 2400;
}
static void s5p_tv_setup(void)
--
1.7.5.4
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[PATCH v5 09/12] ARM: dts: add clock provider information for all controllers in Exynos4 SoC
For all supported peripheral controllers on Exynos4, add clock lookup information. Cc: Kukjin Kim kgene@samsung.com Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- arch/arm/boot/dts/exynos4.dtsi | 50 1 files changed, 50 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e1347fc..825601c 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -86,6 +86,8 @@ compatible = samsung,s3c2410-wdt; reg = 0x1006 0x100; interrupts = 0 43 0; + clocks = clock 345; + clock-names = watchdog; status = disabled; }; @@ -93,6 +95,8 @@ compatible = samsung,s3c6410-rtc; reg = 0x1007 0x100; interrupts = 0 44 0, 0 45 0; + clocks = clock 346; + clock-names = rtc; status = disabled; }; @@ -100,6 +104,8 @@ compatible = samsung,s5pv210-keypad; reg = 0x100A 0x100; interrupts = 0 109 0; + clocks = clock 347; + clock-names = keypad; status = disabled; }; @@ -107,6 +113,8 @@ compatible = samsung,exynos4210-sdhci; reg = 0x1251 0x100; interrupts = 0 73 0; + clocks = clock 297, clock 145; + clock-names = hsmmc, mmc_busclk.2; status = disabled; }; @@ -114,6 +122,8 @@ compatible = samsung,exynos4210-sdhci; reg = 0x1252 0x100; interrupts = 0 74 0; + clocks = clock 298, clock 146; + clock-names = hsmmc, mmc_busclk.2; status = disabled; }; @@ -121,6 +131,8 @@ compatible = samsung,exynos4210-sdhci; reg = 0x1253 0x100; interrupts = 0 75 0; + clocks = clock 299, clock 147; + clock-names = hsmmc, mmc_busclk.2; status = disabled; }; @@ -128,6 +140,8 @@ compatible = samsung,exynos4210-sdhci; reg = 0x1254 0x100; interrupts = 0 76 0; + clocks = clock 300, clock 148; + clock-names = hsmmc, mmc_busclk.2; status = disabled; }; @@ -135,6 +149,8 @@ compatible = samsung,exynos4210-uart; reg = 0x1380 0x100; interrupts = 0 52 0; + clocks = clock 312, clock 151; + clock-names = uart, clk_uart_baud0; status = disabled; }; @@ -142,6 +158,8 @@ compatible = samsung,exynos4210-uart; reg = 0x1381 0x100; interrupts = 0 53 0; + clocks = clock 313, clock 152; + clock-names = uart, clk_uart_baud0; status = disabled; }; @@ -149,6 +167,8 @@ compatible = samsung,exynos4210-uart; reg = 0x1382 0x100; interrupts = 0 54 0; + clocks = clock 314, clock 153; + clock-names = uart, clk_uart_baud0; status = disabled; }; @@ -156,6 +176,8 @@ compatible = samsung,exynos4210-uart; reg = 0x1383 0x100; interrupts = 0 55 0; + clocks = clock 315, clock 154; + clock-names = uart, clk_uart_baud0; status = disabled; }; @@ -165,6 +187,8 @@ compatible = samsung,s3c2440-i2c; reg = 0x1386 0x100; interrupts = 0 58 0; + clocks = clock 317; + clock-names = i2c; status = disabled; }; @@ -174,6 +198,8 @@ compatible = samsung,s3c2440-i2c; reg = 0x1387 0x100; interrupts = 0 59 0; + clocks = clock 318; + clock-names = i2c; status = disabled; }; @@ -183,6 +209,8 @@ compatible = samsung,s3c2440-i2c; reg = 0x1388 0x100; interrupts = 0 60 0; + clocks = clock 319; + clock-names = i2c; status = disabled; }; @@ -192,6 +220,8 @@ compatible = samsung,s3c2440-i2c; reg = 0x1389 0x100; interrupts = 0 61 0; + clocks = clock 320; + clock-names = i2c; status = disabled; }; @@ -201,6 +231,8 @@ compatible = samsung,s3c2440-i2c; reg = 0x138A 0x100; interrupts = 0 62 0; + clocks = clock 321; + clock-names = i2c; status =
[PATCH v5 10/12] ARM: Exynos4: remove auxdata table from machine file
With support for device tree based clock lookup now available, remove the
auxdata table from exynos4 dt-enabled machine file.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/mach-exynos4-dt.c | 69 +---
1 files changed, 2 insertions(+), 67 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index a7471ae..c02a537 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,78 +11,14 @@
* published by the Free Software Foundation.
*/
+#include linux/kernel.h
#include linux/of_platform.h
-#include linux/serial_core.h
#include asm/mach/arch.h
#include asm/hardware/gic.h
-#include mach/map.h
-
-#include plat/cpu.h
-#include plat/regs-serial.h
#include common.h
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA(samsung,exynos4210-uart, EXYNOS4_PA_UART0,
- exynos4210-uart.0, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-uart, EXYNOS4_PA_UART1,
- exynos4210-uart.1, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-uart, EXYNOS4_PA_UART2,
- exynos4210-uart.2, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-uart, EXYNOS4_PA_UART3,
- exynos4210-uart.3, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-sdhci, EXYNOS4_PA_HSMMC(0),
- exynos4-sdhci.0, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-sdhci, EXYNOS4_PA_HSMMC(1),
- exynos4-sdhci.1, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-sdhci, EXYNOS4_PA_HSMMC(2),
- exynos4-sdhci.2, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-sdhci, EXYNOS4_PA_HSMMC(3),
- exynos4-sdhci.3, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(0),
- s3c2440-i2c.0, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(1),
- s3c2440-i2c.1, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(2),
- s3c2440-i2c.2, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(3),
- s3c2440-i2c.3, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(4),
- s3c2440-i2c.4, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(5),
- s3c2440-i2c.5, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(6),
- s3c2440-i2c.6, NULL),
- OF_DEV_AUXDATA(samsung,s3c2440-i2c, EXYNOS4_PA_IIC(7),
- s3c2440-i2c.7, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-spi, EXYNOS4_PA_SPI0,
- exynos4210-spi.0, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-spi, EXYNOS4_PA_SPI1,
- exynos4210-spi.1, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-spi, EXYNOS4_PA_SPI2,
- exynos4210-spi.2, NULL),
- OF_DEV_AUXDATA(arm,pl330, EXYNOS4_PA_PDMA0, dma-pl330.0, NULL),
- OF_DEV_AUXDATA(arm,pl330, EXYNOS4_PA_PDMA1, dma-pl330.1, NULL),
- OF_DEV_AUXDATA(arm,pl330, EXYNOS4_PA_MDMA1, dma-pl330.2, NULL),
- OF_DEV_AUXDATA(samsung,exynos4210-tmu, EXYNOS4_PA_TMU,
- exynos-tmu, NULL),
- {},
-};
-
static void __init exynos4_dt_map_io(void)
{
exynos_init_io(NULL, 0);
@@ -90,8 +26,7 @@ static void __init exynos4_dt_map_io(void)
static void __init exynos4_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos4_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos4_dt_compat[] __initdata = {
--
1.7.5.4
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[PATCH v5 11/12] ARM: Exynos: use fin_pll clock as the tick clock source for mct
With the migration of Exynos4 clocks to use common clock framework, the old
styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used
as the tick clock for mct controller.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/mct.c | 14 +-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 448ce86..71e1502 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -487,10 +487,22 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
+#ifdef CONFIG_COMMON_CLK
+ struct clk *tick_clk;
+
+ tick_clk = clk_get(NULL, fin_pll);
+ if (IS_ERR(tick_clk))
+ panic(%s: unable to determine tick clock rate\n, __func__);
+ clk_rate = clk_get_rate(tick_clk);
+#else
+ /*
+* todo: remove this legacy code after adding common clock support for
+* exynos5250.
+*/
struct clk *mct_clk;
mct_clk = clk_get(NULL, xtal);
-
clk_rate = clk_get_rate(mct_clk);
+#endif
reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
if (!reg_base)
--
1.7.5.4
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[PATCH v5 12/12] ARM: Exynos: add support for mct clock setup
Add support for mct clock lookup and setup to ensure that the mct clock
is has been turned on.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/mach-exynos/mct.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 71e1502..843856f 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -488,7 +488,12 @@ static struct local_timer_ops exynos4_mct_tick_ops
__cpuinitdata = {
static void __init exynos4_timer_resources(struct device_node *np)
{
#ifdef CONFIG_COMMON_CLK
- struct clk *tick_clk;
+ struct clk *mct_clk, *tick_clk;
+
+ mct_clk = clk_get(NULL, mct);
+ if (IS_ERR(mct_clk))
+ panic(%s: unable to retrieve mct clock instance\n, __func__);
+ clk_prepare_enable(mct_clk);
tick_clk = clk_get(NULL, fin_pll);
if (IS_ERR(tick_clk))
--
1.7.5.4
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Re: [PATCH v3 0/5] ARM: Exynos: Enable device tree support for MCT controller
On Sat, Dec 29, 2012 at 12:50:33PM -0800, Thomas Abraham wrote: Changes since v2: - Rebased to linux 3.8-rc1 Changes since v1: - Includes changes suggested by Sylwester Nawrocki sylvester.nawro...@gmail.com This patch series adds device tree support for Exynos4/5 MCT controller. This patch series has been tested on Exynos4210 based Origen board, Exynos4412 based Origen board and Exynos5250 based SMDK board. Hi, Nice cleanups -- no specific comments on those at this time. But this is a good time to move the MCT driver out of arch/arm and into drivers/clocksource. Can you please do that in this series as well, please? Thanks, -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 00/12] clk: exynos4: migrate to common clock framework
On Sat, Dec 29, 2012 at 04:33:29PM -0800, Thomas Abraham wrote: Changes since v4: - Rebased to linux-3.8-rc1. Changes since v3: - Includes changes suggested by Tomasz Figa tomasz.f...@gmail.com This patch series migrates the Samsung Exynos4 SoC clock code to adopt the common clock framework. The use of Samsung specific clock structures has been removed and all board support code has been updated. imx-style of clock registration and lookup has been adopted for device tree based exynos4 platforms. I'd prefer to see if exynos4 and 5 were kept common here, and both transitioned at the same time. Especially since there are no legacy boards for exynos5, it would mean you could have a very clean transition there. What's the plan to follow up with 5? What are the plans to remove legacy board files on exynos4 at this time and switch them to DT-only? You could do it gradually like Stephen Warren did on Tegra, with hooks that call out to some of the legacy code, but configure the board through device tree and do away with the classic machine descriptors, etc. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Add missing fixed regulators on Origen board
Hi, On Fri, Dec 28, 2012 at 12:34 AM, Tushar Behera tushar.beh...@linaro.org wrote: This patchset adds vmmc and hdmi-en regulators for Origen board. Tushar Behera (2): ARM: EXYNOS: Add vmmc regulator for Origen board ARM: EXYNOS: Add hdmi-en regulator for Origen board The vmmc one seems to already be there in the dts file for origen. It looks like the HDMI one is still needed though. Please move to using DT board files instead of expanding the legacy board files. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
