[PATCH] i2c: exynos5: add High Speed I2C controller driver

2013-03-11 Thread Naveen Krishna Chatradhi 
Adds support for High Speed I2C driver found in Exynos5 and later
SoCs from Samsung. This driver currently supports Auto mode.

Driver only supports Device Tree method.
Note: Added debugfs support for registers view, not tested.

Signed-off-by: Taekgyun Ko 
Signed-off-by: Naveen Krishna Chatradhi 
Cc: R. Chandrasekar 
---
Changes since v3: http://lkml.org/lkml/2012/12/28/46
1. Added Documentation for DT bindings
2. Removed the bus_num, as Doug's pick id from DT is merged in i2c/for-next
3. Split the xfer function for better clarity.
4. Streamlined code flow in isr, handled trans_status register in xfer_msg call.

 .../devicetree/bindings/i2c/i2c-exynos5.txt|   50 ++
 drivers/i2c/busses/Kconfig |7 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-exynos5.c   |  743 
 4 files changed, 801 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
 create mode 100644 drivers/i2c/busses/i2c-exynos5.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt 
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
new file mode 100644
index 000..0bc9347
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -0,0 +1,50 @@
+* Samsung's High Speed I2C controller
+
+The Samsung's High Speed I2C controller is used to interface with I2C devices
+at various speeds ranging from 100khz to 3.4Mhz.
+
+Required properties:
+  - compatible: value should be.
+  (a) "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.
+  - reg: physical base address of the controller and length of memory mapped
+region.
+  - interrupts: interrupt number to the cpu.
+
+  - Samsung GPIO variant (deprecated):
+- gpios: The order of the gpios should be the following: .
+  The gpio specifier depends on the gpio controller.
+  - Pinctrl variant (preferred, if available):
+- pinctrl-0: Pin control group to be used for this controller.
+- pinctrl-names: Should contain only one value - "default".
+
+Optional properties:
+  - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not
+specified, default value is 0.
+  - samsung,hs-clock-freq: Desired operating frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+  - samsung,fs-clock-freq: Desired operarting frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+
+Example:
+
+   hsi2c@12ca {
+   compatible = "samsung,exynos5-hsi2c";
+   reg = <0x12ca 0x100>;
+   interrupts = <56>;
+   samsung,fs-clock-freq = <10>;
+   /* Samsung GPIO variant begins here */
+   gpios = <&gpd1 2 0 /* SDA */
+&gpd1 3 0 /* SCL */>;
+   /* Samsung GPIO variant ends here */
+   /* Pinctrl variant begins here */
+   pinctrl-0 = <&i2c4_bus>;
+   pinctrl-names = "default";
+   /* Pinctrl variant ends here */
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   s2mps11_pmic@66 {
+   compatible = "samsung,s2mps11-pmic";
+   reg = <0x66>;
+   };
+   };
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3725de..78b4936 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -434,6 +434,13 @@ config I2C_EG20T
  ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
  ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
 
+config I2C_EXYNOS5
+   tristate "Exynos5 high-speed I2C driver"
+   depends on ARCH_EXYNOS5 && OF
+   help
+ Say Y here to include support for High-speed I2C controller in the
+ Exynos5 based Samsung SoCs.
+
 config I2C_GPIO
tristate "GPIO-based bitbanging I2C"
depends on GENERIC_GPIO
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..b19366c 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
 obj-$(CONFIG_I2C_DESIGNWARE_PCI)   += i2c-designware-pci.o
 i2c-designware-pci-objs := i2c-designware-pcidrv.o
 obj-$(CONFIG_I2C_EG20T)+= i2c-eg20t.o
+obj-$(CONFIG_I2C_EXYNOS5)  += i2c-exynos5.o
 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
 obj-$(CONFIG_I2C_IBM_IIC)  += i2c-ibm_iic.o
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
new file mode 100644
index 000..fe30b0b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -0,0 +1,743 @@
+/**
+ * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you ca

[PATCH 7/7] DO_NOT_APPLY: convert s3c2416 to use the common clock framework

2013-03-11 Thread Heiko Stübner 
Switch the s3c2416 and smdk2416 from using the Samsung clocks to
the common clock framework. This is not meant to be the final result,
as it uses the temporary pwm clocks and the clock init itself also
needs changes, especially as the _init_time function stolen from exynos
is currently board specific due to the xtal frequency which needs
to be set.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/mach-s3c24xx/Kconfig  |2 +-
 arch/arm/mach-s3c24xx/Makefile |2 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c  |  173 
 arch/arm/mach-s3c24xx/common-s3c2443.c |   10 ++
 arch/arm/mach-s3c24xx/common.h |9 ++
 arch/arm/mach-s3c24xx/mach-smdk2416.c  |9 ++-
 6 files changed, 28 insertions(+), 177 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0a8663c..351c198 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -54,7 +54,7 @@ config CPU_S3C2416
select S3C2416_PM if PM
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
-   select SAMSUNG_CLKSRC
+   select COMMON_CLK
select SAMSUNG_HRT
help
  Support for the S3C2416 SoC from the S3C24XX line
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index be6e4d0..820524e 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)   += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
 
-obj-$(CONFIG_CPU_S3C2416)  += s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)  += s3c2416.o
 obj-$(CONFIG_S3C2416_PM)   += pm-s3c2416.o
 
 obj-$(CONFIG_CPU_S3C2440)  += s3c2440.o clock-s3c2440.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c 
b/arch/arm/mach-s3c24xx/clock-s3c2416.c
deleted file mode 100644
index 036056ce..000
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/clock.c
- *
- * Copyright (c) 2010 Simtec Electronics
- * Copyright (c) 2010 Ben Dooks 
- *
- * S3C2416 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include 
-#include 
-
-#include 
-#include 
-#include 
-
-#include 
-#include 
-
-#include 
-
-#include 
-#include 
-
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
- * The real clock definition is done in s3c2443-clock.c,
- * only the armdiv divisor table must be defined here.
-*/
-
-static unsigned int armdiv[8] = {
-   [0] = 1,
-   [1] = 2,
-   [2] = 3,
-   [3] = 4,
-   [5] = 6,
-   [7] = 8,
-};
-
-static struct clksrc_clk hsspi_eplldiv = {
-   .clk = {
-   .name   = "hsspi-eplldiv",
-   .parent = &clk_esysclk.clk,
-   .ctrlbit = (1 << 14),
-   .enable = s3c2443_clkcon_enable_s,
-   },
-   .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
-};
-
-static struct clk *hsspi_sources[] = {
-   [0] = &hsspi_eplldiv.clk,
-   [1] = NULL, /* to fix */
-};
-
-static struct clksrc_clk hsspi_mux = {
-   .clk= {
-   .name   = "hsspi-if",
-   },
-   .sources = &(struct clksrc_sources) {
-   .sources = hsspi_sources,
-   .nr_sources = ARRAY_SIZE(hsspi_sources),
-   },
-   .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
-};
-
-static struct clksrc_clk hsmmc_div[] = {
-   [0] = {
-   .clk = {
-   .name   = "hsmmc-div",
-   .devname= "s3c-sdhci.0",
-   .parent = &clk_esysclk.clk,
-   },
-   .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
-   },
-   [1] = {
-   .clk = {
-   .name   = "hsmmc-div",
-   .devname= "s3c-sdhci.1",
-   .parent = &clk_esysclk.clk,
-   },
-   .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
-   },
-};
-
-static struct clksrc_clk hsmmc_mux0 = {
-   .clk= {
-   .name   = "hsmmc-if",
-   .devname= "s3c-sdhci.0",
-   .ctrlbit= (1 << 6),
-   .enable = s3c2443_clkcon_enable_s,
-   },
-   .sources= &(struct clksrc_sources) {
-   .nr_sources = 2,
-   .sources= (struct clk * []) {
-   [0] = &hsmmc_div[0].clk,
-   [1] = NULL, /* to fix */
-

[PATCH 6/7] ARM: SAMSUNG: use clk_prepare_enable in samsung-time

2013-03-11 Thread Heiko Stübner 
The common clock framework expects clocks to be prepared
before they are enabled.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/plat-samsung/samsung-time.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-samsung/samsung-time.c 
b/arch/arm/plat-samsung/samsung-time.c
index f899cbc..6ebb851 100644
--- a/arch/arm/plat-samsung/samsung-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -355,7 +355,7 @@ static void __init samsung_timer_resources(void)
if (IS_ERR(timerclk))
panic("failed to get timers clock for timer");
 
-   clk_enable(timerclk);
+   clk_prepare_enable(timerclk);
 
sprintf(devname, "s3c24xx-pwm.%lu", event_id);
s3c_device_timer[event_id].id = event_id;
@@ -369,7 +369,7 @@ static void __init samsung_timer_resources(void)
if (IS_ERR(tdiv_event))
panic("failed to get pwm-tdiv clock for event timer");
 
-   clk_enable(tin_event);
+   clk_prepare_enable(tin_event);
 
sprintf(devname, "s3c24xx-pwm.%lu", source_id);
s3c_device_timer[source_id].id = source_id;
@@ -383,7 +383,7 @@ static void __init samsung_timer_resources(void)
if (IS_ERR(tdiv_source))
panic("failed to get pwm-tdiv clock for source timer");
 
-   clk_enable(tin_source);
+   clk_prepare_enable(tin_source);
 }
 
 void __init samsung_timer_init(void)
-- 
1.7.2.3

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[PATCH 5/7] DO_NOT_APPLY: add clock driver for Samsung pwm clocks

2013-03-11 Thread Heiko Stübner 
This ports the pwm-clock code from plat-samsung to the common clock
framework to make available the pwm clocks used by samsung-time and
the samsung pwm driver.

This is needed to enable the usage of the samsung-time clocksource
when using the common clock framework on s3c arches but the correct
solution will be in the upcoming time/pwm driver which will handle
the pwm clocks itself.

Signed-off-by: Heiko Stuebner 
---
 drivers/clk/samsung/Makefile  |2 +-
 drivers/clk/samsung/clk-pwm.c |  554 +
 2 files changed, 555 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/samsung/clk-pwm.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 7462ec5..0f227c3 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,4 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
-obj-$(CONFIG_S3C2443_COMMON)   += clk-s3c2443.o
+obj-$(CONFIG_S3C2443_COMMON)   += clk-s3c2443.o clk-pwm.o
diff --git a/drivers/clk/samsung/clk-pwm.c b/drivers/clk/samsung/clk-pwm.c
new file mode 100644
index 000..19142e8
--- /dev/null
+++ b/drivers/clk/samsung/clk-pwm.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2007 Simtec Electronics
+ * Copyright (c) 2007, 2008 Ben Dooks
+ * Ben Dooks 
+ * Copyright (c) 2013 Heiko Stuebner 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * Common Clock Framework support for Samsung pwm clocks
+*/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "clk.h"
+
+/* Each of the timers 0 through 5 go through the following
+ * clock tree, with the inputs depending on the timers.
+ *
+ * pclk  [ prescaler 0 ] -+---> timer 0
+ *   +---> timer 1
+ *
+ * pclk  [ prescaler 1 ] -+---> timer 2
+ *   +---> timer 3
+ *   \---> timer 4
+ *
+ * Which are fed into the timers as so:
+ *
+ * prescaled 0  [ div 2,4,8,16 ] ---\
+ *[mux] -> timer 0
+ * tclk 0 --/
+ *
+ * prescaled 0  [ div 2,4,8,16 ] ---\
+ *[mux] -> timer 1
+ * tclk 0 --/
+ *
+ *
+ * prescaled 1  [ div 2,4,8,16 ] ---\
+ *[mux] -> timer 2
+ * tclk 1 --/
+ *
+ * prescaled 1  [ div 2,4,8,16 ] ---\
+ *[mux] -> timer 3
+ * tclk 1 --/
+ *
+ * prescaled 1  [ div 2,4,8, 16 ] --\
+ *[mux] -> timer 4
+ * tclk 1 --/
+ *
+ * Since the mux and the divider are tied together in the
+ * same register space, it is impossible to set the parent
+ * and the rate at the same time. To avoid this, we add an
+ * intermediate 'prescaled-and-divided' clock to select
+ * as the parent for the timer input clock called tdiv.
+ *
+ * prescaled clk --> pwm-tdiv ---\
+ * [ mux ] --> timer X
+ * tclk -/
+*/
+
+enum pwm_clks {
+   none,
+
+   tclk0, tclk1, tdiv0, tdiv1, tdiv2, tdiv3, tdiv4,
+   tin0, tin1, tin2, tin3, tin4,
+
+   nr_clks,
+};
+
+/* the soc types */
+enum supported_socs {
+   S3C24XX,
+   S3C64XX, /* also S5PC100 */
+   S5P64XX,
+};
+
+/* clock controller register offsets */
+#define TCFG0  0
+#define TCFG1  0x4
+
+static DEFINE_SPINLOCK(lock);
+static int current_soc;
+static void __iomem *reg_base;
+static struct clk **clk_table;
+#ifdef CONFIG_OF
+static struct clk_onecell_data clk_data;
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump reg_dump[2] = {
+   { .offset = TCFG0 },
+   { .offset = TCFG1 },
+};
+
+static int samsung_clk_pwm_suspend(void)
+{
+   reg_dump[0].value = readl_relaxed(reg_base + reg_dump[0].offset);
+   reg_dump[1].value = readl_relaxed(reg_base + reg_dump[1].offset);
+   return 0;
+}
+
+static void samsung_clk_pwm_resume(void)
+{
+   writel_relaxed(reg_dump[0].value, reg_base + reg_dump[0].offset);
+   writel_relaxed(reg_dump[1].value, reg_base + reg_dump[1].offset);
+}
+
+static struct syscore_ops samsung_clk_pwm_syscore_ops = {
+   .suspend= samsung_clk_pwm_suspend,
+   .resume = samsung_clk_pwm_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+#define S3C2410_TCFG1_MUX_TCLK(4 << 0)
+#define S3C64XX_TCFG1_MUX_TCLK(5 << 0)
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given c

[PATCH 4/7] clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450

2013-03-11 Thread Heiko Stübner 
The three SoCs share a common clock tree which only differs in the
existence of some special clocks. The s3c2450 specific clocks will
only be reachable via DT in the near future, as there is no generic
way to distinguish between the similar s3c2416 and s3c2450 SoCs.

As with all parts common to these three SoCs the driver is named
after the s3c2443, as it was the first SoC introducing this structure
and there exists no other label to describe this s3c24xx epoch.

The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure. As an example the sclk_uart was never handled previously and
the div_uart was made the clock used by the serial driver.

Signed-off-by: Heiko Stuebner 
---
 drivers/clk/samsung/Makefile  |1 +
 drivers/clk/samsung/clk-s3c2443.c |  463 +
 2 files changed, 464 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..7462ec5 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
+obj-$(CONFIG_S3C2443_COMMON)   += clk-s3c2443.o
diff --git a/drivers/clk/samsung/clk-s3c2443.c 
b/drivers/clk/samsung/clk-s3c2443.c
new file mode 100644
index 000..45681f1
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for S3C2416 SoCs.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include "clk.h"
+#include "clk-pll.h"
+
+/* S3C2416 clock controller register offsets */
+#define MPLLCON0x10
+#define EPLLCON0x18
+#define EPLLCON_K  0x1C
+#define CLKSRC 0x20
+#define CLKDIV00x24
+#define CLKDIV10x28
+#define CLKDIV20x2C
+#define HCLKCON0x30
+#define PCLKCON0x34
+#define SCLKCON0x38
+
+/* the soc types */
+enum supported_socs {
+   S3C2416,
+   S3C2443,
+   S3C2450,
+};
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the 
clock
+ * for device tree based platforms. The clocks are categorized into four
+ * sections: core, sclk gate, bus interface gate and mux clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum s3c2443_clks {
+   none,
+
+   /* core clocks */
+   xti, ext, ext_i2s, ext_uart, msysclk, esysclk, armdiv, armclk, hclk,
+
+   /* gate for special clocks (sclk) */
+   sclk_hsspi0 = 128, sclk_fimd, sclk_i2s0, sclk_i2s1, sclk_hsmmc1,
+   sclk_hsmmcext, sclk_cam, sclk_uart, sclk_usbh,
+
+   /* gate clocks */
+   hsmmc0 = 256, hsmmc1, nand, ssmc, usbh, usbd, lcd, dma0, dma1, dma2,
+   dma3, dma4, dma5, dma6, dma7, gpio, rtc, wdt, pwm, i2s0, i2s1, ac97,
+   pcm, adc, spi0, spi1, i2c0, i2c1, uart0, uart1, uart2, uart3, cfc,
+   sdi, cam, chipid,
+
+   /* mux clocks */
+   mux_hsspi0 = 384, mux_hsspi1, mux_hsmmc0, mux_hsmmc1,
+
+   nr_clks,
+};
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long s3c2443_clk_regs[] = {
+   MPLLCON,
+   EPLLCON,
+   EPLLCON_K,
+   CLKSRC,
+   CLKDIV0,
+   CLKDIV1,
+   CLKDIV2,
+   PCLKCON,
+   HCLKCON,
+   SCLKCON,
+};
+
+PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
+PNAME(esysclk_p) = { "epllref", "epll" };
+PNAME(msysclk_p) = { "mpllref, mdivclk", "mpll", "mpll" };
+PNAME(armclk_p) = { "armdiv" , "hclk" };
+PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
+   FRATE(xti, "xti", NULL, CLK_IS_ROOT, 0),
+   FRATE(ext, "ext", NULL, CLK_IS_ROOT, 0),
+   FRATE(ext_i2s, "ext_i2s", NULL, CLK_IS_ROOT, 0),
+   FRATE(ext_uart, "ext_uart", NULL, CLK_IS_ROOT, 0),
+};
+
+/* mpllref is a direct descendant of clk_xtal by default, but it is not
+ * elided as the EPLL can be either sourced

[PATCH 3/7] ARM: S3C24XX: enable legacy clock code only when SAMSUNG_CLOCK selected

2013-03-11 Thread Heiko Stübner 
This enables a smooth transition, as not all S3C24XX SoCs need to be
converted at the same time and can instead simply exchange their
select SAMSUNG_CLOCK with a select COMMON_CLK after the conversion.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/mach-s3c24xx/common-s3c2443.c |2 ++
 arch/arm/mach-s3c24xx/common.c |2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c 
b/arch/arm/mach-s3c24xx/common-s3c2443.c
index f6b9f2e..b5bbeb7 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -28,6 +28,7 @@
 #include 
 
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
 {
u32 ctrlbit = clk->ctrlbit;
@@ -673,3 +674,4 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn 
get_mpll,
 
s3c2443_common_setup_clocks(get_mpll);
 }
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index d97533d..9131eb2 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -285,6 +285,7 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] 
__initdata = {
 
 /* initialise all the clocks */
 
+#ifdef CONFIG_SAMSUNG_CLOCK
 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
   unsigned long hclk,
   unsigned long pclk)
@@ -297,3 +298,4 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long 
fclk,
clk_p.rate = pclk;
clk_f.rate = fclk;
 }
+#endif
-- 
1.7.2.3

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[PATCH 2/7] ARM: S3C24XX: add soc_is_s3c2416 and soc_is_s3c2443

2013-03-11 Thread Heiko Stübner 
This is needed to distinguish between them during at least the clock init.

Signed-off-by: Heiko Stuebner 
---
 arch/arm/plat-samsung/include/plat/cpu.h |   20 
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/cpu.h 
b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe..33dad1c 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -26,6 +26,12 @@ extern unsigned long samsung_cpu_id;
 #define S3C2412_CPU_ID 0x32412000
 #define S3C2412_CPU_MASK   0xF000
 
+#define S3C2416_CPU_ID 0x3245
+#define S3C2416_CPU_MASK   0xF000
+
+#define S3C2443_CPU_ID 0x32443000
+#define S3C2443_CPU_MASK   0xF000
+
 #define S3C6400_CPU_ID 0x3640
 #define S3C6410_CPU_ID 0x3641
 #define S3C64XX_CPU_MASK   0xF000
@@ -57,6 +63,8 @@ static inline int is_samsung_##name(void) \
 
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2416, S3C2416_CPU_ID, S3C2416_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2443, S3C2443_CPU_ID, S3C2443_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
@@ -84,6 +92,18 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, 
EXYNOS5_SOC_MASK)
 # define soc_is_s3c2412()  0
 #endif
 
+#if defined(CONFIG_CPU_S3C2416)
+# define soc_is_s3c2416()  is_samsung_s3c2416()
+#else
+# define soc_is_s3c2416()  0
+#endif
+
+#if defined(CONFIG_CPU_S3C2443)
+# define soc_is_s3c2443()  is_samsung_s3c2443()
+#else
+# define soc_is_s3c2443()  0
+#endif
+
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
 # define soc_is_s3c64xx()  (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
-- 
1.7.2.3

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[PATCH 1/7] clk: samsung: add plls used in s3c2416 and s3c2443

2013-03-11 Thread Heiko Stübner 
This adds support for pll2126x, pll3000x, pll6552x and pll6553x.

Signed-off-by: Heiko Stuebner 
---
 drivers/clk/samsung/clk-pll.c |  376 +
 drivers/clk/samsung/clk-pll.h |8 +
 2 files changed, 384 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4b24511..b772f9e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -400,6 +400,97 @@ struct clk * __init samsung_clk_register_pll46xx(const 
char *name,
 }
 
 /*
+ * PLL2126x Clock Type
+ */
+
+#define PLL2126X_MDIV_MASK (0xFF)
+#define PLL2126X_PDIV_MASK (0x3)
+#define PLL2126X_SDIV_MASK (0x3)
+#define PLL2126X_MDIV_SHIFT(16)
+#define PLL2126X_PDIV_SHIFT(8)
+#define PLL2126X_SDIV_SHIFT(0)
+
+struct samsung_clk_pll2126x {
+   struct clk_hw   hw;
+   const void __iomem  *con_reg;
+};
+
+#define to_clk_pll2126x(_hw) container_of(_hw, struct samsung_clk_pll2126x, hw)
+
+static unsigned long samsung_pll2126x_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct samsung_clk_pll2126x *pll = to_clk_pll2126x(hw);
+   u32 pll_con, mdiv, pdiv, sdiv;
+   u64 fvco = parent_rate;
+
+   pll_con = __raw_readl(pll->con_reg);
+   mdiv = (pll_con >> PLL2126X_MDIV_SHIFT) & PLL2126X_MDIV_MASK;
+   pdiv = (pll_con >> PLL2126X_PDIV_SHIFT) & PLL2126X_PDIV_MASK;
+   sdiv = (pll_con >> PLL2126X_SDIV_SHIFT) & PLL2126X_SDIV_MASK;
+
+   fvco *= (mdiv + 8);
+   do_div(fvco, (pdiv + 2) << sdiv);
+
+   return (unsigned long)fvco;
+}
+
+/* todo: implement pll2126x clock round rate operation */
+static long samsung_pll2126x_round_rate(struct clk_hw *hw,
+   unsigned long drate, unsigned long *prate)
+{
+   return -ENOTSUPP;
+}
+
+/* todo: implement pll2126x clock set rate */
+static int samsung_pll2126x_set_rate(struct clk_hw *hw, unsigned long drate,
+   unsigned long prate)
+{
+   return -ENOTSUPP;
+}
+
+static const struct clk_ops samsung_pll2126x_clk_ops = {
+   .recalc_rate = samsung_pll2126x_recalc_rate,
+   .round_rate = samsung_pll2126x_round_rate,
+   .set_rate = samsung_pll2126x_set_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2126x(const char *name,
+   const char *pname, const void __iomem *con_reg)
+{
+   struct samsung_clk_pll2126x *pll;
+   struct clk *clk;
+   struct clk_init_data init;
+
+   pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+   if (!pll) {
+   pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+   return NULL;
+   }
+
+   init.name = name;
+   init.ops = &samsung_pll2126x_clk_ops;
+   init.flags = CLK_GET_RATE_NOCACHE;
+   init.parent_names = &pname;
+   init.num_parents = 1;
+
+   pll->hw.init = &init;
+   pll->con_reg = con_reg;
+
+   clk = clk_register(NULL, &pll->hw);
+   if (IS_ERR(clk)) {
+   pr_err("%s: failed to register pll clock %s\n", __func__,
+   name);
+   kfree(pll);
+   }
+
+   if (clk_register_clkdev(clk, name, NULL))
+   pr_err("%s: failed to register lookup for %s", __func__, name);
+
+   return clk;
+}
+
+/*
  * PLL2550x Clock Type
  */
 
@@ -497,3 +588,288 @@ struct clk * __init samsung_clk_register_pll2550x(const 
char *name,
 
return clk;
 }
+
+/*
+ * PLL3000x Clock Type
+ */
+
+#define PLL3000X_MDIV_MASK (0xFF)
+#define PLL3000X_PDIV_MASK (0x3)
+#define PLL3000X_SDIV_MASK (0x3)
+#define PLL3000X_MDIV_SHIFT(16)
+#define PLL3000X_PDIV_SHIFT(8)
+#define PLL3000X_SDIV_SHIFT(0)
+
+struct samsung_clk_pll3000x {
+   struct clk_hw   hw;
+   const void __iomem  *con_reg;
+};
+
+#define to_clk_pll3000x(_hw) container_of(_hw, struct samsung_clk_pll3000x, hw)
+
+static unsigned long samsung_pll3000x_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct samsung_clk_pll3000x *pll = to_clk_pll3000x(hw);
+   u32 pll_con, mdiv, pdiv, sdiv;
+   u64 fvco = parent_rate;
+
+   pll_con = __raw_readl(pll->con_reg);
+   mdiv = (pll_con >> PLL3000X_MDIV_SHIFT) & PLL3000X_MDIV_MASK;
+   pdiv = (pll_con >> PLL3000X_PDIV_SHIFT) & PLL3000X_PDIV_MASK;
+   sdiv = (pll_con >> PLL3000X_SDIV_SHIFT) & PLL3000X_SDIV_MASK;
+
+   fvco *= (2 * (mdiv + 8));
+   do_div(fvco, pdiv << sdiv);
+
+   return (unsigned long)fvco;
+}
+
+/* todo: implement pll3000x clock round rate operation */
+static long samsung_pll3000x_round_rate(struct clk_hw *hw,
+   unsigned long drate, unsigned long *prate)
+{
+   return -ENOTSUPP;
+}
+
+/* todo: implement pll3000x clock set rate */
+static int samsung_pll3000x_set_rate(struct clk_hw *hw, unsigned long drate,
+

[PATCH 0/7] ARM: S3C24XX: Convert S3C2416 to common clock framework

2013-03-11 Thread Heiko Stübner 
Due to the upcoming change in pwm/samsung-time handling, this series is meant
as mere discussion source. Nevertheless applied to the current linux-samsung
for-next it sucessfully enables the s3c2416 to use the common clock framework.

This series is dependant on the previous samsung-clock fixes and obviously
tested on a s3c2416.

Heiko Stuebner (7):
  clk: samsung: add plls used in s3c2416 and s3c2443
  ARM: S3C24XX: add soc_is_s3c2416 and soc_is_s3c2443
  ARM: S3C24XX: enable legacy clock code only when SAMSUNG_CLOCK selected
  clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
  DO_NOT_APPLY: add clock driver for Samsung pwm clocks
  ARM: SAMSUNG: use clk_prepare_enable in samsung-time
  DO_NOT_APPLY: convert s3c2416 to use the common clock framework

 arch/arm/mach-s3c24xx/Kconfig|2 +-
 arch/arm/mach-s3c24xx/Makefile   |2 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c|  173 --
 arch/arm/mach-s3c24xx/common-s3c2443.c   |   12 +
 arch/arm/mach-s3c24xx/common.c   |2 +
 arch/arm/mach-s3c24xx/common.h   |9 +
 arch/arm/mach-s3c24xx/mach-smdk2416.c|9 +-
 arch/arm/plat-samsung/include/plat/cpu.h |   20 +
 arch/arm/plat-samsung/samsung-time.c |6 +-
 drivers/clk/samsung/Makefile |1 +
 drivers/clk/samsung/clk-pll.c|  376 
 drivers/clk/samsung/clk-pll.h|8 +
 drivers/clk/samsung/clk-pwm.c|  554 ++
 drivers/clk/samsung/clk-s3c2443.c|  463 +
 14 files changed, 1457 insertions(+), 180 deletions(-)
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 create mode 100644 drivers/clk/samsung/clk-pwm.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c

-- 
1.7.2.3

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[PATCH 4/4] clk: samsung: add infrastructure to add separate aliases

2013-03-11 Thread Heiko Stübner 
The current code adds aliases, if necessary, directly when adding the clock,
limiting the number of possible aliases to one.

Some platforms need more than one alias, like the hsmmc pclocks on s3c2416
which need a "hsmmc" and "mmc_busclk.0" alias for the s3c-sdhci driver.

Therefore add the possibility to separately add clock aliases for previously
created clocks.

Signed-off-by: Heiko Stuebner 
---
change since the discussion: removed the list->alias check

 drivers/clk/samsung/clk.c |   33 +
 drivers/clk/samsung/clk.h |   21 +
 2 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 7c943f8..20ec566 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -94,6 +94,39 @@ void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
clk_table[id] = clk;
 }
 
+/* register a list of aliases */
+void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
+   unsigned int nr_clk)
+{
+   struct clk *clk;
+   unsigned int idx, ret;
+
+   if (!clk_table) {
+   pr_err("%s: clock table missing\n", __func__);
+   return;
+   }
+
+   for (idx = 0; idx < nr_clk; idx++, list++) {
+   if (!list->id) {
+   pr_err("%s: clock id missing for index %d\n", __func__,
+   idx);
+   continue;
+   }
+
+   clk = clk_table[list->id];
+   if (!clk) {
+   pr_err("%s: failed to find clock %d\n", __func__,
+   list->id);
+   continue;
+   }
+
+   ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+   if (ret)
+   pr_err("%s: failed to register lookup %s\n",
+   __func__, list->alias);
+   }
+}
+
 /* register a list of fixed clocks */
 void __init samsung_clk_register_fixed_rate(
struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 26a752b..6bacd6f 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -23,6 +23,25 @@
 #include 
 
 /**
+ * struct samsung_clock_alias: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_clock_alias {
+   unsigned intid;
+   const char  *dev_name;
+   const char  *alias;
+};
+
+#define ALIAS(_id, dname, a)   \
+   {   \
+   .id = _id,  \
+   .dev_name   = dname,\
+   .alias  = a,\
+   }
+
+/**
  * struct samsung_fixed_rate_clock: information about fixed-rate clock
  * @id: platform specific id of the clock.
  * @name: name of this fixed-rate clock.
@@ -251,6 +270,8 @@ extern void __init samsung_clk_of_register_fixed_ext(
 
 extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
 
+extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
+   unsigned int nr_clk);
 extern void __init samsung_clk_register_fixed_rate(
struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
 extern void __init samsung_clk_register_fixed_factor(
-- 
1.7.2.3

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[PATCH 3/4] clk: samsung: always allocate the clk_table

2013-03-11 Thread Heiko Stübner 
This is needed to allow looking up previous created clocks when
adding separate aliases to them.

Signed-off-by: Heiko Stuebner 
---
 drivers/clk/samsung/clk.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 1a5de69..7c943f8 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -58,11 +58,11 @@ void __init samsung_clk_init(struct device_node *np, void 
__iomem *base,
 {
reg_base = base;
 
-#ifdef CONFIG_OF
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
if (!clk_table)
panic("could not allocate clock lookup table\n");
 
+#ifdef CONFIG_OF
clk_data.clks = clk_table;
clk_data.clk_num = nr_clks;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-- 
1.7.2.3

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[PATCH 2/4] clk: samsung: remove np check in clock init

2013-03-11 Thread Heiko Stübner 
This let to the suspend init never being reached on non-DT platforms.

Signed-off-by: Heiko Stueber 
---
 drivers/clk/samsung/clk.c |2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index d36cdd5..1a5de69 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -57,8 +57,6 @@ void __init samsung_clk_init(struct device_node *np, void 
__iomem *base,
unsigned long nr_rdump)
 {
reg_base = base;
-   if (!np)
-   return;
 
 #ifdef CONFIG_OF
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
-- 
1.7.2.3

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[PATCH 1/4] clk: samsung: register clk_div_tables for divider clocks

2013-03-11 Thread Heiko Stübner 
On some Samsung platforms divider clocks only use specific divider combinations
like the armdiv on s3c2443 and s3c2416. For these usecases the generic divider
clock already provides the option of providing a lookup table mapping register
values to divider values.

Therefore add a new field to samsung_div_clock and if filled with a table,
use clk_register_divider_table instead of clk_register_divider to register
a divider clock

Signed-off-by: Heiko Stuebner 
---
 drivers/clk/samsung/clk.c |   14 +++---
 drivers/clk/samsung/clk.h |   13 +
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 91d12f3..d36cdd5 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -183,9 +183,17 @@ void __init samsung_clk_register_div(struct 
samsung_div_clock *list,
unsigned int idx, ret;
 
for (idx = 0; idx < nr_clk; idx++, list++) {
-   clk = clk_register_divider(NULL, list->name, list->parent_name,
-   list->flags, reg_base + list->offset, list->shift,
-   list->width, list->div_flags, &lock);
+   if (list->table)
+   clk = clk_register_divider_table(NULL, list->name,
+   list->parent_name, list->flags,
+   reg_base + list->offset, list->shift,
+   list->width, list->div_flags,
+   list->table, &lock);
+   else
+   clk = clk_register_divider(NULL, list->name,
+   list->parent_name, list->flags,
+   reg_base + list->offset, list->shift,
+   list->width, list->div_flags, &lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 961192f..26a752b 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -150,9 +150,10 @@ struct samsung_div_clock {
u8  width;
u8  div_flags;
const char  *alias;
+   struct clk_div_table*table;
 };
 
-#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a) \
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)  \
{   \
.id = _id,  \
.dev_name   = dname,\
@@ -164,16 +165,20 @@ struct samsung_div_clock {
.width  = w,\
.div_flags  = df,   \
.alias  = a,\
+   .table  = t,\
}
 
 #define DIV(_id, cname, pname, o, s, w)\
-   __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL)
+   __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
 
 #define DIV_A(_id, cname, pname, o, s, w, a)   \
-   __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a)
+   __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
 
 #define DIV_F(_id, cname, pname, o, s, w, f, df)   \
-   __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL)
+   __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+
+#define DIV_T(_id, cname, pname, o, s, w, t)   \
+   __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
 
 /**
  * struct samsung_gate_clock: information about gate clock
-- 
1.7.2.3

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[PATCH 0/4] clk: samsung: small fixes and enhancements

2013-03-11 Thread Heiko Stübner 
Small fixes and enhancements that came up when implementing the
common clock support for s3c2443, s3c2416 and s3c2450.

The 3rd and 4th patch enable the adding of separate aliases
to previously defined clocks, as discussed with Sylwester Nawrocki.

This is often needed as some clocks need more than one alias. The hsmmc
hclks on s3c2416 for example are both "hsmmc" and "mmc_busclk.0" .

These changes are required for the common clock conversion of s3c24xx SoCs.

Heiko Stuebner (4):
  clk: samsung: register clk_div_tables for divider clocks
  clk: samsung: remove np check in clock init
  clk: samsung: always allocate the clk_table
  clk: samsung: add infrastructure to add separate aliases

 drivers/clk/samsung/clk.c |   51 +++-
 drivers/clk/samsung/clk.h |   34 ++---
 2 files changed, 75 insertions(+), 10 deletions(-)

-- 
1.7.2.3

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Re: [PATCH 1/2] ARM: exynos: pl330: Add #dma-cells for generic dma binding support

2013-03-11 Thread Arnd Bergmann 
On Thursday 07 March 2013, Kukjin Kim wrote:
> > Can you please take this patch in 3.9 rc2 ?
> > 
> Sure, I will.
> 
> BTW, Arnd, I'm not sure second one(socfpga.dtsi) can be handled in samsung
> tree.

I guess you're right, I've applied the second one to the fixes branch now.

Thanks,

Arnd
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[RFC PATCH 8/8] s5p-fimc: Create media links for the FIMC-IS entities

2013-03-11 Thread Sylwester Nawrocki 
Create disabled links from the FIMC-LITE subdevs to the FIMC-IS-ISP
subdev and from FIMC-IS-ISP to all FIMC subdevs.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   78 +++-
 1 file changed, 62 insertions(+), 16 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index 1521dec..5304da5 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -807,9 +807,17 @@ static int __fimc_md_create_fimc_sink_links(struct fimc_md 
*fmd,
struct fimc_sensor_info *s_info = NULL;
struct media_entity *sink;
unsigned int flags = 0;
-   int ret, i;
+   int i, ret = 0;
 
-   for (i = 0; i < FIMC_MAX_DEVS; i++) {
+   if (sensor) {
+   s_info = v4l2_get_subdev_hostdata(sensor);
+   /* Skip direct FIMC links in the logical FIMC-IS sensor path */
+   if (s_info && s_info->pdata.fimc_bus_type ==
+   FIMC_BUS_TYPE_ISP_WRITEBACK)
+   ret = 1;
+   }
+
+   for (i = 0; !ret && i < FIMC_MAX_DEVS; i++) {
if (!fmd->fimc[i])
continue;
/*
@@ -838,7 +846,7 @@ static int __fimc_md_create_fimc_sink_links(struct fimc_md 
*fmd,
 
if (flags == 0 || sensor == NULL)
continue;
-   s_info = v4l2_get_subdev_hostdata(sensor);
+
if (!WARN_ON(s_info == NULL)) {
unsigned long irq_flags;
spin_lock_irqsave(&fmd->slock, irq_flags);
@@ -851,25 +859,20 @@ static int __fimc_md_create_fimc_sink_links(struct 
fimc_md *fmd,
if (!fmd->fimc_lite[i])
continue;
 
-   if (link_mask & (1 << (i + FIMC_MAX_DEVS)))
-   flags = MEDIA_LNK_FL_ENABLED;
-   else
-   flags = 0;
-
sink = &fmd->fimc_lite[i]->subdev.entity;
ret = media_entity_create_link(source, pad, sink,
-  FLITE_SD_PAD_SINK, flags);
+  FLITE_SD_PAD_SINK, 0);
if (ret)
return ret;
 
/* Notify FIMC-LITE subdev entity */
ret = media_entity_call(sink, link_setup, &sink->pads[0],
-   &source->pads[pad], flags);
+   &source->pads[pad], 0);
if (ret)
break;
 
-   v4l2_info(&fmd->v4l2_dev, "created link [%s] %c> [%s]\n",
- source->name, flags ? '=' : '-', sink->name);
+   v4l2_info(&fmd->v4l2_dev, "created link [%s] -> [%s]\n",
+ source->name, sink->name);
}
return 0;
 }
@@ -878,26 +881,59 @@ static int __fimc_md_create_fimc_sink_links(struct 
fimc_md *fmd,
 static int __fimc_md_create_flite_source_links(struct fimc_md *fmd)
 {
struct media_entity *source, *sink;
-   unsigned int flags = MEDIA_LNK_FL_ENABLED;
int i, ret = 0;
 
for (i = 0; i < FIMC_LITE_MAX_DEVS; i++) {
struct fimc_lite *fimc = fmd->fimc_lite[i];
+
if (fimc == NULL)
continue;
+
source = &fimc->subdev.entity;
sink = &fimc->vfd.entity;
/* FIMC-LITE's subdev and video node */
ret = media_entity_create_link(source, FLITE_SD_PAD_SOURCE_DMA,
-  sink, 0, flags);
+  sink, 0, 0);
+   if (ret)
+   break;
+   /* Link from FIMC-LITE to IS-ISP subdev */
+   sink = &fmd->fimc_is->isp.subdev.entity;
+   ret = media_entity_create_link(source, FLITE_SD_PAD_SOURCE_ISP,
+  sink, 0, 0);
if (ret)
break;
-   /* TODO: create links to other entities */
}
 
return ret;
 }
 
+/* Create FIMC-IS links */
+static int __fimc_md_create_fimc_is_links(struct fimc_md *fmd)
+{
+   struct media_entity *source, *sink;
+   int i, ret;
+
+   source = &fmd->fimc_is->isp.subdev.entity;
+
+   for (i = 0; i < FIMC_MAX_DEVS; i++) {
+   if (fmd->fimc[i] == NULL)
+   continue;
+
+   /* Link from IS-ISP subdev to FIMC */
+   sink = &fmd->fimc[i]->vid_cap.subdev.entity;
+   ret = media_entity_create_link(source, FIMC_IS_SD_PAD_SRC_FIFO,
+  sink, FIMC_SD_PAD_SINK_FIFO, 0);
+   if (ret)
+   return ret;
+   }
+
+   /* Link from IS-ISP subdev

[RFC PATCH 6/8] fimc-is: Add Exynos4x12 FIMC-IS device tree bindings documentation

2013-03-11 Thread Sylwester Nawrocki 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 .../devicetree/bindings/media/exynos4-fimc-is.txt  |   41 
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos4-fimc-is.txt

diff --git a/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt 
b/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt
new file mode 100644
index 000..ef994d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt
@@ -0,0 +1,41 @@
+Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
+
+The FIMC-IS is an subsystem for processing image signal from an image sensor.
+The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
+processor, ISP, DRC and FD IP blocks and peripheral IPs such as I2C, SPI, UART
+bus controllers, Multi-PWM and ADC.
+
+fimc-is node
+
+
+Required properties:
+
+- compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
+  Exynos4412 SoCs;
+- reg   : physical base address and size of the device memory mapped
+  registers;
+- interrupts : should contain FIMC-IS interrupts;
+
+The following are the FIMC-IS peripheral device nodes and can be specified
+either standalone or as fimc-is child nodes.
+
+pmu subnode
+---
+
+Required properties:
+ - reg : should contain PMU physical base address of the memory mapped
+  registers and size, the value of size should be 0x3000.
+
+
+i2c-isp (ISP I2C bus controller) nodes
+--
+
+Required properties:
+
+- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212 and
+  Exynos4412 SoCs;
+- reg   : physical base address and size of the device memory mapped
+  registers;
+
+For the above nodes it is required to specify a pinctrl state named "default",
+according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
-- 
1.7.9.5

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[RFC PATCH 7/8] s5p-fimc: Add fimc-is subdevs registration

2013-03-11 Thread Sylwester Nawrocki 
This patch allows to register FIMC-IS device represented by FIMC-IS-ISP
subdev to the top level media device driver. The use_isp platform data
structure field allows to select whether the fimc-is ISP subdev should
be tried to be registered or not.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Andrzej Hajda 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   51 ++--
 drivers/media/platform/s5p-fimc/fimc-mdevice.h |   15 +++
 2 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index e9e5337..1521dec 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -31,6 +31,7 @@
 #include 
 
 #include "fimc-core.h"
+#include "fimc-is.h"
 #include "fimc-lite.h"
 #include "fimc-mdevice.h"
 #include "mipi-csis.h"
@@ -85,9 +86,11 @@ static void fimc_pipeline_prepare(struct fimc_pipeline *p,
case GRP_ID_FIMC:
/* No need to control FIMC subdev through subdev ops */
break;
+   case GRP_ID_FIMC_IS:
+   p->subdevs[IDX_IS_ISP] = sd;
+   break;
default:
-   pr_warn("%s: Unknown subdev grp_id: %#x\n",
-   __func__, sd->grp_id);
+   break;
}
me = &sd->entity;
if (me->num_pads == 1)
@@ -291,6 +294,7 @@ static void fimc_md_unregister_sensor(struct v4l2_subdev 
*sd)
 
if (!client)
return;
+
v4l2_device_unregister_subdev(sd);
 
if (!client->dev.of_node) {
@@ -341,7 +345,11 @@ static int fimc_md_of_add_sensor(struct fimc_md *fmd,
goto mod_put;
 
v4l2_set_subdev_hostdata(sd, si);
-   sd->grp_id = GRP_ID_SENSOR;
+   if (si->pdata.fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
+   sd->grp_id = GRP_ID_FIMC_IS_SENSOR;
+   else
+   sd->grp_id = GRP_ID_SENSOR;
+
si->subdev = sd;
v4l2_info(&fmd->v4l2_dev, "Registered sensor subdevice: %s (%d)\n",
  sd->name, fmd->num_sensors);
@@ -360,7 +368,7 @@ static int fimc_md_parse_port_node(struct fimc_md *fmd,
   struct device_node *port,
   unsigned int index)
 {
-   struct device_node *rem, *endpoint;
+   struct device_node *rem, *endpoint, *np;
struct fimc_source_info *pd;
struct v4l2_of_endpoint bus_cfg;
u32 tmp, reg = 0;
@@ -415,6 +423,18 @@ static int fimc_md_parse_port_node(struct fimc_md *fmd,
v4l2_err(&fmd->v4l2_dev, "Wrong port id (%u) at node %s\n",
 reg, rem->full_name);
}
+   /*
+* For FIMC-IS handled sensors, that are placed under fimc-is-i2c
+* device node, FIMC is connected to the FIMC-IS through its ISP
+* Writeback input. Sensors are attached to the FIMC-LITE hostdata
+* interface directly or through MIPI-CSIS, depending on the external
+* media bus used. This needs to be handled in a more reliable way,
+* not by just checking parent's node name.
+*/
+   if ((np = of_get_parent(rem)) && !of_node_cmp(np->name, "i2c-isp"))
+   pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
+   else
+   pd->fimc_bus_type = pd->sensor_bus_type;
 
ret = fimc_md_of_add_sensor(fmd, rem, index);
of_node_put(rem);
@@ -607,6 +627,22 @@ static int register_csis_entity(struct fimc_md *fmd,
return ret;
 }
 
+static int register_fimc_is_entity(struct fimc_md *fmd, struct fimc_is *is)
+{
+   struct v4l2_subdev *sd = &is->isp.subdev;
+   int ret;
+
+   ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
+   if (ret) {
+   v4l2_err(&fmd->v4l2_dev,
+"Failed to register FIMC-ISP (%d)\n", ret);
+   return ret;
+   }
+
+   fmd->fimc_is = is;
+   return 0;
+}
+
 static int fimc_md_register_platform_entity(struct fimc_md *fmd,
struct platform_device *pdev,
int plat_entity)
@@ -634,6 +670,9 @@ static int fimc_md_register_platform_entity(struct fimc_md 
*fmd,
case IDX_CSIS:
ret = register_csis_entity(fmd, pdev, drvdata);
break;
+   case IDX_IS_ISP:
+   ret = register_fimc_is_entity(fmd, drvdata);
+   break;
default:
ret = -ENODEV;
}
@@ -697,6 +736,8 @@ static int fimc_md_register_of_platform_entities(struct 
fimc_md *fmd,
/* If driver of any entity isn't ready try all again later. */
if (!strcmp(node->nam

[RFC PATCH 5/8] s5p-fimc: Add ISP video capture driver stubs

2013-03-11 Thread Sylwester Nawrocki 
This patch adds a video capture node for the FIMC-IS ISP IP block
and Makefile/Kconfig to actually enable the driver's compilation.

The ISP video capture driver is still a work in progress.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/Kconfig  |   13 +
 drivers/media/platform/s5p-fimc/Makefile |4 +
 drivers/media/platform/s5p-fimc/fimc-isp-video.c |  414 ++
 drivers/media/platform/s5p-fimc/fimc-isp-video.h |   50 +++
 4 files changed, 481 insertions(+)
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp-video.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp-video.h

diff --git a/drivers/media/platform/s5p-fimc/Kconfig 
b/drivers/media/platform/s5p-fimc/Kconfig
index c16b20d..1253e25 100644
--- a/drivers/media/platform/s5p-fimc/Kconfig
+++ b/drivers/media/platform/s5p-fimc/Kconfig
@@ -46,4 +46,17 @@ config VIDEO_EXYNOS_FIMC_LITE
  module will be called exynos-fimc-lite.
 endif
 
+if (SOC_EXYNOS4212 || SOC_EXYNOS4412) && OF && !ARCH_MULTIPLATFORM
+
+config VIDEO_EXYNOS4_FIMC_IS
+   tristate "EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver"
+   select VIDEOBUF2_DMA_CONTIG
+   help
+ This is a V4L2 driver for Samsung EXYNOS4x12 SoC FIMC-IS
+ (Imaging Subsystem).
+
+ To compile this driver as a module, choose M here: the
+ module will be called exynos-fimc-is.
+endif
+
 endif # VIDEO_SAMSUNG_S5P_FIMC
diff --git a/drivers/media/platform/s5p-fimc/Makefile 
b/drivers/media/platform/s5p-fimc/Makefile
index 4648514..55b171a 100644
--- a/drivers/media/platform/s5p-fimc/Makefile
+++ b/drivers/media/platform/s5p-fimc/Makefile
@@ -1,7 +1,11 @@
 s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-m2m.o fimc-capture.o 
fimc-mdevice.o
 exynos-fimc-lite-objs += fimc-lite-reg.o fimc-lite.o
+exynos-fimc-is-objs := fimc-is.o fimc-isp.o fimc-is-sensor.o fimc-is-regs.o
+exynos-fimc-is-objs += fimc-is-param.o fimc-is-errno.o fimc-is-i2c.o
+exynos-fimc-is-objs += fimc-isp-video.o
 s5p-csis-objs := mipi-csis.o
 
 obj-$(CONFIG_VIDEO_S5P_MIPI_CSIS)  += s5p-csis.o
 obj-$(CONFIG_VIDEO_EXYNOS_FIMC_LITE)   += exynos-fimc-lite.o
+obj-$(CONFIG_VIDEO_EXYNOS4_FIMC_IS)+= exynos-fimc-is.o
 obj-$(CONFIG_VIDEO_S5P_FIMC)   += s5p-fimc.o
diff --git a/drivers/media/platform/s5p-fimc/fimc-isp-video.c 
b/drivers/media/platform/s5p-fimc/fimc-isp-video.c
new file mode 100644
index 000..bdeacaa
--- /dev/null
+++ b/drivers/media/platform/s5p-fimc/fimc-isp-video.c
@@ -0,0 +1,414 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-mdevice.h"
+#include "fimc-core.h"
+#include "fimc-is.h"
+
+static int isp_video_capture_start_streaming(struct vb2_queue *q,
+   unsigned int count)
+{
+   /* TODO: start ISP output DMA */
+   return 0;
+}
+
+static int isp_video_capture_stop_streaming(struct vb2_queue *q)
+{
+   /* TODO: stop ISP output DMA */
+   return 0;
+}
+
+static int isp_video_capture_queue_setup(struct vb2_queue *vq,
+   const struct v4l2_format *pfmt,
+   unsigned int *num_buffers, unsigned int *num_planes,
+   unsigned int sizes[], void *allocators[])
+{
+   const struct v4l2_pix_format_mplane *pixm = NULL;
+   struct fimc_isp *isp = vq->drv_priv;
+   struct fimc_isp_frame *frame = &isp->out_frame;
+   const struct fimc_fmt *fmt = isp->video_capture_format;
+   unsigned long wh;
+   int i;
+
+   if (pfmt) {
+   pixm = &pfmt->fmt.pix_mp;
+   fmt = fimc_isp_find_format(&pixm->pixelformat, NULL, -1);
+   wh = pixm->width * pixm->height;
+   } else {
+   wh = frame->f_width * frame->f_height;
+   }
+
+   if (fmt == NULL)
+   return -EINVAL;
+
+   *num_planes = fmt->memplanes;
+
+   for (i = 0; i < fmt->memplanes; i++) {
+   unsigned int size = (wh * fmt->depth[i]) / 8;
+   if (pixm)
+   sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
+   else
+   sizes[i] = size;
+   allocators[i] = isp->alloc_ctx;
+   }
+
+   return 0;
+}
+
+static int isp_video_capture_buffer_prepare(struct vb2_buffer *vb)
+{
+   struct vb2_queue *vq = vb->vb2_queue;
+   struct fimc_isp *isp = vq->drv_priv;
+   int i;
+
+   if (isp->video_capture_format == NULL)
+   return -EINVAL;
+
+   for

[RFC PATCH 4/8] s5p-fimc: Add common FIMC-IS image sensor driver

2013-03-11 Thread Sylwester Nawrocki 
This subdev driver currently only handles an image sensor's
power supplies and reset signal. There is no any I2C communication
here as it is handled by the ISP's firmware.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-is-sensor.c |  308 ++
 drivers/media/platform/s5p-fimc/fimc-is-sensor.h |   80 ++
 2 files changed, 388 insertions(+)
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-sensor.h

diff --git a/drivers/media/platform/s5p-fimc/fimc-is-sensor.c 
b/drivers/media/platform/s5p-fimc/fimc-is-sensor.c
new file mode 100644
index 000..151915c
--- /dev/null
+++ b/drivers/media/platform/s5p-fimc/fimc-is-sensor.c
@@ -0,0 +1,308 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Sylwester Nawrocki 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-is.h"
+#include "fimc-is-sensor.h"
+
+#define DRIVER_NAME "FIMC-IS-SENSOR"
+
+static const char * const sensor_supply_names[] = {
+   "svdda",
+   "svddio",
+};
+
+static const struct v4l2_mbus_framefmt fimc_is_sensor_formats[] = {
+   {
+   .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+   .colorspace = V4L2_COLORSPACE_SRGB,
+   .field = V4L2_FIELD_NONE,
+   }
+};
+
+static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev *sd)
+{
+   return container_of(sd, struct fimc_is_sensor, subdev);
+}
+
+static const struct v4l2_mbus_framefmt *find_sensor_format(
+   struct v4l2_mbus_framefmt *mf)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(fimc_is_sensor_formats); i++)
+   if (mf->code == fimc_is_sensor_formats[i].code)
+   return &fimc_is_sensor_formats[i];
+
+   return &fimc_is_sensor_formats[0];
+}
+
+static int fimc_is_sensor_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+   if (code->index >= ARRAY_SIZE(fimc_is_sensor_formats))
+   return -EINVAL;
+
+   code->code = fimc_is_sensor_formats[code->index].code;
+   return 0;
+}
+
+static void fimc_is_sensor_try_format(struct fimc_is_sensor *sensor,
+ struct v4l2_mbus_framefmt *mf)
+{
+   const struct sensor_drv_data *dd = sensor->drvdata;
+   const struct v4l2_mbus_framefmt *fmt;
+
+   fmt = find_sensor_format(mf);
+   mf->code = fmt->code;
+   v4l_bound_align_image(&mf->width, 16 + 8, dd->width, 0,
+ &mf->height, 12 + 8, dd->height, 0, 0);
+}
+
+static struct v4l2_mbus_framefmt *__fimc_is_sensor_get_format(
+   struct fimc_is_sensor *sensor, struct v4l2_subdev_fh *fh,
+   u32 pad, enum v4l2_subdev_format_whence which)
+{
+   if (which == V4L2_SUBDEV_FORMAT_TRY)
+   return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
+
+   return &sensor->format;
+}
+
+static int fimc_is_sensor_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+   struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+   struct v4l2_mbus_framefmt *mf;
+
+   fimc_is_sensor_try_format(sensor, &fmt->format);
+
+   mf = __fimc_is_sensor_get_format(sensor, fh, fmt->pad, fmt->which);
+   if (mf) {
+   mutex_lock(&sensor->lock);
+   if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+   sensor->format = *mf;
+   mutex_unlock(&sensor->lock);
+   }
+   return 0;
+}
+
+static int fimc_is_sensor_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+   struct fimc_is_sensor *sensor = sd_to_fimc_is_sensor(sd);
+   struct v4l2_mbus_framefmt *mf;
+
+   mf = __fimc_is_sensor_get_format(sensor, fh, fmt->pad, fmt->which);
+
+   mutex_lock(&sensor->lock);
+   fmt->format = *mf;
+   mutex_unlock(&sensor->lock);
+   return 0;
+}
+
+static struct v4l2_subdev_pad_ops fimc_is_sensor_pad_ops = {
+   .enum_mbus_code = fimc_is_sensor_enum_mbus_code,
+   .get_fmt= fimc_is_sensor_get_fmt,
+   .set_fmt= fimc_is_sensor_set_fmt,
+};
+
+static int fimc_is_sensor_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh 
*fh)
+{
+   struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(

[RFC PATCH 3/8] s5p-fimc: Add FIMC-IS parameter region definitions

2013-03-11 Thread Sylwester Nawrocki 
This patch adds ISP processing parameters interface files.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-is-param.c |  971 +
 drivers/media/platform/s5p-fimc/fimc-is-param.h | 1018 +++
 2 files changed, 1989 insertions(+)
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-param.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-param.h

diff --git a/drivers/media/platform/s5p-fimc/fimc-is-param.c 
b/drivers/media/platform/s5p-fimc/fimc-is-param.c
new file mode 100644
index 000..5674c3b
--- /dev/null
+++ b/drivers/media/platform/s5p-fimc/fimc-is-param.c
@@ -0,0 +1,971 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * Authors: Younghwan Joo 
+ *  Sylwester Nawrocki 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fimc-is.h"
+#include "fimc-is-command.h"
+#include "fimc-is-errno.h"
+#include "fimc-is-param.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-sensor.h"
+
+static void __hw_param_copy(void *dst, void *src)
+{
+   memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
+}
+
+void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
+{
+   struct param_global_shotmode *dst, *src;
+
+   dst = &is->is_p_region->parameter.global.shotmode;
+   src = &is->cfg_param[is->scenario_id].global.shotmode;
+   __hw_param_copy(dst, src);
+}
+
+void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
+{
+   struct param_sensor_framerate *dst, *src;
+
+   dst = &is->is_p_region->parameter.sensor.frame_rate;
+   src = &is->cfg_param[is->scenario_id].sensor.frame_rate;
+   __hw_param_copy(dst, src);
+}
+
+int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
+{
+   struct is_param_region *par = &is->is_p_region->parameter;
+   struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
+
+   switch (offset) {
+   case PARAM_ISP_CONTROL:
+   __hw_param_copy(&par->isp.control, &cfg->isp.control);
+   break;
+
+   case PARAM_ISP_OTF_INPUT:
+   __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
+   break;
+
+   case PARAM_ISP_DMA1_INPUT:
+   __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
+   break;
+
+   case PARAM_ISP_DMA2_INPUT:
+   __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
+   break;
+
+   case PARAM_ISP_AA:
+   __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
+   break;
+
+   case PARAM_ISP_FLASH:
+   __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
+   break;
+
+   case PARAM_ISP_AWB:
+   __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
+   break;
+
+   case PARAM_ISP_IMAGE_EFFECT:
+   __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
+   break;
+
+   case PARAM_ISP_ISO:
+   __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
+   break;
+
+   case PARAM_ISP_ADJUST:
+   __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
+   break;
+
+   case PARAM_ISP_METERING:
+   __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
+   break;
+
+   case PARAM_ISP_AFC:
+   __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
+   break;
+
+   case PARAM_ISP_OTF_OUTPUT:
+   __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
+   break;
+
+   case PARAM_ISP_DMA1_OUTPUT:
+   __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
+   break;
+
+   case PARAM_ISP_DMA2_OUTPUT:
+   __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
+   break;
+
+   case PARAM_DRC_CONTROL:
+   __hw_param_copy(&par->drc.control, &cfg->drc.control);
+   break;
+
+   case PARAM_DRC_OTF_INPUT:
+   __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
+   break;
+
+   case PARAM_DRC_DMA_INPUT:
+   __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
+   break;
+
+   case PARAM_DRC_OTF_OUTPUT:
+   __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
+   break;
+
+   case PARAM_FD_CONTROL:
+   __hw_param_copy(&par->fd.control, &cfg

[RFC PATCH 2/8] s5p-fimc: Add FIMC-IS ISP I2C bus driver

2013-03-11 Thread Sylwester Nawrocki 
This patch adds the ISP I2C bus controller driver files.

Creating a standard I2C bus adapter, even if the driver doesn't
actually communicates with the hardware and it is instead used
by the ISP firmware running on the Cortex-A5, allows to use
standard hardware description in the device tree. As the sensor
would have actually had a standard V4L2 sub-device driver run
on the host CPU.

This approach allows to adapt the driver with a relatively small
effort should the Imaging Subsystem architecture change so that
the I2C bus is controlled by the host CPU, rather than the
internal FIMC-IS ARM CPU. The image sensor drivers can be
standard I2C client driver, as in case of most existing image
sensor driver.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-is-i2c.c |   81 +
 drivers/media/platform/s5p-fimc/fimc-is-i2c.h |   15 +
 2 files changed, 96 insertions(+)
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-i2c.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-i2c.h

diff --git a/drivers/media/platform/s5p-fimc/fimc-is-i2c.c 
b/drivers/media/platform/s5p-fimc/fimc-is-i2c.c
new file mode 100644
index 000..d4c75dc
--- /dev/null
+++ b/drivers/media/platform/s5p-fimc/fimc-is-i2c.c
@@ -0,0 +1,81 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Sylwester Nawrocki 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include 
+#include 
+#include 
+#include "fimc-is-i2c.h"
+
+/*
+ * An empty algorithm is used as the actual I2C bus controller driver
+ * is implemented in the FIMC-IS subsystem firmware and the host CPU
+ * doesn't touch the hardware.
+ */
+static const struct i2c_algorithm fimc_is_i2c_algorithm;
+
+static int fimc_is_i2c_probe(struct platform_device *pdev)
+{
+   struct device_node *node = pdev->dev.of_node;
+   struct i2c_adapter *i2c_adap;
+   int ret;
+
+   i2c_adap = devm_kzalloc(&pdev->dev, sizeof(*i2c_adap), GFP_KERNEL);
+
+   i2c_adap->dev.of_node = node;
+   i2c_adap->dev.parent = &pdev->dev;
+   strlcpy(i2c_adap->name, "exynos4x12-is-i2c", sizeof(i2c_adap->name));
+   i2c_adap->owner = THIS_MODULE;
+   i2c_adap->algo = &fimc_is_i2c_algorithm;
+   i2c_adap->class = I2C_CLASS_SPD;
+
+   ret = i2c_add_adapter(i2c_adap);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "failed to add I2C bus %s\n",
+   node->full_name);
+   return ret;
+   }
+   of_i2c_register_devices(i2c_adap);
+
+   return 0;
+}
+
+static int fimc_is_i2c_remove(struct platform_device *pdev)
+{
+   return 0;
+}
+
+static const struct of_device_id fimc_is_i2c_of_match[] = {
+   { .compatible = FIMC_IS_I2C_COMPATIBLE },
+   { },
+};
+MODULE_DEVICE_TABLE(of, fimc_is_i2c_of_match);
+
+static struct platform_driver fimc_is_i2c_driver = {
+   .probe  = fimc_is_i2c_probe,
+   .remove = fimc_is_i2c_remove,
+   .driver = {
+   .of_match_table = fimc_is_i2c_of_match,
+   .name   = "fimc-is-i2c",
+   .owner  = THIS_MODULE,
+   }
+};
+
+int fimc_is_register_i2c_driver(void)
+{
+   return platform_driver_register(&fimc_is_i2c_driver);
+}
+
+void fimc_is_unregister_i2c_driver(void)
+{
+   platform_driver_unregister(&fimc_is_i2c_driver);
+}
+
diff --git a/drivers/media/platform/s5p-fimc/fimc-is-i2c.h 
b/drivers/media/platform/s5p-fimc/fimc-is-i2c.h
new file mode 100644
index 000..0d38d6b
--- /dev/null
+++ b/drivers/media/platform/s5p-fimc/fimc-is-i2c.h
@@ -0,0 +1,15 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Sylwester Nawrocki 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define FIMC_IS_I2C_COMPATIBLE "samsung,exynos4212-i2c-isp"
+
+int fimc_is_register_i2c_driver(void);
+void fimc_is_unregister_i2c_driver(void);
-- 
1.7.9.5

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[RFC PATCH 0/8] A V4L2 driver for Exynos4x12 Imaging Subsystem

2013-03-11 Thread Sylwester Nawrocki 
This patch series is an initial version of a driver for the camera ISP
subsystem (FIMC-IS) embedded in Samsung Exynos4x12 SoCs.

The FIMC-IS subsystem is build around a ARM Cortex-A5 CPU that controls
its dedicated peripherals, like I2C, SPI, UART, PWM, ADC,...  and the
ISP chain. There are 3 hardware image processing blocks: ISP, DRC
(dynamic range compression) and FD (face detection) that are normally
controlled by the Cortex-A5 firmware.

The driver currently exposes two additional sub-device to user space:
the image sensor and FIMC-IS-ISP sub-device. Another one might be
added in future for the FD features.

The FIMC-IS has various data inputs, it can capture data from memory
or from other SoC IP blocks (FIMC-LITE). It is currently plugged
between FIMC-LITE and FIMC IP blocks, so there is a media pipeline
like:

sensor -> MIPI-CSIS -> FIMC-LITE -> FIMC-IS-ISP -> FIMC -> memory

A raw Bayer image data can be captured from the ISP block which has
it's own DMA engines. Support for this is not really included in
this series though, only a video capture node driver stubs are added.

This is a bit complicated code, nevertheless I would really appreciate
any review comments you might have.

And this is just a basic set of futures this patch series addresses.
Others include input/output DMA support for the DRC and FD blocks,
support for more ISP controls, etc.

But it all is not immediately needed to make use of this really
great ISP!

A full git tree with all dependencies can be found at:
git://linuxtv.org/snawrocki/samsung.git
http://git.linuxtv.org/snawrocki/samsung.git/exynos4-fimc-is

Sylwester Nawrocki (8):
  s5p-fimc: Add Exynos4x12 FIMC-IS driver
  s5p-fimc: Add FIMC-IS ISP I2C bus driver
  s5p-fimc: Add FIMC-IS parameter region definitions
  s5p-fimc: Add common FIMC-IS image sensor driver
  s5p-fimc: Add ISP video capture driver stubs
  fimc-is: Add Exynos4x12 FIMC-IS device tree bindings documentation
  s5p-fimc: Add fimc-is subdevs registration
  s5p-fimc: Create media links for the FIMC-IS entities

 .../devicetree/bindings/media/exynos4-fimc-is.txt  |   41 +
 drivers/media/platform/s5p-fimc/Kconfig|   13 +
 drivers/media/platform/s5p-fimc/Makefile   |4 +
 drivers/media/platform/s5p-fimc/fimc-is-command.h  |  147 +++
 drivers/media/platform/s5p-fimc/fimc-is-errno.c|  272 ++
 drivers/media/platform/s5p-fimc/fimc-is-errno.h|  248 +
 drivers/media/platform/s5p-fimc/fimc-is-i2c.c  |   81 ++
 drivers/media/platform/s5p-fimc/fimc-is-i2c.h  |   15 +
 drivers/media/platform/s5p-fimc/fimc-is-param.c|  971 +++
 drivers/media/platform/s5p-fimc/fimc-is-param.h| 1018 
 drivers/media/platform/s5p-fimc/fimc-is-regs.c |  242 +
 drivers/media/platform/s5p-fimc/fimc-is-regs.h |  164 
 drivers/media/platform/s5p-fimc/fimc-is-sensor.c   |  308 ++
 drivers/media/platform/s5p-fimc/fimc-is-sensor.h   |   80 ++
 drivers/media/platform/s5p-fimc/fimc-is.c  |  970 +++
 drivers/media/platform/s5p-fimc/fimc-is.h  |  344 +++
 drivers/media/platform/s5p-fimc/fimc-isp-video.c   |  414 
 drivers/media/platform/s5p-fimc/fimc-isp-video.h   |   50 +
 drivers/media/platform/s5p-fimc/fimc-isp.c |  791 +++
 drivers/media/platform/s5p-fimc/fimc-isp.h |  205 
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |  129 ++-
 drivers/media/platform/s5p-fimc/fimc-mdevice.h |   15 +
 22 files changed, 6502 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos4-fimc-is.txt
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-command.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-errno.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-errno.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-i2c.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-i2c.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-param.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-param.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-regs.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-regs.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is-sensor.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-is.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp-video.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp-video.h
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp.c
 create mode 100644 drivers/media/platform/s5p-fimc/fimc-isp.h

--
1.7.9.5

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[PATCH RFC 11/11] V4L: Add MATRIX option to V4L2_CID_EXPOSURE_METERING control

2013-03-11 Thread Sylwester Nawrocki 
This patch adds a menu option to the V4L2_CID_EXPOSURE_METERING
control for multi-zone metering.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 Documentation/DocBook/media/v4l/controls.xml |9 -
 drivers/media/v4l2-core/v4l2-ctrls.c |1 +
 include/uapi/linux/v4l2-controls.h   |1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/DocBook/media/v4l/controls.xml 
b/Documentation/DocBook/media/v4l/controls.xml
index 7fe5be1..0484a7d 100644
--- a/Documentation/DocBook/media/v4l/controls.xml
+++ b/Documentation/DocBook/media/v4l/controls.xml
@@ -3159,6 +3159,13 @@ giving priority to the center of the metered 
area.
  
V4L2_EXPOSURE_METERING_SPOT 
  Measure only very small area at the center of the 
frame.

+   
+ 
V4L2_EXPOSURE_METERING_MATRIX 
+ A multi-zone metering. The light intensity is measured
+in several points of the frame and the the results are combined. The
+algorithm of the zones selection and their significance in calculating the
+final value is device dependant.
+   
  

  
@@ -3986,7 +3993,7 @@ interface and may change in the future.
 
   
   Flash Control IDs
-
+
   


diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c 
b/drivers/media/v4l2-core/v4l2-ctrls.c
index 4b45d49..6b56d7b 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -234,6 +234,7 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
"Average",
"Center Weighted",
"Spot",
+   "Matrix",
NULL
};
static const char * const camera_auto_focus_range[] = {
diff --git a/include/uapi/linux/v4l2-controls.h 
b/include/uapi/linux/v4l2-controls.h
index f56c945..22556a2 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -642,6 +642,7 @@ enum v4l2_exposure_metering {
V4L2_EXPOSURE_METERING_AVERAGE  = 0,
V4L2_EXPOSURE_METERING_CENTER_WEIGHTED  = 1,
V4L2_EXPOSURE_METERING_SPOT = 2,
+   V4L2_EXPOSURE_METERING_MATRIX   = 3,
 };
 
 #define V4L2_CID_SCENE_MODE(V4L2_CID_CAMERA_CLASS_BASE+26)
-- 
1.7.9.5

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[PATCH RFC 10/11] s5p-fimc: Remove dependency on fimc-core.h in fimc-lite driver

2013-03-11 Thread Sylwester Nawrocki 
Drop fimc-lite.h header inclusion to make the exynos-fimc-lite
module independent on other modules. Move struct fimc_fmt
declaration to the driver's private headers as it is used in
multiple modules.

Reported-by: Shaik Ameer Basha 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-core.h |   32 -
 drivers/media/platform/s5p-fimc/fimc-lite.c |1 -
 drivers/media/platform/s5p-fimc/fimc-lite.h |3 +--
 include/media/s5p_fimc.h|   34 +++
 4 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-core.h 
b/drivers/media/platform/s5p-fimc/fimc-core.h
index d95aa66..6e2fa1a 100644
--- a/drivers/media/platform/s5p-fimc/fimc-core.h
+++ b/drivers/media/platform/s5p-fimc/fimc-core.h
@@ -40,7 +40,6 @@
 #define DMA_MIN_SIZE   8
 #define FIMC_CAMIF_MAX_HEIGHT  0x2000
 #define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
-#define FIMC_MAX_PLANES3
 #define FIMC_PIX_LIMITS_MAX6
 #define FIMC_DEF_MIN_SIZE  16
 #define FIMC_DEF_HEIGHT_ALIGN  2
@@ -138,37 +137,6 @@ enum fimc_color_fmt {
 #defineFIMC_COLOR_RANGE_NARROW (1 << 3)
 
 /**
- * struct fimc_fmt - the driver's internal color format data
- * @mbus_code: Media Bus pixel code, -1 if not applicable
- * @name: format description
- * @fourcc: the fourcc code for this format, 0 if not applicable
- * @color: the corresponding fimc_color_fmt
- * @memplanes: number of physically non-contiguous data planes
- * @colplanes: number of physically contiguous data planes
- * @depth: per plane driver's private 'number of bits per pixel'
- * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
- * @flags: flags indicating which operation mode format applies to
- */
-struct fimc_fmt {
-   enum v4l2_mbus_pixelcode mbus_code;
-   char*name;
-   u32 fourcc;
-   u32 color;
-   u16 memplanes;
-   u16 colplanes;
-   u8  depth[VIDEO_MAX_PLANES];
-   u16 mdataplanes;
-   u16 flags;
-#define FMT_FLAGS_CAM  (1 << 0)
-#define FMT_FLAGS_M2M_IN   (1 << 1)
-#define FMT_FLAGS_M2M_OUT  (1 << 2)
-#define FMT_FLAGS_M2M  (1 << 1 | 1 << 2)
-#define FMT_HAS_ALPHA  (1 << 3)
-#define FMT_FLAGS_COMPRESSED   (1 << 4)
-#define FMT_FLAGS_WRITEBACK(1 << 5)
-};
-
-/**
  * struct fimc_dma_offset - pixel offset information for DMA
  * @y_h:   y value horizontal offset
  * @y_v:   y value vertical offset
diff --git a/drivers/media/platform/s5p-fimc/fimc-lite.c 
b/drivers/media/platform/s5p-fimc/fimc-lite.c
index 97050ee..412fcb8 100644
--- a/drivers/media/platform/s5p-fimc/fimc-lite.c
+++ b/drivers/media/platform/s5p-fimc/fimc-lite.c
@@ -32,7 +32,6 @@
 #include 
 
 #include "fimc-mdevice.h"
-#include "fimc-core.h"
 #include "fimc-lite.h"
 #include "fimc-lite-reg.h"
 
diff --git a/drivers/media/platform/s5p-fimc/fimc-lite.h 
b/drivers/media/platform/s5p-fimc/fimc-lite.h
index 7085761..4c234508 100644
--- a/drivers/media/platform/s5p-fimc/fimc-lite.h
+++ b/drivers/media/platform/s5p-fimc/fimc-lite.h
@@ -20,12 +20,11 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
-#include "fimc-core.h"
-
 #define FIMC_LITE_DRV_NAME "exynos-fimc-lite"
 #define FLITE_CLK_NAME "flite"
 #define FIMC_LITE_MAX_DEVS 2
diff --git a/include/media/s5p_fimc.h b/include/media/s5p_fimc.h
index e2434bb..2363aff 100644
--- a/include/media/s5p_fimc.h
+++ b/include/media/s5p_fimc.h
@@ -13,6 +13,7 @@
 #define S5P_FIMC_H_
 
 #include 
+#include 
 
 /*
  * Enumeration of data inputs to the camera subsystem.
@@ -93,6 +94,39 @@ struct s5p_platform_fimc {
  */
 #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
 
+#define FIMC_MAX_PLANES3
+
+/**
+ * struct fimc_fmt - color format data structure
+ * @mbus_code: media bus pixel code, -1 if not applicable
+ * @name: format description
+ * @fourcc: fourcc code for this format, 0 if not applicable
+ * @color: the driver's private color format id
+ * @memplanes: number of physically non-contiguous data planes
+ * @colplanes: number of physically contiguous data planes
+ * @depth: per plane driver's private 'number of bits per pixel'
+ * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
+ * @flags: flags indicating which operation mode format applies to
+ */
+struct fimc_fmt {
+   enum v4l2_mbus_pixelcode mbus_code;
+   char*name;
+   u32 fourcc;
+   u32 color;
+   u16 memplanes;
+   u16 colplanes;
+   u8  depth[FIMC_MAX_PLANES];
+   u16 mdataplanes;
+   u16 flags;
+#define FMT_FLAGS_CAM  (1 << 0)
+#define FMT_FLAGS_M2M_IN   (1 << 1)
+#define FMT_FLAGS_M2M_OUT  (1 << 2)
+#define FMT_FLAGS_M2M  (1 << 1 | 1 << 2)
+#define FMT_HAS_ALPHA  (1 << 3)
+#define FMT_FLAGS_COMPRESSED   (1 << 4)
+#define FMT_FLAGS_WRITEBACK(1 << 5

[PATCH RFC 09/11] s5p-fimc: Ensure proper s_power() call order in the ISP datapaths

2013-03-11 Thread Sylwester Nawrocki 
Since the FIMC-IS firmware communicates with an image sensor directly
through the ISP I2C bus controllers the sub-devices power supplies
cannot be simply enabled from left to right or disabled from right
to left along the processing pipeline. Thus a subdev index to call
s_power() on is looked up from a table, rather than doing the op call
based on increasing/decreasing indexes.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   26 
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index c99802d..e9e5337 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -128,23 +128,33 @@ static int __subdev_set_power(struct v4l2_subdev *sd, int 
on)
  *
  * Needs to be called with the graph mutex held.
  */
-static int fimc_pipeline_s_power(struct fimc_pipeline *p, bool state)
+static int fimc_pipeline_s_power(struct fimc_pipeline *p, bool on)
 {
-   unsigned int i;
-   int ret;
+   static const u8 seq[2][IDX_MAX - 1] = {
+   { IDX_IS_ISP, IDX_SENSOR, IDX_CSIS, IDX_FLITE },
+   { IDX_CSIS, IDX_FLITE, IDX_SENSOR, IDX_IS_ISP },
+   };
+   int i, ret = 0;
 
if (p->subdevs[IDX_SENSOR] == NULL)
return -ENXIO;
 
-   for (i = 0; i < IDX_MAX; i++) {
-   unsigned int idx = state ? (IDX_MAX - 1) - i : i;
+   for (i = 0; i < IDX_MAX - 1; i++) {
+   unsigned int idx = seq[on][i];
+
+   ret = __subdev_set_power(p->subdevs[idx], on);
+
 
-   ret = __subdev_set_power(p->subdevs[idx], state);
if (ret < 0 && ret != -ENXIO)
-   return ret;
+   goto error;
}
-
return 0;
+error:
+   for (; i >= 0; i--) {
+   unsigned int idx = seq[on][i];
+   __subdev_set_power(p->subdevs[idx], !on);
+   }
+   return ret;
 }
 
 /**
-- 
1.7.9.5

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[PATCH RFC 08/11] s5p-fimc: Ensure proper s_stream() call order in the ISP datapaths

2013-03-11 Thread Sylwester Nawrocki 
Since the FIMC-IS firmware communicates with an image sensor directly
through the ISP I2C bus controllers data streaming cannot be simply
enabled from left to right or disabled from right to left along the
processing pipeline. Thus a subdev index to call s_stream() on is
looked up from a table, rather than doing the op call based on
increasing/decreasing indexes.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index c336ed1..c99802d 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -194,28 +194,36 @@ static int __fimc_pipeline_close(struct fimc_pipeline *p)
 }
 
 /**
- * __fimc_pipeline_s_stream - invoke s_stream on pipeline subdevs
+ * __fimc_pipeline_s_stream - call s_stream() on pipeline subdevs
  * @pipeline: video pipeline structure
- * @on: passed as the s_stream call argument
+ * @on: passed as the s_stream() callback argument
  */
 static int __fimc_pipeline_s_stream(struct fimc_pipeline *p, bool on)
 {
-   int i, ret;
+   static const u8 seq[2][IDX_MAX] = {
+   { IDX_FIMC, IDX_SENSOR, IDX_IS_ISP, IDX_CSIS, IDX_FLITE },
+   { IDX_CSIS, IDX_FLITE, IDX_FIMC, IDX_SENSOR, IDX_IS_ISP },
+   };
+   int i, ret = 0;
 
if (p->subdevs[IDX_SENSOR] == NULL)
return -ENODEV;
 
for (i = 0; i < IDX_MAX; i++) {
-   unsigned int idx = on ? (IDX_MAX - 1) - i : i;
+   unsigned int idx = seq[on][i];
 
ret = v4l2_subdev_call(p->subdevs[idx], video, s_stream, on);
 
if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
-   return ret;
+   goto error;
}
-
return 0;
-
+error:
+   for (; i >= 0; i--) {
+   unsigned int idx = seq[on][i];
+   v4l2_subdev_call(p->subdevs[idx], video, s_stream, !on);
+   }
+   return ret;
 }
 
 /* Media pipeline operations for the FIMC/FIMC-LITE video device driver */
-- 
1.7.9.5

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[PATCH RFC 07/11] s5p-fimc: Ensure CAMCLK clock can be enabled by FIMC-LITE devices

2013-03-11 Thread Sylwester Nawrocki 
In configurations where FIMC-LITE is used to capture image signal
from an external sensor only we need to ensure one of FIMC devices
is in active power state and the "fimc" gate clock is enabled.
Otherwise the CAMCLK clock output signal will be masked off
preventing an external sensor's operation.
This affect processing pipelines like:

 - sensor -> FIMC-LITE -> memory
 - sensor -> MIPI-CSIS -> FIMC-LITE -> memory

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   18 ++
 drivers/media/platform/s5p-fimc/fimc-mdevice.h |2 ++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index d26b7bf..c336ed1 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -464,7 +464,6 @@ static int fimc_md_register_sensor_entities(struct fimc_md 
*fmd)
 {
struct s5p_platform_fimc *pdata = fmd->pdev->dev.platform_data;
struct device_node *of_node = fmd->pdev->dev.of_node;
-   struct fimc_dev *fd = NULL;
int num_clients = 0;
int ret, i;
 
@@ -472,13 +471,10 @@ static int fimc_md_register_sensor_entities(struct 
fimc_md *fmd)
 * Runtime resume one of the FIMC entities to make sure
 * the sclk_cam clocks are not globally disabled.
 */
-   for (i = 0; !fd && i < ARRAY_SIZE(fmd->fimc); i++)
-   if (fmd->fimc[i])
-   fd = fmd->fimc[i];
-   if (!fd)
+   if (!fmd->pmf)
return -ENXIO;
 
-   ret = pm_runtime_get_sync(&fd->pdev->dev);
+   ret = pm_runtime_get_sync(fmd->pmf);
if (ret < 0)
return ret;
 
@@ -512,7 +508,7 @@ static int fimc_md_register_sensor_entities(struct fimc_md 
*fmd)
}
}
 
-   pm_runtime_put(&fd->pdev->dev);
+   pm_runtime_put(fmd->pmf);
return ret;
 }
 
@@ -557,6 +553,8 @@ static int register_fimc_entity(struct fimc_md *fmd, struct 
fimc_dev *fimc)
 
ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
if (!ret) {
+   if (!fmd->pmf && fimc->pdev)
+   fmd->pmf = &fimc->pdev->dev;
fmd->fimc[fimc->id] = fimc;
fimc->vid_cap.user_subdev_api = fmd->user_subdev_api;
} else {
@@ -1048,7 +1046,7 @@ static int __fimc_md_set_camclk(struct fimc_md *fmd,
struct fimc_camclk_info *camclk;
int ret = 0;
 
-   if (WARN_ON(pdata->clk_id >= FIMC_MAX_CAMCLKS) || fmd == NULL)
+   if (WARN_ON(pdata->clk_id >= FIMC_MAX_CAMCLKS) || !fmd || !fmd->pmf)
return -EINVAL;
 
camclk = &fmd->camclk[pdata->clk_id];
@@ -1064,6 +1062,9 @@ static int __fimc_md_set_camclk(struct fimc_md *fmd,
if (camclk->use_count++ == 0) {
clk_set_rate(camclk->clock, pdata->clk_frequency);
camclk->frequency = pdata->clk_frequency;
+   ret = pm_runtime_get_sync(fmd->pmf);
+   if (ret < 0)
+   return ret;
ret = clk_enable(camclk->clock);
dbg("Enabled camclk %d: f: %lu", pdata->clk_id,
clk_get_rate(camclk->clock));
@@ -1076,6 +1077,7 @@ static int __fimc_md_set_camclk(struct fimc_md *fmd,
 
if (--camclk->use_count == 0) {
clk_disable(camclk->clock);
+   pm_runtime_put(fmd->pmf);
dbg("Disabled camclk %d", pdata->clk_id);
}
return ret;
diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.h 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.h
index 91be5db..a827bf9 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.h
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.h
@@ -80,6 +80,7 @@ struct fimc_sensor_info {
  * @num_sensors: actual number of registered sensors
  * @camclk: external sensor clock information
  * @fimc: array of registered fimc devices
+ * @pmf: handle to the CAMCLK clock control FIMC helper device
  * @media_dev: top level media device
  * @v4l2_dev: top level v4l2_device holding up the subdevs
  * @pdev: platform device this media device is hooked up into
@@ -97,6 +98,7 @@ struct fimc_md {
struct clk *wbclk[FIMC_MAX_WBCLKS];
struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS];
struct fimc_dev *fimc[FIMC_MAX_DEVS];
+   struct device *pmf;
struct media_device media_dev;
struct v4l2_device v4l2_dev;
struct platform_device *pdev;
-- 
1.7.9.5

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[PATCH RFC 06/11] s5p-fimc: Add the FIMC ISP writeback input support

2013-03-11 Thread Sylwester Nawrocki 
A second sink pad is added to each FIMC.N subdev that will be used
to link it to the ISP subdev. Only V4L2_MBUS_FMT_YUV10_1X30 format
is supported at the pad FIMC_SD_PAD_SINK_FIFO.

TODO:
 - Implement the FIMC input bus type selection based on
   state of media link from FIMC-IS-ISP to FIMC.N subdev.
 - Implement an interface for CAMBLK registers, the CAMBLK glue
   logic registers are shared by multiple drivers so this
   probably belongs to the platform at arch/arm/mach-exynos/.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-capture.c |   31 +++
 drivers/media/platform/s5p-fimc/fimc-core.c|4 ++
 drivers/media/platform/s5p-fimc/fimc-core.h|6 ++-
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |5 ++
 drivers/media/platform/s5p-fimc/fimc-reg.c |   65 +++-
 drivers/media/platform/s5p-fimc/fimc-reg.h |   10 
 6 files changed, 108 insertions(+), 13 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-capture.c 
b/drivers/media/platform/s5p-fimc/fimc-capture.c
index 52abc9f..a3a58c4 100644
--- a/drivers/media/platform/s5p-fimc/fimc-capture.c
+++ b/drivers/media/platform/s5p-fimc/fimc-capture.c
@@ -46,6 +46,9 @@ static int fimc_capture_hw_init(struct fimc_dev *fimc)
 
sensor = v4l2_get_subdev_hostdata(p->subdevs[IDX_SENSOR]);
 
+   if (sensor->pdata.fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
+   fimc_hw_camblk_set_isp_wb(fimc, 1 << fimc->id, 1);
+
spin_lock_irqsave(&fimc->slock, flags);
fimc_prepare_dma_offset(ctx, &ctx->d_frame);
fimc_set_yuv_order(ctx);
@@ -647,18 +650,22 @@ static struct fimc_fmt *fimc_capture_try_format(struct 
fimc_ctx *ctx,
fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
*code = ctx->s_frame.fmt->mbus_code;
 
-   if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad != FIMC_SD_PAD_SINK)
+   if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad == FIMC_SD_PAD_SOURCE)
mask |= FMT_FLAGS_M2M;
 
+   if (pad == FIMC_SD_PAD_SINK_FIFO)
+   mask = FMT_FLAGS_WRITEBACK;
+
ffmt = fimc_find_format(fourcc, code, mask, 0);
if (WARN_ON(!ffmt))
return NULL;
+
if (code)
*code = ffmt->mbus_code;
if (fourcc)
*fourcc = ffmt->fourcc;
 
-   if (pad == FIMC_SD_PAD_SINK) {
+   if (pad != FIMC_SD_PAD_SOURCE) {
max_w = fimc_fmt_is_user_defined(ffmt->color) ?
pl->scaler_dis_w : pl->scaler_en_w;
/* Apply the camera input interface pixel constraints */
@@ -1552,12 +1559,16 @@ static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,
}
mf = &fmt->format;
mf->colorspace = V4L2_COLORSPACE_JPEG;
-   ff = fmt->pad == FIMC_SD_PAD_SINK ? &ctx->s_frame : &ctx->d_frame;
+   if (fmt->pad == FIMC_SD_PAD_SOURCE)
+   ff = &ctx->d_frame;
+   else
+   ff = &ctx->s_frame;
 
mutex_lock(&fimc->lock);
/* The pixel code is same on both input and output pad */
if (!WARN_ON(ctx->s_frame.fmt == NULL))
mf->code = ctx->s_frame.fmt->mbus_code;
+
mf->width  = ff->f_width;
mf->height = ff->f_height;
mutex_unlock(&fimc->lock);
@@ -1601,9 +1612,10 @@ static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
fimc_alpha_ctrl_update(ctx);
 
fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
-
-   ff = fmt->pad == FIMC_SD_PAD_SINK ?
-   &ctx->s_frame : &ctx->d_frame;
+   if (fmt->pad == FIMC_SD_PAD_SOURCE)
+   ff = &ctx->d_frame;
+   else
+   ff = &ctx->s_frame;
 
mutex_lock(&fimc->lock);
set_frame_bounds(ff, mf->width, mf->height);
@@ -1614,7 +1626,7 @@ static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE)))
set_frame_crop(ff, 0, 0, mf->width, mf->height);
 
-   if (fmt->pad == FIMC_SD_PAD_SINK)
+   if (fmt->pad != FIMC_SD_PAD_SOURCE)
ctx->state &= ~FIMC_COMPOSE;
mutex_unlock(&fimc->lock);
return 0;
@@ -1630,7 +1642,7 @@ static int fimc_subdev_get_selection(struct v4l2_subdev 
*sd,
struct v4l2_rect *r = &sel->r;
struct v4l2_rect *try_sel;
 
-   if (sel->pad != FIMC_SD_PAD_SINK)
+   if (sel->pad == FIMC_SD_PAD_SOURCE)
return -EINVAL;
 
mutex_lock(&fimc->lock);
@@ -1686,7 +1698,7 @@ static int fimc_subdev_set_selection(struct v4l2_subdev 
*sd,
struct v4l2_rect *try_sel;
unsigned long flags;
 
-   if (sel->pad != FIMC_SD_PAD_SINK)
+   if (sel->pad == FIMC_SD_PAD_SOURCE)
return -EINVAL;
 
mutex_lock(&fimc->lock);
@@ -1892,6 +1904,7 @@ int fimc_initialize_capture_subdev(struct fimc_dev *fimc)
snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->id);

[PATCH RFC 05/11] s5p-fimc: Add support for PIXELASYNCMx clocks

2013-03-11 Thread Sylwester Nawrocki 
This patch ads handling of clocks for the CAMBLK subsystem which
is a glue logic for FIMC-IS or LCD controller and FIMC IP.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   41 +++-
 drivers/media/platform/s5p-fimc/fimc-mdevice.h |8 +
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index 0a7c95b..b9f9976 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -944,7 +944,7 @@ static int fimc_md_create_links(struct fimc_md *fmd)
 }
 
 /*
- * The peripheral sensor clock management.
+ * The peripheral sensor and CAM_BLK (PIXELASYNCMx) clocks management.
  */
 static void fimc_md_put_clocks(struct fimc_md *fmd)
 {
@@ -957,6 +957,17 @@ static void fimc_md_put_clocks(struct fimc_md *fmd)
clk_put(fmd->camclk[i].clock);
fmd->camclk[i].clock = ERR_PTR(-EINVAL);
}
+
+   /* Writeback (PIXELASYNCMx) clocks */
+   for (i = 0; i < FIMC_MAX_WBCLKS; i++) {
+   if (IS_ERR(fmd->wbclk[i]))
+   continue;
+   /* FIXME: find better place to disable this clock! */
+   clk_disable(fmd->wbclk[i]);
+   clk_unprepare(fmd->wbclk[i]);
+   clk_put(fmd->wbclk[i]);
+   fmd->wbclk[i] = ERR_PTR(-EINVAL);
+   }
 }
 
 static int fimc_md_get_clocks(struct fimc_md *fmd)
@@ -993,6 +1004,34 @@ static int fimc_md_get_clocks(struct fimc_md *fmd)
if (ret)
fimc_md_put_clocks(fmd);
 
+   if (!fmd->use_isp)
+   return 0;
+   /*
+* For now get only PIXELASYNCM1 clock (Writeback B/ISP),
+* leave PIXELASYNCM0 out for the display driver.
+*/
+   for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) {
+   snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i);
+   clock = clk_get(dev, clk_name);
+   if (IS_ERR(clock)) {
+   v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n",
+ clk_name);
+   ret = PTR_ERR(clock);
+   break;
+   }
+   ret = clk_prepare(clock);
+   if (ret < 0) {
+   clk_put(clock);
+   fmd->wbclk[i] = ERR_PTR(-EINVAL);
+   break;
+   }
+   fmd->wbclk[i] = clock;
+   /* FIXME: find better place to enable this clock! */
+   clk_enable(clock);
+   }
+   if (ret)
+   fimc_md_put_clocks(fmd);
+
return ret;
 }
 
diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.h 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.h
index 5d6146e..91be5db 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.h
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.h
@@ -41,6 +41,13 @@
 #define FIMC_MAX_SENSORS   8
 #define FIMC_MAX_CAMCLKS   2
 
+/* LCD/ISP Writeback clocks (PIXELASYNCMx) */
+enum {
+   CLK_IDX_WB_A,
+   CLK_IDX_WB_B,
+   FIMC_MAX_WBCLKS
+};
+
 struct fimc_csis_info {
struct v4l2_subdev *sd;
int id;
@@ -87,6 +94,7 @@ struct fimc_md {
struct fimc_sensor_info sensor[FIMC_MAX_SENSORS];
int num_sensors;
struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS];
+   struct clk *wbclk[FIMC_MAX_WBCLKS];
struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS];
struct fimc_dev *fimc[FIMC_MAX_DEVS];
struct media_device media_dev;
-- 
1.7.9.5

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[PATCH RFC 04/11] s5p-fimc: Update graph traversal for entities with multiple source pads

2013-03-11 Thread Sylwester Nawrocki 
We cannot assume that the passed entity the fimc_pipeline_prepare()
function is supposed to start the media graph traversal from will
always have its sink pad at pad index 0. Find the starting media
entity's sink pad by iterating over its all pads and checking the
pad flags. This ensures proper handling of FIMC, FIMC-LITE and
FIMC-IS-ISP subdevs that have more than one sink and one source pad.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |   22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c 
b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
index 19cd628..0a7c95b 100644
--- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c
+++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c
@@ -47,7 +47,6 @@ static int __fimc_md_set_camclk(struct fimc_md *fmd,
 static void fimc_pipeline_prepare(struct fimc_pipeline *p,
  struct media_entity *me)
 {
-   struct media_pad *pad = &me->pads[0];
struct v4l2_subdev *sd;
int i;
 
@@ -55,15 +54,21 @@ static void fimc_pipeline_prepare(struct fimc_pipeline *p,
p->subdevs[i] = NULL;
 
while (1) {
-   if (!(pad->flags & MEDIA_PAD_FL_SINK))
-   break;
+   struct media_pad *pad = NULL;
+
+   /* Find remote source pad */
+   for (i = 0; i < me->num_pads; i++) {
+   struct media_pad *spad = &me->pads[i];
+   if (!(spad->flags & MEDIA_PAD_FL_SINK))
+   continue;
+   pad = media_entity_remote_source(spad);
+   if (pad)
+   break;
+   }
 
-   /* source pad */
-   pad = media_entity_remote_source(pad);
if (pad == NULL ||
media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
break;
-
sd = media_entity_to_v4l2_subdev(pad->entity);
 
switch (sd->grp_id) {
@@ -84,8 +89,9 @@ static void fimc_pipeline_prepare(struct fimc_pipeline *p,
pr_warn("%s: Unknown subdev grp_id: %#x\n",
__func__, sd->grp_id);
}
-   /* sink pad */
-   pad = &sd->entity.pads[0];
+   me = &sd->entity;
+   if (me->num_pads == 1)
+   break;
}
 }
 
-- 
1.7.9.5

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[PATCH RFC 02/11] s5p-fimc: Add parent clock setup

2013-03-11 Thread Sylwester Nawrocki 
With this patch the driver will set "parent" clock as a parent
clock of "mux" clock. When the samsung clocks driver is reworked
to use new composite clock type, the "mux" clock can be removed.

"parent" clock should be set in related dtsi file and can be
overwritten in a board dts file. This way it is ensured the
SCLK_FIMC clock has correct parent clock set, and the parent
clock can be selected per each board if required.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-core.c |   63 ++-
 drivers/media/platform/s5p-fimc/fimc-core.h |6 ++-
 2 files changed, 46 insertions(+), 23 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-core.c 
b/drivers/media/platform/s5p-fimc/fimc-core.c
index d7fe332..c968e80 100644
--- a/drivers/media/platform/s5p-fimc/fimc-core.c
+++ b/drivers/media/platform/s5p-fimc/fimc-core.c
@@ -33,8 +33,8 @@
 #include "fimc-reg.h"
 #include "fimc-mdevice.h"
 
-static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
-   "sclk_fimc", "fimc"
+static char *fimc_clocks[CLK_FIMC_MAX] = {
+   "sclk_fimc", "fimc", "mux", "parent"
 };
 
 static struct fimc_fmt fimc_formats[] = {
@@ -787,10 +787,10 @@ struct fimc_fmt *fimc_find_format(const u32 *pixelformat, 
const u32 *mbus_code,
return def_fmt;
 }
 
-static void fimc_clk_put(struct fimc_dev *fimc)
+static void fimc_put_clocks(struct fimc_dev *fimc)
 {
int i;
-   for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
+   for (i = 0; i < CLK_FIMC_MAX; i++) {
if (IS_ERR(fimc->clock[i]))
continue;
clk_unprepare(fimc->clock[i]);
@@ -799,15 +799,21 @@ static void fimc_clk_put(struct fimc_dev *fimc)
}
 }
 
-static int fimc_clk_get(struct fimc_dev *fimc)
+static int fimc_get_clocks(struct fimc_dev *fimc)
 {
+   struct device *dev = &fimc->pdev->dev;
+   unsigned int num_clocks = CLK_FIMC_MAX;
int i, ret;
 
-   for (i = 0; i < MAX_FIMC_CLOCKS; i++)
+   /* Skip parent and mux clocks for non-dt platforms */
+   if (!dev->of_node)
+   num_clocks -= 2;
+
+   for (i = 0; i < CLK_FIMC_MAX; i++)
fimc->clock[i] = ERR_PTR(-EINVAL);
 
-   for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
-   fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
+   for (i = 0; i < num_clocks; i++) {
+   fimc->clock[i] = clk_get(dev, fimc_clocks[i]);
if (IS_ERR(fimc->clock[i])) {
ret = PTR_ERR(fimc->clock[i]);
goto err;
@@ -821,12 +827,32 @@ static int fimc_clk_get(struct fimc_dev *fimc)
}
return 0;
 err:
-   fimc_clk_put(fimc);
-   dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
-   fimc_clocks[i]);
+   fimc_put_clocks(fimc);
+   dev_err(dev, "failed to get clock: %s\n", fimc_clocks[i]);
return -ENXIO;
 }
 
+static int fimc_setup_clocks(struct fimc_dev *fimc, unsigned long freq)
+{
+   int ret;
+
+   if (!IS_ERR(fimc->clock[CLK_PARENT])) {
+   ret = clk_set_parent(fimc->clock[CLK_MUX],
+fimc->clock[CLK_PARENT]);
+   if (ret < 0) {
+   dev_err(&fimc->pdev->dev,
+   "%s(): failed to set parent: %d\n",
+   __func__, ret);
+   return ret;
+   }
+   }
+   ret = clk_set_rate(fimc->clock[CLK_BUS], freq);
+   if (ret < 0)
+   return ret;
+
+   return clk_enable(fimc->clock[CLK_BUS]);
+}
+
 static int fimc_m2m_suspend(struct fimc_dev *fimc)
 {
unsigned long flags;
@@ -968,18 +994,13 @@ static int fimc_probe(struct platform_device *pdev)
return -ENXIO;
}
 
-   ret = fimc_clk_get(fimc);
-   if (ret)
+   ret = fimc_get_clocks(fimc);
+   if (ret < 0)
return ret;
-
if (lclk_freq == 0)
lclk_freq = fimc->drv_data->lclk_frequency;
 
-   ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq);
-   if (ret < 0)
-   return ret;
-
-   ret = clk_enable(fimc->clock[CLK_BUS]);
+   ret = fimc_setup_clocks(fimc, lclk_freq);
if (ret < 0)
return ret;
 
@@ -1016,7 +1037,7 @@ err_sd:
fimc_unregister_capture_subdev(fimc);
 err_clk:
clk_disable(fimc->clock[CLK_BUS]);
-   fimc_clk_put(fimc);
+   fimc_put_clocks(fimc);
return ret;
 }
 
@@ -1103,7 +1124,7 @@ static int fimc_remove(struct platform_device *pdev)
vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
 
clk_disable(fimc->clock[CLK_BUS]);
-   fimc_clk_put(fimc);
+   fimc_put_clocks(fimc);
 
dev_info(&pdev->dev, "driver unloaded\n");
return 0;
diff --git a/drivers/media/platform/s5p-fimc/fimc-core.h 
b/drivers/media/platform/s5p-fimc/fimc-core.h
index 58b674e..67e3201 100644
--- a/driver

[PATCH RFC 03/11] s5p-csis: Add parent clock setup

2013-03-11 Thread Sylwester Nawrocki 
With this patch the driver will set "parent" clock as a parent
clock of "mux" clock. When the samsung clocks driver is reworked
to use new composite clock type, the "mux" clock can be removed.

"parent" clock should be set in relevant dtsi file and can be
overwritten in a board dts file. This way it is ensured the
SCLK_CSIS has correct parent clock set, and the parent clock
can be selected per each board if required.

Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/mipi-csis.c |   66 ++-
 1 file changed, 45 insertions(+), 21 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c 
b/drivers/media/platform/s5p-fimc/mipi-csis.c
index 4673625..6854c9e 100644
--- a/drivers/media/platform/s5p-fimc/mipi-csis.c
+++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
@@ -108,13 +108,17 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)");
 #define S5PCSIS_PKTDATA_SIZE   SZ_4K
 
 enum {
-   CSIS_CLK_MUX,
+   CSIS_CLK_BUS,
CSIS_CLK_GATE,
+   CSIS_CLK_MUX,
+   CSIS_CLK_PARENT,
 };
 
 static char *csi_clock_name[] = {
-   [CSIS_CLK_MUX]  = "sclk_csis",
+   [CSIS_CLK_BUS]  = "sclk_csis",
[CSIS_CLK_GATE] = "csis",
+   [CSIS_CLK_MUX] = "mux",
+   [CSIS_CLK_PARENT] = "parent",
 };
 #define NUM_CSIS_CLOCKSARRAY_SIZE(csi_clock_name)
 #define DEFAULT_SCLK_CSIS_FREQ 16600UL
@@ -362,7 +366,7 @@ static void s5pcsis_set_params(struct csis_state *state)
s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
 }
 
-static void s5pcsis_clk_put(struct csis_state *state)
+static void s5pcsis_put_clocks(struct csis_state *state)
 {
int i;
 
@@ -375,11 +379,16 @@ static void s5pcsis_clk_put(struct csis_state *state)
}
 }
 
-static int s5pcsis_clk_get(struct csis_state *state)
+static int s5pcsis_get_clocks(struct csis_state *state)
 {
struct device *dev = &state->pdev->dev;
+   unsigned int num_clocks = NUM_CSIS_CLOCKS;
int i, ret;
 
+   /* Skip parent and mux clocks for non-dt platforms */
+   if (!dev->of_node)
+   num_clocks -= 2;
+
for (i = 0; i < NUM_CSIS_CLOCKS; i++)
state->clock[i] = ERR_PTR(-EINVAL);
 
@@ -398,11 +407,32 @@ static int s5pcsis_clk_get(struct csis_state *state)
}
return 0;
 err:
-   s5pcsis_clk_put(state);
+   s5pcsis_put_clocks(state);
dev_err(dev, "failed to get clock: %s\n", csi_clock_name[i]);
return ret;
 }
 
+static int s5pcsis_setup_clocks(struct csis_state *state)
+{
+   int ret;
+
+   if (!IS_ERR(state->clock[CSIS_CLK_PARENT])) {
+   ret = clk_set_parent(state->clock[CSIS_CLK_MUX],
+state->clock[CSIS_CLK_PARENT]);
+   if (ret < 0) {
+   dev_err(&state->pdev->dev,
+   "%s(): failed to set parent: %d\n",
+   __func__, ret);
+   return ret;
+   }
+   }
+   ret = clk_set_rate(state->clock[CSIS_CLK_BUS],
+   state->clk_frequency);
+   if (ret < 0)
+   return ret;
+   return clk_enable(state->clock[CSIS_CLK_BUS]);
+}
+
 static void dump_regs(struct csis_state *state, const char *label)
 {
struct {
@@ -725,8 +755,10 @@ static int s5pcsis_get_platform_data(struct 
platform_device *pdev,
dev_err(&pdev->dev, "Platform data not specified\n");
return -EINVAL;
}
-
-   state->clk_frequency = pdata->clk_rate;
+   if (pdata->clk_rate)
+   state->clk_frequency = pdata->clk_rate;
+   else
+   state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
state->num_lanes = pdata->lanes;
state->hs_settle = pdata->hs_settle;
state->index = max(0, pdev->id);
@@ -830,19 +862,11 @@ static int s5pcsis_probe(struct platform_device *pdev)
if (ret)
return ret;
 
-   ret = s5pcsis_clk_get(state);
+   ret = s5pcsis_get_clocks(state);
if (ret < 0)
return ret;
 
-   if (state->clk_frequency)
-   ret = clk_set_rate(state->clock[CSIS_CLK_MUX],
-  state->clk_frequency);
-   else
-   dev_WARN(dev, "No clock frequency specified!\n");
-   if (ret < 0)
-   goto e_clkput;
-
-   ret = clk_enable(state->clock[CSIS_CLK_MUX]);
+   ret = s5pcsis_setup_clocks(state);
if (ret < 0)
goto e_clkput;
 
@@ -885,9 +909,9 @@ static int s5pcsis_probe(struct platform_device *pdev)
return 0;
 
 e_clkdis:
-   clk_disable(state->clock[CSIS_CLK_MUX]);
+   clk_disable(state->clock[CSIS_CLK_BUS]);
 e_clkput:
-   s5pcsis_clk_put(state);
+   s5pcsis_put_clocks(state);
return ret;
 }
 
@@ -990,9 +1014,9 @@ static int s5pcsis_remove(struct platform_device *pdev

[PATCH RFC 01/11] s5p-fimc: Added error checks for pipeline stream on callbacks

2013-03-11 Thread Sylwester Nawrocki 
From: Andrzej Hajda 

set_stream error for pipelines is logged or reported to user
space if possible.

Signed-off-by: Andrzej Hajda 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Kyungmin Park 
---
 drivers/media/platform/s5p-fimc/fimc-capture.c |   15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/s5p-fimc/fimc-capture.c 
b/drivers/media/platform/s5p-fimc/fimc-capture.c
index 2a1da4c..52abc9f 100644
--- a/drivers/media/platform/s5p-fimc/fimc-capture.c
+++ b/drivers/media/platform/s5p-fimc/fimc-capture.c
@@ -286,8 +286,8 @@ static int start_streaming(struct vb2_queue *q, unsigned 
int count)
fimc_activate_capture(ctx);
 
if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
-   fimc_pipeline_call(fimc, set_stream,
-  &fimc->pipeline, 1);
+   return fimc_pipeline_call(fimc, set_stream,
+ &fimc->pipeline, 1);
}
 
return 0;
@@ -443,12 +443,17 @@ static void buffer_queue(struct vb2_buffer *vb)
if (vb2_is_streaming(&vid_cap->vbq) &&
vid_cap->active_buf_cnt >= min_bufs &&
!test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
+   int ret;
+
fimc_activate_capture(ctx);
spin_unlock_irqrestore(&fimc->slock, flags);
 
-   if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
-   fimc_pipeline_call(fimc, set_stream,
-  &fimc->pipeline, 1);
+   if (test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
+   return;
+
+   ret = fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 1);
+   if (ret < 0)
+   v4l2_err(&vid_cap->vfd, "stream on failed: %d\n", ret);
return;
}
spin_unlock_irqrestore(&fimc->slock, flags);
-- 
1.7.9.5

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[PATCH RFC 00/11] s5p-fimc: Exynos4x12 FIMC-IS support prerequisite

2013-03-11 Thread Sylwester Nawrocki 
This patch series contains couple fixes to the s5p-fimc driver
and changes necessary for the Exynos4x12 FIMC-IS support.

Andrzej Hajda (1):
  s5p-fimc: Added error checks for pipeline stream on callbacks

Sylwester Nawrocki (10):
  s5p-fimc: Add parent clock setup
  s5p-csis: Add parent clock setup
  s5p-fimc: Update graph traversal for entities with multiple source
pads
  s5p-fimc: Add support for PIXELASYNCMx clocks
  s5p-fimc: Add the FIMC ISP writeback input support
  s5p-fimc: Ensure CAMCLK clock can be enabled by FIMC-LITE devices
  s5p-fimc: Ensure proper s_stream() call order in the ISP datapaths
  s5p-fimc: Ensure proper s_power() call order in the ISP datapaths
  s5p-fimc: Remove dependency on fimc-core.h in fimc-lite driver
  V4L: Add MATRIX option to V4L2_CID_EXPOSURE_METERING control

 Documentation/DocBook/media/v4l/controls.xml   |9 +-
 drivers/media/platform/s5p-fimc/fimc-capture.c |   46 +---
 drivers/media/platform/s5p-fimc/fimc-core.c|   67 
 drivers/media/platform/s5p-fimc/fimc-core.h|   42 ++--
 drivers/media/platform/s5p-fimc/fimc-lite.c|1 -
 drivers/media/platform/s5p-fimc/fimc-lite.h|3 +-
 drivers/media/platform/s5p-fimc/fimc-mdevice.c |  134 ++--
 drivers/media/platform/s5p-fimc/fimc-mdevice.h |   10 ++
 drivers/media/platform/s5p-fimc/fimc-reg.c |   65 +++-
 drivers/media/platform/s5p-fimc/fimc-reg.h |   10 ++
 drivers/media/platform/s5p-fimc/mipi-csis.c|   66 
 drivers/media/v4l2-core/v4l2-ctrls.c   |1 +
 include/media/s5p_fimc.h   |   34 ++
 include/uapi/linux/v4l2-controls.h |1 +
 14 files changed, 360 insertions(+), 129 deletions(-)

--
1.7.9.5

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Re: [PATCH] mmc: dwmmc: let device core setup the default pin configuration

2013-03-11 Thread Doug Anderson 
Thomas,

On Wed, Mar 6, 2013 at 4:04 AM, Thomas Abraham
 wrote:
> With device core now able to setup the default pin configuration,
> the pin configuration code based on the deprecated Samsung specific
> gpio bindings is removed.
>
> Signed-off-by: Thomas Abraham 
> ---
>  drivers/mmc/host/dw_mmc-exynos.c |   38 
> --
>  1 files changed, 0 insertions(+), 38 deletions(-)

It would be good to address Seungwon Jeon's comments (change prefix to
dw_mmc and remove setup_bus), but in general this looks good to me,
so...

With  on exynos5250-snow
(ARM Chromebook):

Reviewed-by: Doug Anderson 
Tested-by: Doug Anderson 


-Doug
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Re: [PATCH] spi: s3c64xx: let device core setup the default pin configuration

2013-03-11 Thread Doug Anderson 
Thomas,

On Wed, Mar 6, 2013 at 3:42 AM, Thomas Abraham
 wrote:
> With device core now able to setup the default pin configuration,
> the pin configuration code based on the deprecated Samsung specific
> gpio bindings is removed.
>
> Signed-off-by: Thomas Abraham 
> ---
>  .../devicetree/bindings/spi/spi-samsung.txt|8 +--
>  drivers/spi/spi-s3c64xx.c  |   66 +--
>  2 files changed, 6 insertions(+), 68 deletions(-)

With  on exynos5250-snow
(ARM Chromebook):

Reviewed-by: Doug Anderson 
Tested-by: Doug Anderson 

-Doug
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Re: [PATCH 2/2] ARM: dts: add pin state information in client nodes for Exynos5 platforms

2013-03-11 Thread Doug Anderson 
Thomas,

Thank you for doing this!  :)

On Wed, Mar 6, 2013 at 4:36 AM, Thomas Abraham
 wrote:>

> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
> b/arch/arm/boot/dts/exynos5250-snow.dts
> index 17dd951..434e440 100644
> --- a/arch/arm/boot/dts/exynos5250-snow.dts
> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
> @@ -35,9 +50,8 @@
>  */
> dwmmc3@1223 {
> slot@0 {
> -   gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
> -   <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
> -   <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;

nit: Move comment about EMI to the "pinctrl@1140" that you added
earlier in this file.  ...then move the pinctrl-names and pinctrl-0 to
"cros5250.dtsi".  This is not major and could be done in a follow-up
patch.


I done basic testing of this patch series on exynos5250-snow atop
linux-next 20130307.  By series I mean these patchwork IDs:

2224531 New  mmc: sdhci-s3c: let device core setup the default
pin configuration
2224621 New  spi: s3c64xx: let device core setup the default
pin configuration
2224731 New  input: samsung-keypad: let device core setup the
default pin configuration
2224801 New  ASoC: samsung: let device core setup the default
pin configuration
2224851 New  mmc: dwmmc: let device core setup the default pin
configuration
2225141 New  [1/2] ARM: dts: add pin state information in
client nodes for Exynos4 platforms
2225151 New  [2/2] ARM: dts: add pin state information in
client nodes for Exynos5 platforms

Tested-by: Doug Anderson 


This patch looks good to me with or without the above nit fix.

Reviewed-by: Doug Anderson 
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[PATCH -next] ARM: EXYNOS: remove duplicated include from common.c

2013-03-11 Thread Wei Yongjun 
From: Wei Yongjun 

Remove duplicated include.

Signed-off-by: Wei Yongjun 
---
 arch/arm/mach-exynos/common.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399..01e4089 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -23,7 +23,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 

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[PATCH 2/2] ARM: EXYNOS: Support CPU hotplug for exynos5440

2013-03-11 Thread Amit Daniel Kachhap 
This patch adds support for CPU hotlpug for the 3 secondary cores
of the exynos5440 SOC. The command to hotplug out/in is,
echo 0 > /sys/devices/system/cpu/cpu[1-3]/online
echo 1 > /sys/devices/system/cpu/cpu[1-3]/online

Cc: Kukjin Kim 
Signed-off-by: Amit Daniel Kachhap 
---
 arch/arm/mach-exynos/hotplug.c |   14 +++---
 arch/arm/mach-exynos/platsmp.c |   26 +-
 2 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index c3f825b..fbee967 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -93,11 +93,19 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   unsigned int val;
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (soc_is_exynos5440()) {
+   void __iomem *pmu_ctrl2_reg = S5P_VA_CHIPID + 0xc4;
+   val = __raw_readl(pmu_ctrl2_reg);
+   val |= (1 << (cpu + 8));
+   __raw_writel(val, pmu_ctrl2_reg);
+   } else {
+   if (cpu == 1)
+   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   }
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 087b73f..8a5eb80 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -101,6 +101,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int 
cpu, struct task_struct
 {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int val;
 
/*
 * Set synchronisation state between this boot processor
@@ -119,7 +120,30 @@ static int __cpuinit exynos_boot_secondary(unsigned int 
cpu, struct task_struct
write_pen_release(phys_cpu);
 
timeout = 10;
-   if (!soc_is_exynos5440()) {
+   if (soc_is_exynos5440()) {
+   void __iomem *pmu_status_reg = S5P_VA_CHIPID + 0xbc;
+   void __iomem *pmu_ctrl_reg = S5P_VA_CHIPID + 0xc0;
+   void __iomem *pmu_ctrl2_reg = S5P_VA_CHIPID + 0xc4;
+
+   if (!(__raw_readl(pmu_status_reg) & (1 << cpu))) {
+   val = __raw_readl(pmu_ctrl_reg);
+   val |= (1 << cpu);
+   __raw_writel(val, pmu_ctrl_reg);
+   /* wait max 10 ms until cpu1 is on */
+   while (!(__raw_readl(pmu_status_reg) & (1 << cpu))) {
+   if (timeout-- == 0)
+   break;
+
+   mdelay(1);
+   }
+   }
+   /* clear the ctrl2 powerdown */
+   val = __raw_readl(pmu_ctrl2_reg);
+   if (val & (1 << (cpu + 8))) {
+   val &= ~(1 << (cpu + 8));
+   __raw_writel(val, pmu_ctrl2_reg);
+   }
+   } else {
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) &
S5P_CORE_LOCAL_PWR_EN)) {
 
-- 
1.7.1

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[PATCH 1/2] ARM: EXYNOS: enable all secondary cores for exynos5440

2013-03-11 Thread Amit Daniel Kachhap 
This patch enables four cores on exynos5440. Also this patch skips the non
exynos5440 pmu control changes.

Cc: Kukjin Kim 
Signed-off-by: Kukjin Kim 
Signed-off-by: Amit Daniel Kachhap 
---
 arch/arm/mach-exynos/platsmp.c |   44 ++-
 1 files changed, 25 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60f7c5b..087b73f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
 {
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+   else if (soc_is_exynos5440())
+   return S5P_VA_CHIPID + 0x560;
return S5P_VA_SYSRAM;
 }
 
@@ -116,27 +118,29 @@ static int __cpuinit exynos_boot_secondary(unsigned int 
cpu, struct task_struct
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
-
-   timeout = 10;
-
-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-   & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-   if (timeout-- == 0)
-   break;
-
-   mdelay(1);
-   }
-
-   if (timeout == 0) {
-   printk(KERN_ERR "cpu1 power enable failed");
-   spin_unlock(&boot_lock);
-   return -ETIMEDOUT;
+   timeout = 10;
+   if (!soc_is_exynos5440()) {
+   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) &
+   S5P_CORE_LOCAL_PWR_EN)) {
+
+   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+S5P_ARM_CORE1_CONFIGURATION);
+
+   /* wait max 10 ms until this cpu is on */
+   while (!(__raw_readl(S5P_ARM_CORE1_STATUS) &
+   S5P_CORE_LOCAL_PWR_EN)) {
+   if (timeout-- == 0)
+   break;
+   mdelay(1);
+   }
}
}
+   if (timeout == 0) {
+   pr_err("cpu%d power enable failed", cpu);
+   spin_unlock(&boot_lock);
+   return -ETIMEDOUT;
+   }
+
/*
 * Send the secondary CPU a soft interrupt, thereby causing
 * the boot monitor to read the system wide flags register,
@@ -178,6 +182,8 @@ static void __init exynos_smp_init_cpus(void)
 
if (soc_is_exynos5250())
ncores = 2;
+   else if (soc_is_exynos5440())
+   ncores = 4;
else
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
-- 
1.7.1

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Re: [PATCH] watchdog: convert to devm_ioremap_resource()

2013-03-11 Thread Sachin Kamat 
Hi,

On 11 March 2013 13:08, Silviu-Mihai Popescu
 wrote:
> Convert all uses of devm_request_and_ioremap() to the newly introduced
> devm_ioremap_resource() which provides more consistent error handling.
>
> devm_ioremap_resource() provides its own error messages so all explicit
> error messages can be removed from the failure code paths.
>
> Signed-off-by: Silviu-Mihai Popescu 

I have already submitted a similar patchset to do this:
http://www.spinics.net/lists/linux-watchdog/msg02101.html


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Re: [PATCH 1/5] ARM: dts: exynos5250-arndale: Add node entry for gpio-buttons

2013-03-11 Thread Tushar Behera 
On 03/11/2013 07:35 AM, Kukjin Kim wrote:
> Tomasz Figa wrote:
>>
>> Hi,
>>
>> I'm wondering why Exynos5250 has not been migrated to use pinctrl yet.
>>
>> Support for it in pinctrl-samsung driver has been already merged, but I
>> don't see any pinctrl nodes in exynos5250.dtsi.
>>
>> This is important because the legacy gpio-samsung support is going to be
>> dropped, as it already happened in case of Exynos 4.
>>
>> CC'ing Thomas Abraham as he might know something.
>>
> Tushar and all,
> 
> I agree with Tomasz's opinion to support pinctrl instead of gpio on exynos5250
> stuff.
> 
> Please re-submit with using pinctrl is in samsung tree.
> 

Ok. I will rebase the patchset on for-next branch and re-submit.


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[PATCH] watchdog: convert to devm_ioremap_resource()

2013-03-11 Thread Silviu-Mihai Popescu 
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.

devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.

Signed-off-by: Silviu-Mihai Popescu 
---
 drivers/watchdog/ath79_wdt.c   |8 +++-
 drivers/watchdog/davinci_wdt.c |8 +++-
 drivers/watchdog/s3c2410_wdt.c |9 +++--
 3 files changed, 9 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c
index 8987990..d184c48 100644
--- a/drivers/watchdog/ath79_wdt.c
+++ b/drivers/watchdog/ath79_wdt.c
@@ -253,11 +253,9 @@ static int ath79_wdt_probe(struct platform_device *pdev)
return -EINVAL;
}
 
-   wdt_base = devm_request_and_ioremap(&pdev->dev, res);
-   if (!wdt_base) {
-   dev_err(&pdev->dev, "unable to remap memory region\n");
-   return -ENOMEM;
-   }
+   wdt_base = devm_ioremap_resource(&pdev->dev, res);
+   if (IS_ERR(wdt_base))
+   return PTR_ERR(wdt_base);
 
wdt_clk = devm_clk_get(&pdev->dev, "wdt");
if (IS_ERR(wdt_clk))
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 7df1fdc..005fd71 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -221,11 +221,9 @@ static int davinci_wdt_probe(struct platform_device *pdev)
return -ENOENT;
}
 
-   wdt_base = devm_request_and_ioremap(dev, wdt_mem);
-   if (!wdt_base) {
-   dev_err(dev, "ioremap failed\n");
-   return -EADDRNOTAVAIL;
-   }
+   wdt_base = devm_ioremap_resource(dev, wdt_mem);
+   if (IS_ERR(wdt_base))
+   return PTR_ERR(wdt_base);
 
ret = misc_register(&davinci_wdt_miscdev);
if (ret < 0) {
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index c1a221c..393496c 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -330,12 +330,9 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
}
 
/* get the memory region for the watchdog timer */
-   wdt_base = devm_request_and_ioremap(dev, wdt_mem);
-   if (wdt_base == NULL) {
-   dev_err(dev, "failed to devm_request_and_ioremap() region\n");
-   ret = -ENOMEM;
-   goto err;
-   }
+   wdt_base = devm_ioremap_resource(dev, wdt_mem);
+   if (IS_ERR(wdt_base))
+   return PTR_ERR(wdt_base);
 
DBG("probe: mapped wdt_base=%p\n", wdt_base);
 
-- 
1.7.9.5

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RE: [PATCH] ARM: S3C24XX: drop "select MACH_NEO1973"

2013-03-11 Thread Kukjin Kim 
Paul Bolle wrote:
> 
> The Kconfig entry for the Openmoko GTA02 / Freerunner phone selects
> MACH_NEO1973. But there is no Kconfig symbol MACH_NEO1973. The select
> statement for that symbol is a nop. It can safely be dropped.
> 
> Signed-off-by: Paul Bolle 
> ---
> 0) Tested with "git grep".
> 
> 1) There appear to be repositories that carry a "config MACH_NEO1973" in
> their tree. I guess it is used to collect functionality common to the
> GTA01 and the GTA02. But except for this select statement, MACH_NEO1973
> was never used in mainline. So if the GTA01 code ever gets merged into
> mainline, this select statement might be added once more (if it is
> actually needed then).
> 
>  arch/arm/mach-s3c24xx/Kconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
> index 7361b9d..bec43fe 100644
> --- a/arch/arm/mach-s3c24xx/Kconfig
> +++ b/arch/arm/mach-s3c24xx/Kconfig
> @@ -641,7 +641,6 @@ comment "S3C2442 Boards"
>  config MACH_NEO1973_GTA02
>   bool "Openmoko GTA02 / Freerunner phone"
>   select I2C
> - select MACH_NEO1973
>   select MFD_PCF50633
>   select PCF50633_GPIO
>   select POWER_SUPPLY
> --
> 1.7.11.7

Yeah, we don't need it.

Applied, thanks.

- Kukjin

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RE: [PATCH v3] arm: plat-samsung: check processor type before cache restoration in resume

2013-03-11 Thread Kukjin Kim 
Inderpal Singh wrote:
> 
> Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check
> the same before restoring the cache in resume.
> 
> This is needed for single kernel image.
> 
> Signed-off-by: Inderpal Singh 
> ---
> changes in v2:
> - check processor midr instead of checking all soc ids as
> suggested by Kukjin
> 
> changes in v3:
>   - simplify by reading midr in assembly as per Russell
> 
>  arch/arm/plat-samsung/s5p-sleep.S |9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-
> sleep.S
> index bdf6dad..6e15993 100644
> --- a/arch/arm/plat-samsung/s5p-sleep.S
> +++ b/arch/arm/plat-samsung/s5p-sleep.S
> @@ -25,6 +25,9 @@
>  #include 
>  #include 
> 
> +#define CPU_MASK 0xff00
> +#define CPU_CORTEX_A90x410fc090
> +
>  /*
>   *The following code is located into the .data section. This is to
>   *allow l2x0_regs_phys to be accessed with a relative load while we
> @@ -51,6 +54,12 @@
> 
>  ENTRY(s3c_cpu_resume)
>  #ifdef CONFIG_CACHE_L2X0
> + mrc p15, 0, r0, c0, c0, 0
> + ldr r1, =CPU_MASK
> + and r0, r0, r1
> + ldr r1, =CPU_CORTEX_A9
> + cmp r0, r1
> + bne resume_l2on
>   adr r0, l2x0_regs_phys
>   ldr r0, [r0]
>   ldr r1, [r0, #L2X0_R_PHY_BASE]
> --
> 1.7.9.5

Looks good to me, applied.

Thanks.

- Kukjin

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