Re: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific suspend/resume callbacks
On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa t.f...@samsung.com wrote: SoC-specific driver might require additional save and restore of registers. This patch adds pair of SoC-specific callbacks per pinctrl device to account for this. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Patch applied for fixes. Hm this is quite a lot of code for fixes, can you confirm that the system is really unusable without all these patches? Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/6] pinctrl: samsung: Allow per-bank SoC-specific private data
On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa t.f...@samsung.com wrote: This patch extends pin bank descriptor structure with SoC-specific private data field that allows SoC-specific drivers to store their own private data. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Patch applied for fixes. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT registers
On Wed, May 22, 2013 at 4:03 PM, Tomasz Figa t.f...@samsung.com wrote: Some GPIO EINT control registers needs to be preserved across suspend/resume cycle. This patch extends the driver to take care of this. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- Changes since v2: - Fixed error path Changes since v1: - Added optional debugging messages - Added proper error path in initialization v2 version applied for fixes. Again confirm you must really have all this. It is not looking good with diffstats like this for fixing regressions. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/6] pinctrl: samsung: Add support for SoC-specific suspend/resume callbacks
Hi Linus, On Friday 24 of May 2013 11:07:41 Linus Walleij wrote: On Fri, May 17, 2013 at 6:24 PM, Tomasz Figa t.f...@samsung.com wrote: SoC-specific driver might require additional save and restore of registers. This patch adds pair of SoC-specific callbacks per pinctrl device to account for this. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Patch applied for fixes. Thanks. Hm this is quite a lot of code for fixes, can you confirm that the system is really unusable without all these patches? Well, it is something that should have been already sent as a fix for 3.8, when this pin control driver was added, because since then suspend/resume has been broken on DT-enabled Exynos boards. Without this, suspending the board and then trying to wake it up is rather unpredictable, leading usually to board reset, interrupt storm or at least some devices failing to resume. Best regards, -- Tomasz Figa Linux Kernel Developer Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 6/6] pinctrl: exynos: Handle suspend/resume of GPIO EINT registers
Hi Linus, On Friday 24 of May 2013 11:12:00 Linus Walleij wrote: On Wed, May 22, 2013 at 4:03 PM, Tomasz Figa t.f...@samsung.com wrote: Some GPIO EINT control registers needs to be preserved across suspend/resume cycle. This patch extends the driver to take care of this. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- Changes since v2: - Fixed error path Changes since v1: - Added optional debugging messages - Added proper error path in initialization v2 version applied for fixes. I posted v3 two days ago. It fixes a stupid mistake in error path I made in a hurry and also addresses some suggestions from Doug. Again confirm you must really have all this. It is not looking good with diffstats like this for fixing regressions. Yes. The whole series is necessary to have correct suspend/resume support of DT-enabled Exynos boards. Best regards, -- Tomasz Figa Linux Kernel Developer Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs
Hi, On Friday 24 of May 2013 11:25:14 Vikas Sajjan wrote: This patch series does the following: 1) Factors out possible common code, unifies the clk strutures used for PLL35XX PLL36XX and usues clk-base instead of clk-con0 2) Defines a common rate_table which will contain recommended p, m, s and k values for supported rates that needs to be changed for changing corresponding PLL's rate 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX Is rebased on branch kgene's for-next https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h= for-next And tested these patch on chromebook for EPLL settings for Audio on our chrome tree. Vikas Sajjan (2): clk: samsung: Add set_rate() clk_ops for PLL36XX clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Yadwinder Singh Brar (3): clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3XXX clk: samsung: Add support to register rate_table for PLL3XXX clk: samsung: Add set_rate() clk_ops for PLL35XX drivers/clk/samsung/clk-exynos4.c| 10 +- drivers/clk/samsung/clk-exynos5250.c | 29 +++- drivers/clk/samsung/clk-pll.c| 243 ++ drivers/clk/samsung/clk-pll.h| 27 +++- 4 files changed, 272 insertions(+), 37 deletions(-) Could you please send the series properly, with all patches arriving to all necessary mailing lists and with all important people on CC? This and your previous attempts fail to meet this requirement, making it impossible to properly review and comment the patches. Also please add linux-arm-ker...@lists.infradead.org , as it is the primary list for sending clock-related patches (see the MAINTAINERS file). Best regards, -- Tomasz Figa Linux Kernel Developer Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs
Hi Yadwinder, On Friday 24 of May 2013 15:30:58 Yadwinder Singh Brar wrote: Hi Tomasz, All the patches are delivered properly in 2nd attempt to linux-samsung-soc mailing list as seen bellow: Sure, they are delivered to this mailing list, but don't have any other recpients, which makes it impossible to properly reply to them. http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18357.html http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18362.html http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18358.html http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18359.html http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18360.html http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg18361.html Please let me know if you still want us to resend series again 3rd time. Please resend the series again with all the necessary recipients, including this list, linux-arm-kernel list and all the applicable people on CC. Also please do _not_ send HTML messages to mailing lists. Only plain text is accepted on most of them and even some people block HTML messages, since most of the SPAM is sent as HTML. See http://vger.kernel.org/majordomo-info.html for general rules of lists at vger.kernel.org . Best regards, Tomasz Regards, Yadwinder On Fri, May 24, 2013 at 2:57 PM, Tomasz Figa t.f...@samsung.com wrote: Hi, On Friday 24 of May 2013 11:25:14 Vikas Sajjan wrote: This patch series does the following: 1) Factors out possible common code, unifies the clk strutures used for PLL35XX PLL36XX and usues clk-base instead of clk-con0 2) Defines a common rate_table which will contain recommended p, m, s and k values for supported rates that needs to be changed for changing corresponding PLL's rate 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX Is rebased on branch kgene's for-next https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h= for-next And tested these patch on chromebook for EPLL settings for Audio on our chrome tree. Vikas Sajjan (2): clk: samsung: Add set_rate() clk_ops for PLL36XX clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Yadwinder Singh Brar (3): clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3XXX clk: samsung: Add support to register rate_table for PLL3XXX clk: samsung: Add set_rate() clk_ops for PLL35XX drivers/clk/samsung/clk-exynos4.c| 10 +- drivers/clk/samsung/clk-exynos5250.c | 29 +++- drivers/clk/samsung/clk-pll.c| 243 ++ drivers/clk/samsung/clk-pll.h| 27 +++- 4 files changed, 272 insertions(+), 37 deletions(-) Could you please send the series properly, with all patches arriving to all necessary mailing lists and with all important people on CC? This and your previous attempts fail to meet this requirement, making it impossible to properly review and comment the patches. Also please add linux-arm-ker...@lists.infradead.org , as it is the primary list for sending clock-related patches (see the MAINTAINERS file). Best regards, -- Tomasz Figa Linux Kernel Developer Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs
This patch series does the following: 1) Factors out possible common code, unifies the clk strutures used for PLL35XX PLL36XX and usues clk-base instead of clk-con0 2) Defines a common rate_table which will contain recommended p, m, s and k values for supported rates that needs to be changed for changing corresponding PLL's rate 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX Is rebased on branch kgene's for-next https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next And tested these patch on chromebook for EPLL settings for Audio on our chrome tree. Vikas Sajjan (2): clk: samsung: Add set_rate() clk_ops for PLL36XX clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Yadwinder Singh Brar (3): clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3XXX clk: samsung: Add support to register rate_table for PLL3XXX clk: samsung: Add set_rate() clk_ops for PLL35XX drivers/clk/samsung/clk-exynos4.c| 10 +- drivers/clk/samsung/clk-exynos5250.c | 29 +++- drivers/clk/samsung/clk-pll.c| 243 ++ drivers/clk/samsung/clk-pll.h| 27 +++- 4 files changed, 272 insertions(+), 37 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 1/5] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
From: Yadwinder Singh Brar yadi.b...@samsung.com
To factor out possible common code, this patch unifies the clk strutures used
for PLL35xx PLL36xx and usues clk-base instead of clk-con0.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 10 ---
drivers/clk/samsung/clk-exynos5250.c | 14 -
drivers/clk/samsung/clk-pll.c| 54 ++
drivers/clk/samsung/clk-pll.h|4 +--
4 files changed, 44 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index d0940e6..cf7d4e7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
#define GATE_IP_PERIL 0xc950
#define E4210_GATE_IP_PERIR0xc960
#define GATE_BLOCK 0xc970
+#define E4X12_MPLL_LOCK0x10008
#define E4X12_MPLL_CON00x10108
#define SRC_DMC0x10200
#define SRC_MASK_DMC 0x10300
#define DIV_DMC0 0x10500
#define DIV_DMC1 0x10504
#define GATE_IP_DMC0x10900
+#define APLL_LOCK 0x14000
#define APLL_CON0 0x14100
#define E4210_MPLL_CON00x14108
#define SRC_CPU0x14200
@@ -1019,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + APLL_CON0);
+ reg_base + APLL_LOCK);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + E4X12_MPLL_CON0);
+ reg_base + E4X12_MPLL_LOCK);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + EPLL_CON0);
+ reg_base + EPLL_LOCK);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
- reg_base + VPLL_CON0);
+ reg_base + VPLL_LOCK);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + 0x100);
+ reg_base);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4100);
+ reg_base + 0x4000);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20110);
+ reg_base + 0x20010);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10150);
+ reg_base + 0x10050);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10120);
+ reg_base + 0x10020);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10130);
+ reg_base + 0x10030);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10140);
+ reg_base + 0x10040);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..01f17cf 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
#include clk.h
#include clk-pll.h
+struct samsung_clk_pll {
+ struct clk_hw hw;
+ const void __iomem *base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset) \
+ __raw_readl((void __iomem *)(pll-base + (offset)));
+#define pll_writel(pll, val, offset) \
+ __raw_writel(val, (void __iomem *)(pll-base + (offset)));
+
/*
* PLL35xx Clock Type
*/
+#define PLL35XX_LOCK_OFFSET 0x0
+#define PLL35XX_CON0_OFFSET 0x100
+#define PLL35XX_CON1_OFFSET 0x104
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
@@ -24,21 +39,14 @@
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
[RESEND PATCH 2/5] clk: samsung: Add support to register rate_table for PLL3xxx
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch defines a common rate_table which will contain recommended p, m, s
and k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
It also sorts the rate table while registering the PLL rate table.
So that this sorted table can be used for making the searching of required
rate efficient.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c|8
drivers/clk/samsung/clk-exynos5250.c | 14 +++---
drivers/clk/samsung/clk-pll.c| 35 --
drivers/clk/samsung/clk-pll.h| 27 --
4 files changed, 69 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + APLL_LOCK);
+ reg_base + APLL_LOCK, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + E4X12_MPLL_LOCK);
+ reg_base + E4X12_MPLL_LOCK, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + EPLL_LOCK);
+ reg_base + EPLL_LOCK, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
- reg_base + VPLL_LOCK);
+ reg_base + VPLL_LOCK, NULL, 0);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base);
+ reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4000);
+ reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20010);
+ reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10050);
+ reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10020);
+ reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030);
+ reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10040);
+ reg_base + 0x10040, NULL, 0);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 01f17cf..b8c0260 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,12 +10,15 @@
*/
#include linux/errno.h
+#include linux/sort.h
#include clk.h
#include clk-pll.h
struct samsung_clk_pll {
struct clk_hw hw;
const void __iomem *base;
+ struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
};
#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -25,6 +28,14 @@ struct samsung_clk_pll {
#define pll_writel(pll, val, offset) \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
+static int samsung_compare_rate(const void *_a, const void *_b)
+{
+ const struct samsung_pll_rate_table *a = _a;
+ const struct samsung_pll_rate_table *b = _b;
+
+ return a-rate - b-rate;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -62,7 +73,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
};
struct clk * __init samsung_clk_register_pll35xx(const char *name,
- const char *pname, const void __iomem *base)
+ const char *pname, const void __iomem *base,
+ struct samsung_pll_rate_table *rate_table,
+
[RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx
From: Yadwinder Singh Brar yadi.b...@samsung.com
Adds set_rate() and round_rate() clk_ops for PLL35xx
The round_rate() implemenation as of now is dummy, it returns the same rate
which is passed as input.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 95 -
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b8c0260..291cc9e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -11,6 +11,7 @@
#include linux/errno.h
#include linux/sort.h
+#include linux/bsearch.h
#include clk.h
#include clk-pll.h
@@ -36,6 +37,21 @@ static int samsung_compare_rate(const void *_a, const void
*_b)
return a-rate - b-rate;
}
+static struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long rate)
+{
+ struct samsung_pll_rate_table req_rate, *tmp;
+
+ req_rate.rate = rate;
+ tmp = bsearch(req_rate, pll-rate_table, pll-rate_count,
+ sizeof(struct samsung_pll_rate_table),
+ samsung_compare_rate);
+ if (tmp)
+ return tmp;
+
+ return NULL;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -46,9 +62,15 @@ static int samsung_compare_rate(const void *_a, const void
*_b)
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
+
+#define PLL35XX_MDIV(_tmp) ((_tmp) (PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT))
+#define PLL35XX_PDIV(_tmp) ((_tmp) (PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT))
+#define PLL35XX_SDIV(_tmp) ((_tmp) (PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT))
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -68,8 +90,76 @@ static unsigned long samsung_pll35xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
-static const struct clk_ops samsung_pll35xx_clk_ops = {
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ if ((mdiv != PLL35XX_MDIV(pll_con)) || (pdiv != PLL35XX_PDIV(pll_con)))
+ return 1;
+ else
+ return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ struct samsung_pll_rate_table *rate;
+
+ u32 tmp, mdiv, pdiv, sdiv;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ mdiv = PLL35XX_MDIV(rate-pll_con0);
+ pdiv = PLL35XX_PDIV(rate-pll_con0);
+ sdiv = PLL35XX_SDIV(rate-pll_con0);
+
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+ if (!(samsung_pll35xx_mp_change(mdiv, pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
+ tmp |= sdiv;
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+ } else {
+ /* Set PLL lock time.
+ Maximum lock time can be 270 * PDIV cycles */
+ pll_writel(pll, (pdiv PLL35XX_PDIV_SHIFT) * 270,
+ PLL35XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT) |
+ (PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT));
+ tmp |= mdiv | pdiv | sdiv;
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+ } while (!(tmp (PLL35XX_LOCK_STAT_MASK
+PLL35XX_LOCK_STAT_SHIFT)));
+ }
+
+ return 0;
+}
+
+static long samsung_pll35xx_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ /* Clock framework cries without this, so implemented dummy */
+ return drate;
+}
+
+static struct clk_ops samsung_pll35xx_clk_ops = {
.recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll35xx_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
};
struct clk * __init samsung_clk_register_pll35xx(const char *name,
@@ -102,6 +192,9
[RESEND PATCH 5/5] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..00d1fa6 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -469,6 +469,21 @@ static __initdata struct of_device_id ext_clk_match[] = {
{ },
};
+static struct samsung_pll_rate_table vpll_tbl[] = {
+ PLL_36XX_RATE(7050, 2, 94, 4, 0),
+};
+
+static struct samsung_pll_rate_table epll_tbl[] = {
+ PLL_36XX_RATE(19200, 48, 3, 1, 0),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+ PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+ PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+ PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+ PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+ PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
/* register exynox5250 clocks */
void __init exynos5250_clk_init(struct device_node *np)
{
@@ -501,9 +516,9 @@ void __init exynos5250_clk_init(struct device_node *np)
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030, NULL, 0);
+ reg_base + 0x10030, epll_tbl, ARRAY_SIZE(epll_tbl));
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10040, NULL, 0);
+ reg_base + 0x10040, vpll_tbl, ARRAY_SIZE(vpll_tbl));
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Pulls and drive strengths in the pinctrl world
On 15:42 Thu 23 May , Stephen Warren wrote: On 05/19/2013 03:17 AM, Jean-Christophe PLAGNIOL-VILLARD wrote: ... how a pin can not have mux? Well, if that's the way HW is designed, that's just the way it is. There are certainly pins on Tegra which don't have a mux in HW, but have some configuration options such as drive strength that can be configured. on Samsung it's not the case I mean on at91 we have fixed mux and configurable mux On Tegra IIRC it's the same Best Regards, J. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC
On 05/23/13 21:15, 이정석 wrote:
This patch fixes software reset logic. Software reset applies only to
powered-on domains in SOC because software reset to all domains causes
reboot failure.
Signed-off-by: Jungseok Leejays@samsung.com
---
arch/arm/mach-exynos/common.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7f431dd..a22615d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -317,9 +317,13 @@ void exynos5_restart(char mode, const char *cmd)
val = 0x1;
addr = EXYNOS_SWRESET;
} else if (of_machine_is_compatible(samsung,exynos5440)) {
+ u32 status;
np = of_find_compatible_node(NULL, NULL,
samsung,exynos5440-clock);
line wrapped?
+ addr = of_iomap(np, 0) + 0xbc;
+ status = __raw_readl(addr);
addr = of_iomap(np, 0) + 0xcc;
- val = (0xfff 20) | (0x1 16);
+ val = __raw_readl(addr);
+ val = (val 0x) | (status 0x);
} else {
pr_err(%s: cannot support non-DT\n, __func__);
return;
Looks good to me, applied after fixing line wrapped.
Thanks.
- Kukjin
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
On 05/16/13 00:09, Tomasz Figa wrote:
Since commit 1977e6d8 (drm/exynos: change the method for getting the
interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
named. This patch fixes probe failure in non-DT cases by adding
appropriate resource names to fimd0 platform device.
Signed-off-by: Tomasz Figat.f...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
arch/arm/plat-samsung/devs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 30c2fe2..0f9c3f4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
#ifdef CONFIG_S5P_DEV_FIMD0
static struct resource s5p_fimd0_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
- [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
- [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
- [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
+ [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, vsync),
+ [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, fifo),
+ [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, lcd_sys),
};
struct platform_device s5p_device_fimd0 = {
Applied into fixes.
Thanks.
- Kukjin
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: SAMSUNG: devs: Add names to fimd0 IRQ resources
On 05/16/13 00:09, Tomasz Figa wrote:
Since commit 1977e6d8 (drm/exynos: change the method for getting the
interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
named. This patch fixes probe failure in non-DT cases by adding
appropriate resource names to fimd0 platform device.
Signed-off-by: Tomasz Figat.f...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
---
arch/arm/plat-samsung/devs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 30c2fe2..0f9c3f4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
#ifdef CONFIG_S5P_DEV_FIMD0
static struct resource s5p_fimd0_resource[] = {
[0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
- [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
- [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
- [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
+ [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, vsync),
+ [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, fifo),
+ [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, lcd_sys),
};
struct platform_device s5p_device_fimd0 = {
Applied into fixes.
Thanks.
- Kukjin
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH 1/5] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Hi, On Friday 24 of May 2013 16:01:14 Vikas Sajjan wrote: From: Yadwinder Singh Brar yadi.b...@samsung.com To factor out possible common code, this patch unifies the clk strutures used for PLL35xx PLL36xx and usues clk-base instead of clk-con0. Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com --- drivers/clk/samsung/clk-exynos4.c| 10 --- drivers/clk/samsung/clk-exynos5250.c | 14 - drivers/clk/samsung/clk-pll.c| 54 ++ drivers/clk/samsung/clk-pll.h |4 +-- 4 files changed, 44 insertions(+), 38 deletions(-) Whether this patch really allows to factor out any significant amount of common code is rather discussible, but generally looks fine. Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: add PM dependency to PM_GENERIC_DOMAINS for Exynos4210
On 05/14/13 10:19, Jingoo Han wrote: PM_GENERIC_DOMAINS needs PM dependency. Fixed build warning as below: warning: (PLAT_S3C64XX CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM) If so, PLAT_S3C64XX should be fixed together. diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 2057853..c04c4ee 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -8,7 +8,7 @@ config PLAT_S3C64XX bool depends on ARCH_S3C64XX default y - select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS if PM select SAMSUNG_WAKEMASK help Base platform code for any Samsung S3C64XX device warning: (PLAT_S3C64XX CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS which has unmet direct dependencies (PM) arch/arm/kernel/return_address.c:63:2: warning: #warning TODO: return_address should use unwind tables [-Wcpp] drivers/base/power/domain.c: In function '__pm_genpd_add_device': drivers/base/power/domain.c:1422:2: error: implicit declaration of function 'genpd_acquire_lock' [-Werror=implicit-function-declaration] drivers/base/power/domain.c:1466:2: error: implicit declaration of function 'genpd_release_lock' [-Werror=implicit-function-declaration] drivers/base/power/domain.c: In function 'pm_genpd_add_subdomain': drivers/base/power/domain.c:1649:3: error: implicit declaration of function 'genpd_sd_counter_inc' [-Werror=implicit-function-declaration] drivers/base/power/domain.c: In function 'pm_genpd_remove_subdomain': drivers/base/power/domain.c:1721:4: error: implicit declaration of function 'genpd_sd_counter_dec' [-Werror=implicit-function-declaration] drivers/base/power/domain.c: In function 'pm_genpd_attach_cpuidle': drivers/base/power/domain.c:1887:2: error: implicit declaration of function 'genpd_recalc_cpu_exit_latency' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors Signed-off-by: Jingoo Hanjg1@samsung.com --- arch/arm/mach-exynos/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d19edff..1f7ddb2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -34,7 +34,7 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 select ARM_CPU_SUSPEND if PM - select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH 2/5] clk: samsung: Add support to register rate_table for PLL3xxx
Hi,
Please see my comments inline.
On Friday 24 of May 2013 16:01:15 Vikas Sajjan wrote:
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch defines a common rate_table which will contain recommended p,
m, s and k values for supported rates that needs to be changed for
changing corresponding PLL's rate.
It also sorts the rate table while registering the PLL rate table.
So that this sorted table can be used for making the searching of
required rate efficient.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c|8
drivers/clk/samsung/clk-exynos5250.c | 14 +++---
drivers/clk/samsung/clk-pll.c| 35
-- drivers/clk/samsung/clk-pll.h
| 27 -- 4 files changed, 69 insertions(+), 15
deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c index cf7d4e7..beff8a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1021,13 +1021,13 @@ void __init exynos4_clk_init(struct device_node
*np, enum exynos4_soc exynos4_so reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll,
fin_pll,
- reg_base + APLL_LOCK);
+ reg_base + APLL_LOCK, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll,
fin_pll,
- reg_base + E4X12_MPLL_LOCK);
+ reg_base + E4X12_MPLL_LOCK, NULL,
0);
epll = samsung_clk_register_pll36xx(fout_epll,
fin_pll,
- reg_base + EPLL_LOCK);
+ reg_base + EPLL_LOCK, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll,
fin_pll,
- reg_base + VPLL_LOCK);
+ reg_base + VPLL_LOCK, NULL, 0);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node
*np) ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base);
+ reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4000);
+ reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20010);
+ reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10050);
+ reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10020);
+ reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030);
+ reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10040);
+ reg_base + 0x10040, NULL, 0);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 01f17cf..b8c0260 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,12 +10,15 @@
*/
#include linux/errno.h
+#include linux/sort.h
#include clk.h
#include clk-pll.h
struct samsung_clk_pll {
struct clk_hw hw;
const void __iomem *base;
+ struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
};
#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -25,6 +28,14 @@ struct samsung_clk_pll {
#define pll_writel(pll, val, offset) \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
+static int samsung_compare_rate(const void *_a, const void *_b)
+{
+ const struct samsung_pll_rate_table *a = _a;
+ const struct samsung_pll_rate_table *b = _b;
+
+ return a-rate - b-rate;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -62,7 +73,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops =
{ };
struct clk * __init samsung_clk_register_pll35xx(const char *name,
- const char *pname, const void __iomem *base)
+ const char *pname, const void __iomem *base,
+ struct
Re: [RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx
Hi,
On Friday 24 of May 2013 16:01:16 Vikas Sajjan wrote:
From: Yadwinder Singh Brar yadi.b...@samsung.com
Adds set_rate() and round_rate() clk_ops for PLL35xx
The round_rate() implemenation as of now is dummy, it returns the same
rate which is passed as input.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 95
- 1 file changed, 94
insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index b8c0260..291cc9e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -11,6 +11,7 @@
#include linux/errno.h
#include linux/sort.h
+#include linux/bsearch.h
#include clk.h
#include clk-pll.h
@@ -36,6 +37,21 @@ static int samsung_compare_rate(const void *_a, const
void *_b) return a-rate - b-rate;
}
+static struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long
rate)
+{
+ struct samsung_pll_rate_table req_rate, *tmp;
+
+ req_rate.rate = rate;
+ tmp = bsearch(req_rate, pll-rate_table, pll-rate_count,
+ sizeof(struct samsung_pll_rate_table),
+ samsung_compare_rate);
Binary search over 10 entries? Isn't it a bit of overkill?
+ if (tmp)
+ return tmp;
+
+ return NULL;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -46,9 +62,15 @@ static int samsung_compare_rate(const void *_a, const
void *_b) #define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
+
+#define PLL35XX_MDIV(_tmp) ((_tmp) (PLL35XX_MDIV_MASK
PLL35XX_MDIV_SHIFT)) +#define PLL35XX_PDIV(_tmp) ((_tmp)
(PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT)) +#define PLL35XX_SDIV(_tmp)
((_tmp) (PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT))
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -68,8 +90,76 @@ static unsigned long
samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned
long)fvco;
}
-static const struct clk_ops samsung_pll35xx_clk_ops = {
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32
pll_con) +{
+ if ((mdiv != PLL35XX_MDIV(pll_con)) || (pdiv !=
PLL35XX_PDIV(pll_con))) + return 1;
+ else
+ return 0;
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ struct samsung_pll_rate_table *rate;
+
+ u32 tmp, mdiv, pdiv, sdiv;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ mdiv = PLL35XX_MDIV(rate-pll_con0);
+ pdiv = PLL35XX_PDIV(rate-pll_con0);
+ sdiv = PLL35XX_SDIV(rate-pll_con0);
You wouldn't need to use those macros if all coefficients were stored as
separate fields in the struct.
+
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+ if (!(samsung_pll35xx_mp_change(mdiv, pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
+ tmp |= sdiv;
This line is correct, but it looks like it wasn't, because:
a) the name suggests that it contains the raw value of S coefficient
b) it's real value is hidden between a macro, name of which suggests the
same as in a) as well.
This makes the code hard to read.
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+ } else {
+ /* Set PLL lock time.
+Maximum lock time can be 270 * PDIV cycles */
+ pll_writel(pll, (pdiv PLL35XX_PDIV_SHIFT) * 270,
+ PLL35XX_LOCK_OFFSET);
Hmm, magic constant in the code? Shouldn't it be defined as a macro?
+
+ /* Change PLL PMS values */
+ tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT)
|
+ (PLL35XX_SDIV_MASK
PLL35XX_SDIV_SHIFT));
+ tmp |= mdiv | pdiv | sdiv;
This looks strange as well, even if it's correct.
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+ } while (!(tmp
Re: [RESEND PATCH 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx
Hi, On Friday 24 of May 2013 16:01:17 Vikas Sajjan wrote: This patch adds set_rate and round_rate clk_ops for PLL36xx The round_rate() implementation as of now is dummy, it returns the same rate which is passed as input. Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org --- drivers/clk/samsung/clk-pll.c | 67 + 1 file changed, 67 insertions(+) I have exactly the same comments for this patch as for patch 3/5. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung fixes-3 for v3.10
The following changes since commit f722406faae2d073cc1d01063d1123c35425939e: Linux 3.10-rc1 (2013-05-11 17:14:08 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-3 for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be: ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 +0900) Fixes following for v3.10 - to get usb2 working on the Chromebook with adding the usb phy node for usb2 on exynos5250 - supporting exynos4210 rev0 SoC - exynos5440 restart applying only to powered-on domains - drm-exynos probe failure with adding resource names to fimd0 platform device Jungseok Lee (1): ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC Tomasz Figa (2): ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC ARM: SAMSUNG: Add names to fimd0 IRQ resources Vivek Gautam (1): ARM: dts: Enabling samsung-usb2phy driver for exynos5250 arch/arm/boot/dts/exynos5250.dtsi | 15 arch/arm/mach-exynos/Kconfig | 3 ++- arch/arm/mach-exynos/common.c | 39 -- arch/arm/mach-exynos/common.h | 2 ++ arch/arm/mach-exynos/mach-universal_c210.c | 5 ++-- arch/arm/plat-samsung/devs.c | 6 ++--- 6 files changed, 61 insertions(+), 9 deletions(-) The following changes since commit f722406faae2d073cc1d01063d1123c35425939e: Linux 3.10-rc1 (2013-05-11 17:14:08 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-3 for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be: ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 +0900) Fixes following for v3.10 - to get usb2 working on the Chromebook with adding the usb phy node for usb2 on exynos5250 - supporting exynos4210 rev0 SoC - exynos5440 restart applying only to powered-on domains - drm-exynos probe failure with adding resource names to fimd0 platform device Jungseok Lee (1): ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC Tomasz Figa (2): ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC ARM: SAMSUNG: Add names to fimd0 IRQ resources Vivek Gautam (1): ARM: dts: Enabling samsung-usb2phy driver for exynos5250 arch/arm/boot/dts/exynos5250.dtsi | 15 arch/arm/mach-exynos/Kconfig | 3 ++- arch/arm/mach-exynos/common.c | 39 -- arch/arm/mach-exynos/common.h | 2 ++ arch/arm/mach-exynos/mach-universal_c210.c | 5 ++-- arch/arm/plat-samsung/devs.c | 6 ++--- 6 files changed, 61 insertions(+), 9 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
