Re: [PATCH v2 0/6] Convert S3C2416 ad S3C2443 to common clock framework
On 10 July 2013 04:27, Heiko Stübner he...@sntech.de wrote: This series provides a clock driver for s3c2416, s3c2443 and s3c2450, which share a common clock tree, but differ fundamentally from earlier s3c24xx SoCs, and converts the mentioned SoCs to use it. The clock driver itself follows the same scheme established by all other Samsung clock drivers. It depends on the pwm cleanup series from Tomasz Figa, which gets rid of the declarations of the pwm-internal clocks. Test on both non-dt and dt s3c2416. Heiko Stuebner (6): clk: samsung: move common plls registration into separate function clk: samsung: fix error handling in pll register functions clk: samsung: add plls used in s3c2416 and s3c2443 ARM: S3C24XX: enable legacy clock code only when SAMSUNG_CLOCK selected clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450 ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework .../bindings/clock/samsung,s3c2443-clock.txt | 48 ++ arch/arm/boot/dts/s3c2416-smdk2416.dts |7 + arch/arm/boot/dts/s3c2416.dtsi | 42 ++ arch/arm/mach-s3c24xx/Kconfig | 14 +- arch/arm/mach-s3c24xx/Makefile |5 +- arch/arm/mach-s3c24xx/clock-s3c2416.c | 171 - arch/arm/mach-s3c24xx/clock-s3c2443.c | 212 -- arch/arm/mach-s3c24xx/common-s3c2443.c | 675 arch/arm/mach-s3c24xx/common.c | 20 +- arch/arm/mach-s3c24xx/common.h |8 + arch/arm/mach-s3c24xx/mach-s3c2416-dt.c| 45 +- arch/arm/mach-s3c24xx/mach-smdk2416.c |9 +- arch/arm/mach-s3c24xx/mach-smdk2443.c |9 +- drivers/clk/Kconfig|1 + drivers/clk/samsung/Kconfig|2 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-pll.c | 374 +-- drivers/clk/samsung/clk-pll.h |8 + drivers/clk/samsung/clk-s3c2443.c | 422 include/dt-bindings/clock/samsung,s3c2443-clock.h | 96 +++ 20 files changed, 998 insertions(+), 1171 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c create mode 100644 drivers/clk/samsung/Kconfig create mode 100644 drivers/clk/samsung/clk-s3c2443.c create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h -- 1.7.10.4 Thanks for consolidating pll registrations. For patches 1 to 3: Reviewed-by: Thomas Abraham thomas.abra...@linaro.org -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] ARM: dts: Correct the /include entry on exynos5420 dtsi file
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 8c54c4b..da55160 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,7 @@
*/
#include exynos5.dtsi
-/include/ exynos5420-pinctrl.dtsi
+#include exynos5420-pinctrl.dtsi
/ {
compatible = samsung,exynos5420;
--
1.7.4.4
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[PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree
From: Andrew Bresticker abres...@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified
via device-tree bindings. Default names will be used when an input clock
is not given. This will be useful when adding support for the Exynos5420
where the audio bus clock is called sclk_maudio0 instead of sclk_audio0.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57833
Reviewed-by: Simon Glass s...@chromium.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++-
drivers/clk/samsung/clk-exynos-audss.c | 28 +++--
2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 3115930..66d4662 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -16,6 +16,21 @@ Required Properties:
- #clock-cells: should be 1.
+Optional Properties:
+
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. fin_pll
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. fout_epll
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. cdclk0 is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. sclk_audio0 is used if
+not specified.
+
+- clock-names: Aliases for the above clocks. They should be pll_ref,
+ pll_in, cdclk, and sclk_audio, respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -38,15 +53,27 @@ pcm_bus 8
sclk_pcm9
adma10 Exynos5420
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: An example of a clock controller node with audio bus input clock
+ specified is listed below.
clock_audss: audss-clock-controller@381 {
compatible = samsung,exynos5250-audss-clock;
reg = 0x0381 0x0C;
#clock-cells = 1;
+ clocks = clock 148;
+ clock-names = sclk_audio;
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..39d3383 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { fin_pll, fout_epll };
-static const char *mout_i2s_p[] = { mout_audss, cdclk0, sclk_audio0 };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
/* register exynos_audss clocks */
void __init exynos_audss_clk_init(struct device_node *np)
{
+ const char *mout_audss_p[] = {fin_pll, fout_epll};
+ const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio;
+
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err(%s: failed to map audss registers\n, __func__);
@@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np)
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+ pll_ref = of_clk_get_by_name(np, pll_ref);
+ pll_in = of_clk_get_by_name(np, pll_in);
+ if (!IS_ERR(pll_ref)) {
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ clk_put(pll_ref);
+ }
+ if (!IS_ERR(pll_in)) {
+ mout_audss_p[1] = __clk_get_name(pll_in);
+ clk_put(pll_in);
+ }
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
+ cdclk = of_clk_get_by_name(np, cdclk);
+ sclk_audio = of_clk_get_by_name(np, sclk_audio);
+ if (!IS_ERR(cdclk)) {
+ mout_i2s_p[1] = __clk_get_name(cdclk);
+
[PATCH 4/4] ARM: dts: exynos5420: add audio clock controller
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57712
Reviewed-by: Simon Glass s...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index da55160..a84f5f1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -15,6 +15,9 @@
#include exynos5.dtsi
#include exynos5420-pinctrl.dtsi
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5420;
@@ -65,6 +68,14 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5420-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ clocks = clock 148;
+ clock-names = sclk_audio;
+ };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
--
1.7.4.4
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[PATCH 1/4] clk: exynos-audss: add support for Exynos 5420
From: Andrew Bresticker abres...@chromium.org
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit.chromium.org/gerrit/57711
Reviewed-by: Simon Glass s...@chromium.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt |7 +--
drivers/clk/samsung/clk-exynos-audss.c |8
include/dt-bindings/clk/exynos-audss-clk.h |3 ++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a120180..3115930 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
- - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
-
+ - samsung,exynos5250-audss-clock - controller compatible with Exynos5250
+SoCs.
+ - samsung,exynos5420-audss-clock - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -34,6 +36,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..86d2606 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np)
div_pcm0, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
+ if (of_device_is_compatible(np, samsung,exynos5420-audss-clock)) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, adma,
+ dout_srp, CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, lock);
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(exynos_audss_clk_syscore_ops);
#endif
@@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk,
samsung,exynos4210-audss-clock,
exynos_audss_clk_init);
CLK_OF_DECLARE(exynos5250_audss_clk, samsung,exynos5250-audss-clock,
exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5420_audss_clk, samsung,exynos5420-audss-clock,
+ exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define EXYNOS_ADMA10
-#define EXYNOS_AUDSS_MAX_CLKS 10
+#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
--
1.7.4.4
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[PATCH 0/2] Move comon DMA nodes to exynos5.dtsi and
Exynos5250 and Exynos5420 has 4 DMA controllers in common. So this patch set moved the common nodes to exynos.dtsi keeping the clk info seperate for both the platforms. Exynos5420 has a separate DMA controller for audio IPs. So this patch set also adds the ADMA node on Exynos5420. Padmavathi Venna (2): ARM: dts: Move the common DMA controller nodes to exynos5.dtsi ARM: dts: Add DMA controller node info on Exynos5420. arch/arm/boot/dts/exynos5.dtsi| 44 + arch/arm/boot/dts/exynos5250.dtsi | 30 - arch/arm/boot/dts/exynos5420.dtsi | 33 +++ 3 files changed, 77 insertions(+), 30 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: Move the common DMA controller nodes to exynos5.dtsi
exynos5250 and exynos5420 has 4 DMA controllers in common. So this patch
moves these nodes to common file keeping the dma controllers clk info in
the exynos5250 dtsi file.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 44 +
arch/arm/boot/dts/exynos5250.dtsi | 30 -
2 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..cac35c8 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,6 +50,50 @@
interrupts = 1 9 0xf04;
};
+ amba {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = arm,amba-bus;
+ interrupt-parent = gic;
+ ranges;
+
+ pdma0: pdma@121A {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121A 0x1000;
+ interrupts = 0 34 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ pdma1: pdma@121B {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x121B 0x1000;
+ interrupts = 0 35 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 32;
+ };
+
+ mdma0: mdma@1080 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x1080 0x1000;
+ interrupts = 0 33 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+
+ mdma1: mdma@11C1 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x11C1 0x1000;
+ interrupts = 0 124 0;
+ #dma-cells = 1;
+ #dma-channels = 8;
+ #dma-requests = 1;
+ };
+ };
+
dwmmc_0: dwmmc0@1220 {
compatible = samsung,exynos5250-dw-mshc;
interrupts = 0 75 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 41cd625..3a474c4 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -511,54 +511,24 @@
};
amba {
- #address-cells = 1;
- #size-cells = 1;
- compatible = arm,amba-bus;
- interrupt-parent = gic;
- ranges;
-
pdma0: pdma@121A {
- compatible = arm,pl330, arm,primecell;
- reg = 0x121A 0x1000;
- interrupts = 0 34 0;
clocks = clock 275;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 32;
};
pdma1: pdma@121B {
- compatible = arm,pl330, arm,primecell;
- reg = 0x121B 0x1000;
- interrupts = 0 35 0;
clocks = clock 276;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 32;
};
mdma0: mdma@1080 {
- compatible = arm,pl330, arm,primecell;
- reg = 0x1080 0x1000;
- interrupts = 0 33 0;
clocks = clock 271;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 1;
};
mdma1: mdma@11C1 {
- compatible = arm,pl330, arm,primecell;
- reg = 0x11C1 0x1000;
- interrupts = 0 124 0;
clocks = clock 271;
clock-names = apb_pclk;
- #dma-cells = 1;
- #dma-channels = 8;
- #dma-requests = 1;
};
};
--
1.7.4.4
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[PATCH 2/2] ARM: dts: Add DMA controller node info on Exynos5420.
Exynos5420 has one separate DMA controller for I2S0 and PCM0. This patch
adds the same node on exynos5420 dtsi and adds the DMA clk info for the
remaining DMA controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index a84f5f1..7035a4b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -137,6 +137,39 @@
interrupts = 0 47 0;
};
+ amba {
+ pdma0: pdma@121A {
+ clocks = clock 362;
+ clock-names = apb_pclk;
+ };
+
+ pdma1: pdma@121B {
+ clocks = clock 363;
+ clock-names = apb_pclk;
+ };
+
+ mdma0: mdma@1080 {
+ clocks = clock 473;
+ clock-names = apb_pclk;
+ };
+
+ mdma1: mdma@11C1 {
+ clocks = clock 442;
+ clock-names = apb_pclk;
+ };
+
+ adma: adma@0388 {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x0388 0x1000;
+ interrupts = 0 110 0;
+ clocks = clock_audss EXYNOS_ADMA;
+ clock-names = apb_pclk;
+ #dma-cells = 1;
+ #dma-channels = 6;
+ #dma-requests = 16;
+ };
+ };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
--
1.7.4.4
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Re: [PATCH] pci: exynos: split into two parts such as Synopsys part and Exynos part
Hi, On Friday 05 July 2013 01:59 PM, Jingoo Han wrote: Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys designware part; other parts are Exynos specific. Also, the Synopsys designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys designware part and Exynos specific part. Thanks for doing that :-) I'll be using the synopsys specific part as Jacinto6 also uses the same pcie core. Once I start implementing, I'll have some queries and comments ;-) Cheers Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
On Wed, July 10, 2013, Doug Anderson wrote:
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Use suspend_noirq as per James Hogan.
drivers/mmc/host/dw_mmc-exynos.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c
b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..36b9620 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -30,6 +30,7 @@
#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
SDMMC_CLKSEL_CCLK_DRIVE(y) |\
SDMMC_CLKSEL_CCLK_DIVIDER(z))
+#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
#define SDMMC_CMD_USE_HOLD_REG BIT(29)
@@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
return 0;
}
+/**
+ * dw_mci_exynos_resume_noirq - Exynos-specific resume code
+ *
+ * We have seen cases (at least on the exynos5420) where turning off the INT
+ * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL
+ * register asserted. This bit is 1 to indicate that it fired and we can
+ * clear it by writing a 1 back. Clear it to prevent interrupts from going
off
+ * constantly.
+ */
As I know this bit is auto-cleared.
Did you find the cause of this problem?
How about your GPIO setting in sleep?
Currently, we don't know why the problem is happened.
At least, we should make it clear.
Thanks,
Seungwon Jeon
+
+static int dw_mci_exynos_resume_noirq(struct dw_mci *host)
+{
+ u32 clksel;
+
+ clksel = mci_readl(host, CLKSEL);
+ if (clksel SDMMC_CLKSEL_WAKEUP_INT)
+ mci_writel(host, CLKSEL, clksel);
+
+ return 0;
+}
+
static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
/*
@@ -165,6 +187,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
.caps = exynos_dwmmc_caps,
.init = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
+ .resume_noirq = dw_mci_exynos_resume_noirq,
.prepare_command= dw_mci_exynos_prepare_command,
.set_ios= dw_mci_exynos_set_ios,
.parse_dt = dw_mci_exynos_parse_dt,
--
1.8.3
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Re: [PATCH v2 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
Seungwon, On Wed, Jul 10, 2013 at 7:54 AM, Seungwon Jeon tgih@samsung.com wrote: On Wed, July 10, 2013, Doug Anderson wrote: If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up looping around forever. This has been seen to happen on exynos5420 silicon despite the fact that we haven't enabled any wakeup events. Signed-off-by: Doug Anderson diand...@chromium.org --- Changes in v2: - Use suspend_noirq as per James Hogan. drivers/mmc/host/dw_mmc-exynos.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index f013e7e..36b9620 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -30,6 +30,7 @@ #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ SDMMC_CLKSEL_CCLK_DRIVE(y) |\ SDMMC_CLKSEL_CCLK_DIVIDER(z)) +#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) #define SDMMC_CMD_USE_HOLD_REG BIT(29) @@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) return 0; } +/** + * dw_mci_exynos_resume_noirq - Exynos-specific resume code + * + * We have seen cases (at least on the exynos5420) where turning off the INT + * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL + * register asserted. This bit is 1 to indicate that it fired and we can + * clear it by writing a 1 back. Clear it to prevent interrupts from going off + * constantly. + */ As I know this bit is auto-cleared. Did you find the cause of this problem? How about your GPIO setting in sleep? Currently, we don't know why the problem is happened. At least, we should make it clear. Yes, the documentation that I have says that this bit is auto cleared as well but doesn't indicate under what conditions it is auto cleared. From testing how this bit reacts I have found that writing a 1 to it clears the bit--in other words it behaves like bits in RINTSTS. That's a terrible design for a bit in a register with shared config but appears to be how it works. Note: in a sense it will be auto cleared because doing a read-modify-write of any other bits in this register will clear the interrupt. I have asked for official confirmation. We have found that on exynos5420 bits 8-10 of CLKSEL are marked as RESERVED. Those bits are documented to enable the WAKEUP_INT on exynos5250. My best guess is that these bits are not used on exynos5420 and the WAKEUP_INT line is left floating, which means it can fire randomly. I have also asked for official confirmation about this. I will likely merge this change locally in our kernel tree while waiting for a response. If you would like to wait before Acking that's very reasonable. Do you have any other problems with this change assuming my understanding above is correct? -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/5] mmc: dw_mmc: fixes for suspend/resume on exynos
This series of patches addresses some suspend/resume problems with dw_mmc on exynos platforms. Since suspend/resume is not fully working on ToT Linux (3.10) on exynos5250-snow, this series was tested against the current ToT ChromeOS 3.8 tree. I have confirmed basic booting and eMMC / SD card usage (and compiling, honest!) against ToT Linux. Changes in v3: - Add freeze/thaw and poweroff/restore noirq entries. Changes in v2: - Fix typo (some - come) - Use ~0 instead of 0x; add comment about value - Use suspend_noirq as per James Hogan. Doug Anderson (5): mmc: dw_mmc: Invalidate cache of current_speed after suspend/resume mmc: dw_mmc: Add suspend_noirq/resume_noirq callbacks for dw_mmc-pltfm mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT mmc: dw_mmc: Always setup the bus after suspend/resume mmc: dw_mmc: Set timeout to max upon resume drivers/mmc/host/dw_mmc-exynos.c | 23 ++ drivers/mmc/host/dw_mmc-pltfm.c | 41 +--- drivers/mmc/host/dw_mmc.c| 15 +++ drivers/mmc/host/dw_mmc.h| 4 4 files changed, 76 insertions(+), 7 deletions(-) -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/5] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v3: None
Changes in v2:
- Use suspend_noirq as per James Hogan.
drivers/mmc/host/dw_mmc-exynos.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index f013e7e..36b9620 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -30,6 +30,7 @@
#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
SDMMC_CLKSEL_CCLK_DRIVE(y) |\
SDMMC_CLKSEL_CCLK_DIVIDER(z))
+#define SDMMC_CLKSEL_WAKEUP_INTBIT(11)
#define SDMMC_CMD_USE_HOLD_REG BIT(29)
@@ -102,6 +103,27 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
return 0;
}
+/**
+ * dw_mci_exynos_resume_noirq - Exynos-specific resume code
+ *
+ * We have seen cases (at least on the exynos5420) where turning off the INT
+ * power rail during suspend will leave the WAKEUP_INT bit in the CLKSEL
+ * register asserted. This bit is 1 to indicate that it fired and we can
+ * clear it by writing a 1 back. Clear it to prevent interrupts from going off
+ * constantly.
+ */
+
+static int dw_mci_exynos_resume_noirq(struct dw_mci *host)
+{
+ u32 clksel;
+
+ clksel = mci_readl(host, CLKSEL);
+ if (clksel SDMMC_CLKSEL_WAKEUP_INT)
+ mci_writel(host, CLKSEL, clksel);
+
+ return 0;
+}
+
static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
/*
@@ -165,6 +187,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
.caps = exynos_dwmmc_caps,
.init = dw_mci_exynos_priv_init,
.setup_clock= dw_mci_exynos_setup_clock,
+ .resume_noirq = dw_mci_exynos_resume_noirq,
.prepare_command= dw_mci_exynos_prepare_command,
.set_ios= dw_mci_exynos_set_ios,
.parse_dt = dw_mci_exynos_parse_dt,
--
1.8.3
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Re: [PATCH v2 1/6] clk: samsung: move common plls registration into separate function
Hi Heiko, On Wed, Jul 10, 2013 at 4:27 AM, Heiko Stübner he...@sntech.de wrote: All Samsung PLLs use similar code to register the clocks and clkdev lookups. Therefore move these into a separate function to reduce code duplication. Suggested-by: Russell King li...@arm.linux.org.uk Signed-off-by: Heiko Stuebner he...@sntech.de --- I have posted patch for adding common pll registration function which some how missed to get merged. I hope will get merged after rc1. Please give a look at that : http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19543.html Regards, Yadwinder -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] usb: phy: samsung-usb2: Toggle HSIC GPIO from device tree
Hi Felipe, This is intended to pull down a reset signal line, not to switch power to the device. I could implement that with the regulator framework too, but I think that would just be confusing and harder to understand without providing any benefit. It's really just a plain old GPIO. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] usb: phy: samsung-usb2: Toggle HSIC GPIO from device tree
On Wednesday, July 10, 2013 9:34 AM, Julius Werner wrote:
This patch adds support for a new 'samsung,hsic-reset-gpio' in the
device tree, which will be interpreted as an active-low reset pin during
PHY initialization when it exists. Useful for intergrated HSIC devices
like an SMSC 3503 hub. It is necessary to add this directly to the PHY
initialization to get the timing right, since resetting a HSIC device
after it has already been enumerated can confuse the USB stack.
Also fixes PHY semaphore code to make sure we always go through the
setup at least once, even if it was already turned on (e.g. by
firmware), and changes a spinlock to a mutex to allow sleeping in the
critical section.
CC'ed Thomas Abraham,
This reset signal pin seems 'HUB_RESET' pin to reset SMSC 3503 hub
on Arndale board. This reset pin is described that 'This active low signal
is used by the system to reset the chip' in SMSC 3503 hub datasheet.
One more thing,
'phy-samsung-usb*.c' files are used and designed to control USB PHY controller
in Exynos SoCs; thus, these files should control only internal USB PHY
controller
in Exynos SoCs.
However, the reset pin is used for reset external SMSC 3503 hub chip
that is not placed in Exynos SoC.
Thus, there should not be HUB reset code
in ./drivers/usb/phy/phy-samsung-usb*.c
This topic was already discussed one month ago.
As Olof Johansson mentioned, 'drivers/platform/arm/' would be
a good alternative; thus, USB hub reset code should be moved
to 'drivers/platform/arm/'. Please refer to the discussion.
(http://patches.linaro.org/16856/)
Best regards,
Jingoo Han
Change-Id: Ieecac52c27daa7a17a7ed3b2863ddba3aeb8d16f
Signed-off-by: Julius Werner jwer...@chromium.org
---
.../devicetree/bindings/usb/samsung-usbphy.txt | 10 ++
drivers/usb/phy/phy-samsung-usb.c | 17 ++
drivers/usb/phy/phy-samsung-usb.h | 7 ++--
drivers/usb/phy/phy-samsung-usb2.c | 38
++
drivers/usb/phy/phy-samsung-usb3.c | 12 +++
5 files changed, 55 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 33fd354..82e2e16 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -31,6 +31,12 @@ Optional properties:
- ranges: allows valid translation between child's address space and parent's
address space.
+- samsung,hsic-reset-gpio: an active low GPIO pin that resets a device
+ connected to the HSIC port. Useful for things like
+ an on-board SMSC3503 hub.
+- pinctrl-0: Pin control group containing the HSIC reset GPIO pin.
+- pinctrl-names: Should contain only one value - default.
+
- The child node 'usbphy-sys' to the node 'usbphy' is for the system
controller
interface for usb-phy. It should provide the following information
required by
usb-phy controller to control phy.
@@ -56,6 +62,10 @@ Example:
clocks = clock 2, clock 305;
clock-names = xusbxti, otg;
+ samsung,hsic-reset-gpio = gpx2 4 1;
+ pinctrl-names = default;
+ pinctrl-0 = hsic_reset;
+
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = 0x10020704 0x8;
diff --git a/drivers/usb/phy/phy-samsung-usb.c
b/drivers/usb/phy/phy-samsung-usb.c
index ac025ca..23f1d70 100644
--- a/drivers/usb/phy/phy-samsung-usb.c
+++ b/drivers/usb/phy/phy-samsung-usb.c
@@ -27,6 +27,7 @@
#include linux/io.h
#include linux/of.h
#include linux/of_address.h
+#include linux/of_gpio.h
#include linux/usb/samsung_usb_phy.h
#include phy-samsung-usb.h
@@ -58,6 +59,22 @@ int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
if (sphy-sysreg == NULL)
dev_warn(sphy-dev, Can't get usb-phy sysreg cfg register\n);
+ /*
+ * Some boards have a separate active-low reset GPIO for their HSIC USB
+ * devices. If they don't, this will just stay at an invalid value and
+ * the init code will ignore it.
+ */
+ sphy-hsic_reset_gpio = of_get_named_gpio(sphy-dev-of_node,
+ samsung,hsic-reset-gpio, 0);
+ if (gpio_is_valid(sphy-hsic_reset_gpio)) {
+ if (devm_gpio_request_one(sphy-dev, sphy-hsic_reset_gpio,
+ GPIOF_OUT_INIT_LOW, samsung_hsic_reset)) {
+ dev_err(sphy-dev, can't request hsic reset gpio %d\n,
+ sphy-hsic_reset_gpio);
+ sphy-hsic_reset_gpio = -EINVAL;
+ }
+ }
+
of_node_put(usbphy_sys);
return 0;
diff --git a/drivers/usb/phy/phy-samsung-usb.h
b/drivers/usb/phy/phy-samsung-usb.h
index
Re: [PATCH] usb: phy: samsung-usb2: Toggle HSIC GPIO from device tree
Hi Julius, On Wed, Jul 10, 2013 at 2:42 PM, Julius Werner jwer...@chromium.org wrote: Hi Felipe, This is intended to pull down a reset signal line, not to switch power to the device. I could implement that with the regulator framework too, but I think that would just be confusing and harder to understand without providing any benefit. It's really just a plain old GPIO. It seems that the reset gpio driver from Phillip Zabel would help in this case: http://permalink.gmane.org/gmane.linux.drivers.devicetree/36830 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/5] mmc: dw_mmc: Add exynos resume callback to clear WAKEUP_INT
On Tue, Jul 9, 2013 at 12:09 PM, Doug Anderson diand...@chromium.org wrote: Hi, On Tue, Jul 9, 2013 at 10:31 AM, Doug Anderson diand...@chromium.org wrote: If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up looping around forever. Signed-off-by: Doug Anderson diand...@chromium.org --- drivers/mmc/host/dw_mmc-exynos.c | 23 +++ 1 file changed, 23 insertions(+) Grant just pointed out that the WAKEUP_INT is supposed to only be enabled if bits 8, 9, or 10 are 1. Our driver never sets those so we _should_ never get a WAKEUP_INT. Bits 8-10 are marked as RESERVED on the exynos5420 manual, so the current guess is that they're broken on that silicon but that sometimes the interrupt fires anyway. In any case, it is still a reasonable thing to clear this interrupt at wakeup if it has fired, even if we're on an exynos device without any problems. I agree. Can add: Reviewed-by: Grant Grundler grund...@chromium.org thanks, grant -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Wednesday, July 10, 2013 11:02 PM, Kishon Vijay Abraham I: On Friday 05 July 2013 01:59 PM, Jingoo Han wrote: Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys designware part; other parts are Exynos specific. Also, the Synopsys designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys designware part and Exynos specific part. Thanks for doing that :-) I'll be using the synopsys specific part as Jacinto6 also uses the same pcie core. Once I start implementing, I'll have some queries and comments ;-) Hi Kishon, OK, I see. I will send v2 patch. Also, I will be CC'ing you. :) Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys designware part;
other parts are Exynos specific.
Also, the Synopsys designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
designware part and Exynos specific part.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Pratyush Anand pratyush.an...@st.com
Cc: Mohit KUMAR mohit.ku...@st.com
---
Changes since v1:
- moved the configuration, I/O, memory space handling to dw_pcie_host_init()
- removed exynos_pcie_abort()
- replaced 'purple_base' with 'block_base'
- replaced 'dbi_base' with 'dbi_addr'
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-designware.c | 963 +---
drivers/pci/host/pcie-designware.h | 71 +++
drivers/pci/host/pcie-exynos.c | 523
4 files changed, 822 insertions(+), 736 deletions(-)
create mode 100644 drivers/pci/host/pcie-designware.h
create mode 100644 drivers/pci/host/pcie-exynos.c
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 086d850..7e59864 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 26bdbda..b372ead 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -1,5 +1,5 @@
/*
- * PCIe host controller driver for Samsung EXYNOS SoCs
+ * Synopsys Designware PCIe host controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -11,64 +11,14 @@
* published by the Free Software Foundation.
*/
-#include linux/clk.h
-#include linux/delay.h
-#include linux/gpio.h
-#include linux/interrupt.h
#include linux/kernel.h
-#include linux/list.h
#include linux/module.h
-#include linux/of.h
#include linux/of_address.h
-#include linux/of_gpio.h
-#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
-#include linux/platform_device.h
-#include linux/resource.h
-#include linux/signal.h
-#include linux/slab.h
#include linux/types.h
-struct pcie_port_info {
- u32 cfg0_size;
- u32 cfg1_size;
- u32 io_size;
- u32 mem_size;
- phys_addr_t io_bus_addr;
- phys_addr_t mem_bus_addr;
-};
-
-struct pcie_port {
- struct device *dev;
- u8 controller;
- u8 root_bus_nr;
- void __iomem*dbi_base;
- void __iomem*elbi_base;
- void __iomem*phy_base;
- void __iomem*purple_base;
- u64 cfg0_base;
- void __iomem*va_cfg0_base;
- u64 cfg1_base;
- void __iomem*va_cfg1_base;
- u64 io_base;
- u64 mem_base;
- spinlock_t conf_lock;
- struct resource cfg;
- struct resource io;
- struct resource mem;
- struct pcie_port_info config;
- struct clk *clk;
- struct clk *bus_clk;
- int irq;
- int reset_gpio;
-};
-
-/*
- * Exynos PCIe IP consists of Synopsys specific part and Exynos
- * specific part. Only core block is a Synopsys designware part;
- * other parts are Exynos specific.
- */
+#include pcie-designware.h
/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
@@ -108,69 +58,14 @@ struct pcie_port {
#define PCIE_ATU_FUNC(x) (((x) 0x7) 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
-/* Exynos specific PCIE configuration registers */
-
-/* PCIe ELBI registers */
-#define PCIE_IRQ_PULSE 0x000
-#define IRQ_INTA_ASSERT(0x1 0)
-#define IRQ_INTB_ASSERT(0x1 2)
-#define IRQ_INTC_ASSERT(0x1 4)
-#define IRQ_INTD_ASSERT(0x1 6)
-#define PCIE_IRQ_LEVEL 0x004
-#define PCIE_IRQ_SPECIAL 0x008
-#define PCIE_IRQ_EN_PULSE 0x00c
-#define PCIE_IRQ_EN_LEVEL 0x010
-#define PCIE_IRQ_EN_SPECIAL0x014
-#define PCIE_PWR_RESET 0x018
-#define PCIE_CORE_RESET0x01c
-#define PCIE_CORE_RESET_ENABLE (0x1 0)
-#define PCIE_STICKY_RESET 0x020
-#define PCIE_NONSTICKY_RESET 0x024
-#define PCIE_APP_INIT_RESET0x028
-#define PCIE_APP_LTSSM_ENABLE 0x02c
-#define PCIE_ELBI_RDLH_LINKUP 0x064
-#define PCIE_ELBI_LTSSM_ENABLE 0x1
-#define PCIE_ELBI_SLV_AWMISC 0x11c
