Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
Hi Jingoo,
On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote:
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys designware part;
other parts are Exynos specific.
Also, the Synopsys designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
designware part and Exynos specific part.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Pratyush Anand pratyush.an...@st.com
Cc: Mohit KUMAR mohit.ku...@st.com
---
Changes since v1:
- moved the configuration, I/O, memory space handling to dw_pcie_host_init()
- removed exynos_pcie_abort()
- replaced 'purple_base' with 'block_base'
- replaced 'dbi_base' with 'dbi_addr'
drivers/pci/host/Makefile |1 +
drivers/pci/host/pcie-designware.c | 963
+---
drivers/pci/host/pcie-designware.h | 71 +++
drivers/pci/host/pcie-exynos.c | 523
4 files changed, 822 insertions(+), 736 deletions(-)
create mode 100644 drivers/pci/host/pcie-designware.h
create mode 100644 drivers/pci/host/pcie-exynos.c
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 086d850..7e59864 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 26bdbda..b372ead 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -1,5 +1,5 @@
/*
- * PCIe host controller driver for Samsung EXYNOS SoCs
+ * Synopsys Designware PCIe host controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -11,64 +11,14 @@
* published by the Free Software Foundation.
*/
-#include linux/clk.h
-#include linux/delay.h
-#include linux/gpio.h
-#include linux/interrupt.h
#include linux/kernel.h
-#include linux/list.h
#include linux/module.h
-#include linux/of.h
#include linux/of_address.h
-#include linux/of_gpio.h
-#include linux/of_pci.h
#include linux/pci.h
#include linux/pci_regs.h
-#include linux/platform_device.h
-#include linux/resource.h
-#include linux/signal.h
-#include linux/slab.h
#include linux/types.h
-struct pcie_port_info {
- u32 cfg0_size;
- u32 cfg1_size;
- u32 io_size;
- u32 mem_size;
- phys_addr_t io_bus_addr;
- phys_addr_t mem_bus_addr;
-};
-
-struct pcie_port {
- struct device *dev;
- u8 controller;
- u8 root_bus_nr;
- void __iomem*dbi_base;
- void __iomem*elbi_base;
- void __iomem*phy_base;
- void __iomem*purple_base;
- u64 cfg0_base;
- void __iomem*va_cfg0_base;
- u64 cfg1_base;
- void __iomem*va_cfg1_base;
- u64 io_base;
- u64 mem_base;
- spinlock_t conf_lock;
- struct resource cfg;
- struct resource io;
- struct resource mem;
- struct pcie_port_info config;
- struct clk *clk;
- struct clk *bus_clk;
- int irq;
- int reset_gpio;
-};
-
-/*
- * Exynos PCIe IP consists of Synopsys specific part and Exynos
- * specific part. Only core block is a Synopsys designware part;
- * other parts are Exynos specific.
- */
+#include pcie-designware.h
/* Synopsis specific PCIE configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
@@ -108,69 +58,14 @@ struct pcie_port {
#define PCIE_ATU_FUNC(x) (((x) 0x7) 16)
#define PCIE_ATU_UPPER_TARGET0x91C
-/* Exynos specific PCIE configuration registers */
-
-/* PCIe ELBI registers */
-#define PCIE_IRQ_PULSE 0x000
-#define IRQ_INTA_ASSERT (0x1 0)
-#define IRQ_INTB_ASSERT (0x1 2)
-#define IRQ_INTC_ASSERT (0x1 4)
-#define IRQ_INTD_ASSERT (0x1 6)
-#define PCIE_IRQ_LEVEL 0x004
-#define PCIE_IRQ_SPECIAL 0x008
-#define PCIE_IRQ_EN_PULSE0x00c
-#define PCIE_IRQ_EN_LEVEL0x010
-#define PCIE_IRQ_EN_SPECIAL 0x014
-#define PCIE_PWR_RESET 0x018
-#define PCIE_CORE_RESET 0x01c
-#define PCIE_CORE_RESET_ENABLE (0x1 0)
-#define PCIE_STICKY_RESET0x020
-#define PCIE_NONSTICKY_RESET 0x024
-#define PCIE_APP_INIT_RESET 0x028
-#define
[PATCH] ASoC: Samsung: Set RFS and BFS in slave mode
As per the User Manual, the RFS and BFS should be set in slave mode
for correct operation.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit-int.chromium.org/37841
Reviewed-by: Simon Glass s...@google.com
---
sound/soc/samsung/i2s.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 82ebb1a..3fcf8d7 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -742,13 +742,13 @@ static int config_setup(struct i2s_dai *i2s)
return -EAGAIN;
}
- /* Don't bother RFS, BFS PSR in Slave mode */
- if (is_slave(i2s))
- return 0;
-
set_bfs(i2s, bfs);
set_rfs(i2s, rfs);
+ /* Don't bother with PSR in Slave mode */
+ if (is_slave(i2s))
+ return 0;
+
if (!(i2s-quirks QUIRK_NO_MUXPSR)) {
psr = i2s-rclk_srcrate / i2s-frmclk / rfs;
writel(((psr - 1) 8) | PSR_PSREN, i2s-addr + I2SPSR);
--
1.7.4.4
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[PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
[abrestic: style cleanup and documentation]
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit-int.chromium.org/37840
Reviewed-by: Simon Glass s...@google.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |2 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 51 ++---
sound/soc/samsung/i2s.c| 117
4 files changed, 132 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..b8593d5 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -28,6 +28,8 @@ Optional SoC Specific Properties:
enabled or disabled based on need.
- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
then this flag is enabled.
+- samsung,supports-tdm: If the I2S controller supports TDM, then this flag
+ must be enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index c0e6d9a..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -95,24 +99,39 @@
#define MOD_RXONLY (1 8)
#define MOD_TXRX (2 8)
#define MOD_MASK (3 8)
-#define MOD_LR_LLOW(0 7)
-#define MOD_LR_RLOW(1 7)
-#define MOD_SDF_IIS(0 5)
-#define MOD_SDF_MSB(1 5)
-#define MOD_SDF_LSB(2 5)
-#define MOD_SDF_MASK (3 5)
-#define MOD_RCLK_256FS (0 3)
-#define MOD_RCLK_512FS (1 3)
-#define MOD_RCLK_384FS (2 3)
-#define MOD_RCLK_768FS (3 3)
-#define MOD_RCLK_MASK (3 3)
-#define MOD_BCLK_32FS (0 1)
-#define MOD_BCLK_48FS (1 1)
-#define MOD_BCLK_16FS (2 1)
-#define MOD_BCLK_24FS (3 1)
-#define MOD_BCLK_MASK (3 1)
+#define MOD_LRP_SHIFT 7
+#define MOD_LR_LLOW0
+#define MOD_LR_RLOW1
+#define MOD_SDF_SHIFT 5
+#define MOD_SDF_IIS0
+#define MOD_SDF_MSB1
+#define MOD_SDF_LSB2
+#define MOD_SDF_MASK 3
+#define MOD_RCLK_SHIFT 3
+#define MOD_RCLK_256FS 0
+#define MOD_RCLK_512FS 1
+#define MOD_RCLK_384FS 2
+#define MOD_RCLK_768FS 3
+#define MOD_RCLK_MASK 3
+#define MOD_BCLK_SHIFT 1
+#define MOD_BCLK_32FS 0
+#define MOD_BCLK_48FS 1
+#define MOD_BCLK_16FS 2
+#define MOD_BCLK_24FS 3
+#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 3fcf8d7..398f8db 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -198,7 +198,13 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) 3) 0x3;
+ u32 rfs;
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Thursday, July 11, 2013 3:40 PM, Kishon Vijay Abraham I wrote: On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-designware.c | 963 +--- drivers/pci/host/pcie-designware.h | 71 +++ drivers/pci/host/pcie-exynos.c | 523 4 files changed, 822 insertions(+), 736 deletions(-) create mode 100644 drivers/pci/host/pcie-designware.h create mode 100644 drivers/pci/host/pcie-exynos.c diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 086d850..7e59864 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c [...] How about making this a separate driver in itself that does all the configurations for designware core? By this I mean we can have a separate dt node (child node of soc specific wrapper), that will have all the configuration space/IO space and memory space. pci_common_init/dw_pcie_host_init should be done in this driver. We just need to think about a way of passing the ops (since that looks like very much needed because of the sideband bits you have to enable before reading/writing). CC'ed Seungwon Jeon(DW-MMC Maintainer), Yulgon Kim (DW-USB Developer) Um, maybe you mean dwc3 usb driver (./drivers/usb/dwc3/)'? But, I referenced dw mmc driver (./drivers/mmc/host/dw_mmc*.c). Now, Exynos PCIe driver, Spear PCIe driver[1], and i.MX PCIe driver[2] are submitted to PCIe mailing-list, these are using designware PCIe core. There are many differences between Exynos PCIe and Spear PCIe. Also, for Exynos PCIe, platform specific part will be changed more. Thus, the dw mmc driver model looked more suitable. [1] http://permalink.gmane.org/gmane.linux.kernel.pci/18400 [2] http://www.spinics.net/lists/linux-pci/msg23489.html Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/6] clk: samsung: move common plls registration into separate function
Hi, On Wednesday 10 of July 2013 22:29:13 Yadwinder Singh Brar wrote: Hi Heiko, On Wed, Jul 10, 2013 at 4:27 AM, Heiko Stübner he...@sntech.de wrote: All Samsung PLLs use similar code to register the clocks and clkdev lookups. Therefore move these into a separate function to reduce code duplication. Suggested-by: Russell King li...@arm.linux.org.uk Signed-off-by: Heiko Stuebner he...@sntech.de --- I have posted patch for adding common pll registration function which some how missed to get merged. I hope will get merged after rc1. Please give a look at that : http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19543.html Yeah, I was going to post a link to it, but I couldn't find it on any mailing list archive. I think we should go with the way of registration introduced by Yadwinder. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/6] clk: samsung: fix error handling in pll register functions
Hi Heiko,
On Wednesday 10 of July 2013 00:58:13 Heiko Stübner wrote:
kmalloc has its own error reporting when the allocation fails and
the register functions also should return the correct ERR_PTR(-ENOMEM)
when it happens.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clk/samsung/clk-pll.c | 30 ++
1 file changed, 10 insertions(+), 20 deletions(-)
This patch looks pretty good, but I'm not sure if this problem still exists
after applying Yadwinder's patches that completely changes the way of PLL
registration.
Best regards,
Tomasz
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 9153e46..0afaec6 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -79,10 +79,8 @@ struct clk * __init samsung_clk_register_pll35xx(const
char *name, struct clk_init_data init;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = samsung_pll35xx_clk_ops;
@@ -153,10 +151,8 @@ struct clk * __init samsung_clk_register_pll36xx(const
char *name, struct clk_init_data init;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = samsung_pll36xx_clk_ops;
@@ -227,10 +223,8 @@ struct clk * __init samsung_clk_register_pll45xx(const
char *name, struct clk_init_data init;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = samsung_pll45xx_clk_ops;
@@ -308,10 +302,8 @@ struct clk * __init samsung_clk_register_pll46xx(const
char *name, struct clk_init_data init;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = samsung_pll46xx_clk_ops;
@@ -385,10 +377,8 @@ struct clk * __init samsung_clk_register_pll2550x(const
char *name, struct clk_init_data init;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err(%s: could not allocate pll clk %s\n, __func__, name);
- return NULL;
- }
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = samsung_pll2550x_clk_ops;
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Re: [PATCH v2 3/6] clk: samsung: add plls used in s3c2416 and s3c2443
Hi Heiko,
On Wednesday 10 of July 2013 00:59:08 Heiko Stübner wrote:
This adds support for pll2126x, pll3000x, pll6552x and pll6553x.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clk/samsung/clk-pll.c | 280
+ drivers/clk/samsung/clk-pll.h |
8 ++
2 files changed, 288 insertions(+)
Generally the patch looks good, but I have some comments to the part related
to 655xx PLLs.
I had a patch adding support for them too, but we can go with yours, since the
way of registration has been changed by Yadwinder's patches and mine would
have to be updated anyway.
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0afaec6..35c15a1 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -323,6 +323,73 @@ struct clk * __init samsung_clk_register_pll46xx(const
char *name, }
/*
+ * PLL2126x Clock Type
+ */
+
+#define PLL2126X_MDIV_MASK (0xFF)
+#define PLL2126X_PDIV_MASK (0x3)
+#define PLL2126X_SDIV_MASK (0x3)
+#define PLL2126X_MDIV_SHIFT (16)
+#define PLL2126X_PDIV_SHIFT (8)
+#define PLL2126X_SDIV_SHIFT (0)
+
+struct samsung_clk_pll2126x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll2126x(_hw) container_of(_hw, struct samsung_clk_pll2126x,
hw) +
+static unsigned long samsung_pll2126x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll2126x *pll = to_clk_pll2126x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL2126X_MDIV_SHIFT) PLL2126X_MDIV_MASK;
+ pdiv = (pll_con PLL2126X_PDIV_SHIFT) PLL2126X_PDIV_MASK;
+ sdiv = (pll_con PLL2126X_SDIV_SHIFT) PLL2126X_SDIV_MASK;
+
+ fvco *= (mdiv + 8);
+ do_div(fvco, (pdiv + 2) sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126x_clk_ops = {
+ .recalc_rate = samsung_pll2126x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2126x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll2126x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll2126x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg = con_reg;
+
+ clk = samsung_register_pll(pll-hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+/*
* PLL2550x Clock Type
*/
@@ -396,3 +463,216 @@ struct clk * __init
samsung_clk_register_pll2550x(const char *name,
return clk;
}
+
+/*
+ * PLL3000x Clock Type
+ */
+
+#define PLL3000X_MDIV_MASK (0xFF)
+#define PLL3000X_PDIV_MASK (0x3)
+#define PLL3000X_SDIV_MASK (0x3)
+#define PLL3000X_MDIV_SHIFT (16)
+#define PLL3000X_PDIV_SHIFT (8)
+#define PLL3000X_SDIV_SHIFT (0)
+
+struct samsung_clk_pll3000x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll3000x(_hw) container_of(_hw, struct samsung_clk_pll3000x,
hw) +
+static unsigned long samsung_pll3000x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll3000x *pll = to_clk_pll3000x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL3000X_MDIV_SHIFT) PLL3000X_MDIV_MASK;
+ pdiv = (pll_con PLL3000X_PDIV_SHIFT) PLL3000X_PDIV_MASK;
+ sdiv = (pll_con PLL3000X_SDIV_SHIFT) PLL3000X_SDIV_MASK;
+
+ fvco *= (2 * (mdiv + 8));
+ do_div(fvco, pdiv sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000x_clk_ops = {
+ .recalc_rate = samsung_pll3000x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll3000x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll3000x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll3000x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg = con_reg;
+
+ clk = samsung_register_pll(pll-hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+/*
+ * PLL6552x Clock Type
+ */
+
+#define PLL6552X_MDIV_MASK (0x3FF)
+#define
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
Hi, On Thursday 11 July 2013 12:35 PM, Jingoo Han wrote: On Thursday, July 11, 2013 3:40 PM, Kishon Vijay Abraham I wrote: On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-designware.c | 963 +--- drivers/pci/host/pcie-designware.h | 71 +++ drivers/pci/host/pcie-exynos.c | 523 4 files changed, 822 insertions(+), 736 deletions(-) create mode 100644 drivers/pci/host/pcie-designware.h create mode 100644 drivers/pci/host/pcie-exynos.c diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 086d850..7e59864 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c [...] How about making this a separate driver in itself that does all the configurations for designware core? By this I mean we can have a separate dt node (child node of soc specific wrapper), that will have all the configuration space/IO space and memory space. pci_common_init/dw_pcie_host_init should be done in this driver. We just need to think about a way of passing the ops (since that looks like very much needed because of the sideband bits you have to enable before reading/writing). CC'ed Seungwon Jeon(DW-MMC Maintainer), Yulgon Kim (DW-USB Developer) Um, maybe you mean dwc3 usb driver (./drivers/usb/dwc3/)'? But, I referenced dw mmc driver (./drivers/mmc/host/dw_mmc*.c). Now, Exynos PCIe driver, Spear PCIe driver[1], and i.MX PCIe driver[2] are submitted to PCIe mailing-list, these are using designware PCIe core. There are many differences between Exynos PCIe and Spear PCIe. Also, for Exynos PCIe, platform specific part will be changed more. Thus, the dw mmc driver model looked more suitable. Alright. I'll go ahead with a similar implementation then. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/6] clk: samsung: add plls used in s3c2416 and s3c2443
Am Donnerstag, 11. Juli 2013, 10:16:41 schrieb Tomasz Figa:
Hi Heiko,
On Wednesday 10 of July 2013 00:59:08 Heiko Stübner wrote:
This adds support for pll2126x, pll3000x, pll6552x and pll6553x.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clk/samsung/clk-pll.c | 280
+ drivers/clk/samsung/clk-pll.h |
8 ++
2 files changed, 288 insertions(+)
Generally the patch looks good, but I have some comments to the part
related to 655xx PLLs.
I had a patch adding support for them too, but we can go with yours, since
the way of registration has been changed by Yadwinder's patches and mine
would have to be updated anyway.
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 0afaec6..35c15a1 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -323,6 +323,73 @@ struct clk * __init
samsung_clk_register_pll46xx(const char *name, }
/*
+ * PLL2126x Clock Type
+ */
+
+#define PLL2126X_MDIV_MASK (0xFF)
+#define PLL2126X_PDIV_MASK (0x3)
+#define PLL2126X_SDIV_MASK (0x3)
+#define PLL2126X_MDIV_SHIFT(16)
+#define PLL2126X_PDIV_SHIFT(8)
+#define PLL2126X_SDIV_SHIFT(0)
+#define PLL2126X_PDIV_MASK (0x3F)
is the correct value.
+
+struct samsung_clk_pll2126x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll2126x(_hw) container_of(_hw, struct
samsung_clk_pll2126x, hw) +
+static unsigned long samsung_pll2126x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll2126x *pll = to_clk_pll2126x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL2126X_MDIV_SHIFT) PLL2126X_MDIV_MASK;
+ pdiv = (pll_con PLL2126X_PDIV_SHIFT) PLL2126X_PDIV_MASK;
+ sdiv = (pll_con PLL2126X_SDIV_SHIFT) PLL2126X_SDIV_MASK;
+
+ fvco *= (mdiv + 8);
+ do_div(fvco, (pdiv + 2) sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126x_clk_ops = {
+ .recalc_rate = samsung_pll2126x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2126x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll2126x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll2126x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg = con_reg;
+
+ clk = samsung_register_pll(pll-hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+/*
* PLL2550x Clock Type
*/
@@ -396,3 +463,216 @@ struct clk * __init
samsung_clk_register_pll2550x(const char *name,
return clk;
}
+
+/*
+ * PLL3000x Clock Type
+ */
+
+#define PLL3000X_MDIV_MASK (0xFF)
+#define PLL3000X_PDIV_MASK (0x3)
+#define PLL3000X_SDIV_MASK (0x3)
+#define PLL3000X_MDIV_SHIFT(16)
+#define PLL3000X_PDIV_SHIFT(8)
+#define PLL3000X_SDIV_SHIFT(0)
these are correct.
+
+struct samsung_clk_pll3000x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll3000x(_hw) container_of(_hw, struct
samsung_clk_pll3000x, hw) +
+static unsigned long samsung_pll3000x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll3000x *pll = to_clk_pll3000x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL3000X_MDIV_SHIFT) PLL3000X_MDIV_MASK;
+ pdiv = (pll_con PLL3000X_PDIV_SHIFT) PLL3000X_PDIV_MASK;
+ sdiv = (pll_con PLL3000X_SDIV_SHIFT) PLL3000X_SDIV_MASK;
+
+ fvco *= (2 * (mdiv + 8));
+ do_div(fvco, pdiv sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000x_clk_ops = {
+ .recalc_rate = samsung_pll3000x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll3000x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll3000x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll3000x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg =
Re: [PATCH v2 1/6] clk: samsung: move common plls registration into separate function
Am Donnerstag, 11. Juli 2013, 09:46:53 schrieb Tomasz Figa: Hi, On Wednesday 10 of July 2013 22:29:13 Yadwinder Singh Brar wrote: Hi Heiko, On Wed, Jul 10, 2013 at 4:27 AM, Heiko Stübner he...@sntech.de wrote: All Samsung PLLs use similar code to register the clocks and clkdev lookups. Therefore move these into a separate function to reduce code duplication. Suggested-by: Russell King li...@arm.linux.org.uk Signed-off-by: Heiko Stuebner he...@sntech.de --- I have posted patch for adding common pll registration function which some how missed to get merged. I hope will get merged after rc1. Please give a look at that : http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19543.ht ml Yeah, I was going to post a link to it, but I couldn't find it on any mailing list archive. I think we should go with the way of registration introduced by Yadwinder. the linked patch looks nice, thanks for the link. So I'll redo the plls against it in the next round. Heiko -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
Hi, On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys designware part; other parts are Exynos specific. Also, the Synopsys designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys designware part and Exynos specific part. Signed-off-by: Jingoo Han jg1@samsung.com Cc: Pratyush Anand pratyush.an...@st.com Cc: Mohit KUMAR mohit.ku...@st.com --- . . snip . . + +/* Exynos PCIe driver does not allow module unload */ Just curious, why is this restriction? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] clk: exynos5250: Staticize local symbols
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 3da0bdf..e6a4be1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -193,24 +193,24 @@ PNAME(mout_spdif_p) = { sclk_audio0,
sclk_audio1, sclk_audio2,
spdif_extclk };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[]
__initdata = {
FRATE(fin_pll, fin_pll, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata
= {
FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_hdmi27m, NULL, CLK_IS_ROOT, 2700),
FRATE(none, sclk_dptxphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_uhostphy, NULL, CLK_IS_ROOT, 4800),
};
-struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[]
__initdata = {
FFACTOR(none, fout_mplldiv2, fout_mpll, 1, 2, 0),
FFACTOR(none, fout_bplldiv2, fout_bpll, 1, 2, 0),
};
-struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX_A(none, mout_apll, mout_apll_p, SRC_CPU, 0, 1, mout_apll),
MUX_A(none, mout_cpu, mout_cpu_p, SRC_CPU, 16, 1, mout_cpu),
MUX(none, mout_mpll_fout, mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
@@ -256,7 +256,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata =
{
MUX(none, mout_spi2, mout_group1_p, SRC_PERIC1, 24, 4),
};
-struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, div_arm, mout_cpu, DIV_CPU0, 0, 3),
DIV(none, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV(none, aclk66_pre, sclk_mpll_user, DIV_TOP1, 24, 3),
@@ -316,7 +316,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata =
{
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
};
-struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(gscl0, gscl0, none, GATE_IP_GSCL, 0, 0, 0),
GATE(gscl1, gscl1, none, GATE_IP_GSCL, 1, 0, 0),
GATE(gscl2, gscl2, aclk266, GATE_IP_GSCL, 2, 0, 0),
@@ -474,7 +474,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynox5250 clocks */
-void __init exynos5250_clk_init(struct device_node *np)
+static void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
--
1.7.9.5
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[PATCH 1/1] ARM: EXYNOS: Cleanup common.h file
Remove unused declarations that got left behind subsequent to
making Exynos a DT-only platform.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/mach-exynos/common.h | 41 -
1 file changed, 41 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index c4abde2..7318e62 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -17,7 +17,6 @@
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
void exynos_init_time(void);
-extern unsigned long xxti_f, xusbxti_f;
struct map_desc;
void exynos_init_io(void);
@@ -25,54 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char
*cmd);
void exynos5_restart(enum reboot_mode mode, const char *cmd);
void exynos_init_late(void);
-/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
-void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem
*reg_base, unsigned long xom);
-void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
-
void exynos_firmware_init(void);
-void exynos_set_timer_source(u8 channels);
-
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
static inline int exynos_pm_late_initcall(void) { return 0; }
#endif
-#ifdef CONFIG_ARCH_EXYNOS4
-void exynos4_register_clocks(void);
-void exynos4_setup_clocks(void);
-
-#else
-#define exynos4_register_clocks()
-#define exynos4_setup_clocks()
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-void exynos5_register_clocks(void);
-void exynos5_setup_clocks(void);
-
-#else
-#define exynos5_register_clocks()
-#define exynos5_setup_clocks()
-#endif
-
-#ifdef CONFIG_CPU_EXYNOS4210
-void exynos4210_register_clocks(void);
-
-#else
-#define exynos4210_register_clocks()
-#endif
-
-#ifdef CONFIG_SOC_EXYNOS4212
-void exynos4212_register_clocks(void);
-
-#else
-#define exynos4212_register_clocks()
-#endif
-
-struct device_node;
-
extern struct smp_operations exynos_smp_ops;
extern void exynos_cpu_die(unsigned int cpu);
--
1.7.9.5
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[PATCH 0/6] clk: exynos: Some fixes and cleanup
Resending some of patches (1, 3 and 5) as per discussion in thread [1]. Other patches in the series are new. [1] http://comments.gmane.org/gmane.linux.kernel.samsung-soc/19933 Sachin Kamat (6): clk: exynos4: Staticize local symbols clk: exynos4: Remove unused function clk: exynos5250: Staticize local symbols clk: exynos5420: Staticize local symbols clk: exynos5440: Staticize local symbols clk: exynos-audss: Staticize exynos_audss_clk_init drivers/clk/samsung/clk-exynos-audss.c |2 +- drivers/clk/samsung/clk-exynos4.c | 42 drivers/clk/samsung/clk-exynos5250.c | 14 +-- drivers/clk/samsung/clk-exynos5420.c | 14 +-- drivers/clk/samsung/clk-exynos5440.c | 14 +-- 5 files changed, 37 insertions(+), 49 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/6] clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
Hi Heiko,
Looks mostly good, but please see my comments inline.
On Wednesday 10 of July 2013 01:00:00 Heiko Stübner wrote:
The three SoCs share a common clock tree which only differs in the
existence of some special clocks.
As with all parts common to these three SoCs the driver is named
after the s3c2443, as it was the first SoC introducing this structure
and there exists no other label to describe this s3c24xx epoch.
The clock structure is built according to the manuals of the included
SoCs and might include changes in comparison to the previous clock
structure. As an example the sclk_uart gate was never handled previously
and the div_uart was made to be the clock used by the serial driver.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
.../bindings/clock/samsung,s3c2443-clock.txt | 48 +++
drivers/clk/Kconfig|1 +
drivers/clk/samsung/Kconfig|2 +
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-s3c2443.c | 422
include/dt-bindings/clock/samsung,s3c2443-clock.h |
96 +
6 files changed, 570 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt create
mode 100644 drivers/clk/samsung/Kconfig
create mode 100644 drivers/clk/samsung/clk-s3c2443.c
create mode 100644 include/dt-bindings/clock/samsung,s3c2443-clock.h
diff --git
a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt new
file mode 100644
index 000..a61d8d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
@@ -0,0 +1,48 @@
+* Samsung S3C2443 Clock Controller
+
+The S3C2443 clock controller generates and supplies clock to various
controllers +within the SoC. The clock binding described here is applicable
to all SoCs in +the s3c24x family starting with the s3c2443.
+
+Required Properties:
+
+- comptible: should be one of the following.
nit: compatible
+ - samsung,s3c2416-clock - controller compatible with S3C2416 SoC.
+ - samsung,s3c2443-clock - controller compatible with S3C2443 SoC.
+ - samsung,s3c2450-clock - controller compatible with S3C2450 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this
identifier +to specify the clock which they consume. Some of the clocks are
available only +on a particular SoC.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c2443-clock.h header and can be used in device
+tree sources.
+
+Example: Clock controller node:
+
+ clocks: clock-controller@4c00 {
+ compatible = samsung,s3c2416-clock;
+ reg = 0x4c00 0x40;
+ #clock-cells = 1;
+ };
+
+Example: UART controller node that consumes the clock generated by the
clock + controller (refer to the standard clock bindings for information
about + clocks and clock-names properties):
+
+ serial@50004000 {
+ compatible = samsung,s3c2440-uart;
+ reg = 0x50004000 0x4000;
+ interrupts = 1 23 3 4, 1 23 4 4;
+ clock-names = uart, clk_uart_baud2,
+ clk_uart_baud3;
+ clocks = clocks PCLK_UART0, clocks PCLK_UART0,
+ clocks SCLK_UART;
+ status = disabled;
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 0357ac4..b2fdd68 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -84,3 +84,4 @@ config COMMON_CLK_AXI_CLKGEN
endmenu
source drivers/clk/mvebu/Kconfig
+source drivers/clk/samsung/Kconfig
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
new file mode 100644
index 000..0cfbb29
--- /dev/null
+++ b/drivers/clk/samsung/Kconfig
@@ -0,0 +1,2 @@
+config COMMON_CLK_S3C2443
+ bool
Do you need to introduce a new Kconfig file for this? I guess it's just a
matter
of preference, but since it's here just temporarily, I would just put this
Kconfig entry into the top level clk Kconfig file or even in arch/arm/mach-
s3c24xx/Kconfig.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 5d4d432..1c7932c 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS)+= clk-exynos-audss.o
+obj-$(CONFIG_COMMON_CLK_S3C2443)+= clk-s3c2443.o
diff --git a/drivers/clk/samsung/clk-s3c2443.c
b/drivers/clk/samsung/clk-s3c2443.c new file mode 100644
index 000..7d57b08
--- /dev/null
+++
[PATCH 6/6] clk: exynos-audss: Staticize exynos_audss_clk_init
exynos_audss_clk_init() is used only in this file. Make it
static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos-audss.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 9b1bbd5..51b48da 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -62,7 +62,7 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
-void __init exynos_audss_clk_init(struct device_node *np)
+static void __init exynos_audss_clk_init(struct device_node *np)
{
reg_base = of_iomap(np, 0);
if (!reg_base) {
--
1.7.9.5
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[PATCH 4/6] clk: exynos5420: Staticize local symbols
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5420.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 68a96cb..125728a 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -262,12 +262,12 @@ PNAME(maudio0_p) = { fin_pll, maudio_clk,
sclk_dpll, sclk_mpll,
sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]
__initdata = {
FRATE(fin_pll, fin_pll, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata
= {
FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_pwi, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_usbh20, NULL, CLK_IS_ROOT, 4800),
@@ -275,11 +275,11 @@ struct samsung_fixed_rate_clock
exynos5420_fixed_rate_clks[] __initdata = {
FRATE(none, sclk_usbh20_scan_clk, NULL, CLK_IS_ROOT, 48000),
};
-struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
+static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[]
__initdata = {
FFACTOR(none, sclk_hsic_12m, fin_pll, 1, 2, 0),
};
-struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
MUX(none, mout_mspll_kfc, mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(none, mout_mspll_cpu, mspll_cpu_p, SRC_TOP7, 12, 2),
MUX(none, mout_apll, apll_p, SRC_CPU, 0, 1),
@@ -399,7 +399,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata =
{
MUX(none, mout_spi2, group2_p, SRC_PERIC1, 28, 3),
};
-struct samsung_div_clock exynos5420_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
DIV(none, div_arm, mout_cpu, DIV_CPU0, 0, 3),
DIV(none, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV(none, armclk2, div_arm, DIV_CPU0, 28, 3),
@@ -479,7 +479,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata =
{
DIV(none, dout_pre_spi2, dout_spi2, DIV_PERIC4, 24, 8),
};
-struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
/* TODO: Re-verify the CG bits for all the gate clocks */
GATE_A(mct, pclk_st, aclk66_psgen, GATE_BUS_PERIS1, 2, 0, 0, mct),
@@ -704,7 +704,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynos5420 clocks */
-void __init exynos5420_clk_init(struct device_node *np)
+static void __init exynos5420_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
--
1.7.9.5
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[PATCH 5/6] clk: exynos5440: Staticize local symbols
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5440.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index 7d54341..6d043a2 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -41,12 +41,12 @@ PNAME(mout_armclk_p)= { cplla, cpllb };
PNAME(mout_spi_p) = { div125, div200 };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[]
__initdata = {
FRATE(none, xtal, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks */
-struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata
= {
FRATE(none, ppll, NULL, CLK_IS_ROOT, 10),
FRATE(none, usb_phy0, NULL, CLK_IS_ROOT, 6000),
FRATE(none, usb_phy1, NULL, CLK_IS_ROOT, 6000),
@@ -55,26 +55,26 @@ struct samsung_fixed_rate_clock
exynos5440_fixed_rate_clks[] __initdata = {
};
/* fixed factor clocks */
-struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[]
__initdata = {
FFACTOR(none, div250, ppll, 1, 4, 0),
FFACTOR(none, div200, ppll, 1, 5, 0),
FFACTOR(none, div125, div250, 1, 2, 0),
};
/* mux clocks */
-struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
MUX(none, mout_spi, mout_spi_p, MISC_DOUT1, 5, 1),
MUX_A(arm_clk, arm_clk, mout_armclk_p,
CPU_CLK_STATUS, 0, 1, armclk),
};
/* divider clocks */
-struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
DIV(spi_baud, div_spi, mout_spi, MISC_DOUT1, 3, 2),
};
/* gate clocks */
-struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
GATE(pb0_250, pb0_250, div250, CLKEN_OV_VAL, 3, 0, 0),
GATE(pr0_250, pr0_250, div250, CLKEN_OV_VAL, 4, 0, 0),
GATE(pr1_250, pr1_250, div250, CLKEN_OV_VAL, 5, 0, 0),
@@ -103,7 +103,7 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynos5440 clocks */
-void __init exynos5440_clk_init(struct device_node *np)
+static void __init exynos5440_clk_init(struct device_node *np)
{
void __iomem *reg_base;
--
1.7.9.5
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[PATCH 1/6] clk: exynos4: Staticize local symbols
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos4.c | 30 --
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 1bdb882..18eadc4 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -338,24 +338,24 @@ PNAME(mout_user_aclk200_p4x12) = {fin_pll,
div_aclk200, };
PNAME(mout_user_aclk266_gps_p4x12) = {fin_pll, div_aclk266_gps, };
/* fixed rate clocks generated outside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[]
__initdata = {
FRATE(xxti, xxti, NULL, CLK_IS_ROOT, 0),
FRATE(xusbxti, xusbxti, NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
-struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
FRATE(none, sclk_hdmi24m, NULL, CLK_IS_ROOT, 2400),
FRATE(none, sclk_hdmiphy, NULL, CLK_IS_ROOT, 2700),
FRATE(none, sclk_usbphy0, NULL, CLK_IS_ROOT, 4800),
};
-struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata
= {
FRATE(none, sclk_usbphy1, NULL, CLK_IS_ROOT, 4800),
};
/* list of mux clocks supported in all exynos4 soc's */
-struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
MUX_FA(mout_apll, mout_apll, mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0, mout_apll),
MUX(none, mout_hdmi, mout_hdmi_p, SRC_TV, 0, 1),
@@ -372,7 +372,7 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
};
/* list of mux clocks supported in exynos4210 soc */
-struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, mout_aclk200, sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(none, mout_aclk100, sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(none, mout_aclk160, sclk_ampll_p4210, SRC_TOP0, 20, 1),
@@ -423,7 +423,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata =
{
};
/* list of mux clocks supported in exynos4x12 soc */
-struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
MUX_A(mout_mpll_user_c, mout_mpll_user_c, mout_mpll_user_p4x12,
SRC_CPU, 24, 1, mout_mpll),
MUX(none, mout_aclk266_gps, aclk_p4412, SRC_TOP1, 4, 1),
@@ -491,7 +491,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata =
{
};
/* list of divider clocks supported in all exynos4 soc's */
-struct samsung_div_clock exynos4_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, div_core, mout_core, DIV_CPU0, 0, 3),
DIV(none, div_core2, div_core, DIV_CPU0, 28, 3),
DIV(none, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -554,7 +554,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
};
/* list of divider clocks supported in exynos4210 soc */
-struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
DIV(aclk200, aclk200, mout_aclk200, DIV_TOP, 0, 3),
DIV(sclk_fimg2d, sclk_fimg2d, mout_g2d, DIV_IMAGE, 0, 4),
DIV(none, div_fimd1, mout_fimd1, E4210_DIV_LCD1, 0, 4),
@@ -565,7 +565,7 @@ struct samsung_div_clock exynos4210_div_clks[] __initdata =
{
};
/* list of divider clocks supported in exynos4x12 soc */
-struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
DIV(none, div_mdnie0, mout_mdnie0, DIV_LCD0, 4, 4),
DIV(none, div_mdnie_pwm0, mout_mdnie_pwm0, DIV_LCD0, 8, 4),
DIV(none, div_mdnie_pwm_pre0, div_mdnie_pwm0, DIV_LCD0, 12, 4),
@@ -590,7 +590,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata =
{
};
/* list of gate clocks supported in all exynos4 soc's */
-struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
/*
* After all Exynos4 based platforms are migrated to use device tree,
* the device name and clock alias names specified below for some
@@ -782,7 +782,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
};
/* list of gate clocks supported in exynos4210 soc */
-struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
GATE(tvenc, tvenc, aclk160,
[PATCH 2/6] clk: exynos4: Remove unused function
Subsequent to the cleanup in commit 3c70348c7c (ARM: EXYNOS:
Remove legacy timer initialization code), this function has no more
users. Hence remove it.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos4.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 18eadc4..75635eb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -969,20 +969,6 @@ static void __init exynos4_clk_register_finpll(unsigned
long xom)
}
-/*
- * This function allows non-dt platforms to specify the clock speed of the
- * xxti and xusbxti clocks. These clocks are then registered with the specified
- * clock speed.
- */
-void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
- unsigned long xusbxti_f)
-{
- exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
- exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
- samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
- ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
-}
-
static __initdata struct of_device_id ext_clk_match[] = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ .compatible = samsung,clock-xusbxti, .data = (void *)1, },
--
1.7.9.5
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Re: [PATCH v2 3/6] clk: samsung: add plls used in s3c2416 and s3c2443
On Thursday 11 of July 2013 10:50:39 Heiko Stübner wrote:
Am Donnerstag, 11. Juli 2013, 10:16:41 schrieb Tomasz Figa:
Hi Heiko,
On Wednesday 10 of July 2013 00:59:08 Heiko Stübner wrote:
This adds support for pll2126x, pll3000x, pll6552x and pll6553x.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clk/samsung/clk-pll.c | 280
+ drivers/clk/samsung/clk-pll.h
|
8 ++
2 files changed, 288 insertions(+)
Generally the patch looks good, but I have some comments to the part
related to 655xx PLLs.
I had a patch adding support for them too, but we can go with yours, since
the way of registration has been changed by Yadwinder's patches and mine
would have to be updated anyway.
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 0afaec6..35c15a1 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -323,6 +323,73 @@ struct clk * __init
samsung_clk_register_pll46xx(const char *name, }
/*
+ * PLL2126x Clock Type
+ */
+
+#define PLL2126X_MDIV_MASK (0xFF)
+#define PLL2126X_PDIV_MASK (0x3)
+#define PLL2126X_SDIV_MASK (0x3)
+#define PLL2126X_MDIV_SHIFT (16)
+#define PLL2126X_PDIV_SHIFT (8)
+#define PLL2126X_SDIV_SHIFT (0)
+#define PLL2126X_PDIV_MASK (0x3F)
is the correct value.
+
+struct samsung_clk_pll2126x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll2126x(_hw) container_of(_hw, struct
samsung_clk_pll2126x, hw) +
+static unsigned long samsung_pll2126x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll2126x *pll = to_clk_pll2126x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL2126X_MDIV_SHIFT) PLL2126X_MDIV_MASK;
+ pdiv = (pll_con PLL2126X_PDIV_SHIFT) PLL2126X_PDIV_MASK;
+ sdiv = (pll_con PLL2126X_SDIV_SHIFT) PLL2126X_SDIV_MASK;
+
+ fvco *= (mdiv + 8);
+ do_div(fvco, (pdiv + 2) sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2126x_clk_ops = {
+ .recalc_rate = samsung_pll2126x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2126x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll2126x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll2126x_clk_ops;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ init.parent_names = pname;
+ init.num_parents = 1;
+
+ pll-hw.init = init;
+ pll-con_reg = con_reg;
+
+ clk = samsung_register_pll(pll-hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+/*
* PLL2550x Clock Type
*/
@@ -396,3 +463,216 @@ struct clk * __init
samsung_clk_register_pll2550x(const char *name,
return clk;
}
+
+/*
+ * PLL3000x Clock Type
+ */
+
+#define PLL3000X_MDIV_MASK (0xFF)
+#define PLL3000X_PDIV_MASK (0x3)
+#define PLL3000X_SDIV_MASK (0x3)
+#define PLL3000X_MDIV_SHIFT (16)
+#define PLL3000X_PDIV_SHIFT (8)
+#define PLL3000X_SDIV_SHIFT (0)
these are correct.
+
+struct samsung_clk_pll3000x {
+ struct clk_hw hw;
+ const void __iomem *con_reg;
+};
+
+#define to_clk_pll3000x(_hw) container_of(_hw, struct
samsung_clk_pll3000x, hw) +
+static unsigned long samsung_pll3000x_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll3000x *pll = to_clk_pll3000x(hw);
+ u32 pll_con, mdiv, pdiv, sdiv;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll-con_reg);
+ mdiv = (pll_con PLL3000X_MDIV_SHIFT) PLL3000X_MDIV_MASK;
+ pdiv = (pll_con PLL3000X_PDIV_SHIFT) PLL3000X_PDIV_MASK;
+ sdiv = (pll_con PLL3000X_SDIV_SHIFT) PLL3000X_SDIV_MASK;
+
+ fvco *= (2 * (mdiv + 8));
+ do_div(fvco, pdiv sdiv);
+
+ return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll3000x_clk_ops = {
+ .recalc_rate = samsung_pll3000x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll3000x(const char *name,
+ const char *pname, const void __iomem *con_reg)
+{
+ struct samsung_clk_pll3000x *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = samsung_pll3000x_clk_ops;
+ init.flags =
Re: [PATCH] gpio: samsung: more generic pinctrl exclude ifdef
Hi Heiko, On Tuesday 09 of July 2013 02:12:31 Heiko Stübner wrote: The exclude check should run any time when either the PINCTRL_SAMSUNG or PINCTRL_EXYNOS5440 are selected. As the real check for the presence of a pinctrl driver is done via a dt lookup it's not necessary to specifiy every pinctrl option in the ifdef individually. This fixes a breakage on s3c2416, when both the legacy and dt boards are selected. Signed-off-by: Heiko Stuebner he...@sntech.de --- Extracted from Tomasz pinctrl series, as it fixes a bug in the current 3.11 development. drivers/gpio/gpio-samsung.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index a1392f4..ceb7971 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -2949,7 +2949,7 @@ static __init int samsung_gpiolib_init(void) int i, nr_chips; int group = 0; -#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440) +#if defined(CONFIG_PINCTRL_SAMSUNG) || defined(CONFIG_PINCTRL_EXYNOS5440) /* * This gpio driver includes support for device tree support and there * are platforms using it. In order to maintain compatibility with those I think we can simplify this even more now, since when booting with DT pinctrl driver is always used. What about just removing the whole check, including the ifdef and looking for compatible nodes and replacing them with: if (of_have_populated_dt()) return -ENODEV; Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 Resend 2/3] of/documentation: Update G2D documentation
Hi Sachin, On Tuesday 09 of July 2013 11:59:15 Sachin Kamat wrote: Exynos5250 G2D IP requires only the gate clock. Update the binding documentation accordingly. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Cc: Inki Dae inki@samsung.com --- Updated the description of clock-names as suggested by Tomasz Figa. --- .../devicetree/bindings/gpu/samsung-g2d.txt|7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt index 3f454ff..c4f358d 100644 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt @@ -11,8 +11,11 @@ Required properties: - interrupts : G2D interrupt number to the CPU. - clocks : from common clock binding: handle to G2D clocks. - - clock-names : from common clock binding: must contain sclk_fimg2d and - fimg2d, corresponding to entries in the clocks property. + - clock-names : names of clocks listed in clocks property, in the same + order, depending on SoC type: + - for S5PV210 and Exynos4 based SoCs: fimg2d and + sclk_fimg2d + - for Exynos5250 SoC: fimg2d. This looks fine for me now. Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
Hi Padmavathi,
On Thursday 11 of July 2013 12:38:24 Padmavathi Venna wrote:
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
[abrestic: style cleanup and documentation]
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-on: https://gerrit-int.chromium.org/37840
Reviewed-by: Simon Glass s...@google.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |2 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 51 ++---
sound/soc/samsung/i2s.c| 117
4 files changed, 132 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index
025e66b..b8593d5 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -28,6 +28,8 @@ Optional SoC Specific Properties:
enabled or disabled based on need.
- samsung,supports-secdai:If I2S block has a secondary FIFO and internal
DMA, then this flag is enabled.
+- samsung,supports-tdm: If the I2S controller supports TDM, then this flag
+ must be enabled.
I think this should be rather handled by a different compatible value, not a
flag. Also a word about what this TDM mode is would be nice.
Best regards,
Tomasz
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR (1 2)
#define QUIRK_NEED_RSTCLR(1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index c0e6d9a..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR 0x34
#define I2SLVL2ADDR 0x38
#define I2SLVL3ADDR 0x3c
+#define I2SSTR1 0x40
+#define I2SVER 0x44
+#define I2SFIC2 0x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS (1 26)
@@ -95,24 +99,39 @@
#define MOD_RXONLY (1 8)
#define MOD_TXRX (2 8)
#define MOD_MASK (3 8)
-#define MOD_LR_LLOW (0 7)
-#define MOD_LR_RLOW (1 7)
-#define MOD_SDF_IIS (0 5)
-#define MOD_SDF_MSB (1 5)
-#define MOD_SDF_LSB (2 5)
-#define MOD_SDF_MASK (3 5)
-#define MOD_RCLK_256FS (0 3)
-#define MOD_RCLK_512FS (1 3)
-#define MOD_RCLK_384FS (2 3)
-#define MOD_RCLK_768FS (3 3)
-#define MOD_RCLK_MASK(3 3)
-#define MOD_BCLK_32FS(0 1)
-#define MOD_BCLK_48FS(1 1)
-#define MOD_BCLK_16FS(2 1)
-#define MOD_BCLK_24FS(3 1)
-#define MOD_BCLK_MASK(3 1)
+#define MOD_LRP_SHIFT7
+#define MOD_LR_LLOW 0
+#define MOD_LR_RLOW 1
+#define MOD_SDF_SHIFT5
+#define MOD_SDF_IIS 0
+#define MOD_SDF_MSB 1
+#define MOD_SDF_LSB 2
+#define MOD_SDF_MASK 3
+#define MOD_RCLK_SHIFT 3
+#define MOD_RCLK_256FS 0
+#define MOD_RCLK_512FS 1
+#define MOD_RCLK_384FS 2
+#define MOD_RCLK_768FS 3
+#define MOD_RCLK_MASK3
+#define MOD_BCLK_SHIFT 1
+#define MOD_BCLK_32FS0
+#define MOD_BCLK_48FS1
+#define MOD_BCLK_16FS2
+#define MOD_BCLK_24FS3
+#define MOD_BCLK_MASK3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT4
+#define EXYNOS5420_MOD_BCLK_SHIFT0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS6
+#define EXYNOS5420_MOD_BCLK_192FS7
+#define EXYNOS5420_MOD_BCLK_256FS8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thu, Jul 11, 2013 at 12:38:24PM +0530, Padmavathi Venna wrote: -#define MOD_LR_LLOW (0 7) -#define MOD_LR_RLOW (1 7) -#define MOD_SDF_IIS (0 5) -#define MOD_SDF_MSB (1 5) -#define MOD_SDF_LSB (2 5) -#define MOD_SDF_MASK (3 5) +#define MOD_LR_LLOW 0 +#define MOD_LR_RLOW 1 +#define MOD_SDF_SHIFT5 +#define MOD_SDF_IIS 0 +#define MOD_SDF_MSB 1 +#define MOD_SDF_LSB 2 +#define MOD_SDF_MASK 3 This patch has an awful lot of coding style changes like this which are just coding style changes and not implementing TDM support. These should be done separately, not as part of the same patch, in order to make the code easier to review. case 768: - mod |= MOD_RCLK_768FS; + mod |= (MOD_RCLK_768FS rfs_shift); break; This stuff is another example. I think the change itself should be fine but I'm not 100% sure I'm correctly identifying what's a stylistic change and what's a functional change. signature.asc Description: Digital signature
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thursday 11 of July 2013 11:48:04 Mark Brown wrote: On Thu, Jul 11, 2013 at 12:38:24PM +0530, Padmavathi Venna wrote: -#define MOD_LR_LLOW(0 7) -#define MOD_LR_RLOW(1 7) -#define MOD_SDF_IIS(0 5) -#define MOD_SDF_MSB(1 5) -#define MOD_SDF_LSB(2 5) -#define MOD_SDF_MASK (3 5) +#define MOD_LR_LLOW0 +#define MOD_LR_RLOW1 +#define MOD_SDF_SHIFT 5 +#define MOD_SDF_IIS0 +#define MOD_SDF_MSB1 +#define MOD_SDF_LSB2 +#define MOD_SDF_MASK 3 This patch has an awful lot of coding style changes like this which are just coding style changes and not implementing TDM support. These should be done separately, not as part of the same patch, in order to make the code easier to review. case 768: - mod |= MOD_RCLK_768FS; + mod |= (MOD_RCLK_768FS rfs_shift); break; This stuff is another example. I think the change itself should be fine but I'm not 100% sure I'm correctly identifying what's a stylistic change and what's a functional change. Right. This could be split into two patches, first reworking the style to give more flexibility with operations on registers and another one adding TDM specific changes, like new bitfield definitions and conditional handling of register accesses to account for new bitfield locations. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Set RFS and BFS in slave mode
On Thu, Jul 11, 2013 at 12:38:25PM +0530, Padmavathi Venna wrote: As per the User Manual, the RFS and BFS should be set in slave mode for correct operation. Applied, thanks. Since this is a fix it should have been the first patch in the series - this allows fixes to be sent to Reviewed-on: https://gerrit-int.chromium.org/37841 Including things like this isn't terribly helpful - this is the Chromium internal system and nobody in the community can view the review. A link to a public system might be useful but a private one should be omitted. signature.asc Description: Digital signature
Re: [PATCH] mfd: sec: Add register cache for interrupt mask registers
On Tue, 02 Jul 2013, Mark Brown wrote: From: Mark Brown broo...@linaro.org The performance of regmap-irq is improved if the interrupt mask registers can be cached since it does read/modify/update cycles so start using the register cache infrastructure for those registers. We should use this more widely but I don't have a datasheet and this is a nice, conservative starting point. Signed-off-by: Mark Brown broo...@linaro.org --- drivers/mfd/sec-core.c | 31 +++ 1 file changed, 31 insertions(+) Applied, thanks. -- Lee Jones Linaro ST-Ericsson Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thu, Jul 11, 2013 at 12:43:22PM +0200, Tomasz Figa wrote: On Thursday 11 of July 2013 12:38:24 Padmavathi Venna wrote: +- samsung,supports-tdm: If the I2S controller supports TDM, then this flag + must be enabled. I think this should be rather handled by a different compatible value, not a This is a bit of a larger project sadly, there was resistance to doing the DT bindings based on compatible strings using the IP version :( signature.asc Description: Digital signature
RE: [PATCH v7 9/9] iommu/exynos: add bus notifier for registering System MMU
From: Prathyush K [mailto:prathy...@chromium.org]
Sent: Thursday, July 11, 2013 12:03 AM
I think this patch can be split further.
There is a lot more added in this patch (suspend/resume functions etc) than
just adding a bus notifier.
Oh, Sorry for that ;-)
Actually, adding bus notifier is to register gpd_pm_ops to master peripheral
devices,
it results in big change in the driver.
I will review further and also, test this patchset.
Thank you very much.
Regards,
Prathyush
On Fri, Jul 5, 2013 at 5:59 PM, Cho KyongHo pullip@samsung.com wrote:
When a device driver is registered, all constructs to handle System MMU
is prepared by bus notifier call.
Signed-off-by: Cho KyongHo pullip@samsung.com
---
drivers/iommu/exynos-iommu.c | 778 ++---
1 files changed, 569 insertions(+), 209 deletions(-)
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index b151e51..51d43bb 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -27,6 +27,9 @@
#include linux/memblock.h
#include linux/export.h
#include linux/of.h
+#include linux/of_platform.h
+#include linux/pm_domain.h
+#include linux/notifier.h
#include asm/cacheflush.h
#include asm/pgtable.h
@@ -80,6 +83,14 @@
#define CTRL_BLOCK 0x7
#define CTRL_DISABLE 0x0
+#define CFG_LRU0x1
+#define CFG_QOS(n) ((n 0xF) 7)
+#define CFG_MASK 0x0150 /* Selecting bit 0-15, 20, 22 and 24 */
+#define CFG_ACGEN (1 24) /* System MMU 3.3 only */
+#define CFG_SYSSEL (1 22) /* System MMU 3.2 only */
+#define CFG_FLPDCACHE (1 20) /* System MMU 3.2+ only */
+#define CFG_SHAREABLE (1 12) /* System MMU 3.x only */
+
#define REG_MMU_CTRL 0x000
#define REG_MMU_CFG0x004
#define REG_MMU_STATUS 0x008
@@ -96,6 +107,9 @@
#define REG_MMU_VERSION0x034
+#define MMU_MAJ_VER(reg) (reg 28)
+#define MMU_MIN_VER(reg) ((reg 21) 0x7F)
+
#define REG_PB0_SADDR 0x04C
#define REG_PB0_EADDR 0x050
#define REG_PB1_SADDR 0x054
@@ -126,16 +140,6 @@ enum exynos_sysmmu_inttype {
SYSMMU_FAULTS_NUM
};
-/*
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if
@itype
- *is SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- * translated. This is 0 if @itype is SYSMMU_BUSERROR.
- */
-typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
- unsigned long pgtable_base, unsigned long fault_addr);
-
static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
REG_PAGE_FAULT_ADDR,
REG_AR_FAULT_ADDR,
@@ -159,6 +163,14 @@ static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
UNKNOWN FAULT
};
+struct exynos_iommu_client {
+ struct list_head node; /* entry of exynos_iommu_domain.clients */
+ struct device *dev;
+ spinlock_t lock;
+ int num_sysmmu;
+ struct device *sysmmu[0];
+};
+
struct exynos_iommu_domain {
struct list_head clients; /* list of sysmmu_drvdata.node */
unsigned long *pgtable; /* lv1 page table, 16KB */
@@ -170,13 +182,13 @@ struct exynos_iommu_domain {
struct sysmmu_drvdata {
struct list_head node; /* entry of exynos_iommu_domain.clients */
struct device *sysmmu; /* System MMU's device descriptor */
- struct device *dev; /* Owner of system MMU */
+ struct device *master; /* Owner of system MMU */
int nsfrs;
struct clk *clk;
int activations;
spinlock_t lock;
struct iommu_domain *domain;
- sysmmu_fault_handler_t fault_handler;
+ bool runtime_active;
unsigned long pgtable;
void __iomem *sfrbases[0];
};
@@ -200,6 +212,20 @@ static bool is_sysmmu_active(struct sysmmu_drvdata *data)
return data-activations 0;
}
+static unsigned int __sysmmu_version(struct sysmmu_drvdata *data,
+ int idx, unsigned int *minor)
+{
+ unsigned int major;
+
+ major = readl(data-sfrbases[idx] + REG_MMU_VERSION);
+
+ if (minor)
+ *minor = MMU_MIN_VER(major);
+ major = MMU_MAJ_VER(major);
+
+ return major;
+}
+
static void sysmmu_unblock(void __iomem *sfrbase)
{
__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
@@ -235,7 +261,6 @@ static void __sysmmu_tlb_invalidate_entry(void __iomem
*sfrbase,
static void __sysmmu_set_ptbase(void __iomem *sfrbase,
unsigned long pgd)
{
- __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
__sysmmu_tlb_invalidate(sfrbase);
@@ -292,34 +317,17 @@ finish:
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thursday 11 of July 2013 12:20:23 Mark Brown wrote: On Thu, Jul 11, 2013 at 12:43:22PM +0200, Tomasz Figa wrote: On Thursday 11 of July 2013 12:38:24 Padmavathi Venna wrote: +- samsung,supports-tdm: If the I2S controller supports TDM, then this flag + must be enabled. I think this should be rather handled by a different compatible value, not a This is a bit of a larger project sadly, there was resistance to doing the DT bindings based on compatible strings using the IP version :( I'm not sure if this case is related to this problem in any way. I just suggested introducing a new include like samsung,exynos5420-i2s, a opposed to using samsung,exynos5250-i2s and adding flags, since the I2S in Exynos5420 is the first one to have this TDM or whatever mode. (I'd still like to hear what it is...) Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v7 6/9] clk: exynos5250: add gate clock descriptions of System MMU
From: Prathyush K [mailto:prathy...@chromium.org]
Sent: Wednesday, July 10, 2013 11:49 PM
On Fri, Jul 5, 2013 at 5:59 PM, Cho KyongHo pullip@samsung.com wrote:
This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c
Signed-off-by: Cho KyongHo pullip@samsung.com
CC: Thomas Abraham thomas.abra...@linaro.org
---
.../devicetree/bindings/clock/exynos5250-clock.txt | 28 +-
drivers/clk/samsung/clk-exynos5250.c | 57 ---
2 files changed, 75 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a627..df49694 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -154,7 +154,33 @@ clock which they consume.
dsim0341
dp 342
mixer343
- hdmi 345
+ hdmi 344
+ camif_top345
+ smmu_fimc_lite0 346
+ smmu_fimc_lite1 347
+ smmu_fimc_lite2 348
+ smmu_tv 349
+ smmu_fimd1 350
+ smmu_2d 351
+ fimc_isp 352
+ fimc_drc 353
+ fimc_fd 354
+ fimc_scc 355
+ fimc_scp 356
+ fimc_mcuctl 357
+ fimc_odc 358
+ fimc_dis 359
+ fimc_3dnr360
+ smmu_fimc_isp361
+ smmu_fimc_drc362
+ smmu_fimc_fd 363
+ smmu_fimc_scc364
+ smmu_fimc_scp365
+ smmu_fimc_mcuctl 366
+ smmu_fimc_odc367
+ smmu_fimc_dis0 368
+ smmu_fimc_dis1 369
+ smmu_fimc_3dnr 370
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 22d7699..1921d6c 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -53,12 +53,15 @@
#define DIV_PERIC3 0x10564
#define DIV_PERIC4 0x10568
#define DIV_PERIC5 0x1056c
+#define GATE_IP_ISP0 0x0C800
+#define GATE_IP_ISP1 0x0C800
#define GATE_IP_GSCL 0x10920
#define GATE_IP_MFC0x1092c
#define GATE_IP_GEN0x10934
#define GATE_IP_FSYS 0x10944
#define GATE_IP_PERIC 0x10950
#define GATE_IP_PERIS 0x10960
+#define GATE_IP_ACP0x18800
#define SRC_CDREX 0x20200
#define PLL_DIV2_SEL 0x20a24
#define GATE_IP_DISP1 0x10928
@@ -100,6 +103,14 @@ enum exynos5250_clks {
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+ camif_top, smmu_fimc_lite0, smmu_fimc_lite1, smmu_fimc_lite2,
+ smmu_tv, smmu_fimd1, smmu_2d,
+ fimc_isp, fimc_drc, fimc_fd, fimc_scc, fimc_scp, fimc_mcuctl,
fimc_odc,
+ fimc_dis, fimc_3dnr,
+ smmu_fimc_isp, smmu_fimc_drc, smmu_fimc_fd, smmu_fimc_scc,
+ smmu_fimc_scp, smmu_fimc_mcuctl, smmu_fimc_odc, smmu_fimc_dis0,
+ smmu_fimc_dis1, smmu_fimc_3dnr,
+
nr_clks,
};
@@ -320,19 +331,26 @@ struct samsung_gate_clock exynos5250_gate_clks[]
__initdata = {
GATE(gscl3, gscl3, aclk266, GATE_IP_GSCL, 3, 0, 0),
GATE(gscl_wa, gscl_wa, div_gscl_wa, GATE_IP_GSCL, 5, 0, 0),
GATE(gscl_wb, gscl_wb, div_gscl_wb, GATE_IP_GSCL, 6, 0, 0),
- GATE(smmu_gscl0, smmu_gscl0, aclk266, GATE_IP_GSCL, 7, 0, 0),
- GATE(smmu_gscl1, smmu_gscl1, aclk266, GATE_IP_GSCL, 8, 0, 0),
- GATE(smmu_gscl2, smmu_gscl2, aclk266, GATE_IP_GSCL, 9, 0, 0),
- GATE(smmu_gscl3, smmu_gscl3, aclk266, GATE_IP_GSCL, 10, 0, 0),
+ GATE(smmu_gscl0, smmu_gscl0, gscl0, GATE_IP_GSCL, 7, 0, 0),
+ GATE(smmu_gscl1, smmu_gscl1, gscl1, GATE_IP_GSCL, 8, 0, 0),
+ GATE(smmu_gscl2, smmu_gscl2, gscl2, GATE_IP_GSCL, 9, 0, 0),
+ GATE(smmu_gscl3, smmu_gscl3, gscl3, GATE_IP_GSCL, 10, 0, 0),
+ GATE(camif_top, camif_top, aclk266, GATE_IP_GSCL, 4, 0, 0),
+ GATE(smmu_fimc_lite0, smmu_fimc_lite0, camif_top,
+ GATE_IP_GSCL, 12, 0, 0),
+ GATE(smmu_fimc_lite1, smmu_fimc_lite1, camif_top,
+ GATE_IP_GSCL, 13, 0, 0),
+ GATE(smmu_fimc_lite2, smmu_fimc_lite2, camif_top,
+ GATE_IP_GSCL, 14, 0, 0),
GATE(mfc, mfc, aclk333, GATE_IP_MFC, 0, 0, 0),
- GATE(smmu_mfcl, smmu_mfcl, aclk333, GATE_IP_MFC, 1, 0, 0),
- GATE(smmu_mfcr, smmu_mfcr, aclk333, GATE_IP_MFC, 2, 0, 0),
+ GATE(smmu_mfcl, smmu_mfcl, mfc, GATE_IP_MFC,
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thu, Jul 11, 2013 at 01:41:40PM +0200, Tomasz Figa wrote: On Thursday 11 of July 2013 12:20:23 Mark Brown wrote: This is a bit of a larger project sadly, there was resistance to doing the DT bindings based on compatible strings using the IP version :( I'm not sure if this case is related to this problem in any way. I just suggested introducing a new include like samsung,exynos5420-i2s, a opposed to using samsung,exynos5250-i2s and adding flags, since the I2S in Exynos5420 is Well, it *should* be samsung,i2s-vN where N is the version number of the IP but documentation on the versioning has been patchy hence this whole thinng. the first one to have this TDM or whatever mode. (I'd still like to hear what it is...) What it *should* be is the option to send more than one audio stream down a link using time division multiplexing. signature.asc Description: Digital signature
Re: Re: [PATCH 1/3] ARM: EXYNOS: remove non-working AFTR mode support
Hi, On Friday, June 28, 2013 11:47:49 PM Daniel Lezcano wrote: On 06/28/2013 06:27 PM, Bartlomiej Zolnierkiewicz wrote: On Friday, June 28, 2013 01:20:09 PM Daniel Lezcano wrote: On 06/28/2013 12:11 PM, Tomasz Figa wrote: Hi Daniel, I've been fighting with this whole AFTR state as well, before Bartlomiej. Let me share my thoughts on this. [ ... ] If you don't unplug all the CPUs 0 the state is obviously never reached. Otherwise the whole system hangs after it tries to enter this mode without any reaction for external events, other than reset. Need investigation. What is the exynos board version where that occurs ? Could you please tell me what exactly do you mean by that? I already wrote that we can reproduce the problem on EXYNOS4210 rev0 and rev1.1 (we don't have rev1.0). Tomek has also reproduced the problem on some later SoCs (I hope that he can give you exact revisions). In our testing we didn't encounter the board on which the problem doesn't occur. Our current working theory is that the problem may be u-boot (or first stage bootloader) related. Ok, the status for what I know: Origen Exynos4210, board ver A: works for me Arndale Exynos5250: works for me but only if u-boot does not enable the hypervisor mode. Chromebook Exynos5250: works for me I've also done some more testing. First I tested on some Exynos4412 devices (M0 and SLP_PQ) and AFTR was not working on them. Then I got my hands on Origen Exynos4210 (thanks to Tomek Figa for providing it) and AFTR is working just fine on it. Finally I tried Trats board again but with the upstream u-boot instead of our custom modified version (thanks to help from Lukasz Majewski) and I found out that after this change AFTR works fine on it! It also gives quite nice power savings (~80mA less current drawn in AFTR mode compared to just WFI one). With the above findings it now seems that the issue is on our side and is outside the kernel. Thanks for help with narrowing down the problem and sorry for wasting your time. Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics I found the following drivers: https://github.com/AndreiLux/Perseus-UNIVERSAL5410/blob/samsung/arch/arm/mach-exynos/cpuidle.c https://github.com/CyanogenMod/hardkernel-kernel-4412/blob/cm-10.1/arch/arm/mach-exynos/cpuidle-exynos4.c Sounds like the num cpus 1 is still there. [ ... ] The kernel is not a playground where you can upstream code and then remove it because a feature seems broken and you don't have an idea of why. Neither me or Tomek did upstream this code and we couldn't react in time because we haven't noticed that it is completely unusable for us as EXYNOS cpuidle driver is not even used by default on EXYNOS (it is not enabled either in defconfig or Kconfig). Moreover the feature we are talking about (AFTR mode) is also not used by default (except EXYNOS4210 rev0 on which it lockups system for us) even with EXYNOS cpuidle driver being enabled (because this specific feature depends on CPU hot-unplug which is not done automatically right now). Such things like unused/broken code removal is not something very unusual in the upstream kernel (I'm speaking from the experience here having maintained large subsystem for a couple of years). In this particular case we are talking about ~130 lines of code which can be trivially brought back later when/if needed. Anyway if the code removal is controversial for you we can just disable AFTR mode by default and enable it only when special command line option is given (i.e. aftr). This would fix all the broken configuration while still allowing the feature to be enabled on systems that had it working previously (since you claim that it works on some chipset/u-boot configurations). Actually, there are several reasons I am not in favor for the moment to remove this code: 1) code can't be pushed upstream and then removed so easily 2) I asked several times what was this cpu1 hack, I had no answer 3) I tried to make both cpus entering the AFTR state, but the cpu1 never wakes up, I asked but no answer. I would like to have some answers :) Before taking the decision to remove this state (btw you can remove the driver directly, no ? the default idle function is WFI), IMO it is worth to investigate and to spend some time to clarify what is happening. Then we can take a decision. I am willing to help. I asked several times the reasons of why the AFTR state couldn't work with multiple CPUs and I had no answer. Unfortunately I don't know the answer for your question. The AFTR mode doesn't work for us *at*all* (even with *one* CPU). Frankly speaking I have a couple of hypothesis: 1. something is not correctly setup and the PMU does not wake up the CPU1 2. there is a silicon bug and no one wants to tell it is the case In any
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Thu, Jul 11, 2013 at 02:49:43PM +0900, Jingoo Han wrote: [...] diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile [...] obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o I think we should keep these sorted alphabetically. Also Tegra and Marvell are PCIe controllers but they still use the pci- prefix instead of pcie-. Perhaps it'd be good to keep consistency here? I initially chose pci- because from a software point of view it doesn't matter all that much whether it's PCI or PCIe and because the drivers are part of the PCI subsystem. However if Exynos now uses the pcie- prefix it makes it look like Tegra and Marvell are plain old PCI. Thierry signature.asc Description: Digital signature
Re: [PATCH v7 00/12] iommu/exynos: Fixes and Enhancements of System MMU driver with DT
On Fri, Jul 5, 2013 at 5:29 AM, Cho KyongHo pullip@samsung.com wrote: The current exynos-iommu(System MMU) driver does not work autonomously since it is lack of support for power management of peripheral blocks. ... Patch summary: [PATCH v7 1/9] iommu/exynos: do not include removed header [PATCH v7 2/9] iommu/exynos: add missing cache flush for removed page table entries [PATCH v7 3/9] iommu/exynos: fix page table maintenance [PATCH v7 4/9] iommu/exynos: allocate lv2 page table from own slab [PATCH v7 5/9] iommu/exynos: change rwlock to spinlock [PATCH v7 6/9] clk: exynos5250: add gate clock descriptions of System MMU [PATCH v7 7/9] ARM: dts: Add description of System MMU of Exynos SoCs [PATCH v7 8/9] iommu/exynos: support for device tree [PATCH v7 9/9] iommu/exynos: add bus notifier for registering System MMU Cho, Of the above patches, nearly all have been applied to chromeos-3.8 (kernel-next git tree) by Doug Anderson and others. AFAICT, the only ones not applied are: [v7,3/9] iommu/exynos: fix page table maintenance [v7,6/9] clk: exynos5250: add gate clock descriptions of System MMU (conflicts in this one) [v7,7/9] ARM: dts: Add description of System MMU of Exynos SoCs (depends on 6/9) We also already have parts of: [v7,9/9] iommu/exynos: add bus notifier for registering System MMU Some of those are being further discussed but I've lost track now exactly which ones. I'm telling you about chromeos-3.8 status since the adopted changes have been reviewed (by me and others) are being tested manually here on several different Samsung Exynos platforms (including 5250 which is our snow platform). Not sure how you should to mark those patches since they aren't identical to your changes (which apply to post 3.10 kernels, not 3.8). You might consider splitting those patches out from the 4 I've listed above to get that series accepted upstream since the additional review/testing should provide some confidence those patches are good. cheers, grant -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 3/9] iommu/exynos: fix page table maintenance
Hi,
Some minor nitpicks below.
On Friday, July 05, 2013 09:29:18 PM Cho KyongHo wrote:
This prevents allocating lv2 page table for the lv1 page table entry
that already has 1MB page mapping. In addition some BUG_ON() is
changed to WARN_ON().
Signed-off-by: Cho KyongHo pullip@samsung.com
---
drivers/iommu/exynos-iommu.c | 34 ++
1 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index e3be3e5..2bfe9fa 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -862,12 +862,14 @@ static unsigned long *alloc_lv2entry(unsigned long
*sent, unsigned long iova,
pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
BUG_ON((unsigned long)pent (LV2TABLE_SIZE - 1));
if (!pent)
- return NULL;
+ return ERR_PTR(-ENOMEM);
*sent = mk_lv1ent_page(__pa(pent));
*pgcounter = NUM_LV2ENTRIES;
pgtable_flush(pent, pent + NUM_LV2ENTRIES);
pgtable_flush(sent, sent + 1);
+ } else if (lv1ent_section(sent)) {
+ return ERR_PTR(-EADDRINUSE);
}
return page_entry(sent, iova);
@@ -944,16 +946,16 @@ static int exynos_iommu_map(struct iommu_domain
*domain, unsigned long iova,
pent = alloc_lv2entry(entry, iova,
priv-lv2entcnt[lv1ent_offset(iova)]);
- if (!pent)
- ret = -ENOMEM;
+ if (IS_ERR(pent))
+ ret = PTR_ERR(pent);
else
ret = lv2set_page(pent, paddr, size,
priv-lv2entcnt[lv1ent_offset(iova)]);
}
if (ret) {
- pr_debug(%s: Failed to map iova 0x%lx/0x%x bytes\n,
- __func__, iova, size);
+ pr_err(%s: Failed(%d) to map iova 0x%#x bytes @ %#lx\n,
+ __func__, ret, size, iova);
}
Intendation is a bit weird, it should be more like:
pr_err(%s: Failed(%d) to map iova 0x%#x bytes @ %#lx\n,
__func__, ret, size, iova);
to be consistent with the rest of the driver.
You could have also removed superfluous braces while at it.
spin_unlock_irqrestore(priv-pgtablelock, flags);
@@ -968,6 +970,7 @@ static size_t exynos_iommu_unmap(struct iommu_domain
*domain,
struct sysmmu_drvdata *data;
unsigned long flags;
unsigned long *ent;
+ size_t err_page;
BUG_ON(priv-pgtable == NULL);
@@ -976,7 +979,8 @@ static size_t exynos_iommu_unmap(struct iommu_domain
*domain,
ent = section_entry(priv-pgtable, iova);
if (lv1ent_section(ent)) {
- BUG_ON(size SECT_SIZE);
+ if (WARN_ON(size SECT_SIZE))
+ goto err;
*ent = 0;
pgtable_flush(ent, ent + 1);
@@ -1008,7 +1012,8 @@ static size_t exynos_iommu_unmap(struct iommu_domain
*domain,
}
/* lv1ent_large(ent) == true here */
- BUG_ON(size LPAGE_SIZE);
+ if (WARN_ON(size LPAGE_SIZE))
+ goto err;
memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
@@ -1023,8 +1028,21 @@ done:
sysmmu_tlb_invalidate_entry(data-dev, iova);
spin_unlock_irqrestore(priv-lock, flags);
-
return size;
+err:
+ spin_unlock_irqrestore(priv-pgtablelock, flags);
+
+ err_page = (
+ ((unsigned long)ent - (unsigned long)priv-pgtable)
+ (NUM_LV1ENTRIES * sizeof(long))
Maybe you could add LV1TABLE_SIZE define and use it here (there is
already a LV2TABLE_SIZE define)?
+) ? SECT_SIZE : LPAGE_SIZE;
It also seems that err_page should be of unsigned long type, no need
to make it size_t one.
The above code is quite ugly currently, it could be rewritten into
something prettier, i.e.:
err_page = (unsigned long)ent - (unsigned long)priv-pgtable;
err_page = (err_page LV1TABLE_SIZE) ? SECT_SIZE : LPAGE_SIZE;
+ pr_err(%s: Failed due to size(%#lx) @ %#x is\
+ smaller than page size %#x\n,
+ __func__, iova, size, err_page);
Aren't iova and size arguments interchanged here?
+
+return 0;
There is an intendation issue here (extra whitespaces).
+
}
static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
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Re: [PATCH] usb: phy: samsung-usb2: Toggle HSIC GPIO from device tree
Hi Jingoo, Yeah, I followed that discussion back then, but it seems to have stalled a little (at least the HSIC patches haven't been picked up in any kernel.org repo yet to my knowledge). The problem is that I think these approaches cannot work reliably. I agree that it would be nice to control the HSIC device from its own driver, and have spent quite some time playing around with the usb/misc/usb3503.c driver to try to make this work... but there's a timing dependency here that you just can't model correctly with independent drivers. If the HSIC device is already active during boot (e.g. because it was used by firmware), there's always a chance that the USB stack will come up before the driver that resets it does. The device will be enumerated as normal, and when the other driver later pulls the reset signal the USB stack will not notice because there is no real disconnect detection on HSIC. Only when you eventually try to send another transfer to the device will you start to get timeouts, and the newly reset device will not be able to reenumerate because the host never asks it to. I really don't see how you could solve this without putting some kind of synchronization mechanism in the USB drivers. So this leaves ehci-s5p and phy-samsung-usb2 as the only possible places, and I chose the latter since all the host-side HSIC initialization is also there already. I think if you think of it as reset whatever is on the other side of this PHY, it's okay to put it as an optional feature into the PHY driver. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Friday, July 12, 2013 12:41 AM, Thierry Reding wrote: On Thu, Jul 11, 2013 at 02:49:43PM +0900, Jingoo Han wrote: [...] diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile [...] obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos.o I think we should keep these sorted alphabetically. Also Tegra and Marvell are PCIe controllers but they still use the pci- prefix instead of pcie-. Perhaps it'd be good to keep consistency here? I initially chose pci- because from a software point of view it doesn't matter all that much whether it's PCI or PCIe and because the drivers are part of the PCI subsystem. However if Exynos now uses the pcie- prefix it makes it look like Tegra and Marvell are plain old PCI. Hi Thierry, I initially chose 'pci-' prefix such as 'pci-designware.c'. However, Pratyush Anand suggested as below: I would suggest to rename it as pcie-designware.c, because synopsis pcie and pci controllers are different. If you have a good idea, please give it to me. :) Thank you. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Thursday, July 11, 2013 5:55 PM, Kishon Vijay Abraham I wrote: On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys designware part; other parts are Exynos specific. Also, the Synopsys designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys designware part and Exynos specific part. Signed-off-by: Jingoo Han jg1@samsung.com Cc: Pratyush Anand pratyush.an...@st.com Cc: Mohit KUMAR mohit.ku...@st.com --- . . snip . . + +/* Exynos PCIe driver does not allow module unload */ Just curious, why is this restriction? CC'ed Thierry Reding, Hi Kishon, That's a good question. Now, we don't have the solution to be able to load and unload the PCI host driver in a loop definitely without crashing or exposing any races or leaks, as Arnd Bergmann said. Please refer to the following thread in mailing-list. (http://archive.arm.linux.org.uk/lurker/message/20130614.123849.4ff363c5.pl.html) Thus, Exynos PCIe did not support unloading module. (http://archive.arm.linux.org.uk/lurker/message/20130614.125338.7d2bbf62.pl.html) Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] usb: phy: samsung-usb2: Toggle HSIC GPIO from device tree
On Friday, July 12, 2013 6:46 AM, Julius Werner wrote: Hi Jingoo, Yeah, I followed that discussion back then, but it seems to have stalled a little (at least the HSIC patches haven't been picked up in any kernel.org repo yet to my knowledge). The problem is that I think these approaches cannot work reliably. I agree that it would be nice to control the HSIC device from its own driver, and have spent quite some time playing around with the usb/misc/usb3503.c driver to try to make this work... but there's a timing dependency here that you just can't model correctly with independent drivers. If the HSIC device is already active during boot (e.g. because it was used by firmware), there's always a chance that the USB stack will come up before the driver that resets it does. The device will be enumerated as normal, and when the other driver later pulls the reset signal the USB stack will not notice because there is no real disconnect detection on HSIC. Only when you eventually try to send another transfer to the device will you start to get timeouts, and the newly reset device will not be able to reenumerate because the host never asks it to. I really don't see how you could solve this without putting some kind of synchronization mechanism in the USB drivers. So this leaves ehci-s5p and phy-samsung-usb2 as the only possible places, and I chose the latter since all the host-side HSIC initialization is also there already. I think if you think of it as reset whatever is on the other side of this PHY, it's okay to put it as an optional feature into the PHY driver. CC'ed Tomasz Figa, Dongjin Kim, Yulgon Kim Hi Tomasz, Dongjin, Julius Werner wants to put 'SMSC 3503 hub reset on Arndale board' to 'phy-samsung-usb*.c' files, because there is a timing dependency above mentioned. The following is the original patch sent by Julius Werner two day ago. (http://www.spinics.net/lists/linux-samsung-soc/msg20250.html) Previously, Olof mentioned that 'drivers/platform/arm/' would be used. (http://patches.linaro.org/16856/) Also, another way was mentioned by Fabio Estevam, using 'drivers/reset/gpio-reset.c' which is not merged yet. (http://permalink.gmane.org/gmane.linux.drivers.devicetree/36830) I think that 'phy-samsung-usb*.c' files are not a good place. However, Julius Werner's comment looks reasonable enough. If you have a comment, please feel free to share it. :) Thank you. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
On Thu, Jul 11, 2013 at 4:37 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On Thursday 11 of July 2013 11:48:04 Mark Brown wrote: On Thu, Jul 11, 2013 at 12:38:24PM +0530, Padmavathi Venna wrote: -#define MOD_LR_LLOW(0 7) -#define MOD_LR_RLOW(1 7) -#define MOD_SDF_IIS(0 5) -#define MOD_SDF_MSB(1 5) -#define MOD_SDF_LSB(2 5) -#define MOD_SDF_MASK (3 5) +#define MOD_LR_LLOW0 +#define MOD_LR_RLOW1 +#define MOD_SDF_SHIFT 5 +#define MOD_SDF_IIS0 +#define MOD_SDF_MSB1 +#define MOD_SDF_LSB2 +#define MOD_SDF_MASK 3 This patch has an awful lot of coding style changes like this which are just coding style changes and not implementing TDM support. These should be done separately, not as part of the same patch, in order to make the code easier to review. case 768: - mod |= MOD_RCLK_768FS; + mod |= (MOD_RCLK_768FS rfs_shift); break; This stuff is another example. I think the change itself should be fine but I'm not 100% sure I'm correctly identifying what's a stylistic change and what's a functional change. Right. This could be split into two patches, first reworking the style to give more flexibility with operations on registers and another one adding TDM specific changes, like new bitfield definitions and conditional handling of register accesses to account for new bitfield locations. Best regards, Tomasz Ok. I will bisect the changes into two patches as suggested. Thanks Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Modify the I2S driver to support I2S on Exynos5420
Hi, On Thu, Jul 11, 2013 at 6:31 PM, Mark Brown broo...@kernel.org wrote: On Thu, Jul 11, 2013 at 01:41:40PM +0200, Tomasz Figa wrote: On Thursday 11 of July 2013 12:20:23 Mark Brown wrote: This is a bit of a larger project sadly, there was resistance to doing the DT bindings based on compatible strings using the IP version :( I'm not sure if this case is related to this problem in any way. I just suggested introducing a new include like samsung,exynos5420-i2s, a opposed to using samsung,exynos5250-i2s and adding flags, since the I2S in Exynos5420 is Well, it *should* be samsung,i2s-vN where N is the version number of the IP but documentation on the versioning has been patchy hence this whole thinng. A new version number is added when a there was some change in the IP like adding a internal mux to the IP, adding multi channel support, adding reset control bit. This was done in the older code with platform device. Same thing is followed here. So as previously done, adding a new compatible name like samsung,i2s-v6 with new quirk samsung,supports-tdm is okey? I will mention about this versioning info in the Documentation in the next patch. the first one to have this TDM or whatever mode. (I'd still like to hear what it is...) What it *should* be is the option to send more than one audio stream down a link using time division multiplexing. Thanks Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: Samsung: Set RFS and BFS in slave mode
Hi, On Thu, Jul 11, 2013 at 4:41 PM, Mark Brown broo...@kernel.org wrote: On Thu, Jul 11, 2013 at 12:38:25PM +0530, Padmavathi Venna wrote: As per the User Manual, the RFS and BFS should be set in slave mode for correct operation. Applied, thanks. Since this is a fix it should have been the first patch in the series - this allows fixes to be sent to Reviewed-on: https://gerrit-int.chromium.org/37841 Including things like this isn't terribly helpful - this is the Chromium internal system and nobody in the community can view the review. A link to a public system might be useful but a private one should be omitted. I thought it was link to the public gerrit review system. Will remove next time. Thanks Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys part and Exynos part
On Friday 12 July 2013 05:30 AM, Jingoo Han wrote: On Thursday, July 11, 2013 5:55 PM, Kishon Vijay Abraham I wrote: On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys designware part; other parts are Exynos specific. Also, the Synopsys designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys designware part and Exynos specific part. Signed-off-by: Jingoo Han jg1@samsung.com Cc: Pratyush Anand pratyush.an...@st.com Cc: Mohit KUMAR mohit.ku...@st.com --- . . snip . . + +/* Exynos PCIe driver does not allow module unload */ Just curious, why is this restriction? CC'ed Thierry Reding, Hi Kishon, That's a good question. Now, we don't have the solution to be able to load and unload the PCI host driver in a loop definitely without crashing or exposing any races or leaks, as Arnd Bergmann said. Please refer to the following thread in mailing-list. (http://archive.arm.linux.org.uk/lurker/message/20130614.123849.4ff363c5.pl.html) That explains. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
