date:20130726

Re: [PATCH 1/3] clk: exynos5250: Add G2D gate clock

2013-07-26 Thread Sachin Kamat

On 5 July 2013 14:12, Sachin Kamat sachin.ka...@linaro.org wrote:
 Adds gate clock for G2D IP for Exynos5250 SoC.

 Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
 Cc: Mike Turquette mturque...@linaro.org
 ---
 This patch depends on the following patch:
 http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
 ---
  .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
  drivers/clk/samsung/clk-exynos5250.c   |5 -
  2 files changed, 5 insertions(+), 1 deletion(-)

 diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 index 1a05761..7e88242 100644
 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 @@ -155,6 +155,7 @@ clock which they consume.
dp   342
mixer343
hdmi 344
 +  g2d  345

  Example 1: An example of a clock controller node is listed below.

 diff --git a/drivers/clk/samsung/clk-exynos5250.c 
 b/drivers/clk/samsung/clk-exynos5250.c
 index 6f767c5..3da0bdf 100644
 --- a/drivers/clk/samsung/clk-exynos5250.c
 +++ b/drivers/clk/samsung/clk-exynos5250.c
 @@ -62,6 +62,7 @@
  #define SRC_CDREX  0x20200
  #define PLL_DIV2_SEL   0x20a24
  #define GATE_IP_DISP1  0x10928
 +#define GATE_IP_ACP0x1

  /*
   * Let each supported clock get a unique id. This id is used to lookup the 
 clock
 @@ -99,7 +100,7 @@ enum exynos5250_clks {
 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, 
 hsi2c2,
 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
 -   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
 +   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,

 nr_clks,
  };
 @@ -152,6 +153,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
 SRC_CDREX,
 PLL_DIV2_SEL,
 GATE_IP_DISP1,
 +   GATE_IP_ACP,
  };

  /* list of all parent clock list */
 @@ -463,6 +465,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] 
 __initdata = {
 GATE(dp, dp, aclk200, GATE_IP_DISP1, 4, 0, 0),
 GATE(mixer, mixer, aclk200, GATE_IP_DISP1, 5, 0, 0),
 GATE(hdmi, hdmi, aclk200, GATE_IP_DISP1, 6, 0, 0),
 +   GATE(g2d, g2d, aclk200, GATE_IP_ACP, 3, 0, 0),
  };

  static __initdata struct of_device_id ext_clk_match[] = {
 --
 1.7.9.5


Ping Mike.

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With warm regards,
Sachin
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Re: XCLKOUT in exynos5250 clock driver

2013-07-26 Thread Tushar Behera

On 07/25/2013 08:21 PM, Mark Brown wrote:
 I appear to be missing something in the clock driver for the exynos5250.
 I'm looking at the Arndale schematic and I see that the audio master
 clock is connected to XCLKOUT on the SoC.  However I can't see any
 reference to XCLKOUT or anything similar in the clock driver or any of
 the DTS files - where is this clock exposed by the clock driver?
 
 Unfortunately I haven't been able to get access to the datasheet for the
 part so I can't check this myself.
 

Information as per Exynos5250 user manual:
XCLKOUT is an output pin for debugging clocks. Exynos5250 has a CLKOUT
logic which can select one of the clocks (within its clock domains) and
output that through XCLKOUT pin.

Not sure if XCLKOUT on Arndale schematics means the same.

-- 
Tushar Behera
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RE: [PATCH 2/2] iommu/exynos: Follow kernel coding style for __sysmmu_enable return type

2013-07-26 Thread Cho KyongHo

 -Original Message-
 From: Antonios Motakis [mailto:a.mota...@virtualopensystems.com]
 Sent: Friday, July 26, 2013 12:35 AM
 
 On success, the __sysmmu_enable returns 1 instead of 0, which does not
 respect the convention described in Chapter 16 of the Linux kernel coding
 style.
 
 In fact, this return value is propagated all the way up to
 iommu_attach_device() and iommu_attach_device() in drivers/iommu.c,
 which results into inconsistent behavior of the IOMMU API with Exynos
 systems, compared to other IOMMUs.
 
 This patch replaces the return value with 0, which makes the Exynos'
 IOMMU driver behavior consistent with that of other IOMMUs.
 
 Signed-off-by: Antonios Motakis a.mota...@virtualopensystems.com
 ---
  drivers/iommu/exynos-iommu.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
 index c7dd4b5..4ea3abb 100644
 --- a/drivers/iommu/exynos-iommu.c
 +++ b/drivers/iommu/exynos-iommu.c
 @@ -504,7 +504,7 @@ static int __sysmmu_enable(struct sysmmu_drvdata *data,
 
   dev_dbg(data-sysmmu, Enabled\n);
   } else {
 - ret = (pgtable == data-pgtable) ? 1 : -EBUSY;
 + ret = (pgtable == data-pgtable) ? 0 : -EBUSY;
 
Ok.

__sysmmu_enable() must return 1 if it is called with the same page table.
I have fixed it exynos_iommu_attach_device() to always return zero on success
in the next patchset which I will post today.

Thank you.

   dev_dbg(data-sysmmu, already enabled\n);
   }
 --
 1.8.1.2

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[PATCH 1/2] ARM: dts: exynos4210-origen: Add fixed voltage regulator to simple bus

2013-07-26 Thread Sachin Kamat

This has been done for Arndale board vide commit aa3edb65
(ARM: dts: Put Arndale fixed voltage regulators on a simple-bus).
Replicate here for consistency and correctness.

Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
 arch/arm/boot/dts/exynos4210-origen.dts |   20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210-origen.dts 
b/arch/arm/boot/dts/exynos4210-origen.dts
index 5537af8..ae2653e 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -32,13 +32,19 @@
bootargs =root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M 
console=ttySAC2,115200 init=/linuxrc;
};
 
-   mmc_reg: voltage-regulator {
-   compatible = regulator-fixed;
-   regulator-name = VMEM_VDD_2.8V;
-   regulator-min-microvolt = 280;
-   regulator-max-microvolt = 280;
-   gpio = gpx1 1 0;
-   enable-active-high;
+   regulators {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   mmc_reg: voltage-regulator {
+   compatible = regulator-fixed;
+   regulator-name = VMEM_VDD_2.8V;
+   regulator-min-microvolt = 280;
+   regulator-max-microvolt = 280;
+   gpio = gpx1 1 0;
+   enable-active-high;
+   };
};
 
tmu@100C {
-- 
1.7.9.5

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[PATCH 2/2] ARM: dts: exynos4412-origen: Add fixed voltage regulator to simple bus

2013-07-26 Thread Sachin Kamat

This has been done for Arndale board vide commit aa3edb65
(ARM: dts: Put Arndale fixed voltage regulators on a simple-bus).
Replicate here for consistency and correctness.

Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
 arch/arm/boot/dts/exynos4412-origen.dts |   20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index 829fd1fb..cf4cdf2 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -27,13 +27,19 @@
bootargs =console=ttySAC2,115200;
};
 
-   mmc_reg: voltage-regulator {
-   compatible = regulator-fixed;
-   regulator-name = VMEM_VDD_2.8V;
-   regulator-min-microvolt = 280;
-   regulator-max-microvolt = 280;
-   gpio = gpx1 1 0;
-   enable-active-high;
+   regulators {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   mmc_reg: voltage-regulator {
+   compatible = regulator-fixed;
+   regulator-name = VMEM_VDD_2.8V;
+   regulator-min-microvolt = 280;
+   regulator-max-microvolt = 280;
+   gpio = gpx1 1 0;
+   enable-active-high;
+   };
};
 
pinctrl@1100 {
-- 
1.7.9.5

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[PATCH v8 00/12] iommu/exynos: Fixes and Enhancements of System MMU driver with DT

2013-07-26 Thread Cho KyongHo

The current exynos-iommu(System MMU) driver does not work autonomously
since it is lack of support for power management of peripheral blocks.
For example, MFC device driver must ensure that its System MMU is disabled
before MFC block is power-down not to invalidate IOTLB in the System MMU
when I/O memory mapping is changed. Because A System MMU is resides in the
same H/W block, access to control registers of System MMU while the H/W
block is turned off must be prohibited.

This set of changes solves the above problem with setting each System MMUs
as the parent of the device which owns the System MMU to recieve the
information when the device is turned off or turned on.

Another big change to the driver is the support for devicetree.
The bindings for System MMU is described in
Documentation/devicetree/bindings/arm/samsung/system-mmu.txt

In addition, this patchset also includes several bug fixes and enhancements
of the current driver.

Change log:
v8:
- Reordered patch list: moved change rwloc to spinlock to the last.
- Fixed remained bug in fix page table maintenance.
- Always return 0 from exynos_iommu_attach_device().
- Removed prefetch buffer setting when System MMU is enabled
  due to the restriction of prefetch buffers:
  A prefetch buffer must not hit from more than one DMA.
  For instance with GScalers, if a single prefetch buffer is initialized
  with 0x0 ~ 0x and a GScaler works on source buffer at 0x1000
  and target buffer @ 0x2000, the System MMU may be got deadlock.
  Clients must initialize prefetch buffers with custom function defined
  in exynos-iommu drivers whenever they need to enable prefetch buffers.
- The clock of System MMU has no relationship with the clock of its master H/W.
  The clock of master H/W is always enabled when exynos-iommu driver needs to
  access MMIO area and disabled as soon as the access finishes.
- Removed err_page variable used in exynos_iommu_unmap() in the previous patch
  fix page table maintenance.
- Split a big patch add bus notifier for registering System MMU.
   Extracted the following 2 patches: 9/12 and 10/12.
- And some additional fixes...

v7:
- Rebased on the stable 3.10
- Registered PM domains and gate clocks with DT
- Changed connection method between a System MMU and its master H/W
   'mmu-master' property in the node of System MMU
   -- 'iommu' property in the node of master H/W
- Marking device descriptor of master H/W of a System MMU with bus notifier.
- Power management (PM_RUNTIME, PM_SLEEP) of System MMUs with gpd_dev_ops
   of Generic IO Powerdomain. gpd_dev_ops are set to the master H/Ws
   before they are probed in the bus notifier.
- Removed additional debugging features like debugfs entries and
   version names.
- Removed support for advanced features of System MMU 3.2 and 3.3
   the current IOMMU API cannot handle the feature
  (A kind of L2 TLB that fetches several consequence page table entries.
   It must be initialized by the driver of master H/W whenever it works.)

v6:
- Rebased on the branch, next/iommu-exynos of
  git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git

v5:
- new bugfix: patch 01
- Reordered patches
  * patch 01 ~ 05: Bugfix and enhancements of the existing driver
  * patch 06 ~ 10: Device Tree support and callbacks for power management
  * patch 11 : System MMU 3.2 and 3.3 support
  * patch 12 ~ 14: Debugging features
- Additional code compaction

v4:
- Remove Change-Id from v3 patches
- Change the order of the third and the first patch
  Thanks to Kukjin Kim.
- Fix memory leak when allocating and assigning exynos_iommu_owner to client
  device if the client device has multiple System MMUs.
  Thanks to Rahul Sharma.

v3:
- Fix prefetch buffer flag definition for System MMU 3.3 (patch 10/12)
- Fix incorrect setting for SET_RUNTIME_PM_OPS (patch 09/12)
  Thanks to Prathyush.

v2:
- Split the patch to iommu/exynos into 9 patches
- Support for System MMU 3.3
- Some code compaction

Patch summary:
[PATCH v8 01/12] iommu/exynos: do not include removed header
[PATCH v8 02/12] iommu/exynos: add missing cache flush for removed page table 
entries
[PATCH v8 03/12] iommu/exynos: fix page table maintenance
[PATCH v8 04/12] iommu/exynos: allocate lv2 page table from own slab
[PATCH v8 05/12] clk: exynos5250: add gate clock descriptions of System MMU
[PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs
[PATCH v8 07/12] iommu/exynos: support for device tree
[PATCH v8 08/12] iommu/exynos: remove prefetch buffer setting when enabling 
System MMU
[PATCH v8 09/12] iommu/exynos: remove custom fault handler
[PATCH v8 10/12] iommu/exynos: add bus notifier for registering System MMU
[PATCH v8 11/12] iommu/exynos: change rwlock to spinlock
[PATCH v8 12/12] iommu/exynos: return 0 if iommu_attach_device() successes

Diffstats:
.../devicetree/bindings/clock/exynos5250-clock.txt |   28 +-
.../bindings/iommu/samsung,exynos4210-sysmmu.txt   |  103 ++
arch/arm/boot/dts/exynos4.dtsi

[PATCH v8 01/12] iommu/exynos: do not include removed header

2013-07-26 Thread Cho KyongHo

This commit remove mach/sysmmu.h which is removed.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 3f32d64..233f382 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -12,6 +12,7 @@
 #define DEBUG
 #endif
 
+#include linux/kernel.h
 #include linux/io.h
 #include linux/interrupt.h
 #include linux/platform_device.h
@@ -29,8 +30,6 @@
 #include asm/cacheflush.h
 #include asm/pgtable.h
 
-#include mach/sysmmu.h
-
 /* We does not consider super section mapping (16MB) */
 #define SECT_ORDER 20
 #define LPAGE_ORDER 16
-- 
1.7.2.5


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[PATCH v8 02/12] iommu/exynos: add missing cache flush for removed page table entries

2013-07-26 Thread Cho KyongHo

This commit adds cache flush for removed small and large page entries
in exynos_iommu_unmap(). Missing cache flush of removed page table
entries can cause missing page fault interrupt when a master IP
accesses an unmapped area.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 233f382..e3be3e5 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -1002,6 +1002,7 @@ static size_t exynos_iommu_unmap(struct iommu_domain 
*domain,
if (lv2ent_small(ent)) {
*ent = 0;
size = SPAGE_SIZE;
+   pgtable_flush(ent, ent +1);
priv-lv2entcnt[lv1ent_offset(iova)] += 1;
goto done;
}
@@ -1010,6 +1011,7 @@ static size_t exynos_iommu_unmap(struct iommu_domain 
*domain,
BUG_ON(size  LPAGE_SIZE);
 
memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
+   pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
 
size = LPAGE_SIZE;
priv-lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
-- 
1.7.2.5


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[PATCH v8 03/12] iommu/exynos: fix page table maintenance

2013-07-26 Thread Cho KyongHo

This prevents allocating lv2 page table for the lv1 page table entry
that already has 1MB page mapping. In addition some BUG_ON() is
changed to WARN_ON().

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   52 +
 1 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index e3be3e5..6c4ecce 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -52,11 +52,11 @@
 #define lv2ent_large(pent) ((*(pent)  3) == 1)
 
 #define section_phys(sent) (*(sent)  SECT_MASK)
-#define section_offs(iova) ((iova)  0xF)
+#define section_offs(iova) ((iova)  ~SECT_MASK)
 #define lpage_phys(pent) (*(pent)  LPAGE_MASK)
-#define lpage_offs(iova) ((iova)  0x)
+#define lpage_offs(iova) ((iova)  ~LPAGE_MASK)
 #define spage_phys(pent) (*(pent)  SPAGE_MASK)
-#define spage_offs(iova) ((iova)  0xFFF)
+#define spage_offs(iova) ((iova)  ~SPAGE_MASK)
 
 #define lv1ent_offset(iova) ((iova)  SECT_ORDER)
 #define lv2ent_offset(iova) (((iova)  0xFF000)  SPAGE_ORDER)
@@ -862,12 +862,14 @@ static unsigned long *alloc_lv2entry(unsigned long *sent, 
unsigned long iova,
pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
BUG_ON((unsigned long)pent  (LV2TABLE_SIZE - 1));
if (!pent)
-   return NULL;
+   return ERR_PTR(-ENOMEM);
 
*sent = mk_lv1ent_page(__pa(pent));
*pgcounter = NUM_LV2ENTRIES;
pgtable_flush(pent, pent + NUM_LV2ENTRIES);
pgtable_flush(sent, sent + 1);
+   } else if (lv1ent_section(sent)) {
+   return ERR_PTR(-EADDRINUSE);
}
 
return page_entry(sent, iova);
@@ -894,6 +896,12 @@ static int lv1set_section(unsigned long *sent, phys_addr_t 
paddr, short *pgcnt)
return 0;
 }
 
+static void clear_page_table(unsigned long *ent, int n)
+{
+   if (n  0)
+   memset(ent, 0, sizeof(*ent) * n);
+}
+
 static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
short *pgcnt)
 {
@@ -908,7 +916,7 @@ static int lv2set_page(unsigned long *pent, phys_addr_t 
paddr, size_t size,
int i;
for (i = 0; i  SPAGES_PER_LPAGE; i++, pent++) {
if (!lv2ent_fault(pent)) {
-   memset(pent, 0, sizeof(*pent) * i);
+   clear_page_table(pent - i, i);
return -EADDRINUSE;
}
 
@@ -944,17 +952,16 @@ static int exynos_iommu_map(struct iommu_domain *domain, 
unsigned long iova,
pent = alloc_lv2entry(entry, iova,
priv-lv2entcnt[lv1ent_offset(iova)]);
 
-   if (!pent)
-   ret = -ENOMEM;
+   if (IS_ERR(pent))
+   ret = PTR_ERR(pent);
else
ret = lv2set_page(pent, paddr, size,
priv-lv2entcnt[lv1ent_offset(iova)]);
}
 
-   if (ret) {
-   pr_debug(%s: Failed to map iova 0x%lx/0x%x bytes\n,
-   __func__, iova, size);
-   }
+   if (ret)
+   pr_err(%s: Failed(%d) to map 0x%#x bytes @ %#lx\n,
+   __func__, ret, size, iova);
 
spin_unlock_irqrestore(priv-pgtablelock, flags);
 
@@ -968,6 +975,7 @@ static size_t exynos_iommu_unmap(struct iommu_domain 
*domain,
struct sysmmu_drvdata *data;
unsigned long flags;
unsigned long *ent;
+   size_t err_pgsize;
 
BUG_ON(priv-pgtable == NULL);
 
@@ -976,7 +984,10 @@ static size_t exynos_iommu_unmap(struct iommu_domain 
*domain,
ent = section_entry(priv-pgtable, iova);
 
if (lv1ent_section(ent)) {
-   BUG_ON(size  SECT_SIZE);
+   if (WARN_ON(size  SECT_SIZE)) {
+   err_pgsize = SECT_SIZE;
+   goto err;
+   }
 
*ent = 0;
pgtable_flush(ent, ent + 1);
@@ -1008,9 +1019,12 @@ static size_t exynos_iommu_unmap(struct iommu_domain 
*domain,
}
 
/* lv1ent_large(ent) == true here */
-   BUG_ON(size  LPAGE_SIZE);
+   if (WARN_ON(size  LPAGE_SIZE)) {
+   err_pgsize = LPAGE_SIZE;
+   goto err;
+   }
 
-   memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
+   clear_page_table(ent, SPAGES_PER_LPAGE);
pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
 
size = LPAGE_SIZE;
@@ -1023,8 +1037,16 @@ done:
sysmmu_tlb_invalidate_entry(data-dev, iova);
spin_unlock_irqrestore(priv-lock, flags);
 
-
return size;
+err:
+   spin_unlock_irqrestore(priv-pgtablelock, flags);
+
+   pr_err(%s:

[PATCH v8 04/12] iommu/exynos: allocate lv2 page table from own slab

2013-07-26 Thread Cho KyongHo

Since kmalloc() does not guarantee that the allignment of 1KiB when it
allocates 1KiB, it is required to allocate lv2 page table from own
slab that guarantees alignment of 1KiB

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   24 
 1 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 6c4ecce..093eea5 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -100,6 +100,8 @@
 #define REG_PB1_SADDR  0x054
 #define REG_PB1_EADDR  0x058
 
+static struct kmem_cache *lv2table_kmem_cache;
+
 static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
 {
return pgtable + lv1ent_offset(iova);
@@ -765,7 +767,8 @@ static void exynos_iommu_domain_destroy(struct iommu_domain 
*domain)
 
for (i = 0; i  NUM_LV1ENTRIES; i++)
if (lv1ent_page(priv-pgtable + i))
-   kfree(__va(lv2table_base(priv-pgtable + i)));
+   kmem_cache_free(lv2table_kmem_cache,
+   __va(lv2table_base(priv-pgtable + i)));
 
free_pages((unsigned long)priv-pgtable, 2);
free_pages((unsigned long)priv-lv2entcnt, 1);
@@ -859,7 +862,7 @@ static unsigned long *alloc_lv2entry(unsigned long *sent, 
unsigned long iova,
if (lv1ent_fault(sent)) {
unsigned long *pent;
 
-   pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
+   pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
BUG_ON((unsigned long)pent  (LV2TABLE_SIZE - 1));
if (!pent)
return ERR_PTR(-ENOMEM);
@@ -884,7 +887,7 @@ static int lv1set_section(unsigned long *sent, phys_addr_t 
paddr, short *pgcnt)
if (*pgcnt != NUM_LV2ENTRIES)
return -EADDRINUSE;
 
-   kfree(page_entry(sent, 0));
+   kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 
*pgcnt = 0;
}
@@ -1092,10 +1095,23 @@ static int __init exynos_iommu_init(void)
 {
int ret;
 
+   lv2table_kmem_cache = kmem_cache_create(exynos-iommu-lv2table,
+   LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
+   if (!lv2table_kmem_cache) {
+   pr_err(%s: Failed to create kmem cache\n, __func__);
+   return -ENOMEM;
+   }
+
ret = platform_driver_register(exynos_sysmmu_driver);
 
if (ret == 0)
-   bus_set_iommu(platform_bus_type, exynos_iommu_ops);
+   ret = bus_set_iommu(platform_bus_type, exynos_iommu_ops);
+
+   if (ret) {
+   pr_err(%s: Failed to register exynos-iommu driver.\n,
+   __func__);
+   kmem_cache_destroy(lv2table_kmem_cache);
+   }
 
return ret;
 }
-- 
1.7.2.5


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[PATCH] [media] exynos-gsc: Register v4l2 device

2013-07-26 Thread Arun Kumar K

Gscaler video device registration was happening without
reference to a parent v4l2_dev causing probe to fail.
The patch creates a parent v4l2 device and uses it for
gsc m2m video device registration.

Signed-off-by: Arun Kumar K arun...@samsung.com
---
 drivers/media/platform/exynos-gsc/gsc-core.c |9 -
 drivers/media/platform/exynos-gsc/gsc-core.h |1 +
 drivers/media/platform/exynos-gsc/gsc-m2m.c  |1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/exynos-gsc/gsc-core.c 
b/drivers/media/platform/exynos-gsc/gsc-core.c
index 559fab2..1ec60264 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.c
+++ b/drivers/media/platform/exynos-gsc/gsc-core.c
@@ -1122,10 +1122,14 @@ static int gsc_probe(struct platform_device *pdev)
goto err_clk;
}
 
-   ret = gsc_register_m2m_device(gsc);
+   ret = v4l2_device_register(dev, gsc-v4l2_dev);
if (ret)
goto err_clk;
 
+   ret = gsc_register_m2m_device(gsc);
+   if (ret)
+   goto err_v4l2;
+
platform_set_drvdata(pdev, gsc);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(pdev-dev);
@@ -1147,6 +1151,8 @@ err_pm:
pm_runtime_put(dev);
 err_m2m:
gsc_unregister_m2m_device(gsc);
+err_v4l2:
+   v4l2_device_unregister(gsc-v4l2_dev);
 err_clk:
gsc_clk_put(gsc);
return ret;
@@ -1157,6 +1163,7 @@ static int gsc_remove(struct platform_device *pdev)
struct gsc_dev *gsc = platform_get_drvdata(pdev);
 
gsc_unregister_m2m_device(gsc);
+   v4l2_device_unregister(gsc-v4l2_dev);
 
vb2_dma_contig_cleanup_ctx(gsc-alloc_ctx);
pm_runtime_disable(pdev-dev);
diff --git a/drivers/media/platform/exynos-gsc/gsc-core.h 
b/drivers/media/platform/exynos-gsc/gsc-core.h
index cc19bba..76435d3 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.h
+++ b/drivers/media/platform/exynos-gsc/gsc-core.h
@@ -343,6 +343,7 @@ struct gsc_dev {
unsigned long   state;
struct vb2_alloc_ctx*alloc_ctx;
struct video_device vdev;
+   struct v4l2_device  v4l2_dev;
 };
 
 /**
diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c 
b/drivers/media/platform/exynos-gsc/gsc-m2m.c
index 40a73f7..e576ff2 100644
--- a/drivers/media/platform/exynos-gsc/gsc-m2m.c
+++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c
@@ -751,6 +751,7 @@ int gsc_register_m2m_device(struct gsc_dev *gsc)
gsc-vdev.release   = video_device_release_empty;
gsc-vdev.lock  = gsc-lock;
gsc-vdev.vfl_dir   = VFL_DIR_M2M;
+   gsc-vdev.v4l2_dev  = gsc-v4l2_dev;
snprintf(gsc-vdev.name, sizeof(gsc-vdev.name), %s.%d:m2m,
GSC_MODULE_NAME, gsc-id);
 
-- 
1.7.9.5

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[PATCH v8 06/12] ARM: dts: Add description of System MMU of Exynos SoCs

2013-07-26 Thread Cho KyongHo

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 .../bindings/iommu/samsung,exynos4210-sysmmu.txt   |  103 +++
 arch/arm/boot/dts/exynos4.dtsi |  122 
 arch/arm/boot/dts/exynos4210.dtsi  |   25 ++
 arch/arm/boot/dts/exynos4x12.dtsi  |   76 +
 arch/arm/boot/dts/exynos5250.dtsi  |  291 
 5 files changed, 617 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt

diff --git 
a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
new file mode 100644
index 000..92f0a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt
@@ -0,0 +1,103 @@
+Samsung Exynos4210 IOMMU H/W, System MMU (System Memory Management Unit)
+
+Samsung's Exynos architecture contains System MMU that enables scattered
+physical memory chunks visible as a contiguous region to DMA-capable peripheral
+devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
+
+System MMU is a sort of IOMMU and support identical translation table format to
+ARMv7 translation tables with minimum set of page properties including access
+permissions, shareability and security protection. In addition, System MMU has
+another capabilities like L2 TLB or block-fetch buffers to minimize translation
+latency.
+
+A System MMU is dedicated to a single master peripheral device.  Thus, it is
+important to specify the correct System MMU in the device node of its master
+device. Whereas a System MMU is dedicated to a master device, the master device
+may have more than one System MMU.
+
+Required properties:
+- compatible: Should be samsung,exynos4210-sysmmu
+- reg: A tuple of base address and size of System MMU registers.
+- interrupt-parent: The phandle of the interrupt controller of System MMU
+- interrupts: A tuple of numbers that indicates the interrupt source.
+- clock-names: Should be sysmmu if the System MMU is needed to gate its 
clock.
+   Please refer to the following documents:
+  Documentation/devicetree/bindings/clock/clock-bindings.txt
+  Documentation/devicetree/bindings/clock/exynos4-clock.txt
+  Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+  Optional master if the clock to the System MMU is gated by
+  another gate clock other than sysmmu. The System MMU driver
+  sets master the parent of sysmmu.
+  Exynos4 SoCs, there needs no master clocks.
+  Exynos5 SoCs, some System MMUs must have master clocks.
+- clocks: Required if the System MMU is needed to gate its clock.
+ Please refer to the documents listed above.
+- samsung,power-domain: Required if the System MMU is needed to gate its power.
+ Please refer to the following document:
+ Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+
+Required properties for the master peripheral devices:
+- iommu: phandles to the System MMUs of the device
+
+Examples:
+A System MMU is dedicated to a single master device.
+   gsc_0:  gsc@0x13e0 {
+   compatible = samsung,exynos5-gsc;
+   reg = 0x13e0 0x1000;
+   interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
+   clocks = clock 256;
+   clock-names = gscl;
+   iommu = sysmmu_gsc1;
+   };
+
+   sysmmu_gsc0: sysmmu@13E8 {
+   compatible = samsung,exynos4210-sysmmu;
+   reg = 0x13E8 0x1000;
+   interrupt-parent = combiner;
+   interrupt-names = sysmmu-gsc0;
+   interrupts = 2 0;
+   clock-names = sysmmu, master;
+   clocks = clock 262, clock 256;
+   samsung,power-domain = pd_gsc;
+   status = ok;
+   };
+
+MFC has 2 System MMUs for each port that MFC is attached. Thus it seems natural
+to define 2 System MMUs for each port of the MFC:
+
+   mfc: codec@1340 {
+   compatible = samsung,mfc-v5;
+   reg = 0x1340 0x1;
+   interrupts = 0 94 0;
+   samsung,power-domain = pd_mfc;
+   clocks = clock 170, clock 273;
+   clock-names = sclk_mfc, mfc;
+   status = ok;
+   iommu = sysmmu_mfc_l, sysmmu_mfc_r;
+   };
+
+   sysmmu_mfc_l: sysmmu@1362 {
+   compatible = samsung,exynos4210-sysmmu;
+   reg = 0x1362 0x1000;
+   interrupt-parent = combiner;
+   interrupt-names = sysmmu-mfc-l;
+   interrupts = 5 5;
+   clock-names = sysmmu;
+   clocks = clock 274;
+   samsung,power-domain = pd_mfc;
+   status = ok;
+   };
+
+   sysmmu_mfc_r: sysmmu@1363 {
+

[PATCH v8 05/12] clk: exynos5250: add gate clock descriptions of System MMU

2013-07-26 Thread Cho KyongHo

This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |   28 +-
 drivers/clk/samsung/clk-exynos5250.c   |   57 ---
 2 files changed, 75 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a627..df49694 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -154,7 +154,33 @@ clock which they consume.
   dsim0341
   dp   342
   mixer343
-  hdmi 345
+  hdmi 344
+  camif_top345
+  smmu_fimc_lite0  346
+  smmu_fimc_lite1  347
+  smmu_fimc_lite2  348
+  smmu_tv  349
+  smmu_fimd1   350
+  smmu_2d  351
+  fimc_isp 352
+  fimc_drc 353
+  fimc_fd  354
+  fimc_scc 355
+  fimc_scp 356
+  fimc_mcuctl  357
+  fimc_odc 358
+  fimc_dis 359
+  fimc_3dnr360
+  smmu_fimc_isp361
+  smmu_fimc_drc362
+  smmu_fimc_fd 363
+  smmu_fimc_scc364
+  smmu_fimc_scp365
+  smmu_fimc_mcuctl 366
+  smmu_fimc_odc367
+  smmu_fimc_dis0   368
+  smmu_fimc_dis1   369
+  smmu_fimc_3dnr   370
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index 22d7699..e242bde 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -53,12 +53,15 @@
 #define DIV_PERIC3 0x10564
 #define DIV_PERIC4 0x10568
 #define DIV_PERIC5 0x1056c
+#define GATE_IP_ISP0   0x0C800
+#define GATE_IP_ISP1   0x0C800
 #define GATE_IP_GSCL   0x10920
 #define GATE_IP_MFC0x1092c
 #define GATE_IP_GEN0x10934
 #define GATE_IP_FSYS   0x10944
 #define GATE_IP_PERIC  0x10950
 #define GATE_IP_PERIS  0x10960
+#define GATE_IP_ACP0x18800
 #define SRC_CDREX  0x20200
 #define PLL_DIV2_SEL   0x20a24
 #define GATE_IP_DISP1  0x10928
@@ -100,6 +103,14 @@ enum exynos5250_clks {
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
 
+   camif_top, smmu_fimc_lite0, smmu_fimc_lite1, smmu_fimc_lite2,
+   smmu_tv, smmu_fimd1, smmu_2d,
+   fimc_isp, fimc_drc, fimc_fd, fimc_scc, fimc_scp, fimc_mcuctl, fimc_odc,
+   fimc_dis, fimc_3dnr,
+   smmu_fimc_isp, smmu_fimc_drc, smmu_fimc_fd, smmu_fimc_scc,
+   smmu_fimc_scp, smmu_fimc_mcuctl, smmu_fimc_odc, smmu_fimc_dis0,
+   smmu_fimc_dis1, smmu_fimc_3dnr,
+
nr_clks,
 };
 
@@ -320,19 +331,26 @@ struct samsung_gate_clock exynos5250_gate_clks[] 
__initdata = {
GATE(gscl3, gscl3, aclk266, GATE_IP_GSCL, 3, 0, 0),
GATE(gscl_wa, gscl_wa, div_gscl_wa, GATE_IP_GSCL, 5, 0, 0),
GATE(gscl_wb, gscl_wb, div_gscl_wb, GATE_IP_GSCL, 6, 0, 0),
-   GATE(smmu_gscl0, smmu_gscl0, aclk266, GATE_IP_GSCL, 7, 0, 0),
-   GATE(smmu_gscl1, smmu_gscl1, aclk266, GATE_IP_GSCL, 8, 0, 0),
-   GATE(smmu_gscl2, smmu_gscl2, aclk266, GATE_IP_GSCL, 9, 0, 0),
-   GATE(smmu_gscl3, smmu_gscl3, aclk266, GATE_IP_GSCL, 10, 0, 0),
+   GATE(smmu_gscl0, smmu_gscl0, none, GATE_IP_GSCL, 7, 0, 0),
+   GATE(smmu_gscl1, smmu_gscl1, none, GATE_IP_GSCL, 8, 0, 0),
+   GATE(smmu_gscl2, smmu_gscl2, none, GATE_IP_GSCL, 9, 0, 0),
+   GATE(smmu_gscl3, smmu_gscl3, none, GATE_IP_GSCL, 10, 0, 0),
+   GATE(camif_top, camif_top, aclk266, GATE_IP_GSCL, 4, 0, 0),
+   GATE(smmu_fimc_lite0, smmu_fimc_lite0, none,
+   GATE_IP_GSCL, 12, 0, 0),
+   GATE(smmu_fimc_lite1, smmu_fimc_lite1, none,
+   GATE_IP_GSCL, 13, 0, 0),
+   GATE(smmu_fimc_lite2, smmu_fimc_lite2, none,
+   GATE_IP_GSCL, 14, 0, 0),
GATE(mfc, mfc, aclk333, GATE_IP_MFC, 0, 0, 0),
-   GATE(smmu_mfcl, smmu_mfcl, aclk333, GATE_IP_MFC, 1, 0, 0),
-   GATE(smmu_mfcr, smmu_mfcr, aclk333, GATE_IP_MFC, 2, 0, 0),
+   GATE(smmu_mfcr, smmu_mfcr, none, GATE_IP_MFC, 1, 0, 0),
+   GATE(smmu_mfcl, smmu_mfcl, none, GATE_IP_MFC, 2, 0, 0),
GATE(rotator, rotator, aclk266, GATE_IP_GEN, 1, 0, 0),
GATE(jpeg, jpeg, aclk166, GATE_IP_GEN, 2, 0, 0),
GATE(mdma1, mdma1, aclk266, GATE_IP_GEN, 4, 0, 0),
-   GATE(smmu_rotator, smmu_rotator, aclk266, GATE_IP_GEN, 6, 0, 0),
-

[PATCH v8 09/12] iommu/exynos: remove custom fault handler

2013-07-26 Thread Cho KyongHo

This commit removes custom fault handler. The device drivers that
need to register fault handler can register
with iommu_set_fault_handler().

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   71 ++
 1 files changed, 17 insertions(+), 54 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 87f6bb7..f9853fe 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -131,16 +131,6 @@ enum exynos_sysmmu_inttype {
SYSMMU_FAULTS_NUM
 };
 
-/*
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if @itype
- *is SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- * translated. This is 0 if @itype is SYSMMU_BUSERROR.
- */
-typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
-   unsigned long pgtable_base, unsigned long fault_addr);
-
 static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
REG_PAGE_FAULT_ADDR,
REG_AR_FAULT_ADDR,
@@ -181,7 +171,6 @@ struct sysmmu_drvdata {
int activations;
rwlock_t lock;
struct iommu_domain *domain;
-   sysmmu_fault_handler_t fault_handler;
unsigned long pgtable;
void __iomem *sfrbases[0];
 };
@@ -313,34 +302,17 @@ finish:
read_unlock_irqrestore(data-lock, flags);
 }
 
-static void __set_fault_handler(struct sysmmu_drvdata *data,
-   sysmmu_fault_handler_t handler)
-{
-   unsigned long flags;
-
-   write_lock_irqsave(data-lock, flags);
-   data-fault_handler = handler;
-   write_unlock_irqrestore(data-lock, flags);
-}
-
-void exynos_sysmmu_set_fault_handler(struct device *dev,
-   sysmmu_fault_handler_t handler)
-{
-   struct sysmmu_drvdata *data = dev_get_drvdata(dev-archdata.iommu);
-
-   __set_fault_handler(data, handler);
-}
-
-static int default_fault_handler(enum exynos_sysmmu_inttype itype,
-unsigned long pgtable_base, unsigned long fault_addr)
+static void show_fault_information(const char *name,
+   enum exynos_sysmmu_inttype itype,
+   unsigned long pgtable_base, unsigned long fault_addr)
 {
unsigned long *ent;
 
if ((itype = SYSMMU_FAULTS_NUM) || (itype  SYSMMU_PAGEFAULT))
itype = SYSMMU_FAULT_UNKNOWN;
 
-   pr_err(%s occurred at 0x%lx(Page table base: 0x%lx)\n,
-   sysmmu_fault_name[itype], fault_addr, pgtable_base);
+   pr_err(%s occurred at 0x%lx by %s(Page table base: 0x%lx)\n,
+   sysmmu_fault_name[itype], fault_addr, name, pgtable_base);
 
ent = section_entry(__va(pgtable_base), fault_addr);
pr_err(\tLv1 entry: 0x%lx\n, *ent);
@@ -353,16 +325,12 @@ static int default_fault_handler(enum 
exynos_sysmmu_inttype itype,
pr_err(Generating Kernel OOPS... because it is unrecoverable.\n);
 
BUG();
-
-   return 0;
 }
 
 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 {
/* SYSMMU is in blocked when interrupt occurred. */
struct sysmmu_drvdata *data = dev_id;
-   struct resource *irqres;
-   struct platform_device *pdev;
enum exynos_sysmmu_inttype itype;
unsigned long addr = -1;
 
@@ -372,14 +340,15 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void 
*dev_id)
 
WARN_ON(!is_sysmmu_active(data));
 
-   pdev = to_platform_device(data-sysmmu);
-   for (i = 0; i  (pdev-num_resources / 2); i++) {
-   irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+   for (i = 0; i  data-nsfrs; i++) {
+   struct resource *irqres;
+   irqres = platform_get_resource(to_platform_device(data-sysmmu),
+   IORESOURCE_IRQ, i);
if (irqres  ((int)irqres-start == irq))
break;
}
 
-   if (i == pdev-num_resources) {
+   if (i == data-nsfrs) {
itype = SYSMMU_FAULT_UNKNOWN;
} else {
itype = (enum exynos_sysmmu_inttype)
@@ -395,19 +364,15 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void 
*dev_id)
ret = report_iommu_fault(data-domain, data-dev,
addr, itype);
 
-   if ((ret == -ENOSYS)  data-fault_handler) {
-   unsigned long base = data-pgtable;
-   if (itype != SYSMMU_FAULT_UNKNOWN)
-   base = __raw_readl(
-   data-sfrbases[i] + REG_PT_BASE_ADDR);
-   ret = data-fault_handler(itype, base, addr);
-   }
-
if (!ret  (itype != SYSMMU_FAULT_UNKNOWN))
__raw_writel(1  itype, data-sfrbases[i] + REG_INT_CLEAR);
-   else
-   dev_dbg(data-sysmmu, %s is not handled.\n,

[PATCH v8 08/12] iommu/exynos: remove prefetch buffer setting when enabling System MMU

2013-07-26 Thread Cho KyongHo

Prefetch buffer must be handled accurately, exact range of a buffer,
frame by frame manually. Otherwise, it may causes page fault or
deadlock in System MMU.
Thus this patch removes prefetch buffer setting when System MMU is
initialized(enabled).

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   32 +++-
 1 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index cfc02ed..87f6bb7 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -80,6 +80,8 @@
 #define CTRL_BLOCK 0x7
 #define CTRL_DISABLE   0x0
 
+#define CFG_FLPDCACHE  (1  20) /* System MMU 3.2+ only */
+
 #define REG_MMU_CTRL   0x000
 #define REG_MMU_CFG0x004
 #define REG_MMU_STATUS 0x008
@@ -96,6 +98,9 @@
 
 #define REG_MMU_VERSION0x034
 
+#define MMU_MAJ_VER(reg)   (reg  28)
+#define MMU_MIN_VER(reg)   ((reg  21)  0x7F)
+
 #define REG_PB0_SADDR  0x04C
 #define REG_PB0_EADDR  0x050
 #define REG_PB1_SADDR  0x054
@@ -200,6 +205,22 @@ static bool is_sysmmu_active(struct sysmmu_drvdata *data)
return data-activations  0;
 }
 
+static unsigned int __sysmmu_version(struct sysmmu_drvdata *data,
+int idx, unsigned int *minor)
+{
+   unsigned long major;
+
+   major = readl(data-sfrbases[idx] + REG_MMU_VERSION);
+
+   if (minor)
+   *minor = MMU_MIN_VER(major);
+
+   if (MMU_MAJ_VER(major)  3)
+   return 1;
+
+   return MMU_MAJ_VER(major);
+}
+
 static void sysmmu_unblock(void __iomem *sfrbase)
 {
__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
@@ -460,14 +481,15 @@ static int __exynos_sysmmu_enable(struct sysmmu_drvdata 
*data,
data-pgtable = pgtable;
 
for (i = 0; i  data-nsfrs; i++) {
+   unsigned int min;
+
__sysmmu_set_ptbase(data-sfrbases[i], pgtable);
 
-   if ((readl(data-sfrbases[i] + REG_MMU_VERSION)  28) == 3) {
-   /* System MMU version is 3.x */
-   __raw_writel((1  12) | (2  28),
+   if ((__sysmmu_version(data, i, min) == 3)  (min  1)) {
+   unsigned long cfg;
+   cfg = __raw_readl(data-sfrbases[i] + REG_MMU_CFG);
+   __raw_writel(cfg | CFG_FLPDCACHE,
data-sfrbases[i] + REG_MMU_CFG);
-   __sysmmu_set_prefbuf(data-sfrbases[i], 0, -1, 0);
-   __sysmmu_set_prefbuf(data-sfrbases[i], 0, -1, 1);
}
 
__raw_writel(CTRL_ENABLE, data-sfrbases[i] + REG_MMU_CTRL);
-- 
1.7.2.5


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[PATCH v8 07/12] iommu/exynos: support for device tree

2013-07-26 Thread Cho KyongHo

This commit adds device tree support for System MMU.
This also include the following changes and enhancements:

* use managed device helper functions.
Simplyfies System MMU device driver.

* use only a single clock descriptor.
System MMU device descriptor is seperate if it is imposible to make
a single clock descriptor to make a device descriptor for a group of
System MMUs.

* removed dbgname member from sysmmu_drvdata structure.
debugging kernel message for a System MMU is distinguisheable with the
name of device descroptors.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/Kconfig|5 +-
 drivers/iommu/exynos-iommu.c |  182 --
 2 files changed, 70 insertions(+), 117 deletions(-)

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index c332fb9..d45f3c9 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -168,16 +168,15 @@ config TEGRA_IOMMU_SMMU
 
 config EXYNOS_IOMMU
bool Exynos IOMMU Support
-   depends on ARCH_EXYNOS  EXYNOS_DEV_SYSMMU
+   depends on ARCH_EXYNOS
select IOMMU_API
+   default n
help
  Support for the IOMMU(System MMU) of Samsung Exynos application
  processor family. This enables H/W multimedia accellerators to see
  non-linear physical memory chunks as a linear memory in their
  address spaces
 
- If unsure, say N here.
-
 config EXYNOS_IOMMU_DEBUG
bool Debugging log for Exynos IOMMU
depends on EXYNOS_IOMMU
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 093eea5..cfc02ed 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -26,6 +26,7 @@
 #include linux/list.h
 #include linux/memblock.h
 #include linux/export.h
+#include linux/of.h
 
 #include asm/cacheflush.h
 #include asm/pgtable.h
@@ -170,15 +171,14 @@ struct sysmmu_drvdata {
struct list_head node; /* entry of exynos_iommu_domain.clients */
struct device *sysmmu;  /* System MMU's device descriptor */
struct device *dev; /* Owner of system MMU */
-   char *dbgname;
int nsfrs;
-   void __iomem **sfrbases;
-   struct clk *clk[2];
+   struct clk *clk;
int activations;
rwlock_t lock;
struct iommu_domain *domain;
sysmmu_fault_handler_t fault_handler;
unsigned long pgtable;
+   void __iomem *sfrbases[0];
 };
 
 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
@@ -385,8 +385,8 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
if (!ret  (itype != SYSMMU_FAULT_UNKNOWN))
__raw_writel(1  itype, data-sfrbases[i] + REG_INT_CLEAR);
else
-   dev_dbg(data-sysmmu, (%s) %s is not handled.\n,
-   data-dbgname, sysmmu_fault_name[itype]);
+   dev_dbg(data-sysmmu, %s is not handled.\n,
+   sysmmu_fault_name[itype]);
 
if (itype != SYSMMU_FAULT_UNKNOWN)
sysmmu_unblock(data-sfrbases[i]);
@@ -410,10 +410,8 @@ static bool __exynos_sysmmu_disable(struct sysmmu_drvdata 
*data)
for (i = 0; i  data-nsfrs; i++)
__raw_writel(CTRL_DISABLE, data-sfrbases[i] + REG_MMU_CTRL);
 
-   if (data-clk[1])
-   clk_disable(data-clk[1]);
-   if (data-clk[0])
-   clk_disable(data-clk[0]);
+   if (data-clk)
+   clk_disable(data-clk);
 
disabled = true;
data-pgtable = 0;
@@ -422,10 +420,10 @@ finish:
write_unlock_irqrestore(data-lock, flags);
 
if (disabled)
-   dev_dbg(data-sysmmu, (%s) Disabled\n, data-dbgname);
+   dev_dbg(data-sysmmu, Disabled\n);
else
-   dev_dbg(data-sysmmu, (%s) %d times left to be disabled\n,
-   data-dbgname, data-activations);
+   dev_dbg(data-sysmmu, %d times left to be disabled\n,
+   data-activations);
 
return disabled;
 }
@@ -452,14 +450,12 @@ static int __exynos_sysmmu_enable(struct sysmmu_drvdata 
*data,
ret = 1;
}
 
-   dev_dbg(data-sysmmu, (%s) Already enabled\n, data-dbgname);
+   dev_dbg(data-sysmmu, Already enabled\n);
goto finish;
}
 
-   if (data-clk[0])
-   clk_enable(data-clk[0]);
-   if (data-clk[1])
-   clk_enable(data-clk[1]);
+   if (data-clk)
+   clk_enable(data-clk);
 
data-pgtable = pgtable;
 
@@ -479,7 +475,7 @@ static int __exynos_sysmmu_enable(struct sysmmu_drvdata 
*data,
 
data-domain = domain;
 
-   dev_dbg(data-sysmmu, (%s) Enabled\n, data-dbgname);
+   dev_dbg(data-sysmmu, Enabled\n);
 finish:
write_unlock_irqrestore(data-lock, flags);
 
@@ -495,7 +491,7 @@ int exynos_sysmmu_enable(struct device *dev, unsigned long 
pgtable)

[PATCH v8 10/12] iommu/exynos: add bus notifier for registering System MMU

2013-07-26 Thread Cho KyongHo

When a device driver is registered, all constructs to handle System MMU
is prepared by bus notifier call.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |  708 -
 1 files changed, 552 insertions(+), 156 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index f9853fe..c62c244 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -27,6 +27,9 @@
 #include linux/memblock.h
 #include linux/export.h
 #include linux/of.h
+#include linux/of_platform.h
+#include linux/pm_domain.h
+#include linux/notifier.h
 
 #include asm/cacheflush.h
 #include asm/pgtable.h
@@ -80,7 +83,13 @@
 #define CTRL_BLOCK 0x7
 #define CTRL_DISABLE   0x0
 
+#define CFG_LRU0x1
+#define CFG_QOS(n) ((n  0xF)  7)
+#define CFG_MASK   0x0150 /* Selecting bit 0-15, 20, 22 and 24 */
+#define CFG_ACGEN  (1  24) /* System MMU 3.3 only */
+#define CFG_SYSSEL (1  22) /* System MMU 3.2 only */
 #define CFG_FLPDCACHE  (1  20) /* System MMU 3.2+ only */
+#define CFG_SHAREABLE  (1  12) /* System MMU 3.x only */
 
 #define REG_MMU_CTRL   0x000
 #define REG_MMU_CFG0x004
@@ -154,6 +163,14 @@ static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
UNKNOWN FAULT
 };
 
+struct exynos_iommu_client {
+   struct list_head node;  /* entry of exynos_iommu_domain.clients */
+   struct device *dev;
+   spinlock_t lock;
+   int num_sysmmu;
+   struct device *sysmmu[0];
+};
+
 struct exynos_iommu_domain {
struct list_head clients; /* list of sysmmu_drvdata.node */
unsigned long *pgtable; /* lv1 page table, 16KB */
@@ -165,12 +182,14 @@ struct exynos_iommu_domain {
 struct sysmmu_drvdata {
struct list_head node; /* entry of exynos_iommu_domain.clients */
struct device *sysmmu;  /* System MMU's device descriptor */
-   struct device *dev; /* Owner of system MMU */
+   struct device *master;  /* Owner of system MMU */
int nsfrs;
struct clk *clk;
+   struct clk *clk_master;
int activations;
rwlock_t lock;
struct iommu_domain *domain;
+   bool runtime_active;
unsigned long pgtable;
void __iomem *sfrbases[0];
 };
@@ -245,7 +264,6 @@ static void __sysmmu_tlb_invalidate_entry(void __iomem 
*sfrbase,
 static void __sysmmu_set_ptbase(void __iomem *sfrbase,
   unsigned long pgd)
 {
-   __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
 
__sysmmu_tlb_invalidate(sfrbase);
@@ -273,6 +291,7 @@ void exynos_sysmmu_set_prefbuf(struct device *dev,
if (!is_sysmmu_active(data))
goto finish;
 
+   clk_enable(data-clk_master);
for (i = 0; i  data-nsfrs; i++) {
if ((readl(data-sfrbases[i] + REG_MMU_VERSION)  28) == 3) {
if (!sysmmu_block(data-sfrbases[i]))
@@ -298,6 +317,7 @@ void exynos_sysmmu_set_prefbuf(struct device *dev,
sysmmu_unblock(data-sfrbases[i]);
}
}
+   clk_disable(data-clk_master);
 finish:
read_unlock_irqrestore(data-lock, flags);
 }
@@ -331,12 +351,13 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void 
*dev_id)
 {
/* SYSMMU is in blocked when interrupt occurred. */
struct sysmmu_drvdata *data = dev_id;
+   struct exynos_iommu_client *client = NULL;
enum exynos_sysmmu_inttype itype;
unsigned long addr = -1;
-
int i, ret = -ENOSYS;
 
-   read_lock(data-lock);
+   if (data-master)
+   client = data-master-archdata.iommu;
 
WARN_ON(!is_sysmmu_active(data));
 
@@ -348,6 +369,10 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
break;
}
 
+   if (client)
+   spin_lock(client-lock);
+   read_lock(data-lock);
+
if (i == data-nsfrs) {
itype = SYSMMU_FAULT_UNKNOWN;
} else {
@@ -361,7 +386,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
}
 
if (data-domain)
-   ret = report_iommu_fault(data-domain, data-dev,
+   ret = report_iommu_fault(data-domain, data-master,
addr, itype);
 
if (!ret  (itype != SYSMMU_FAULT_UNKNOWN))
@@ -378,177 +403,251 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void 
*dev_id)
sysmmu_unblock(data-sfrbases[i]);
 
read_unlock(data-lock);
+   if (client)
+   spin_unlock(client-lock);
 
return IRQ_HANDLED;
 }
 
-static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
+static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 {
-   unsigned long flags;
-   bool disabled = false;
int i;
 
-   write_lock_irqsave(data-lock, flags);
+

[PATCH v8 11/12] iommu/exynos: change rwlock to spinlock

2013-07-26 Thread Cho KyongHo

Since acquiring read_lock is not more frequent than write_lock, it is
not beneficial to use rwlock, this commit changes rwlock to spinlock.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   36 ++--
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index c62c244..51e5b35 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -187,7 +187,7 @@ struct sysmmu_drvdata {
struct clk *clk;
struct clk *clk_master;
int activations;
-   rwlock_t lock;
+   spinlock_t lock;
struct iommu_domain *domain;
bool runtime_active;
unsigned long pgtable;
@@ -287,7 +287,7 @@ void exynos_sysmmu_set_prefbuf(struct device *dev,
BUG_ON((base0 + size0) = base0);
BUG_ON((size1  0)  ((base1 + size1) = base1));
 
-   read_lock_irqsave(data-lock, flags);
+   spin_lock_irqsave(data-lock, flags);
if (!is_sysmmu_active(data))
goto finish;
 
@@ -319,7 +319,7 @@ void exynos_sysmmu_set_prefbuf(struct device *dev,
}
clk_disable(data-clk_master);
 finish:
-   read_unlock_irqrestore(data-lock, flags);
+   spin_unlock_irqrestore(data-lock, flags);
 }
 
 static void show_fault_information(const char *name,
@@ -371,7 +371,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 
if (client)
spin_lock(client-lock);
-   read_lock(data-lock);
+   spin_lock(data-lock);
 
if (i == data-nsfrs) {
itype = SYSMMU_FAULT_UNKNOWN;
@@ -402,7 +402,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
if (itype != SYSMMU_FAULT_UNKNOWN)
sysmmu_unblock(data-sfrbases[i]);
 
-   read_unlock(data-lock);
+   spin_unlock(data-lock);
if (client)
spin_unlock(client-lock);
 
@@ -429,7 +429,7 @@ static bool __sysmmu_disable(struct sysmmu_drvdata *data)
bool disabled;
unsigned long flags;
 
-   write_lock_irqsave(data-lock, flags);
+   spin_lock_irqsave(data-lock, flags);
 
disabled = set_sysmmu_inactive(data);
 
@@ -446,7 +446,7 @@ static bool __sysmmu_disable(struct sysmmu_drvdata *data)
data-activations);
}
 
-   write_unlock_irqrestore(data-lock, flags);
+   spin_unlock_irqrestore(data-lock, flags);
 
return disabled;
 }
@@ -493,7 +493,7 @@ static int __sysmmu_enable(struct sysmmu_drvdata *data,
int ret = 0;
unsigned long flags;
 
-   write_lock_irqsave(data-lock, flags);
+   spin_lock_irqsave(data-lock, flags);
if (set_sysmmu_active(data)) {
data-pgtable = pgtable;
data-domain = domain;
@@ -511,7 +511,7 @@ static int __sysmmu_enable(struct sysmmu_drvdata *data,
if (WARN_ON(ret  0))
set_sysmmu_inactive(data); /* decrement count */
 
-   write_unlock_irqrestore(data-lock, flags);
+   spin_unlock_irqrestore(data-lock, flags);
 
return ret;
 }
@@ -602,7 +602,7 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, 
unsigned long iova)
 
data = dev_get_drvdata(client-sysmmu[i]);
 
-   read_lock_irqsave(data-lock, flags);
+   spin_lock_irqsave(data-lock, flags);
if (is_sysmmu_active(data)  data-runtime_active) {
int i;
clk_enable(data-clk_master);
@@ -615,7 +615,7 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, 
unsigned long iova)
disabled. Skipping TLB invalidation @ %#lx\n,
iova);
}
-   read_unlock_irqrestore(data-lock, flags);
+   spin_unlock_irqrestore(data-lock, flags);
}
 }
 
@@ -630,7 +630,7 @@ void exynos_sysmmu_tlb_invalidate(struct device *dev)
 
data = dev_get_drvdata(client-sysmmu[i]);
 
-   read_lock_irqsave(data-lock, flags);
+   spin_lock_irqsave(data-lock, flags);
if (is_sysmmu_active(data) 
data-runtime_active) {
int i;
@@ -646,7 +646,7 @@ void exynos_sysmmu_tlb_invalidate(struct device *dev)
} else {
dev_dbg(dev, disabled. Skipping TLB invalidation\n);
}
-   read_unlock_irqrestore(data-lock, flags);
+   spin_unlock_irqrestore(data-lock, flags);
}
 }
 
@@ -735,7 +735,7 @@ static int __init exynos_sysmmu_probe(struct 
platform_device *pdev)
 
data-runtime_active = !pm_runtime_enabled(dev);
 
-   rwlock_init(data-lock);
+   spin_lock_init(data-lock);
INIT_LIST_HEAD(data-node);
 
platform_set_drvdata(pdev, data);
@@ -749,11 +749,11 @@ static int sysmmu_suspend(struct device *dev)

[PATCH v8 12/12] iommu/exynos: return 0 if iommu_attach_device() successes

2013-07-26 Thread Cho KyongHo

iommu_attach_device() against exynos-iommu positive integer on success
if the caller calls iommu_attach_device() with the same iommu_domain
multiple times without call to iommu_detach_device() to inform the
caller how many calls to iommu_detach_device() to really detach iommu.

However the convention of the return value of success of common API is
zero, this patch makes iommu_attach_device() call against exynos-iommu
always return zero if the given device is successfully attached to
the given iommu_domain even though it is already attached to the same
iommu_domain.

Signed-off-by: Cho KyongHo pullip@samsung.com
---
 drivers/iommu/exynos-iommu.c |   13 +++--
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 51e5b35..6eed6d6 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -882,15 +882,16 @@ static int exynos_iommu_attach_device(struct iommu_domain 
*domain,
 
spin_unlock_irqrestore(priv-lock, flags);
 
-   if (ret  0)
+   if (ret  0) {
dev_err(dev, %s: Failed to attach IOMMU with pgtable %#lx\n,
__func__, __pa(priv-pgtable));
-   else
-   dev_dbg(dev, %s: Attached IOMMU with pgtable 0x%lx%s\n,
-   __func__, __pa(priv-pgtable),
-   (ret == 0) ?  : , again);
+   return ret;
+   }
 
-   return ret;
+   dev_dbg(dev, %s: Attached IOMMU with pgtable 0x%lx%s\n,
+   __func__, __pa(priv-pgtable), (ret == 0) ?  : , again);
+
+   return 0;
 }
 
 static void exynos_iommu_detach_device(struct iommu_domain *domain,
-- 
1.7.2.5


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Re: XCLKOUT in exynos5250 clock driver

2013-07-26 Thread Sylwester Nawrocki

On 07/26/2013 11:56 AM, Tushar Behera wrote:

On 07/25/2013 08:21 PM, Mark Brown wrote:

I appear to be missing something in the clock driver for the exynos5250.
I'm looking at the Arndale schematic and I see that the audio master
clock is connected to XCLKOUT on the SoC. However I can't see any
reference to XCLKOUT or anything similar in the clock driver or any of
the DTS files - where is this clock exposed by the clock driver?

This is something that's not yet supported in the mainline kernels I'm
afraid.

Unfortunately I haven't been able to get access to the datasheet for the
part so I can't check this myself.

Information as per Exynos5250 user manual:
XCLKOUT is an output pin for debugging clocks. Exynos5250 has a CLKOUT
logic which can select one of the clocks (within its clock domains) and
output that through XCLKOUT pin.

Not sure if XCLKOUT on Arndale schematics means the same.

I suspect that the same, you can easily verify that by checking what ball
identifier corresponds to XCLKOUT pin and how the routing looks like on
the schematics.

We have a bit hackish patch that adds support for the CLKOUT at the
Exynos4 clocks driver to enable the audio codec. An issue here is that the
CLKOUT mux and divider control bitfield is in the PMU registers (as opposed
to CMU where the clock control registers normally are) and additionally
single register contains the clock mux/divider bitfield as well as couple
other unrelated control bits. Depending if those other bits are considered
really important or not it it might another reason to expose (part of ?)
PMU registers through syscon-like interface. There are registers in PMU
that multiple drivers would be interested in, so instead of all of them to
independently memory map and mess with single registers, probably a regmap
interface could be used. Not sure if this solves the problem well, since
each driver would need to have coded SoC specific register offsets.

It can be seen in the Galaxy S3 kernel code how the Exynos5 CLKOUT handling
might look like. See enum xclkout_select [1], exynos5_pmu_xclkout_set [2].
It would be good someone who has access to the datasheet come up with at
with some patch so the audio works are not blocked. I'm not working right
now on Exynos5 :P.

[1]
thttps://github.com/sgs3/GT-I9300_Kernel/blob/master/arch/arm/mach-exynos/include/mach/pmu.h
[2]
https://github.com/sgs3/GT-I9300_Kernel/blob/master/arch/arm/mach-exynos/pmu-exynos5.c

--
Thanks,
Sylwester
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