Re: [PATCH V3] watchdog: s3c2410_wdt: remove the global variables
Hello Kukjin Kim,
As Wim Van Sebroeck is not responding, is it possible for you to merge
this patch into your tree?
Best Wishes,
Leela Krishna.
On Tue, Jul 30, 2013 at 11:35 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Hello Wim Van Sebroeck,
Can you please review this patch and take necessary action.
Best Wishes,
Leela Krishna Amudala.
On Wed, Jul 24, 2013 at 1:23 PM, Kukjin Kim kg...@kernel.org wrote:
Leela Krishna Amudala wrote:
This patch removes the global variables in the driver file and
group them into a structure.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
(+ Wim Van Sebroeck)
Looks good to me,
Acked-by: Kukjin Kim kgene@samsung.com
Thanks,
Kukjin
---
Note: This patch is rebased on kgene's for-next branch and tested on
SMDK5420.
Changes since V2:
- Addressed comments given by Tomasz Figa t.f...@samsung.com
https://patchwork.kernel.org/patch/2831032/
- Renamed structure name from s3c2410_watchdog to s3c2410_wdt.
Changes since V1:
- changed the patch subject.
- indentation correction in s3c2410_watchdog structure.
drivers/watchdog/s3c2410_wdt.c | 225 +++
-
1 file changed, 131 insertions(+), 94 deletions(-)
diff --git a/drivers/watchdog/s3c2410_wdt.c
b/drivers/watchdog/s3c2410_wdt.c
index 6a22cf5..739dbd3 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -84,13 +84,17 @@ MODULE_PARM_DESC(soft_noboot, Watchdog action, set to
1 to ignore reboots,
0 to reboot (default 0));
MODULE_PARM_DESC(debug, Watchdog debug, set to 1 for debug (default
0));
-static struct device*wdt_dev;/* platform device attached to */
-static struct resource *wdt_mem;
-static struct resource *wdt_irq;
-static struct clk*wdt_clock;
-static void __iomem *wdt_base;
-static unsigned int wdt_count;
-static DEFINE_SPINLOCK(wdt_lock);
+struct s3c2410_wdt {
+ struct device *dev;
+ struct clk *clock;
+ void __iomem*reg_base;
+ unsigned intcount;
+ spinlock_t lock;
+ unsigned long wtcon_save;
+ unsigned long wtdat_save;
+ struct watchdog_device wdt_device;
+ struct notifier_block freq_transition;
+};
/* watchdog control routines */
@@ -102,29 +106,43 @@ do {
\
/* functions */
+static inline struct s3c2410_wdt *to_s3c2410_wdt(struct watchdog_device
*wdd)
+{
+ return container_of(wdd, struct s3c2410_wdt, wdt_device);
+}
+
+static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
+{
+ return container_of(nb, struct s3c2410_wdt, freq_transition);
+}
+
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
- spin_lock(wdt_lock);
- writel(wdt_count, wdt_base + S3C2410_WTCNT);
- spin_unlock(wdt_lock);
+ struct s3c2410_wdt *wdt = to_s3c2410_wdt(wdd);
+
+ spin_lock(wdt-lock);
+ writel(wdt-count, wdt-reg_base + S3C2410_WTCNT);
+ spin_unlock(wdt-lock);
return 0;
}
-static void __s3c2410wdt_stop(void)
+static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
{
unsigned long wtcon;
- wtcon = readl(wdt_base + S3C2410_WTCON);
+ wtcon = readl(wdt-reg_base + S3C2410_WTCON);
wtcon = ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
- writel(wtcon, wdt_base + S3C2410_WTCON);
+ writel(wtcon, wdt-reg_base + S3C2410_WTCON);
}
static int s3c2410wdt_stop(struct watchdog_device *wdd)
{
- spin_lock(wdt_lock);
- __s3c2410wdt_stop();
- spin_unlock(wdt_lock);
+ struct s3c2410_wdt *wdt = to_s3c2410_wdt(wdd);
+
+ spin_lock(wdt-lock);
+ __s3c2410wdt_stop(wdt);
+ spin_unlock(wdt-lock);
return 0;
}
@@ -132,12 +150,13 @@ static int s3c2410wdt_stop(struct watchdog_device
*wdd)
static int s3c2410wdt_start(struct watchdog_device *wdd)
{
unsigned long wtcon;
+ struct s3c2410_wdt *wdt = to_s3c2410_wdt(wdd);
- spin_lock(wdt_lock);
+ spin_lock(wdt-lock);
- __s3c2410wdt_stop();
+ __s3c2410wdt_stop(wdt);
- wtcon = readl(wdt_base + S3C2410_WTCON);
+ wtcon = readl(wdt-reg_base + S3C2410_WTCON);
wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
if (soft_noboot) {
@@ -148,25 +167,26 @@ static int s3c2410wdt_start(struct watchdog_device
*wdd)
wtcon |= S3C2410_WTCON_RSTEN;
}
- DBG(%s: wdt_count=0x%08x, wtcon=%08lx\n,
- __func__, wdt_count, wtcon);
+ DBG(%s: count=0x%08x, wtcon=%08lx\n,
+ __func__, wdt-count, wtcon);
- writel(wdt_count, wdt_base + S3C2410_WTDAT);
- writel(wdt_count, wdt_base + S3C2410_WTCNT);
- writel(wtcon, wdt_base +
Re: [PATCH] ARM: DT: Exynos: fix number of interrupt-cells in mct node
ping
On 23 July 2013 15:17, Chander Kashyap chander.kash...@linaro.org wrote:
ping.
On 14 June 2013 20:11, Chander Kashyap chander.kash...@linaro.org wrote:
Two cells were used to specify interrupts in mct node, while second cell
always remains unused. Hence use only one cell.
Suggested by Tomasz Figa.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
arch/arm/boot/dts/exynos4210.dtsi | 19 +--
arch/arm/boot/dts/exynos4212.dtsi | 19 +--
arch/arm/boot/dts/exynos4412.dtsi | 23 +++
arch/arm/boot/dts/exynos5250.dtsi | 19 +--
4 files changed, 38 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de..ad50010 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -52,23 +52,22 @@
compatible = samsung,exynos4210-mct;
reg = 0x1005 0x800;
interrupt-controller;
- #interrups-cells = 2;
+ #interrups-cells = 1;
interrupt-parent = mct_map;
- interrupts = 0 0, 1 0, 2 0, 3 0,
-4 0, 5 0;
+ interrupts = 0, 1, 2, 3, 4, 5;
clocks = clock 3, clock 344;
clock-names = fin_pll, mct;
mct_map: mct-map {
- #interrupt-cells = 2;
+ #interrupt-cells = 1;
#address-cells = 0;
#size-cells = 0;
- interrupt-map = 0x0 0 gic 0 57 0,
- 0x1 0 gic 0 69 0,
- 0x2 0 combiner 12 6,
- 0x3 0 combiner 12 7,
- 0x4 0 gic 0 42 0,
- 0x5 0 gic 0 48 0;
+ interrupt-map = 0 gic 0 57 0,
+ 1 gic 0 69 0,
+ 2 combiner 12 6,
+ 3 combiner 12 7,
+ 4 gic 0 42 0,
+ 5 gic 0 48 0;
};
};
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..ba9ada1 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -39,21 +39,20 @@
compatible = samsung,exynos4412-mct;
reg = 0x1005 0x800;
interrupt-controller;
- #interrups-cells = 2;
+ #interrups-cells = 1;
interrupt-parent = mct_map;
- interrupts = 0 0, 1 0, 2 0, 3 0,
-4 0, 5 0;
+ interrupts = 0, 1, 2, 3, 4, 5;
mct_map: mct-map {
- #interrupt-cells = 2;
+ #interrupt-cells = ;
#address-cells = 0;
#size-cells = 0;
- interrupt-map = 0x0 0 gic 0 57 0,
- 0x1 0 combiner 12 5,
- 0x2 0 combiner 12 6,
- 0x3 0 combiner 12 7,
- 0x4 0 gic 1 12 0,
- 0x5 0 gic 1 12 0;
+ interrupt-map = 0 gic 0 57 0,
+ 1 combiner 12 5,
+ 2 combiner 12 6,
+ 3 combiner 12 7,
+ 4 gic 1 12 0,
+ 5 gic 1 12 0;
};
};
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389..a680de7 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -39,25 +39,24 @@
compatible = samsung,exynos4412-mct;
reg = 0x1005 0x800;
interrupt-controller;
- #interrups-cells = 2;
+ #interrups-cells = 1;
interrupt-parent = mct_map;
- interrupts = 0 0, 1 0, 2 0, 3 0,
-4 0, 5 0, 6 0, 7 0;
+ interrupts = 0, 1, 2, 3, 4, 5, 6, 7;
clocks = clock 3, clock 344;
clock-names = fin_pll, mct;
mct_map: mct-map {
- #interrupt-cells = 2;
+ #interrupt-cells = 1;
#address-cells = 0;
#size-cells = 0;
- interrupt-map = 0x0 0 gic 0 57 0,
- 0x1 0 combiner 12 5,
-
Re: [PATCH v2 1/7] ARM: dts: Move display-timimg information inside FIMD DT node for exynos5250
Hi Kukjin,
On Mon, Aug 5, 2013 at 3:59 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
On 5 August 2013 15:34, Vikas Sajjan sajjan.li...@gmail.com wrote:
Hi All,
On Thu, Aug 1, 2013 at 8:19 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Vikas,
On Tuesday 30 of July 2013 16:49:32 Vikas Sajjan wrote:
As the display-timing information is parsed by FIMD driver, it makes
sense to move the display-timimg DT node inside FIMD DT node for
exynos5250
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 29
- 1 file changed, 16 insertions(+), 13
deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c2..d176dbb
100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -262,19 +262,22 @@
pinctrl-0 = dp_hpd;
};
- display-timings {
- native-mode = timing0;
- timing0: timing@0 {
- /* 1280x800 */
- clock-frequency = 5;
- hactive = 1280;
- vactive = 800;
- hfront-porch = 4;
- hback-porch = 4;
- hsync-len = 4;
- vback-porch = 4;
- vfront-porch = 4;
- vsync-len = 4;
+ fimd@1440 {
+ status = okay;
+ display-timings {
+ native-mode = timing0;
+ timing0: timing@0 {
+ /* 1280x800 */
+ clock-frequency = 5;
+ hactive = 1280;
+ vactive = 800;
+ hfront-porch = 4;
+ hback-porch = 4;
+ hsync-len = 4;
+ vback-porch = 4;
+ vfront-porch = 4;
+ vsync-len = 4;
+ };
};
};
Looks good to me, but I would like some other people from the device tree
mailing list to comment on node naming: Do we want to conform to the
recommendation of ePAPR about node naming, which states that node names
should be generic, not platform specific or we are free to ignore it?
Any more comments on this series.
One trivial typo in patch subject and commit message:
s/timimg/timing
Can you apply this series (by correcting typo s/timimg/timing) OR you
want me to respin V3 with this typo correction.
--
With warm regards,
Sachin
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RE: [PATCH v5 2/4] mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
Doug,
Looks good to me except for minor comment.
On Sat, August 10, 2013, Doug Anderson wrote:
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v5:
- Cleaned up dw_mci_exynos_resume_noirq() comment as per Seungwon.
- Don't memcpy dev_pm_ops structure, define a new one.
Changes in v4:
- Take Seungwon's suggestion and don't add any dw_mmc-pltfm code.
Changes in v3:
- Add freeze/thaw and poweroff/restore noirq entries.
Changes in v2:
- Use suspend_noirq as per James Hogan.
drivers/mmc/host/dw_mmc-exynos.c | 56
+++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c
b/drivers/mmc/host/dw_mmc-exynos.c
index 866edef..7d88583 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -30,6 +30,7 @@
#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
SDMMC_CLKSEL_CCLK_DRIVE(y) |\
SDMMC_CLKSEL_CCLK_DIVIDER(z))
+#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
@@ -100,6 +101,52 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+/*
+ * TODO: we should probably disable the clock to the card in the suspend
path.
In suspend, clock is gated, isn't it?
Rather, no comment looks better, if intention is not clear.
Thanks,
Seungwon Jeon
+ */
+static int dw_mci_exynos_suspend(struct device *dev)
+{
+ struct dw_mci *host = dev_get_drvdata(dev);
+
+ return dw_mci_suspend(host);
+}
+
+static int dw_mci_exynos_resume(struct device *dev)
+{
+ struct dw_mci *host = dev_get_drvdata(dev);
+
+ return dw_mci_resume(host);
+}
+
+/**
+ * dw_mci_exynos_resume_noirq - Exynos-specific resume code
+ *
+ * On exynos5420 there is a silicon errata that will sometimes leave the
+ * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
+ * that it fired and we can clear it by writing a 1 back. Clear it to
prevent
+ * interrupts from going off constantly.
+ *
+ * We run this code on all exynos variants because it doesn't hurt.
+ */
+
+static int dw_mci_exynos_resume_noirq(struct device *dev)
+{
+ struct dw_mci *host = dev_get_drvdata(dev);
+ u32 clksel;
+
+ clksel = mci_readl(host, CLKSEL);
+ if (clksel SDMMC_CLKSEL_WAKEUP_INT)
+ mci_writel(host, CLKSEL, clksel);
+
+ return 0;
+}
+#else
+#define dw_mci_exynos_suspendNULL
+#define dw_mci_exynos_resume NULL
+#define dw_mci_exynos_resume_noirq NULL
+#endif /* CONFIG_PM_SLEEP */
+
static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
{
/*
@@ -187,13 +234,20 @@ static int dw_mci_exynos_probe(struct platform_device
*pdev)
return dw_mci_pltfm_register(pdev, drv_data);
}
+const struct dev_pm_ops dw_mci_exynos_pmops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
+ .resume_noirq = dw_mci_exynos_resume_noirq,
+ .thaw_noirq = dw_mci_exynos_resume_noirq,
+ .restore_noirq = dw_mci_exynos_resume_noirq,
+};
+
static struct platform_driver dw_mci_exynos_pltfm_driver = {
.probe = dw_mci_exynos_probe,
.remove = __exit_p(dw_mci_pltfm_remove),
.driver = {
.name = dwmmc_exynos,
.of_match_table = dw_mci_exynos_match,
- .pm = dw_mci_pltfm_pmops,
+ .pm = dw_mci_exynos_pmops,
},
};
--
1.8.3
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[PATCH] ARM: dts: Add RTC DT node to Exynos5420 SoC
Adds RTC DT node to Exynos5420 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos5.dtsi|2 +-
arch/arm/boot/dts/exynos5250.dtsi |2 +-
arch/arm/boot/dts/exynos5420.dtsi |6 ++
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..4a8e223 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
interrupts = 0 54 0;
};
- rtc {
+ rtc@101E {
compatible = samsung,s3c6410-rtc;
reg = 0x101E 0x100;
interrupts = 0 43 0, 0 44 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..f426ce6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -178,7 +178,7 @@
samsung,power-domain = pd_mfc;
};
- rtc {
+ rtc@101E {
clocks = clock 337;
clock-names = rtc;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..b48d62c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -145,4 +145,10 @@
clocks = clock 260, clock 131;
clock-names = uart, clk_uart_baud0;
};
+
+ rtc@101E {
+ clocks = clock 317;
+ clock-names = rtc;
+ };
+
};
--
1.7.9.5
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Re: [PATCH] ARM: dts: Add RTC DT node to Exynos5420 SoC
Hi Vikas,
On 12 August 2013 13:07, Vikas Sajjan vikas.saj...@linaro.org wrote:
Adds RTC DT node to Exynos5420 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
arch/arm/boot/dts/exynos5.dtsi|2 +-
arch/arm/boot/dts/exynos5250.dtsi |2 +-
arch/arm/boot/dts/exynos5420.dtsi |6 ++
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..4a8e223 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
interrupts = 0 54 0;
};
- rtc {
+ rtc@101E {
compatible = samsung,s3c6410-rtc;
reg = 0x101E 0x100;
interrupts = 0 43 0, 0 44 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..f426ce6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -178,7 +178,7 @@
samsung,power-domain = pd_mfc;
};
- rtc {
+ rtc@101E {
clocks = clock 337;
clock-names = rtc;
};
Since with this binding the h/w is depicted completely (for
functioning), IMO you should change the status to okay here.
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..b48d62c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -145,4 +145,10 @@
clocks = clock 260, clock 131;
clock-names = uart, clk_uart_baud0;
};
+
+ rtc@101E {
+ clocks = clock 317;
+ clock-names = rtc;
+ };
+
ditto.
--
With warm regards,
Sachin
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[PATCH] PCI: exynos: add support for MSI
This patch adds support for Message Signaled Interrupt in the
Exynops PCIe diver using Synopsys designware PCIe core IP.
Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
Signed-off-by: Srikanth T Shivanand ts.srika...@samsung.com
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Pratyush Anand pratyush.an...@st.com
Cc: Mohit KUMAR mohit.ku...@st.com
---
arch/arm/boot/dts/exynos5440.dtsi |2 +
arch/arm/mach-exynos/Kconfig |1 +
drivers/pci/host/pci-exynos.c | 60 ++
drivers/pci/host/pcie-designware.c | 213
drivers/pci/host/pcie-designware.h |8 ++
5 files changed, 284 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 586134e..3746835 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -249,6 +249,7 @@
interrupt-map-mask = 0 0 0 0;
interrupt-map = 0x0 0 gic 53;
num-lanes = 4;
+ msi-base = 200;
};
pcie@2a {
@@ -269,5 +270,6 @@
interrupt-map-mask = 0 0 0 0;
interrupt-map = 0x0 0 gic 56;
num-lanes = 4;
+ msi-base = 232;
};
};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 855d4a7..9ef1c95 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,7 @@ config SOC_EXYNOS5440
default y
depends on ARCH_EXYNOS5
select ARCH_HAS_OPP
+ select ARCH_SUPPORTS_MSI
select HAVE_ARM_ARCH_TIMER
select AUTO_ZRELADDR
select MIGHT_HAVE_PCI
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 012ca8a..d0477d0 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -48,6 +48,7 @@ struct exynos_pcie {
#define PCIE_IRQ_SPECIAL 0x008
#define PCIE_IRQ_EN_PULSE 0x00c
#define PCIE_IRQ_EN_LEVEL 0x010
+#define IRQ_MSI_ENABLE (0x1 2)
#define PCIE_IRQ_EN_SPECIAL0x014
#define PCIE_PWR_RESET 0x018
#define PCIE_CORE_RESET0x01c
@@ -320,9 +321,51 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void
*arg)
return IRQ_HANDLED;
}
+#ifdef CONFIG_PCI_MSI
+static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ val = readl(elbi_base + PCIE_IRQ_LEVEL);
+ writel(val, elbi_base + PCIE_IRQ_LEVEL);
+ return;
+}
+
+static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ /* handle msi irq */
+ dw_handle_msi_irq(pp);
+ exynos_pcie_clear_irq_level(pp);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_pcie_msi_init(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ dw_pcie_msi_init(pp);
+
+ /* enable MSI interrupt */
+ val = readl(elbi_base + PCIE_IRQ_EN_LEVEL);
+ val |= IRQ_MSI_ENABLE;
+ writel(val, elbi_base + PCIE_IRQ_EN_LEVEL);
+ return;
+}
+#endif
+
static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
{
exynos_pcie_enable_irq_pulse(pp);
+#ifdef CONFIG_PCI_MSI
+ exynos_pcie_msi_init(pp);
+#endif
return;
}
@@ -408,6 +451,23 @@ static int add_pcie_port(struct pcie_port *pp, struct
platform_device *pdev)
return ret;
}
+#ifdef CONFIG_PCI_MSI
+ pp-msi_irq = platform_get_irq(pdev, 0);
+
+ if (!pp-msi_irq) {
+ dev_err(pdev-dev, failed to get msi irq\n);
+ return -ENODEV;
+ }
+
+ ret = devm_request_irq(pdev-dev, pp-msi_irq,
+ exynos_pcie_msi_irq_handler,
+ IRQF_SHARED, exynos-pcie, pp);
+ if (ret) {
+ dev_err(pdev-dev, failed to request msi irq\n);
+ return ret;
+ }
+#endif
+
pp-root_bus_nr = -1;
pp-ops = exynos_pcie_host_ops;
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 77b0c25..5a47f11 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -11,8 +11,10 @@
* published by the Free Software Foundation.
*/
+#include linux/irq.h
#include linux/kernel.h
#include linux/module.h
+#include linux/msi.h
#include linux/of_address.h
#include linux/pci.h
#include linux/pci_regs.h
@@ -62,6 +64,14 @@
#define PCIE_ATU_FUNC(x) (((x) 0x7) 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#ifdef CONFIG_PCI_MSI
+#define MAX_MSI_IRQS 32
+#define MAX_MSI_CTRLS 8
+
+static unsigned int msi_data;
Re: [PATCH] PCI: exynos: add support for MSI
Hi Jingoo,
On 12 August 2013 14:26, Jingoo Han jg1@samsung.com wrote:
This patch adds support for Message Signaled Interrupt in the
Exynops PCIe diver using Synopsys designware PCIe core IP.
s/Exynops PCIe diver/Exynos PCIe driver
Signed-off-by: Siva Reddy Kallam siva.kal...@samsung.com
Signed-off-by: Srikanth T Shivanand ts.srika...@samsung.com
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Pratyush Anand pratyush.an...@st.com
Cc: Mohit KUMAR mohit.ku...@st.com
---
arch/arm/boot/dts/exynos5440.dtsi |2 +
arch/arm/mach-exynos/Kconfig |1 +
drivers/pci/host/pci-exynos.c | 60 ++
drivers/pci/host/pcie-designware.c | 213
drivers/pci/host/pcie-designware.h |8 ++
5 files changed, 284 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 586134e..3746835 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -249,6 +249,7 @@
interrupt-map-mask = 0 0 0 0;
interrupt-map = 0x0 0 gic 53;
num-lanes = 4;
+ msi-base = 200;
Please update the bindings documentation too.
};
pcie@2a {
@@ -269,5 +270,6 @@
[snip]
+#ifdef CONFIG_PCI_MSI
+static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ val = readl(elbi_base + PCIE_IRQ_LEVEL);
+ writel(val, elbi_base + PCIE_IRQ_LEVEL);
Sorry, I did not get this. Writing the value read from the same
register without any operation.
--
With warm regards,
Sachin
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[PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
Samsung has different versions of I2S introduced in different
platforms. Each version has some new support added for multichannel,
secondary fifo, s/w reset control and internal mux for rclk src clk.
Each newly added change has a quirk. So this patch adds all the
required quirks as driver data and based on compatible string from
dtsi fetches the quirks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 18 ++
sound/soc/samsung/i2s.c| 62 +++
2 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 025e66b..25a0024 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -2,7 +2,11 @@
Required SoC Specific Properties:
-- compatible : samsung,i2s-v5
+- compatible : should be one of the following.
+ - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
+ - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
+ secondary fifo, s/w reset control and internal mux for root clk src.
+
- reg: physical base address of the controller and length of memory mapped
region.
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
@@ -21,13 +25,6 @@ Required SoC Specific Properties:
Optional SoC Specific Properties:
-- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
- support, this flag is enabled.
-- samsung,supports-rstclr: This flag should be set if I2S software reset bit
- control is required. When this flag is set I2S software reset bit will be
- enabled or disabled based on need.
-- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
- then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
@@ -36,7 +33,7 @@ Optional SoC Specific Properties:
Example:
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -46,9 +43,6 @@ i2s0: i2s@0383 {
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 47e08dd..1671d9b 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -40,6 +40,7 @@ enum samsung_dai_type {
struct samsung_i2s_dai_data {
int dai_type;
+ u32 quirks;
};
struct i2s_dai {
@@ -1032,18 +1033,18 @@ static struct i2s_dai *i2s_alloc_dai(struct
platform_device *pdev, bool sec)
static const struct of_device_id exynos_i2s_match[];
-static inline int samsung_i2s_get_driver_data(struct platform_device *pdev)
+static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data(
+ struct platform_device *pdev)
{
#ifdef CONFIG_OF
- struct samsung_i2s_dai_data *data;
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
- data = (struct samsung_i2s_dai_data *) match-data;
- return data-dai_type;
+ return match-data;
} else
#endif
- return platform_get_device_id(pdev)-driver_data;
+ return (struct samsung_i2s_dai_data *)
+ platform_get_device_id(pdev)-driver_data;
}
#ifdef CONFIG_PM_RUNTIME
@@ -1074,13 +1075,13 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
struct resource *res;
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
- enum samsung_dai_type samsung_dai_type;
+ const struct samsung_i2s_dai_data *i2s_dai_data;
int ret = 0;
/* Call during Seconday interface registration */
- samsung_dai_type = samsung_i2s_get_driver_data(pdev);
+ i2s_dai_data = samsung_i2s_get_driver_data(pdev);
- if (samsung_dai_type == TYPE_SEC) {
+ if (i2s_dai_data-dai_type == TYPE_SEC) {
sec_dai = dev_get_drvdata(pdev-dev);
if (!sec_dai) {
dev_err(pdev-dev, Unable to get drvdata\n);
@@ -1129,15 +1130,7 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
idma_addr = i2s_cfg-idma_addr;
}
} else {
- if (of_find_property(np,
[PATCH V4 3/4] ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi
I2S nodes shares some properties across exynos5 SoCs (exynos5250
and exyno5420). Common code is moved to exynos5.dtsi which is
included in exyno5250 and exynos5420 SoC files.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi| 21 +
arch/arm/boot/dts/exynos5250.dtsi | 12
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..aae2fa1 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -108,4 +108,25 @@
interrupts = 0 42 0;
status = disabled;
};
+
+ i2s0: i2s@0383 {
+ reg = 0x0383 0x100;
+ samsung,idma-addr = 0x0300;
+ };
+
+ i2s1: i2s@12D6 {
+ compatible = samsung,i2s-v5;
+ reg = 0x12D6 0x100;
+ dmas = pdma1 12
+ pdma1 11;
+ dma-names = tx, rx;
+ };
+
+ i2s2: i2s@12D7 {
+ compatible = samsung,i2s-v5;
+ reg = 0x12D7 0x100;
+ dmas = pdma0 12
+ pdma0 11;
+ dma-names = tx, rx;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index ef57277..f941d52 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -406,7 +406,6 @@
i2s0: i2s@0383 {
compatible = samsung,i2s-v5;
- reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -418,17 +417,11 @@
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
- samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
- reg = 0x12D6 0x100;
- dmas = pdma1 12
- pdma1 11;
- dma-names = tx, rx;
clocks = clock 307, clock 157;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
@@ -436,11 +429,6 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
- reg = 0x12D7 0x100;
- dmas = pdma0 12
- pdma0 11;
- dma-names = tx, rx;
clocks = clock 308, clock 158;
clock-names = iis, i2s_opclk0;
pinctrl-names = default;
--
1.7.4.4
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[PATCH V4 0/4] Add i2s support on smdk5420
Samsung has different versions of I2S introduced in different platforms. Each version has some new support added for multichannel, secondary fifo, s/w reset control, internal mux for rclk src clk and tdm support. Each newly added change has a quirk. So this patch adds all the required quirks as driver data and based on compatible string from dtsi fetches the quirks. This also adds i2s support on exynos5420. Changes since V3: - Addressed review comments by Tomasz Figa related to const qualifier for samsung_i2s_dai_data - Removed passing quirks as driver data for non-dt platforms. - Separated out adding i2s nodes and enabling audio support on 5420 into different patch set as they are dependent on some of already posted but not yet merged i2c, dwmmc, dma and audss clock controller patches. Changes since V2: - Separated out driver side changes and dts changes in two patch sets. - Replaced samsung,s3c6410-i2s-v4 with samsung,s3c6410-i2s-multi for more clarity as suggested by Tomasz Figa. Changes since V1: - Pass quirks as driver data and fetch the quirks based on compatible string from dtsi file as suggested by Tomasz Figa and Mark Brown - Make the I2S driver more flexible with respect to register access as suggested by Tomasz Figa and Mark Brown - Add 5420 support in the driver. - Modify the dtsi files with the corresponding compatible strings and removed the i2s quirks from 5250 dtsi file. - Updated the i2s Documentation with relevent changes and i2s versioning info. - Add i2s nodes on exynos5420.dtsi - Enable sound support on smdk5420 This patch set is made based on Mark Brown for-next branch on sound.git. Padmavathi Venna (4): ASoC: Samsung: I2S: Add quirks as driver data in I2S ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420 ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi ARM: dts: Change i2s compatible string on exynos5250 .../devicetree/bindings/sound/samsung-i2s.txt | 22 ++-- arch/arm/boot/dts/exynos5.dtsi | 21 +++ arch/arm/boot/dts/exynos5250.dtsi | 17 +--- include/linux/platform_data/asoc-s3c.h |1 + sound/soc/samsung/i2s-regs.h | 15 ++ sound/soc/samsung/i2s.c| 143 +++- 6 files changed, 157 insertions(+), 62 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/4] ASoC: Samsung: I2S: Modify the I2S driver to support I2S on Exynos5420
Exynos5420 added support for I2S TDM mode. For this, there are some
register changes in the I2S controller. This patch adds the relevant
register changes to support I2S in normal mode. This patch adds a
quirk for TDM mode and if TDM mode is present all the relevent changes
will be applied.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt |4 +
include/linux/platform_data/asoc-s3c.h |1 +
sound/soc/samsung/i2s-regs.h | 15
sound/soc/samsung/i2s.c| 81 ++--
4 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 25a0024..7386d44 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -6,6 +6,10 @@ Required SoC Specific Properties:
- samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
secondary fifo, s/w reset control and internal mux for root clk src.
+ - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with
+ secondary fifo, s/w reset control, internal mux for root clk src and
+ TDM support. TDM (Time division multiplexing) is to allow transfer of
+ multiple channel audio data on single data line.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/include/linux/platform_data/asoc-s3c.h
b/include/linux/platform_data/asoc-s3c.h
index 8827259..9efc04d 100644
--- a/include/linux/platform_data/asoc-s3c.h
+++ b/include/linux/platform_data/asoc-s3c.h
@@ -36,6 +36,7 @@ struct samsung_i2s {
*/
#define QUIRK_NO_MUXPSR(1 2)
#define QUIRK_NEED_RSTCLR (1 3)
+#define QUIRK_SUPPORTS_TDM (1 4)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h
index 30513b7..821a502 100644
--- a/sound/soc/samsung/i2s-regs.h
+++ b/sound/soc/samsung/i2s-regs.h
@@ -31,6 +31,10 @@
#define I2SLVL1ADDR0x34
#define I2SLVL2ADDR0x38
#define I2SLVL3ADDR0x3c
+#define I2SSTR10x40
+#define I2SVER 0x44
+#define I2SFIC20x48
+#define I2STDM 0x4c
#define CON_RSTCLR (1 31)
#define CON_FRXOFSTATUS(1 26)
@@ -117,6 +121,17 @@
#define MOD_BCLK_MASK 3
#define MOD_8BIT (1 0)
+#define EXYNOS5420_MOD_LRP_SHIFT 15
+#define EXYNOS5420_MOD_SDF_SHIFT 6
+#define EXYNOS5420_MOD_RCLK_SHIFT 4
+#define EXYNOS5420_MOD_BCLK_SHIFT 0
+#define EXYNOS5420_MOD_BCLK_64FS 4
+#define EXYNOS5420_MOD_BCLK_96FS 5
+#define EXYNOS5420_MOD_BCLK_128FS 6
+#define EXYNOS5420_MOD_BCLK_192FS 7
+#define EXYNOS5420_MOD_BCLK_256FS 8
+#define EXYNOS5420_MOD_BCLK_MASK 0xf
+
#define MOD_CDCLKCON (1 12)
#define PSR_PSREN (1 15)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 1671d9b..ce487c2 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -199,7 +199,12 @@ static inline bool is_manager(struct i2s_dai *i2s)
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
- u32 rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
+ u32 rfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs = (readl(i2s-addr + I2SMOD) MOD_RCLK_SHIFT);
rfs = MOD_RCLK_MASK;
switch (rfs) {
@@ -214,8 +219,12 @@ static inline unsigned get_rfs(struct i2s_dai *i2s)
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
u32 mod = readl(i2s-addr + I2SMOD);
- int rfs_shift = MOD_RCLK_SHIFT;
+ int rfs_shift;
+ if (i2s-quirks QUIRK_SUPPORTS_TDM)
+ rfs_shift = EXYNOS5420_MOD_RCLK_SHIFT;
+ else
+ rfs_shift = MOD_RCLK_SHIFT;
mod = ~(MOD_RCLK_MASK rfs_shift);
switch (rfs) {
@@ -239,10 +248,22 @@ static inline void set_rfs(struct i2s_dai *i2s, unsigned
rfs)
/* Read Bit-Clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
- u32 bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
- bfs = MOD_BCLK_MASK;
+ u32 bfs;
+
+ if (i2s-quirks QUIRK_SUPPORTS_TDM) {
+ bfs = readl(i2s-addr + I2SMOD) EXYNOS5420_MOD_BCLK_SHIFT;
+ bfs = EXYNOS5420_MOD_BCLK_MASK;
+ } else {
+ bfs = readl(i2s-addr + I2SMOD) MOD_BCLK_SHIFT;
+ bfs = MOD_BCLK_MASK;
+ }
switch (bfs) {
+ case 8: return 256;
+ case 7:
[PATCH V4 4/4] ARM: dts: Change i2s compatible string on exynos5250
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi|4 ++--
arch/arm/boot/dts/exynos5250.dtsi |5 +
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index aae2fa1..309894e 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -115,7 +115,7 @@
};
i2s1: i2s@12D6 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D6 0x100;
dmas = pdma1 12
pdma1 11;
@@ -123,7 +123,7 @@
};
i2s2: i2s@12D7 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s3c6410-i2s;
reg = 0x12D7 0x100;
dmas = pdma0 12
pdma0 11;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index f941d52..ac5f5a1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -405,7 +405,7 @@
};
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
dmas = pdma0 10
pdma0 9
pdma0 8;
@@ -414,9 +414,6 @@
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
};
--
1.7.4.4
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[PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250. is rebased on Mike's https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;h=refs/heads/clk-next Vikas Sajjan (2): clk: samsung: Add GPLL freq table for exynos5250 SoC clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC drivers/clk/samsung/clk-exynos5250.c | 19 +++- drivers/clk/samsung/clk-exynos5420.c | 81 ++ 2 files changed, 99 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC
Adds GPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index a9916a4..c400e82 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[]
__initdata = {
GATE(g2d, g2d, aclk200, GATE_IP_ACP, 3, 0, 0),
};
+static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(14, 175, 3, 0), /* for 466MHz */
+ PLL_35XX_RATE(8, 100, 3, 0), /* for 400MHz, 200MHz */
+ PLL_35XX_RATE(66700, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */
+ PLL_35XX_RATE(6, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */
+ PLL_35XX_RATE(53300, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */
+ PLL_35XX_RATE(45000, 450, 12, 1), /* for 450Hz */
+ PLL_35XX_RATE(4, 100, 3, 1),
+ PLL_35XX_RATE(33300, 222, 4, 2),
+ PLL_35XX_RATE(2, 100, 3, 2),
+ { },
+};
+
static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
/* sorted in descending order */
/* PLL_36XX_RATE(rate, m, p, s, k) */
@@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
fin_pll_rate = _get_rate(fin_pll);
- if (fin_pll_rate == 24 * MHZ)
+ if (fin_pll_rate == 24 * MHZ) {
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
+ exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl;
+ }
vpllsrc = __clk_lookup(mout_vpllsrc);
if (vpllsrc)
--
1.7.9.5
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[PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC
Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5420.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index e035fd0..42cea7e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -757,10 +757,81 @@ static struct of_device_id ext_clk_match[] __initdata = {
{ },
};
+static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(19, 475, 6, 0),
+ PLL_35XX_RATE(18, 225, 3, 0),
+ PLL_35XX_RATE(17, 425, 6, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 400, 4, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+ { },
+};
+
+static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 400, 4, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+ { },
+};
+
+static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(19200, 64, 2, 2, 0),
+ PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
+ PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
+ PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
+ PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
+ PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+ { },
+};
+
+static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(53300, 533, 6, 2),
+ PLL_35XX_RATE(48000, 160, 2, 2),
+ PLL_35XX_RATE(42000, 140, 2, 2),
+ PLL_35XX_RATE(35000, 175, 3, 2),
+ PLL_35XX_RATE(26600, 266, 3, 3),
+ PLL_35XX_RATE(17700, 118, 2, 3),
+ PLL_35XX_RATE(1, 200, 3, 4),
+ { },
+};
+
/* register exynos5420 clocks */
static void __init exynos5420_clk_init(struct device_node *np)
{
void __iomem *reg_base;
+ unsigned long fin_pll_rate;
if (np) {
reg_base = of_iomap(np, 0);
@@ -776,6 +847,16 @@ static void __init exynos5420_clk_init(struct device_node
*np)
samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
ext_clk_match);
+
+ fin_pll_rate = _get_rate(fin_pll);
+
+ if (fin_pll_rate == 24 * MHZ) {
+ exynos5420_plls[apll].rate_table = apll_24mhz_tbl;
+ exynos5420_plls[kpll].rate_table = kpll_24mhz_tbl;
+ exynos5420_plls[epll].rate_table = epll_24mhz_tbl;
+ exynos5420_plls[vpll].rate_table = vpll_24mhz_tbl;
+ }
+
samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
reg_base);
samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
--
1.7.9.5
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RE: [GIT PULL] Samsung PWM support cleanup
Olof Johansson wrote: [...] Just note that I also have pulled into samsung tree because of dependency with others, this will be pulled directly by Olof though. Have you already pulled this into your tree? There was a patch[1] that was posted for 3.11 at the time this series was merged in your for-next branch, before it got dropped, that fixed one found build issue that I missed. In the end the series got dropped, that patch was not applied and I forgot about this issue. This was caught by Andrew Bresticker after I already sent my pull request. According to Olof, he hasn't pulled this yet and you don't seem to have it in your public tree either, so we could either drop this pull request and send another one with the fixup patch squashed or apply the fixup patch separately on top of this. What do you think? I have not pulled anything from Kukjin yet, so please respin your branch as needed, Tomasz. Also, see the reply about making a signed tag. OK, I see. Let me drop this in my local and will wait for Tomasz' new pull request. Thanks, Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/4] ARM: dts: Add i2c bus 1 and it's audio codec child node on smdk5420
This patch adds i2c bus 1 and wm8994 codec node on i2c bus1 and the
required regulator supplies and properties on smdk5420 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 62 +
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index d05de7a..1ef7e2e 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,4 +68,66 @@
bus-width = 4;
};
};
+
+ fixed-regulators {
+ compatible = simple-bus;
+
+ avdd2: fixed-regulator-0 {
+ compatible = regulator-fixed;
+ regulator-name = avdd2-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ cpvdd: fixed-regulator-1 {
+ compatible = regulator-fixed;
+ regulator-name = cpvdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd: fixed-regulator-2 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd: fixed-regulator-3 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+ };
+
+ i2c@12C7 {
+ status = okay;
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-max-bus-freq = 2;
+
+ eeprom@51 {
+ compatible = samsung,s524ad0xd1;
+ reg = 0x51;
+ };
+
+ wm8994: wm8994@1a {
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = avdd2;
+ CPVDD-supply = cpvdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd;
+ SPKVDD2-supply = spkvdd;
+ };
+ };
+
};
--
1.7.4.4
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[PATCH V4 4/4] ARM: dts: Enable sound support on smdk5420
This patch enables i2s0 and sound support on smdk5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index a898b3f..b1b745c 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -139,4 +139,14 @@
};
};
+ i2s0: i2s@0383 {
+ status = okay;
+ };
+
+ sound {
+ compatible = samsung,smdk-wm8994;
+
+ samsung,i2s-controller = i2s0;
+ samsung,audio-codec = wm8994;
+ };
};
--
1.7.4.4
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[PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the i2s controllers on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-on: https://gerrit.chromium.org/gerrit/57713
---
arch/arm/boot/dts/exynos5420.dtsi | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d2fdb87..8d57369 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -242,4 +242,36 @@
pinctrl-names = default;
pinctrl-0 = i2c3_bus;
};
+
+ i2s_0: i2s@0383 {
+ compatible = samsung,exynos5420-i2s;
+ dmas = adma 0
+ adma 2
+ adma 1;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
+ };
+
+ i2s_1: i2s@12D6 {
+ clocks = clock 275, clock 138;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s1_bus;
+ status = disabled;
+ };
+
+ i2s_2: i2s@12D7 {
+ clocks = clock 276, clock 139;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s2_bus;
+ status = disabled;
+ };
+
};
--
1.7.4.4
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[PATCH V4 3/4] ARM: dts: Add osc clock node on smdk5420.
This patch adds 16MHz oscillator clock node required for audio
on smdk5420 and adds the phandle of the same in wm8994 clock info.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 1ef7e2e..a898b3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,12 @@
};
};
+ osc3_clk16mhz: oscillator-0 {
+ compatible = fixed-clock;
+ #clock-cells = 0;
+ clock-frequency = 16934400;
+ };
+
dwmmc0@1220 {
status = okay;
num-slots = 1;
@@ -127,6 +133,9 @@
DBVDD-supply = dbvdd;
SPKVDD1-supply = spkvdd;
SPKVDD2-supply = spkvdd;
+
+ clocks = osc3_clk16mhz;
+ clock-names = mclk1;
};
};
--
1.7.4.4
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Re: [PATCH 17/18] spi: s3c64xx: Always select S3C64XX_PL080 when ARCH_S3C64XX is enabled
On Mon, Aug 12, 2013 at 01:03:19AM +0200, Tomasz Figa wrote: On Sunday 11 of August 2013 20:11:40 Mark Brown wrote: Do we need the select here (or should we have other selects for the Exynos SoCs)? The driver would build fine without this symbol selected, but since it relies on availability of DMA, it doesn't make too much sense to build it this way. This kind of selects makes kernel configuration more user friendly IMHO. Possibly adding appropriate selects (PL330) for s5p* and exynos could make sense. Right. On these SoCs it's probably worth doing it in the arch/arm code rather than for every device using the controller though, it's the same DMA controller for everything. signature.asc Description: Digital signature
Re: [PATCH 0/4] clk: Samsung: audss: Add support for Exynos5420
Hi Kukjin, Any comments on this patch set? Thanks Padma On Wed, Jul 10, 2013 at 5:41 PM, Padmavathi Venna padm...@samsung.com wrote: This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of parent clks for mout_i2s are also different from Exynos5250. So this patch adds provision for supporting both the platforms by passing the parent clk names through device tree. Andrew Bresticker (3): clk: exynos-audss: add support for Exynos 5420 clk: exynos-audss: allow input clocks to be specified in device tree ARM: dts: exynos5420: add audio clock controller Padmavathi Venna (1): ARM: dts: Correct the /include entry on exynos5420 dtsi file .../devicetree/bindings/clock/clk-exynos-audss.txt | 38 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 ++- drivers/clk/samsung/clk-exynos-audss.c | 36 -- include/dt-bindings/clk/exynos-audss-clk.h |3 +- 4 files changed, 80 insertions(+), 10 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] Move comon DMA nodes to exynos5.dtsi and
Hi Kukjin, Any comment on this patch set? If not can you take into your tree? Thanks Padma On Wed, Jul 10, 2013 at 5:44 PM, Padmavathi Venna padm...@samsung.com wrote: Exynos5250 and Exynos5420 has 4 DMA controllers in common. So this patch set moved the common nodes to exynos.dtsi keeping the clk info seperate for both the platforms. Exynos5420 has a separate DMA controller for audio IPs. So this patch set also adds the ADMA node on Exynos5420. Padmavathi Venna (2): ARM: dts: Move the common DMA controller nodes to exynos5.dtsi ARM: dts: Add DMA controller node info on Exynos5420. arch/arm/boot/dts/exynos5.dtsi| 44 + arch/arm/boot/dts/exynos5250.dtsi | 30 - arch/arm/boot/dts/exynos5420.dtsi | 33 +++ 3 files changed, 77 insertions(+), 30 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] PCI: exynos: add support for MSI
On Mon, Aug 12, 2013 at 05:56:47PM +0900, Jingoo Han wrote:
[...]
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 855d4a7..9ef1c95 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,7 @@ config SOC_EXYNOS5440
default y
depends on ARCH_EXYNOS5
select ARCH_HAS_OPP
+ select ARCH_SUPPORTS_MSI
This symbol goes away in Thomas Petazzoni's MSI patch series which is
targetted at 3.12, so I don't think you should add that here.
+#ifdef CONFIG_PCI_MSI
+static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ val = readl(elbi_base + PCIE_IRQ_LEVEL);
+ writel(val, elbi_base + PCIE_IRQ_LEVEL);
+ return;
+}
I'm a little confused by this: the above code seems to access the PCIe
controller registers to clear an interrupt, but you pass in a PCIe
port...
+static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ /* handle msi irq */
+ dw_handle_msi_irq(pp);
+ exynos_pcie_clear_irq_level(pp);
... so here dw_handle_msi_irq() seems to operate on a single port, while
clearing the IRQ is done on a per-controller basis.
I see that the Exynos PCIe driver hasn't made it into linux-next yet, so
I don't have full context surrounding this, but it strikes me as odd
that MSI's would be handled per-port instead of per-controller. And
furthermore that the DesignWare part handles it per-port yet the Exynos
specific part handles it per-controller.
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_pcie_msi_init(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ dw_pcie_msi_init(pp);
+
+ /* enable MSI interrupt */
+ val = readl(elbi_base + PCIE_IRQ_EN_LEVEL);
+ val |= IRQ_MSI_ENABLE;
+ writel(val, elbi_base + PCIE_IRQ_EN_LEVEL);
+ return;
+}
This function is called per-port, yet operates on per-controller
registers. It's not terribly bad in this case because it only sets one
bit, but it could eventually lead to problems in case you need to extend
this function in the future to do more, which could then potentially be
run multiple times and cause problems.
+#endif
+
static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
{
exynos_pcie_enable_irq_pulse(pp);
+#ifdef CONFIG_PCI_MSI
+ exynos_pcie_msi_init(pp);
+#endif
return;
}
Instead of the whole #ifdef business above, can't you just use something
like this in exynos_pcie_enable_interrupts():
if (IS_ENABLED(CONFIG_PCI_MSI))
exynos_pcie_msi_init(pp);
Now you can drop the #ifdef guards and the compiler will throw away all
the related code automatically if PCI_MSI is not selected because the
functions are all static and unused. This has the advantage of compiling
all the code whether or not PCI_MSI is selected or not, therefore
increasing compile coverage of the driver.
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
[...]
@@ -62,6 +64,14 @@
#define PCIE_ATU_FUNC(x) (((x) 0x7) 16)
#define PCIE_ATU_UPPER_TARGET0x91C
+#ifdef CONFIG_PCI_MSI
+#define MAX_MSI_IRQS 32
+#define MAX_MSI_CTRLS8
+
+static unsigned int msi_data;
+static DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
+#endif
+
static struct hw_pci dw_pci;
unsigned long global_io_offset;
@@ -144,6 +154,202 @@ int dw_pcie_wr_own_conf(struct pcie_port *pp, int
where, int size,
return ret;
}
+#ifdef CONFIG_PCI_MSI
+static struct irq_chip dw_msi_chip = {
+ .name = PCI-MSI,
+ .irq_enable = unmask_msi_irq,
+ .irq_disable = mask_msi_irq,
+ .irq_mask = mask_msi_irq,
+ .irq_unmask = unmask_msi_irq,
+};
+
+/* MSI int handler */
+void dw_handle_msi_irq(struct pcie_port *pp)
+{
+ unsigned long val;
+ int i, pos;
+
+ for (i = 0; i MAX_MSI_CTRLS; i++) {
+ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
+ (u32 *)val);
+ if (val) {
+ pos = 0;
+ while ((pos = find_next_bit(val, 32, pos)) != 32) {
+ generic_handle_irq(pp-msi_irq_start
+ + (i * 32) + pos);
+ pos++;
+ }
+ }
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
+ }
+}
+
+void dw_pcie_msi_init(struct pcie_port *pp)
+{
+ /* program the msi_data */
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
+ __virt_to_phys((u32)(msi_data)));
That's slightly odd. You
Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
Hi Padmavathi, Andrew,
On Monday 12 of August 2013 15:37:47 Padmavathi Venna wrote:
From: Andrew Bresticker abres...@chromium.org
This adds device-tree bindings for the i2s controllers on Exynos 5420.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-on: https://gerrit.chromium.org/gerrit/57713
---
arch/arm/boot/dts/exynos5420.dtsi | 32
1 files changed, 32 insertions(+), 0
deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi index d2fdb87..8d57369 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -242,4 +242,36 @@
pinctrl-names = default;
pinctrl-0 = i2c3_bus;
};
+
+ i2s_0: i2s@0383 {
+ compatible = samsung,exynos5420-i2s;
+ dmas = adma 0
+ adma 2
+ adma 1;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
+ status = disabled;
If a node does not require any board-specific properties for the device to
operate properly, there is no point in disabling it, just to add a single
status property at board level.
+ };
+
+ i2s_1: i2s@12D6 {
+ clocks = clock 275, clock 138;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s1_bus;
+ status = disabled;
Ditto.
+ };
+
+ i2s_2: i2s@12D7 {
+ clocks = clock 276, clock 139;
+ clock-names = iis, i2s_opclk0;
+ pinctrl-names = default;
+ pinctrl-0 = i2s2_bus;
+ status = disabled;
Ditto.
Best regards,
Tomasz
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Re: [PATCH V4 4/4] ARM: dts: Enable sound support on smdk5420
Hi Padmavathi,
On Monday 12 of August 2013 15:37:50 Padmavathi Venna wrote:
This patch enables i2s0 and sound support on smdk5420.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index a898b3f..b1b745c
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -139,4 +139,14 @@
};
};
+ i2s0: i2s@0383 {
+ status = okay;
+ };
After addressing my comment on node status for patch 1/4, you could get rid
of the node above.
Best regards,
Tomasz
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Re: [PATCH V4 0/4] Add i2s nodes on Exynos5420 and enable sound support on sdmk5420
Hi Padmavathi, On Monday 12 of August 2013 15:37:46 Padmavathi Venna wrote: Changes since V3: - used existent fixed-clock binding for registering oscillator clock as fixed rate clock as pointed by Tomasz Figa - Made some changes in wm8994 regulator nodes as suggested by Tomasz Figa - Separated out only adding i2s nodes and enabling sound support on smdk5420 into different patch set as they are dependent on on some of already posted but not yet merged i2c, dwmmc, dma and audss clock controller patches on Kukjin for-next branch. Changes since V2: - Separated out driver side changes and dts changes in two patch sets - Added proper names for wm8994 regulators as commented by Mark - Moved common i2s nodes into the exynos5.dtsi - Added clock info in wm8994 node as requested by Mark. - Registered the 16.9MHz oscillator clock as fixed clock in the machine file. Right now no user of this clock but as Mark requested to add mclk info in wm8994 node, I added this part. This patch set is dependent on the following i2c, dma and audio subsystem clk controller patches. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20077 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20661 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20668 This patch set is made based on Kukjin Kim for-next branch. Andrew Bresticker (1): ARM: dts: exynos5420: add i2s controllers Padmavathi Venna (3): ARM: dts: Add i2c bus 1 and it's audio codec child node on smdk5420 ARM: dts: Add osc clock node on smdk5420. ARM: dts: Enable sound support on smdk5420 arch/arm/boot/dts/exynos5420-smdk5420.dts | 81 + arch/arm/boot/dts/exynos5420.dtsi | 32 +++ 2 files changed, 113 insertions(+), 0 deletions(-) Except the node status misuse that I commented on in patches 1/4 and 4/4, looks good to me: Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
On Mon, Aug 12, 2013 at 01:14:20PM +0200, Tomasz Figa wrote:
On Monday 12 of August 2013 15:37:47 Padmavathi Venna wrote:
+ i2s_0: i2s@0383 {
+ status = disabled;
If a node does not require any board-specific properties for the device to
operate properly, there is no point in disabling it, just to add a single
status property at board level.
I'd expect that to interact badly with the pinmuxing - unless the device
is disabled it'll try to grab its pins on probe which is not going to be
a good idea unless it is actually wired up for use in the system. Or is
there some other mechanism for handling that?
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Description: Digital signature
Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
On Monday 12 of August 2013 12:34:48 Mark Brown wrote:
On Mon, Aug 12, 2013 at 01:14:20PM +0200, Tomasz Figa wrote:
On Monday 12 of August 2013 15:37:47 Padmavathi Venna wrote:
+ i2s_0: i2s@0383 {
+ status = disabled;
If a node does not require any board-specific properties for the device
to operate properly, there is no point in disabling it, just to add a
single status property at board level.
I'd expect that to interact badly with the pinmuxing - unless the device
is disabled it'll try to grab its pins on probe which is not going to be
a good idea unless it is actually wired up for use in the system. Or is
there some other mechanism for handling that?
Ah, good point. Now I wonder whether pinctrl nodes shouldn't be considered
board-specific and specified in board-level dts instead?
Best regards,
Tomasz
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Re: [PATCH] PCI: exynos: add support for MSI
On Mon, Aug 12, 2013 at 06:56:40PM +0800, Thierry Reding wrote:
On Mon, Aug 12, 2013 at 05:56:47PM +0900, Jingoo Han wrote:
[...]
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 855d4a7..9ef1c95 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,7 @@ config SOC_EXYNOS5440
default y
depends on ARCH_EXYNOS5
select ARCH_HAS_OPP
+ select ARCH_SUPPORTS_MSI
This symbol goes away in Thomas Petazzoni's MSI patch series which is
targetted at 3.12, so I don't think you should add that here.
+#ifdef CONFIG_PCI_MSI
+static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ void __iomem *elbi_base = exynos_pcie-elbi_base;
+
+ val = readl(elbi_base + PCIE_IRQ_LEVEL);
+ writel(val, elbi_base + PCIE_IRQ_LEVEL);
+ return;
+}
I'm a little confused by this: the above code seems to access the PCIe
controller registers to clear an interrupt, but you pass in a PCIe
port...
One struct pcie_port is associated with one controller and it has been
assumed that there is only one root port per controller.
[...]
+void dw_pcie_msi_init(struct pcie_port *pp)
+{
+ /* program the msi_data */
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
+ __virt_to_phys((u32)(msi_data)));
That's slightly odd. You convert the virtual address of a local variable
(local to the file) to a physical address and program that into a
register. I assume that it works since you've probably tested this, but
I wonder if it's safe to do this. Perhaps a better way would be to
allocate a single free page (__get_free_pages(GFP_KERNEL, 0)) and write
the physical address of that into the register instead.
also msi_data must be different for different controller. Something
like msi_data[pp-port].
[...]
+void arch_teardown_msi_irq(unsigned int irq)
+{
+ clear_irq(irq);
+}
And we've reworked this largely so that drivers no longer provide arch_*
functions because that prevents multi-platform support. So I think you
need to port this to the new msi_chip infrastructure that's being
introduced in 3.12.
Yes, its needed.
Regards
Pratyush
Thierry
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[PATCH V2] ARM: dts: Add RTC DT node to Exynos5420 SoC
Adds RTC DT node to Exynos5420 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
changes since v1:
- made DT node status as okay in the dtsi file itself.
---
arch/arm/boot/dts/exynos5.dtsi|2 +-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
arch/arm/boot/dts/exynos5420.dtsi |7 +++
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..4a8e223 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
interrupts = 0 54 0;
};
- rtc {
+ rtc@101E {
compatible = samsung,s3c6410-rtc;
reg = 0x101E 0x100;
interrupts = 0 43 0, 0 44 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..c82137b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -178,9 +178,10 @@
samsung,power-domain = pd_mfc;
};
- rtc {
+ rtc@101E {
clocks = clock 337;
clock-names = rtc;
+ status = okay;
};
tmu@1006 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..8f1bb08 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -145,4 +145,11 @@
clocks = clock 260, clock 131;
clock-names = uart, clk_uart_baud0;
};
+
+ rtc@101E {
+ clocks = clock 317;
+ clock-names = rtc;
+ status = okay;
+ };
+
};
--
1.7.9.5
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Re: [PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
Hi Padmavathi,
On Monday 12 of August 2013 15:19:51 Padmavathi Venna wrote:
Samsung has different versions of I2S introduced in different
platforms. Each version has some new support added for multichannel,
secondary fifo, s/w reset control and internal mux for rclk src clk.
Each newly added change has a quirk. So this patch adds all the
required quirks as driver data and based on compatible string from
dtsi fetches the quirks.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 18 ++
sound/soc/samsung/i2s.c| 62
+++ 2 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index
025e66b..25a0024 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -2,7 +2,11 @@
Required SoC Specific Properties:
-- compatible : samsung,i2s-v5
+- compatible : should be one of the following.
+ - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
+ - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
+ secondary fifo, s/w reset control and internal mux for root clk
src. +
- reg: physical base address of the controller and length of memory
mapped region.
- dmas: list of DMA controller phandle and DMA request line ordered
pairs. @@ -21,13 +25,6 @@ Required SoC Specific Properties:
Optional SoC Specific Properties:
-- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
- support, this flag is enabled.
-- samsung,supports-rstclr: This flag should be set if I2S software reset
bit - control is required. When this flag is set I2S software reset bit
will be - enabled or disabled based on need.
-- samsung,supports-secdai:If I2S block has a secondary FIFO and internal
DMA, - then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
@@ -36,7 +33,7 @@ Optional SoC Specific Properties:
Example:
i2s0: i2s@0383 {
- compatible = samsung,i2s-v5;
+ compatible = samsung,s5pv210-i2s;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
@@ -46,9 +43,6 @@ i2s0: i2s@0383 {
clock_audss EXYNOS_I2S_BUS,
clock_audss EXYNOS_SCLK_I2S;
clock-names = iis, i2s_opclk0, i2s_opclk1;
- samsung,supports-6ch;
- samsung,supports-rstclr;
- samsung,supports-secdai;
samsung,idma-addr = 0x0300;
pinctrl-names = default;
pinctrl-0 = i2s0_bus;
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 47e08dd..1671d9b 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -40,6 +40,7 @@ enum samsung_dai_type {
struct samsung_i2s_dai_data {
int dai_type;
+ u32 quirks;
};
struct i2s_dai {
@@ -1032,18 +1033,18 @@ static struct i2s_dai *i2s_alloc_dai(struct
platform_device *pdev, bool sec)
static const struct of_device_id exynos_i2s_match[];
-static inline int samsung_i2s_get_driver_data(struct platform_device
*pdev) +static inline const struct samsung_i2s_dai_data
*samsung_i2s_get_driver_data( +
struct platform_device
*pdev)
{
#ifdef CONFIG_OF
- struct samsung_i2s_dai_data *data;
if (pdev-dev.of_node) {
const struct of_device_id *match;
match = of_match_node(exynos_i2s_match, pdev-dev.of_node);
- data = (struct samsung_i2s_dai_data *) match-data;
- return data-dai_type;
+ return match-data;
} else
#endif
- return platform_get_device_id(pdev)-driver_data;
+ return (struct samsung_i2s_dai_data *)
+ platform_get_device_id(pdev)-driver_data;
}
#ifdef CONFIG_PM_RUNTIME
@@ -1074,13 +1075,13 @@ static int samsung_i2s_probe(struct
platform_device *pdev) struct resource *res;
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
- enum samsung_dai_type samsung_dai_type;
+ const struct samsung_i2s_dai_data *i2s_dai_data;
int ret = 0;
/* Call during Seconday interface registration */
- samsung_dai_type = samsung_i2s_get_driver_data(pdev);
+ i2s_dai_data = samsung_i2s_get_driver_data(pdev);
- if (samsung_dai_type == TYPE_SEC) {
+ if (i2s_dai_data-dai_type == TYPE_SEC) {
sec_dai = dev_get_drvdata(pdev-dev);
if (!sec_dai) {
dev_err(pdev-dev, Unable to get drvdata\n);
@@ -1129,15 +1130,7 @@ static int samsung_i2s_probe(struct
platform_device *pdev) idma_addr = i2s_cfg-idma_addr;
}
Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
On Mon, Aug 12, 2013 at 01:41:23PM +0200, Tomasz Figa wrote: On Monday 12 of August 2013 12:34:48 Mark Brown wrote: I'd expect that to interact badly with the pinmuxing - unless the device is disabled it'll try to grab its pins on probe which is not going to be a good idea unless it is actually wired up for use in the system. Or is there some other mechanism for handling that? Ah, good point. Now I wonder whether pinctrl nodes shouldn't be considered board-specific and specified in board-level dts instead? It seems a bit cleaner to use the current mechanism in that it stops the device appearing at all and hence repeated efforts to probe, plus a simple enable is less error prone, the way these SoCs are designed you don't have to pick which pinmux is in use for most of the IPs. Where there are multiple options it does seem like a good approach though. Tastes may differ though. signature.asc Description: Digital signature
Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers
On Monday 12 of August 2013 14:12:36 Mark Brown wrote: On Mon, Aug 12, 2013 at 01:41:23PM +0200, Tomasz Figa wrote: On Monday 12 of August 2013 12:34:48 Mark Brown wrote: I'd expect that to interact badly with the pinmuxing - unless the device is disabled it'll try to grab its pins on probe which is not going to be a good idea unless it is actually wired up for use in the system. Or is there some other mechanism for handling that? Ah, good point. Now I wonder whether pinctrl nodes shouldn't be considered board-specific and specified in board-level dts instead? It seems a bit cleaner to use the current mechanism in that it stops the device appearing at all and hence repeated efforts to probe, plus a simple enable is less error prone, the way these SoCs are designed you don't have to pick which pinmux is in use for most of the IPs. Where there are multiple options it does seem like a good approach though. Tastes may differ though. Right, if this SoC has only one pinmux setting for this IP, then it's fine. Padmavathi, this was the only issue I spotted, so have my: Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v2] ARM: dts: Add USBPHY nodes to Exynos4x12
This patch adds device nodes for USBPHY to Exynos4x12.
Signed-off-by: Dongjin Kim tobet...@gmail.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
---
* Changes from v1
o. 'status = disabled' is removed to probe as default
arch/arm/boot/dts/exynos4x12.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194..3ee6102 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -73,4 +73,21 @@
clock-names = sclk_fimg2d, fimg2d;
status = disabled;
};
+
+ usbphy@125B0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = samsung,exynos4x12-usb2phy;
+ reg = 0x125B 0x100;
+ ranges;
+
+ clocks = clock 2, clock 305;
+ clock-names = xusbxti, otg;
+
+ usbphy-sys {
+ /* USB device and host PHY_CONTROL registers */
+ reg = 0x10020704 0xc,
+ 0x1001021c 0x4;
+ };
+ };
};
--
1.7.9.5
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Re: [GIT PULL] Samsung-fixes-2 for v3.11
Kukjin Kim kgene@samsung.com writes: The following changes since commit 5ae90d8e467e625e447000cb4335c4db973b1095: Linux 3.11-rc3 (2013-07-28 20:53:33 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-2 for you to fetch changes up to 35f8550c8f27968af94ba5235cc611e3b6d86981: ARM: SAMSUNG: fix to support for missing cpu specific map_io (2013-07-30 13:30:57 +0900) In the future, please send arm-soc pull request to a...@kernel.org also, this makes filtering easier when non-Arnd/Olof folks (like me) are helping. Thanks, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 16/18] clk: samsung: s3c64xx: Remove clock aliases of old DMA driver
Quoting Tomasz Figa (2013-08-11 10:59:28)
Since the old DMA driver got removed, these aliases are no longer
necessary.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Acked-by: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-s3c64xx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c
b/drivers/clk/samsung/clk-s3c64xx.c
index 79ee9a6..dd47a83 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -331,9 +331,7 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[]
= {
ALIAS(HCLK_HSMMC1, s3c-sdhci.1, mmc_busclk.0),
ALIAS(HCLK_HSMMC0, s3c-sdhci.0, hsmmc),
ALIAS(HCLK_HSMMC0, s3c-sdhci.0, mmc_busclk.0),
- ALIAS(HCLK_DMA1, NULL, dma1),
ALIAS(HCLK_DMA1, dma-pl080s.1, apb_pclk),
- ALIAS(HCLK_DMA0, NULL, dma0),
ALIAS(HCLK_DMA0, dma-pl080s.0, apb_pclk),
ALIAS(HCLK_CAMIF, s3c-camif, camif),
ALIAS(HCLK_LCD, s3c-fb, lcd),
--
1.8.3.2
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Re: [PATCH 14/18] clk: samsung: s3c64xx: Add aliases for DMA clocks
Quoting Tomasz Figa (2013-08-11 10:59:26)
This patch adds clkdev aliases for clocks used by PL08x DMA driver.
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
Acked-by: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-s3c64xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c
b/drivers/clk/samsung/clk-s3c64xx.c
index eeda567..79ee9a6 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -332,7 +332,9 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[]
= {
ALIAS(HCLK_HSMMC0, s3c-sdhci.0, hsmmc),
ALIAS(HCLK_HSMMC0, s3c-sdhci.0, mmc_busclk.0),
ALIAS(HCLK_DMA1, NULL, dma1),
+ ALIAS(HCLK_DMA1, dma-pl080s.1, apb_pclk),
ALIAS(HCLK_DMA0, NULL, dma0),
+ ALIAS(HCLK_DMA0, dma-pl080s.0, apb_pclk),
ALIAS(HCLK_CAMIF, s3c-camif, camif),
ALIAS(HCLK_LCD, s3c-fb, lcd),
ALIAS(PCLK_SPI1, s3c6410-spi.1, spi),
--
1.8.3.2
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Re: [PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
On Mon, Aug 12, 2013 at 04:57:53PM -0600, Stephen Warren wrote: On 08/12/2013 03:49 AM, Padmavathi Venna wrote: +- compatible : should be one of the following. + - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. + - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with + secondary fifo, s/w reset control and internal mux for root clk src. Those descriptions seem a little odd. If I have an SoC that isn't s5pv210, yet supports 8/16/24bit multichannel(5.1) I2S with secondary fifo, s/w reset control and internal mux for root clk src, will compatible=samsung,s5pv210-i2s work for my HW? I wonder if you should instead include the IP block version in the compatible value? We've been round this loop several times, I'd prefer the IP block versions too but they're at best patchily documented and so as a general policy the Samsung bindings use the name of the SoC an IP first appeared in as the version. In other words, I don't think we have an answer to the question: Should differences between similar HW blocks be encoded into DT properties, or should the driver encode them into some table, and look them up from compatible value? For usability it seems better to just be able to say which IP you've got, this also makes it easier to implement support for new IP features later on without having to go back and add new properties which would be sad. (although I dare say that at least samsung,supports-rstclr should be modified to use the new reset controller bindings) Really? That doesn't seem terribly sane - I had thought that was for bodging resets on the side of things that don't normally have them or need board specific logic. Also note that this is actually a magic register write done to reset the IP on some specific IPs. signature.asc Description: Digital signature
Re: [PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
On 08/12/2013 05:13 PM, Mark Brown wrote: On Mon, Aug 12, 2013 at 04:57:53PM -0600, Stephen Warren wrote: On 08/12/2013 03:49 AM, Padmavathi Venna wrote: +- compatible : should be one of the following. + - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. + - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with + secondary fifo, s/w reset control and internal mux for root clk src. Those descriptions seem a little odd. If I have an SoC that isn't s5pv210, yet supports 8/16/24bit multichannel(5.1) I2S with secondary fifo, s/w reset control and internal mux for root clk src, will compatible=samsung,s5pv210-i2s work for my HW? I wonder if you should instead include the IP block version in the compatible value? We've been round this loop several times, I'd prefer the IP block versions too but they're at best patchily documented and so as a general policy the Samsung bindings use the name of the SoC an IP first appeared in as the version. In other words, I don't think we have an answer to the question: Should differences between similar HW blocks be encoded into DT properties, or should the driver encode them into some table, and look them up from compatible value? For usability it seems better to just be able to say which IP you've got, this also makes it easier to implement support for new IP features later on without having to go back and add new properties which would be sad. That seems quite reasonable, but I don't think everyone involved in DT has come out and agreed on that. I'm quite happy with the approach of looking up everything based on compatible. (although I dare say that at least samsung,supports-rstclr should be modified to use the new reset controller bindings) Really? That doesn't seem terribly sane - I had thought that was for bodging resets on the side of things that don't normally have them or need board specific logic. Also note that this is actually a magic register write done to reset the IP on some specific IPs. I believe that's exactly what the reset subsystem and associated DT bindings were designed for. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/4] ASoC: Samsung: I2S: Add quirks as driver data in I2S
On Mon, Aug 12, 2013 at 05:18:34PM -0600, Stephen Warren wrote: On 08/12/2013 05:13 PM, Mark Brown wrote: (although I dare say that at least samsung,supports-rstclr should be modified to use the new reset controller bindings) Really? That doesn't seem terribly sane - I had thought that was for bodging resets on the side of things that don't normally have them or need board specific logic. Also note that this is actually a magic register write done to reset the IP on some specific IPs. I believe that's exactly what the reset subsystem and associated DT bindings were designed for. That seems... interesting. It seems like this is fairly core device functionality I'd expect the driver to just be able to understand; the main thing this property was doing was deciding if the reset was needed. I'm not sure I see the benefit here? signature.asc Description: Digital signature
[PATCH] drm/exynos: Add missing includes
From: Mark Brown broo...@linaro.org Ensure that all externally accessed functions are correctly prototyped when defined in each file by making sure the headers with the protoypes are included in the file with the definition. Signed-off-by: Mark Brown broo...@linaro.org --- drivers/gpu/drm/exynos/exynos_drm_connector.c | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_dmabuf.c| 1 + drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 1 + drivers/gpu/drm/exynos/exynos_drm_fimc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_g2d.c | 1 + drivers/gpu/drm/exynos/exynos_drm_gsc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 + drivers/gpu/drm/exynos/exynos_drm_rotator.c | 1 + drivers/gpu/drm/exynos/exynos_drm_vidi.c | 1 + 10 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c index 02a8bc5..3f80673 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_connector.c +++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c @@ -17,6 +17,7 @@ #include drm/exynos_drm.h #include exynos_drm_drv.h #include exynos_drm_encoder.h +#include exynos_drm_connector.h #define to_exynos_connector(x) container_of(x, struct exynos_drm_connector,\ drm_connector) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 9a35d17..6b836c1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -15,6 +15,7 @@ #include drm/drmP.h #include drm/drm_crtc_helper.h +#include exynos_drm_crtc.h #include exynos_drm_drv.h #include exynos_drm_encoder.h #include exynos_drm_plane.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c index a0f997e..2b25ac8 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c @@ -11,6 +11,7 @@ #include drm/drmP.h #include drm/exynos_drm.h +#include exynos_drm_dmabuf.h #include exynos_drm_drv.h #include exynos_drm_gem.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index 8e60bd6..3199f5b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -19,6 +19,7 @@ #include exynos_drm_drv.h #include exynos_drm_fb.h +#include exynos_drm_fbdev.h #include exynos_drm_gem.h #include exynos_drm_iommu.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 6e047bd..a8ab4a4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -21,6 +21,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include regs-fimc.h +#include exynos_drm_drv.h #include exynos_drm_ipp.h #include exynos_drm_fimc.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index eddea49..1262434 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -23,6 +23,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include exynos_drm_drv.h +#include exynos_drm_g2d.h #include exynos_drm_gem.h #include exynos_drm_iommu.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 90b8a1a..e69d1d2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -20,6 +20,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include regs-gsc.h +#include exynos_drm_drv.h #include exynos_drm_ipp.h #include exynos_drm_gsc.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 6ee55e6..98eb1f7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -16,6 +16,7 @@ #include exynos_drm_encoder.h #include exynos_drm_fb.h #include exynos_drm_gem.h +#include exynos_drm_plane.h #define to_exynos_plane(x) container_of(x, struct exynos_plane, base) diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c index 49669aa..54b7360 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c +++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c @@ -21,6 +21,7 @@ #include drm/exynos_drm.h #include regs-rotator.h #include exynos_drm.h +#include exynos_drm_drv.h #include exynos_drm_ipp.h /* diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index c57c565..4400330 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -23,6 +23,7 @@ #include exynos_drm_drv.h #include exynos_drm_crtc.h #include exynos_drm_encoder.h +#include exynos_drm_vidi.h /* vidi has totally three virtual windows. */ #define WINDOWS_NR 3 -- 1.8.4.rc1 -- To unsubscribe
Re: [PATCH 10/18] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX
On Tuesday 13 of August 2013 00:36:41 Mark Brown wrote: On Sun, Aug 11, 2013 at 07:59:22PM +0200, Tomasz Figa wrote: With support for amba-pl08x driver, on S3C64xx the generic DMA engine API can be used instead of the private s3c-dma interface. I'm still getting issues for SPI with this: [ 50.952845] s3c64xx-spi s3c6410-spi.0: Failed to get RX DMA channel [ 50.953520] spi_master spi0: failed to prepare transfer hardware when I test (with -next with this series applied on top), this is from the first transfer that tries to DMA - there's actually no RX data. No errors are reported by the DMA controller itself. I'm also getting crashes setting up the audio DMA while derferencecing the channel. This is without DT - are there any hookups missing because of that? Hmm, strange. I've been testing this without any significant patches, like PWM, CCF or DT support, just everything from the branch I pointed to and some board- specific patches to help in debugging. Anyway, this is the exact branch I've been using: git://github.com/tom3q/linux.git v3.12-pl080-devel Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] drm/exynos: Add missing includes
-Original Message- From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc- ow...@vger.kernel.org] On Behalf Of Mark Brown Sent: Tuesday, August 13, 2013 8:47 AM To: David Airlie Cc: linux-samsung-soc@vger.kernel.org; dri-de...@lists.freedesktop.org; Mark Brown Subject: [PATCH] drm/exynos: Add missing includes From: Mark Brown broo...@linaro.org Ensure that all externally accessed functions are correctly prototyped when defined in each file by making sure the headers with the protoypes are included in the file with the definition. I definitely missed it. sorry about that. Actually I was going to try to incur something such as compile warning. You mean that the warning could be incurred by compiler in case that a external module includes a header of Exynos drm but the prototype of the header file differs from the one of .c file? I will apply it to -next but I'd like to understand why this patch is needed surely. And it seems like that other drivers have same issue also. :) Thanks, Inki Dae Signed-off-by: Mark Brown broo...@linaro.org --- drivers/gpu/drm/exynos/exynos_drm_connector.c | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_dmabuf.c| 1 + drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 1 + drivers/gpu/drm/exynos/exynos_drm_fimc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_g2d.c | 1 + drivers/gpu/drm/exynos/exynos_drm_gsc.c | 1 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 + drivers/gpu/drm/exynos/exynos_drm_rotator.c | 1 + drivers/gpu/drm/exynos/exynos_drm_vidi.c | 1 + 10 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c index 02a8bc5..3f80673 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_connector.c +++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c @@ -17,6 +17,7 @@ #include drm/exynos_drm.h #include exynos_drm_drv.h #include exynos_drm_encoder.h +#include exynos_drm_connector.h #define to_exynos_connector(x) container_of(x, struct exynos_drm_connector,\ drm_connector) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 9a35d17..6b836c1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -15,6 +15,7 @@ #include drm/drmP.h #include drm/drm_crtc_helper.h +#include exynos_drm_crtc.h #include exynos_drm_drv.h #include exynos_drm_encoder.h #include exynos_drm_plane.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c index a0f997e..2b25ac8 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c @@ -11,6 +11,7 @@ #include drm/drmP.h #include drm/exynos_drm.h +#include exynos_drm_dmabuf.h #include exynos_drm_drv.h #include exynos_drm_gem.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index 8e60bd6..3199f5b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -19,6 +19,7 @@ #include exynos_drm_drv.h #include exynos_drm_fb.h +#include exynos_drm_fbdev.h #include exynos_drm_gem.h #include exynos_drm_iommu.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 6e047bd..a8ab4a4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -21,6 +21,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include regs-fimc.h +#include exynos_drm_drv.h #include exynos_drm_ipp.h #include exynos_drm_fimc.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index eddea49..1262434 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -23,6 +23,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include exynos_drm_drv.h +#include exynos_drm_g2d.h #include exynos_drm_gem.h #include exynos_drm_iommu.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 90b8a1a..e69d1d2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -20,6 +20,7 @@ #include drm/drmP.h #include drm/exynos_drm.h #include regs-gsc.h +#include exynos_drm_drv.h #include exynos_drm_ipp.h #include exynos_drm_gsc.h diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 6ee55e6..98eb1f7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -16,6 +16,7 @@ #include exynos_drm_encoder.h #include exynos_drm_fb.h #include exynos_drm_gem.h +#include exynos_drm_plane.h
[PATCHv3 1/4] drm/exynos: add device tree support for rotator
The exynos4 platform is only dt-based since 3.10, we should convert driver data
and ids to dt-based parsing methods. The rotator driver has a limit table to get
size limit of input picture. Each SoCs has slightly different limit value
compared with any others.
For example, exynos4210's max_size of RGB888 is 16k x 16k. But, others have
8k x 8k. Another example the exynos5250 should have multiple of 2 pixel size
for its X/Y axis. Thus, we should keep different tables for each of them.
This patch also includes desciptions of each nodes for the rotator and specifies
a example how to bind it.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Cc: Inki Dae inki@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/gpu/samsung-rotator.txt| 27 +
drivers/gpu/drm/exynos/exynos_drm_rotator.c| 108 +++-
2 files changed, 107 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpu/samsung-rotator.txt
diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt
b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt
new file mode 100644
index 000..82cd1ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt
@@ -0,0 +1,27 @@
+* Samsung Image Rotator
+
+Required properties:
+ - compatible : value should be one of the following:
+ (a) samsung,exynos4210-rotator for Rotator IP in Exynos4210
+ (b) samsung,exynos4212-rotator for Rotator IP in Exynos4212/4412
+ (c) samsung,exynos5250-rotator for Rotator IP in Exynos5250
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : Interrupt specifier for rotator interrupt, according to format
+specific to interrupt parent.
+
+ - clocks : Clock specifier for rotator clock, according to generic clock
+bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
+
+ - clock-names : Names of clocks. For exynos rotator, it should be rotator.
+
+Example:
+ rotator@1281 {
+ compatible = samsung,exynos4210-rotator;
+ reg = 0x1281 0x1000;
+ interrupts = 0 83 0;
+ clocks = clock 278;
+ clock-names = rotator;
+ };
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c
b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
index 427640a..0485aea5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -632,21 +632,98 @@ static int rotator_ippdrv_start(struct device *dev, enum
drm_exynos_ipp_cmd cmd)
return 0;
}
+static struct rot_limit_table rot_limit_tbl_4210 = {
+ .ycbcr420_2p = {
+ .min_w = 32,
+ .min_h = 32,
+ .max_w = SZ_64K,
+ .max_h = SZ_64K,
+ .align = 3,
+ },
+ .rgb888 = {
+ .min_w = 8,
+ .min_h = 8,
+ .max_w = SZ_16K,
+ .max_h = SZ_16K,
+ .align = 2,
+ },
+};
+
+static struct rot_limit_table rot_limit_tbl_4x12 = {
+ .ycbcr420_2p = {
+ .min_w = 32,
+ .min_h = 32,
+ .max_w = SZ_32K,
+ .max_h = SZ_32K,
+ .align = 3,
+ },
+ .rgb888 = {
+ .min_w = 8,
+ .min_h = 8,
+ .max_w = SZ_8K,
+ .max_h = SZ_8K,
+ .align = 2,
+ },
+};
+
+static struct rot_limit_table rot_limit_tbl_5250 = {
+ .ycbcr420_2p = {
+ .min_w = 32,
+ .min_h = 32,
+ .max_w = SZ_32K,
+ .max_h = SZ_32K,
+ .align = 3,
+ },
+ .rgb888 = {
+ .min_w = 8,
+ .min_h = 8,
+ .max_w = SZ_8K,
+ .max_h = SZ_8K,
+ .align = 1,
+ },
+};
+
+static const struct of_device_id exynos_rotator_match[] = {
+ {
+ .compatible = samsung,exynos4210-rotator,
+ .data = rot_limit_tbl_4210,
+ },
+ {
+ .compatible = samsung,exynos4212-rotator,
+ .data = rot_limit_tbl_4x12,
+ },
+ {
+ .compatible = samsung,exynos5250-rotator,
+ .data = rot_limit_tbl_5250,
+ },
+ {},
+};
+
static int rotator_probe(struct platform_device *pdev)
{
struct device *dev = pdev-dev;
struct rot_context *rot;
struct exynos_drm_ippdrv *ippdrv;
+ const struct of_device_id *match;
int ret;
+ if (!dev-of_node) {
+ dev_err(dev, cannot find of_node.\n);
+ return -ENODEV;
+ }
+
rot = devm_kzalloc(dev, sizeof(*rot), GFP_KERNEL);
if (!rot) {
dev_err(dev, failed to allocate rot\n);
return -ENOMEM;
}
- rot-limit_tbl = (struct
[PATCHv3 4/4] ARM: dts: Add rotator node for exynos5250
This patch adds a rotator node for exynos5250. It has different align value of
image size compared with any other chips. So, we should define new compatible
for the exynos5250.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: Inki Dae inki@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 6f356ce..f579546 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -570,6 +570,14 @@
};
};
+ rotator@11C0 {
+ compatible = samsung,exynos5250-rotator;
+ reg = 0x11C0 0x1000;
+ interrupts = 0 84 0;
+ clocks = clock 269;
+ clock-names = rotator;
+ };
+
gsc_0: gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
--
1.7.9.5
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[PATCHv3 0/4] device tree support for exynos rotator
This patchset includes device tree support for rotator of exynos4210/4x12/5250. Unfortunately, each of them has slightly different limitations of image size. The rotator can support several image formats(RGB888/555, YCbCr422/420_2/3p). For convinience, however, exynos drm rotator driver only support RGB888 and YCbCr420 2-Plane formats. For example, the exynos4210 has 16k x 16k maximum size . But rest of them has 8k x 8k. In addition, RGB888 X/Y pixel size of exynos5250 should be multiple of 2. But others are multiple of 4. Thus, we should define different compatibles and limit tables for each chipsets. This patchset is based on the Kukjin's dt-exynos tree. (git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v3.12-next/dt-exynos) Changes from v2: - Remove unnecessary 'of_match_ptr' - Consolidate dt support code and documentation into one patch - Fix typo and remove status node. Changes from v1: - Added exynos5250 binding. - Move limit table into driver code from DT-nodes Chanho Park (4): drm/exynos: add device tree support for rotator ARM: dts: Add rotator node for exynos4210 ARM: dts: Add rotator node for exynos4x12 ARM: dts: Add rotator node for exynos5250 .../devicetree/bindings/gpu/samsung-rotator.txt| 27 + arch/arm/boot/dts/exynos4.dtsi |8 ++ arch/arm/boot/dts/exynos4x12.dtsi |4 + arch/arm/boot/dts/exynos5250.dtsi |8 ++ drivers/gpu/drm/exynos/exynos_drm_rotator.c| 108 +++- 5 files changed, 127 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/samsung-rotator.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv3 3/4] ARM: dts: Add rotator node for exynos4x12
This patch adds a rotator node for exynos4212 and 4412. These have different
limitation of image size compared with the exynos4210. So, we should define
new compatible to distinguish it from the exynos4210.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: Inki Dae inki@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4x12.dtsi |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 954628c..280c56f 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -176,4 +176,8 @@
};
};
};
+
+ rotator@1281 {
+ compatible = samsung,exynos4212-rotator;
+ };
};
--
1.7.9.5
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[PATCHv3 2/4] ARM: dts: Add rotator node for exynos4210
This patch adds a rotator node for exynos4210. The exynos4210 has different
limitation of image size compared with later chips.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: Inki Dae inki@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 597cfcf..baa3e56 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -243,6 +243,14 @@
status = disabled;
};
+ rotator@1281 {
+ compatible = samsung,exynos4210-rotator;
+ reg = 0x1281 0x1000;
+ interrupts = 0 83 0;
+ clocks = clock 278;
+ clock-names = rotator;
+ };
+
mfc: codec@1340 {
compatible = samsung,mfc-v5;
reg = 0x1340 0x1;
--
1.7.9.5
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