[PATCH 0/2] Add device tree based lookup of boost mode OPPs
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds support for CPU boost mode for CPUfreq drivers. To use the new boost mode, CPUfreq drivers have to specify the boost mode frequency and voltage within the CPUfreq driver, which is the case for Exynos4x12 CPUfreq driver. But for CPUfreq drivers which obtain the OPPs from cpus node, this patch series adds support to specify boost mode OPPs in dt node. This requirement came up when Lukasz pointed out the regression caused by the Exynos CPUfreq driver consolidation patches. Thomas Abraham (2): PM / OPP: Add support for 'boost' mode OPP Documentation: devicetree: Add boost-opp binding to list boost mode OPPs Documentation/devicetree/bindings/power/opp.txt |9 +++ drivers/base/power/opp.c| 69 ++- 2 files changed, 65 insertions(+), 13 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] PM / OPP: Add support for 'boost' mode OPP
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost OPPs from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/base/power/opp.c | 69 +-
1 file changed, 56 insertions(+), 13 deletions(-)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index 2553867..de4d52d 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -62,6 +62,7 @@ struct dev_pm_opp {
struct list_head node;
bool available;
+ bool boost;
unsigned long rate;
unsigned long u_volt;
@@ -380,10 +381,12 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct
device *dev,
EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
/**
- * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * dev_pm_opp_add_flags() - Add an OPP to device OPP list with flags
* @dev: device for which we do this operation
* @freq: Frequency in Hz for this OPP
* @u_volt:Voltage in uVolts for this OPP
+ * @available: initial availability of the OPP with adding it to the list.
+ * @boost: availability of this opp in controller's boost operating mode.
*
* This function adds an opp definition to the opp list and returns status.
* The opp is made available by default and it can be controlled using
@@ -395,7 +398,8 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
* that this function is *NOT* called under RCU protection or in contexts where
* mutex cannot be locked.
*/
-int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+static int dev_pm_opp_add_flags(struct device *dev, unsigned long freq,
+ unsigned long u_volt, bool available, bool boost)
{
struct device_opp *dev_opp = NULL;
struct dev_pm_opp *opp, *new_opp;
@@ -441,7 +445,8 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq,
unsigned long u_volt)
new_opp-dev_opp = dev_opp;
new_opp-rate = freq;
new_opp-u_volt = u_volt;
- new_opp-available = true;
+ new_opp-available = available;
+ new_opp-boost = boost;
/* Insert new OPP in order of increasing frequency */
head = dev_opp-opp_list;
@@ -462,6 +467,27 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq,
unsigned long u_volt)
srcu_notifier_call_chain(dev_opp-head, OPP_EVENT_ADD, new_opp);
return 0;
}
+
+/**
+ * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * @dev: device for which we do this operation
+ * @freq: Frequency in Hz for this OPP
+ * @u_volt:Voltage in uVolts for this OPP
+ *
+ * This function adds an opp definition to the opp list and returns status.
+ * The opp is made available by default and it can be controlled using
+ * dev_pm_opp_enable/disable functions.
+ *
+ * Locking: The internal device_opp and opp structures are RCU protected.
+ * Hence this function internally uses RCU updater strategy with mutex locks
+ * to keep the integrity of the internal data structures. Callers should ensure
+ * that this function is *NOT* called under RCU protection or in contexts where
+ * mutex cannot be locked.
+ */
+int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+{
+ return dev_pm_opp_add_flags(dev, freq, u_volt, true, false);
+}
EXPORT_SYMBOL_GPL(dev_pm_opp_add);
/**
@@ -651,7 +677,8 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
list_for_each_entry(opp, dev_opp-opp_list, node) {
if (opp-available) {
- freq_table[i].driver_data = i;
+ freq_table[i].driver_data =
+ opp-boost ? CPUFREQ_BOOST_FREQ : i;
freq_table[i].frequency = opp-rate / 1000;
i++;
}
@@ -701,19 +728,14 @@ struct srcu_notifier_head *dev_pm_opp_get_notifier(struct
device *dev)
}
#ifdef CONFIG_OF
-/**
- * of_init_opp_table() - Initialize opp table from device tree
- * @dev: device pointer used to lookup device OPPs.
- *
- * Register the initial OPP table with the OPP library for given device.
- */
-int of_init_opp_table(struct device *dev)
+static int of_parse_opp_table(struct device *dev, const char *prop_name,
+ bool boost)
{
const struct property *prop;
const __be32 *val;
int nr;
- prop = of_find_property(dev-of_node, operating-points, NULL);
+ prop = of_find_property(dev-of_node, prop_name, NULL);
if (!prop)
return -ENODEV;
if (!prop-value)
@@ -734,7 +756,7 @@ int of_init_opp_table(struct device *dev)
unsigned long freq =
[PATCH 2/2] Documentation: devicetree: Add boost-opp binding to list boost mode OPPs
From: Thomas Abraham thomas...@samsung.com
Certain CPUs or devices can support optional boost operating modes. Add a new
binding to list OPPs to be additionally made available in boost operating modes.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
Documentation/devicetree/bindings/power/opp.txt |9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/opp.txt
b/Documentation/devicetree/bindings/power/opp.txt
index 74499e5..4df5cca 100644
--- a/Documentation/devicetree/bindings/power/opp.txt
+++ b/Documentation/devicetree/bindings/power/opp.txt
@@ -10,6 +10,10 @@ Properties:
freq: clock frequency in kHz
vol: voltage in microvolt
+Optional Properties:
+- boost-opp: Similar to operating-points property but usable only in
+ optional boost operating modes.
+
Examples:
cpu@0 {
@@ -22,4 +26,9 @@ cpu@0 {
396000 95
198000 85
;
+ boost-opp =
+ /* kHz uV */
+ 150 135
+ 140 1285000
+ ;
};
--
1.7.10.4
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Re: [PATCH 2/2] Documentation: devicetree: Add boost-opp binding to list boost mode OPPs
On Tue, Feb 4, 2014 at 3:41 AM, Thomas Abraham ta.oma...@gmail.com wrote:
From: Thomas Abraham thomas...@samsung.com
Certain CPUs or devices can support optional boost operating modes. Add a new
binding to list OPPs to be additionally made available in boost operating
modes.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
Documentation/devicetree/bindings/power/opp.txt |9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/opp.txt
b/Documentation/devicetree/bindings/power/opp.txt
index 74499e5..4df5cca 100644
--- a/Documentation/devicetree/bindings/power/opp.txt
+++ b/Documentation/devicetree/bindings/power/opp.txt
@@ -10,6 +10,10 @@ Properties:
freq: clock frequency in kHz
vol: voltage in microvolt
+Optional Properties:
+- boost-opp: Similar to operating-points property but usable only in
+ optional boost operating modes.
+
Examples:
cpu@0 {
@@ -22,4 +26,9 @@ cpu@0 {
396000 95
198000 85
;
+ boost-opp =
+ /* kHz uV */
+ 150 135
+ 140 1285000
+ ;
This looks like an example of needing to add more properties to the
OPP table. There are ongoing discussions on how to extend OPP table
and map to C states. This should be part of that discussion.
Rob
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Re: [PATCH v6 8/8] usb: ehci-exynos: Change to use phy provided by the generic phy framework
Hi Alan, On 29.01.2014 21:42, Alan Stern wrote: On Wed, 29 Jan 2014, Kamil Debski wrote: Change the phy provider used from the old one using the USB phy framework to a new one using the Generic phy framework. Signed-off-by: Kamil Debski k.deb...@samsung.com --- .../devicetree/bindings/usb/exynos-usb.txt | 13 +++ drivers/usb/host/ehci-exynos.c | 97 +--- 2 files changed, 76 insertions(+), 34 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index d967ba1..25e199a 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -12,6 +12,10 @@ Required properties: - interrupts: interrupt number to the cpu. - clocks: from common clock binding: handle to usb clock. - clock-names: from common clock binding: Shall be usbhost. + - port: if in the SoC there are EHCI phys, they should be listed here. +One phy per port. Each port should have its reg entry with a consecutive +number. Also it should contain phys and phy-names entries specifying the +phy used by the port. What is the reg entry number used for? As far as I can see, it isn't used for anything. In which case, why have it at all? The reg property is here to identify which EHCI port the node is describing. This should be mentioned in the documentation, though, as well as the whole description of port nodes should be written in a more structured manner, just as other properties. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] PM / OPP: Add support for 'boost' mode OPP
On 02/04/2014 03:41 AM, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost OPPs from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
Why is a cpufreq feature being pushed on to OPP library? you can very
well have a property boot-frequencies = a b c and be done with the
job.
I agree with Rob's comment that this is something we have to discuss
in wider add features to an OPP discussion[1].
[1] http://marc.info/?t=13910894641r=1w=2
drivers/base/power/opp.c | 69
+-
1 file changed, 56 insertions(+), 13 deletions(-)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index 2553867..de4d52d 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -62,6 +62,7 @@ struct dev_pm_opp {
struct list_head node;
bool available;
+ bool boost;
unsigned long rate;
unsigned long u_volt;
@@ -380,10 +381,12 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct
device *dev,
EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
/**
- * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * dev_pm_opp_add_flags() - Add an OPP to device OPP list with flags
* @dev: device for which we do this operation
* @freq:Frequency in Hz for this OPP
* @u_volt: Voltage in uVolts for this OPP
+ * @available: initial availability of the OPP with adding it to the
list.
+ * @boost: availability of this opp in controller's boost operating mode.
*
* This function adds an opp definition to the opp list and returns status.
* The opp is made available by default and it can be controlled using
@@ -395,7 +398,8 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
* that this function is *NOT* called under RCU protection or in contexts
where
* mutex cannot be locked.
*/
-int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+static int dev_pm_opp_add_flags(struct device *dev, unsigned long freq,
+ unsigned long u_volt, bool available, bool boost)
{
struct device_opp *dev_opp = NULL;
struct dev_pm_opp *opp, *new_opp;
@@ -441,7 +445,8 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
new_opp-dev_opp = dev_opp;
new_opp-rate = freq;
new_opp-u_volt = u_volt;
- new_opp-available = true;
+ new_opp-available = available;
+ new_opp-boost = boost;
/* Insert new OPP in order of increasing frequency */
head = dev_opp-opp_list;
@@ -462,6 +467,27 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
srcu_notifier_call_chain(dev_opp-head, OPP_EVENT_ADD, new_opp);
return 0;
}
+
+/**
+ * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * @dev: device for which we do this operation
+ * @freq:Frequency in Hz for this OPP
+ * @u_volt: Voltage in uVolts for this OPP
+ *
+ * This function adds an opp definition to the opp list and returns status.
+ * The opp is made available by default and it can be controlled using
+ * dev_pm_opp_enable/disable functions.
+ *
+ * Locking: The internal device_opp and opp structures are RCU protected.
+ * Hence this function internally uses RCU updater strategy with mutex locks
+ * to keep the integrity of the internal data structures. Callers should
ensure
+ * that this function is *NOT* called under RCU protection or in contexts
where
+ * mutex cannot be locked.
+ */
+int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+{
+ return dev_pm_opp_add_flags(dev, freq, u_volt, true, false);
+}
EXPORT_SYMBOL_GPL(dev_pm_opp_add);
/**
@@ -651,7 +677,8 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
list_for_each_entry(opp, dev_opp-opp_list, node) {
if (opp-available) {
- freq_table[i].driver_data = i;
+ freq_table[i].driver_data =
+ opp-boost ? CPUFREQ_BOOST_FREQ : i;
freq_table[i].frequency = opp-rate / 1000;
i++;
}
@@ -701,19 +728,14 @@ struct srcu_notifier_head
*dev_pm_opp_get_notifier(struct device *dev)
}
#ifdef CONFIG_OF
-/**
- * of_init_opp_table() - Initialize opp table from device tree
- * @dev: device pointer used to lookup device OPPs.
- *
- * Register the initial OPP table with the OPP library for given device.
- */
-int of_init_opp_table(struct device *dev)
+static int of_parse_opp_table(struct device *dev, const char *prop_name,
+
Re: [PATCH 1/2] PM / OPP: Add support for 'boost' mode OPP
On Tue, Feb 4, 2014 at 8:45 PM, Nishanth Menon n...@ti.com wrote:
On 02/04/2014 03:41 AM, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost OPPs from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
Why is a cpufreq feature being pushed on to OPP library? you can very
well have a property boot-frequencies = a b c and be done with the
job.
The boost-opp was not limited to be a cpu/cpufreq only feature. Any
device (such as a bus) which has OPPs and if it can support optional
boost OPPs, can utilize this feature. The boost OPPs also require a
voltage to be associated with the frequency and hence the binding
boost-frequencies would not be suffice. The code changes in this patch
also do not have anything that is cpufreq specific.
I agree with Rob's comment that this is something we have to discuss
in wider add features to an OPP discussion[1].
Okay. I have read through the discussion in [1]. Thanks for the link.
Assuming that the current OPP tuple format will not change, I do not
feel the code changes in this patch will be hinder the outcome of the
discussion in [1].
Regards,
Thomas.
[1] http://marc.info/?t=13910894641r=1w=2
drivers/base/power/opp.c | 69
+-
1 file changed, 56 insertions(+), 13 deletions(-)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index 2553867..de4d52d 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -62,6 +62,7 @@ struct dev_pm_opp {
struct list_head node;
bool available;
+ bool boost;
unsigned long rate;
unsigned long u_volt;
@@ -380,10 +381,12 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct
device *dev,
EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
/**
- * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * dev_pm_opp_add_flags() - Add an OPP to device OPP list with flags
* @dev: device for which we do this operation
* @freq:Frequency in Hz for this OPP
* @u_volt: Voltage in uVolts for this OPP
+ * @available: initial availability of the OPP with adding it to the
list.
+ * @boost: availability of this opp in controller's boost operating mode.
*
* This function adds an opp definition to the opp list and returns status.
* The opp is made available by default and it can be controlled using
@@ -395,7 +398,8 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
* that this function is *NOT* called under RCU protection or in contexts
where
* mutex cannot be locked.
*/
-int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+static int dev_pm_opp_add_flags(struct device *dev, unsigned long freq,
+ unsigned long u_volt, bool available, bool boost)
{
struct device_opp *dev_opp = NULL;
struct dev_pm_opp *opp, *new_opp;
@@ -441,7 +445,8 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
new_opp-dev_opp = dev_opp;
new_opp-rate = freq;
new_opp-u_volt = u_volt;
- new_opp-available = true;
+ new_opp-available = available;
+ new_opp-boost = boost;
/* Insert new OPP in order of increasing frequency */
head = dev_opp-opp_list;
@@ -462,6 +467,27 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
srcu_notifier_call_chain(dev_opp-head, OPP_EVENT_ADD, new_opp);
return 0;
}
+
+/**
+ * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * @dev: device for which we do this operation
+ * @freq:Frequency in Hz for this OPP
+ * @u_volt: Voltage in uVolts for this OPP
+ *
+ * This function adds an opp definition to the opp list and returns status.
+ * The opp is made available by default and it can be controlled using
+ * dev_pm_opp_enable/disable functions.
+ *
+ * Locking: The internal device_opp and opp structures are RCU protected.
+ * Hence this function internally uses RCU updater strategy with mutex locks
+ * to keep the integrity of the internal data structures. Callers should
ensure
+ * that this function is *NOT* called under RCU protection or in contexts
where
+ * mutex cannot be locked.
+ */
+int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+{
+ return dev_pm_opp_add_flags(dev, freq, u_volt, true, false);
+}
EXPORT_SYMBOL_GPL(dev_pm_opp_add);
/**
@@ -651,7 +677,8 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
list_for_each_entry(opp, dev_opp-opp_list, node) {
if (opp-available) {
- freq_table[i].driver_data = i;
+
Re: [PATCH 1/2] PM / OPP: Add support for 'boost' mode OPP
On 02/04/2014 09:59 AM, Thomas Abraham wrote:
On Tue, Feb 4, 2014 at 8:45 PM, Nishanth Menon n...@ti.com wrote:
On 02/04/2014 03:41 AM, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
Commit 6f19efc0 (cpufreq: Add boost frequency support in core) adds
support for CPU boost mode. This patch adds support for finding available
boost OPPs from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon n...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
Why is a cpufreq feature being pushed on to OPP library? you can very
well have a property boot-frequencies = a b c and be done with the
job.
The boost-opp was not limited to be a cpu/cpufreq only feature. Any
device (such as a bus) which has OPPs and if it can support optional
boost OPPs, can utilize this feature. The boost OPPs also require a
voltage to be associated with the frequency and hence the binding
boost-frequencies would not be suffice. The code changes in this patch
also do not have anything that is cpufreq specific.
if we have
operating-points = Fa Va
Fb Vb
Fc Vc
Fd Vd
;
boost-frequencies = Fc Fd;
you can easily pick up the voltages from the table.
The point being - there does not seem to be a need to modify the
existing definitions to introduce new OPP definitions.
a way to flip this over is to consider iMX6(see
arch/arm/mach-imx/mach-imx6q.) where OPP tuple Fd Vd can only be
enabled *iff* efuse register x has bit y set.
Would we want to introduce efuse offsets into OPP definitions? into
something like additional field definition 'efuse_controlled'?
I agree with Rob's comment that this is something we have to discuss
in wider add features to an OPP discussion[1].
Okay. I have read through the discussion in [1]. Thanks for the link.
Assuming that the current OPP tuple format will not change, I do not
feel the code changes in this patch will be hinder the outcome of the
discussion in [1].
The context of that discussion is to consider what is the data form we
consider OPP as? should we consider OPP as a data that is extensible
(as in phandle with properties that we add on) OR should we consider
key, value pair which provides a key (frequency) into another table
for other data (like efuse bit map, boost set etc..).
Both approaches I mentioned will work, and will take additional code
to make it happen. But having custom properties like this limits
extensibility - that is not scalable for other property definitions
we'd like to make in the future.
Regards,
Thomas.
[1] http://marc.info/?t=13910894641r=1w=2
drivers/base/power/opp.c | 69
+-
1 file changed, 56 insertions(+), 13 deletions(-)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index 2553867..de4d52d 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -62,6 +62,7 @@ struct dev_pm_opp {
struct list_head node;
bool available;
+ bool boost;
unsigned long rate;
unsigned long u_volt;
@@ -380,10 +381,12 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct
device *dev,
EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
/**
- * dev_pm_opp_add() - Add an OPP table from a table definitions
+ * dev_pm_opp_add_flags() - Add an OPP to device OPP list with flags
* @dev: device for which we do this operation
* @freq:Frequency in Hz for this OPP
* @u_volt: Voltage in uVolts for this OPP
+ * @available: initial availability of the OPP with adding it to the
list.
+ * @boost: availability of this opp in controller's boost operating mode.
*
* This function adds an opp definition to the opp list and returns status.
* The opp is made available by default and it can be controlled using
@@ -395,7 +398,8 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor);
* that this function is *NOT* called under RCU protection or in contexts
where
* mutex cannot be locked.
*/
-int dev_pm_opp_add(struct device *dev, unsigned long freq, unsigned long
u_volt)
+static int dev_pm_opp_add_flags(struct device *dev, unsigned long freq,
+ unsigned long u_volt, bool available, bool boost)
{
struct device_opp *dev_opp = NULL;
struct dev_pm_opp *opp, *new_opp;
@@ -441,7 +445,8 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
new_opp-dev_opp = dev_opp;
new_opp-rate = freq;
new_opp-u_volt = u_volt;
- new_opp-available = true;
+ new_opp-available = available;
+ new_opp-boost = boost;
/* Insert new OPP in order of increasing frequency */
head = dev_opp-opp_list;
@@ -462,6 +467,27 @@ int dev_pm_opp_add(struct device *dev, unsigned long
freq, unsigned long u_volt)
srcu_notifier_call_chain(dev_opp-head, OPP_EVENT_ADD, new_opp);
return 0;
}
+
s5p-mfc firmware load path
Hi, linux-firmware git layout suggests that s5p-mfc firmware should be installed to /lib/firmware/s5p-mfc and this is where distros seem to be installing it. However, the request_firmware calls in the s5p-mfc driver cause the kernel to look for the firmware at /lib/firmware directly, and fail to find it under such configurations. Which is the correct fix for this inconsistency? Thanks, Daniel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCHv1] usb: dwc2: Combine dwc2/s3c-hsotg into a single DRD
From: Dinh Nguyen dingu...@altera.com
Hello,
This patch is my first attempt in combining the Synopsys DWC2 host and the
s3c-hsotg peripheral into a single dual-role driver.
The patch:
* Moves the s3c-hsotg driver into the dwc2 folder.
* Adds the gadget data structure into the dwc2_hsotg data structure.
* Replace the s3c-hsotg.h defines with the hw.h defines in dwc2
* Uses the otg clock for both host/peripheral.
* Uses the dwc2_handle_common_intr() IRQ handler for both modes.
I have only been able to test the driver on the SOCFPGA platform, which has
v2.93a of the dual-role core.
Any comments and testing would be greatly appreciated.
Thanks,
Dinh Nguyen (1):
usb: dwc2: Combine the dwc2 and s3c_hsotg into a single USB DRD
driver.
drivers/usb/dwc2/Kconfig | 35 +-
drivers/usb/dwc2/Makefile|2 +
drivers/usb/dwc2/core.c |1 +
drivers/usb/dwc2/core.h | 173 ++-
drivers/usb/dwc2/core_intr.c | 134 ++-
drivers/usb/dwc2/hcd.c |7 +-
drivers/usb/dwc2/hcd.h |1 +
drivers/usb/dwc2/hw.h| 23 +-
drivers/usb/dwc2/platform.c | 49 +-
drivers/usb/{gadget = dwc2}/s3c-hsotg.c | 1835 --
drivers/usb/gadget/Kconfig |7 -
drivers/usb/gadget/Makefile |1 -
drivers/usb/gadget/s3c-hsotg.h | 378 --
13 files changed, 1088 insertions(+), 1558 deletions(-)
rename drivers/usb/{gadget = dwc2}/s3c-hsotg.c (57%)
delete mode 100644 drivers/usb/gadget/s3c-hsotg.h
---
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Paul Zimmerman pa...@synopsys.com
Cc: Felipe Balbi ba...@ti.com
Cc: Ben Dooks ben-li...@fluff.org
Cc: Matt Porter mpor...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Matthijs Kooijman matth...@stdin.nl
Cc: Fengguang Wu fengguang...@intel.com
Cc: Dan Carpenter dan.carpen...@oracle.com
Cc: Wei Yongjun yongjun_...@trendmicro.com.cn
Cc: Wolfram Sang w...@the-dreams.de
Cc: Yijing Wang wangyij...@huawei.com
Cc: Ray Jui r...@broadcom.com
Cc: Julien Delacou julien.dela...@stericsson.com
Cc: Dom Cobley popcorn...@gmail.com
Cc: Rashika Kheria rashika.khe...@gmail.com
Cc: Jingoo Han jg1@samsung.com
Cc: Sachin Kamat sachin.ka...@linaro.org
Cc: Robert Baldyga r.bald...@samsung.com
Cc: Kishon Vijay Abraham I kis...@ti.com
--
1.7.9.5
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RE: [RFC PATCHv1] usb: dwc2: Combine the dwc2 and s3c_hsotg into a single USB DRD driver.
From: dingu...@altera.com [mailto:dingu...@altera.com] Sent: Tuesday, February 04, 2014 1:46 PM From: Dinh Nguyen dingu...@altera.com This means that the driver can be in host or peripheral mode when the appropriate connector is used. When an A-cable is plugged in, the driver behaves in host mode, and when a B-cable is used, the driver will be in peripheral mode. This commit: - Replaces in the defines used in s3c_hsotg.h with the defines used in the dwc2 hw.h defines. - Use the dw2_hsotg as the unified data structure for the host/gadget. - Uses the dwc2 IRQ handler for host/gadget. - A single spinlock. Hi Dinh, Putting all of these changes into a single patch makes them unreviewable as far I am concerned. You need to break this into a series of smaller patches. I would suggest something like this: 1 of n: Make the minimum changes to the dwc2 header files needed to support s3c-hsotg as a standalone driver. 2 of n: Make the spelling changes to s3c-hsotg.c needed to use the dwc2 headers, and move it to the dwc2/ directory. Make the Kconfig and Makefile changes needed for the move. Delete s3c-hsotg.h. 3 of n: Move the struct defines etc. from s3c-hsotg.c to the dwc2 header files. .. of n: Make the changes required to combine the functionality of both drivers into one. Preferably this would also be a series of patches instead of one big one. At each step of the series, both drivers should still compile and work. Also, please follow the patch style used on the linux lists. 'git format-patch --cover-letter' should do most of this for you automatically. And you should probably trim the Cc list to something more reasonable. -- Paul -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/9] Samsung clock PM consolidation part 1
Hi Tomasz, Are you planning to respin this series? It is not applying on mike's for-next. Regards, Rahul Sharma. On 16 October 2013 16:38, Tomasz Figa t.f...@samsung.com wrote: This series reworks suspend/resume handling of Samsung clock drivers to cover more SoC specific aspects that are beyond simple register save and restore. The goal is to have all the suspend/resume code that touches the clock controller in single place, which is the clock driver. On Exynos4210-based Trats, Exynos4412-based Trats2 and Exynos5250-based Arndale boards (except suspend/resume, which is broken because of unrelated reasons): Tested-by: Tomasz Figa t.f...@samsung.com Tomasz Figa (9): clk: exynos4: Remove remnants of non-DT support clk: samsung: Provide common helpers for register save/restore clk: samsung: exynos4: Move suspend/resume handling to SoC driver clk: samsung: exynos5250: Move suspend/resume handling to SoC driver clk: samsung: exynos5420: Move suspend/resume handling to SoC driver clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver clk: samsung: Drop old suspend/resume code clk: samsung: exynos4: Add remaining suspend/resume handling ARM: EXYNOS: pm: Drop legacy Exynos4 clock suspend/resume code arch/arm/mach-exynos/pm.c| 125 +- drivers/clk/samsung/clk-exynos4.c| 170 ++- drivers/clk/samsung/clk-exynos5250.c | 49 -- drivers/clk/samsung/clk-exynos5420.c | 49 -- drivers/clk/samsung/clk-exynos5440.c | 2 +- drivers/clk/samsung/clk-s3c64xx.c| 79 +--- drivers/clk/samsung/clk.c| 71 ++- drivers/clk/samsung/clk.h| 14 ++- 8 files changed, 346 insertions(+), 213 deletions(-) -- 1.8.3.2 ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Pankaj Dubey pankaj.du...@samsung.com
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/mach-exynos/Kconfig |9 +
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |1 +
6 files changed, 38 insertions(+)
mode change 100644 = 100755 arch/arm/mach-exynos/include/mach/map.h
mode change 100644 = 100755 arch/arm/mach-exynos/mach-exynos5-dt.c
mode change 100644 = 100755 arch/arm/plat-samsung/include/plat/cpu.h
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..5c96248 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,15 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5260
+ bool SAMSUNG EXYNOS5260
+ default y
+ depends on ARCH_EXYNOS5
+ select AUTO_ZRELADDR
+ select SAMSUNG_DMADEV
+ help
+ Enable EXYNOS5260 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 72ae5d3..4ee14ed 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5260[] = EXYNOS5260;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5260_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5260,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5260())
+ iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
old mode 100644
new mode 100755
index 7b046b5..bd6fa02
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5260_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
old mode 100644
new mode 100755
index 65a4646..18aee57
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5260,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
old mode 100644
new mode 100755
index 335beb3..60687aa
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5260_SOC_ID 0xE526
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define
[PATCH V2 3/3] ARM: dts: add dts files for xyref5260 board
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 +++
2 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fa70ea2..c513a69 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 000..b4c9c35
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,105 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5260.dtsi
+
+/ {
+ model = SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260;
+ compatible = samsung,xyref5260, samsung,exynos5260;
+
+ memory {
+ reg = 0x2000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: oscillator@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+ };
+
+ pinctrl@1160 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = gpx3-7;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ serial@12C0 {
+ status = okay;
+ };
+
+ serial@12C1 {
+ status = okay;
+ };
+
+ serial@12C2 {
+ status = okay;
+ };
+
+ serial@1286 {
+ status = okay;
+ };
+
+ mmc0@1214 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ fifo-depth = 0x40;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_rdqs sd0_clk sd0_cmd sd0_bus1 sd0_bus4
sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc2@1216 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x40;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+};
--
1.7.9.5
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[PATCH V2 2/3] ARM: dts: add dts files for exynos5260 SoC
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +
arch/arm/boot/dts/exynos5260.dtsi | 317
2 files changed, 889 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000..3f2c5c4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,572 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1160 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+
Re: [PATCH V2 0/3] exynos: arch: add support for exynos5260 SoC
On Wednesday, February 05, 2014 2:16 PM, Rahul Sharma wrote: This is re-spin of V2 which add arch-side support for exynos5260 SoC. V2: 1) Split up DT patch into SoC and Board patch. This series is based on Kukjin's for-next branch at http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git Pankaj Dubey (1): ARM: EXYNOS: initial board support for exynos5260 SoC Rahul Sharma (2): ARM: dts: add dts files for exynos5260 SoC ARM: dts: add dts files for xyref5260 board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 + arch/arm/boot/dts/exynos5260.dtsi | 317 + arch/arm/mach-exynos/Kconfig|9 + arch/arm/mach-exynos/common.c | 18 + arch/arm/mach-exynos/include/mach/map.h |1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/plat-samsung/include/plat/cpu.h|8 + arch/arm/plat-samsung/include/plat/map-s5p.h|1 + 10 files changed, 1033 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi mode change 100644 = 100755 arch/arm/mach-exynos/include/mach/map.h mode change 100644 = 100755 arch/arm/mach-exynos/mach-exynos5-dt.c mode change 100644 = 100755 arch/arm/plat-samsung/include/plat/cpu.h The mode of these three files should NOT be changed to 100755. Please fix it. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/9] Samsung clock PM consolidation part 1
Hi Rahul, On 05.02.2014 05:45, Rahul Sharma wrote: Hi Tomasz, Are you planning to respin this series? It is not applying on mike's for-next. Yes, I have already rebased it and was planning to resend it later today or tomorrow after checking one more thing. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [RFC PATCHv1] usb: dwc2: Combine the dwc2 and s3c_hsotg into a single USB DRD driver.
On Wed, 2014-02-05 at 00:42 +, Paul Zimmerman wrote: From: dingu...@altera.com [mailto:dingu...@altera.com] Sent: Tuesday, February 04, 2014 1:46 PM From: Dinh Nguyen dingu...@altera.com This means that the driver can be in host or peripheral mode when the appropriate connector is used. When an A-cable is plugged in, the driver behaves in host mode, and when a B-cable is used, the driver will be in peripheral mode. This commit: - Replaces in the defines used in s3c_hsotg.h with the defines used in the dwc2 hw.h defines. - Use the dw2_hsotg as the unified data structure for the host/gadget. - Uses the dwc2 IRQ handler for host/gadget. - A single spinlock. Hi Dinh, Putting all of these changes into a single patch makes them unreviewable as far I am concerned. You need to break this into a series of smaller patches. I would suggest something like this: 1 of n: Make the minimum changes to the dwc2 header files needed to support s3c-hsotg as a standalone driver. 2 of n: Make the spelling changes to s3c-hsotg.c needed to use the dwc2 headers, and move it to the dwc2/ directory. Make the Kconfig and Makefile changes needed for the move. Delete s3c-hsotg.h. 3 of n: Move the struct defines etc. from s3c-hsotg.c to the dwc2 header files. .. of n: Make the changes required to combine the functionality of both drivers into one. Preferably this would also be a series of patches instead of one big one. At each step of the series, both drivers should still compile and work. I agree. My original thought was to also split this patch, but I just didn't know how to split it. This is why I designated as an RFC. I was really looking for feedback as this is the correct way to combine this driver. I was also looking for testing purpose to make sure I did not break anything for the s3c platform. Also, please follow the patch style used on the linux lists. 'git format-patch --cover-letter' should do most of this for you automatically. I did use --cover-letter on this patch series. And you should probably trim the Cc list to something more reasonable. I looked through all the commits for the dwc2 driver for the cc list. I also CC a bunch of the Samsung people as I figured that the biggest impact of the work would affect the s3c folks. Dinh -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 0/3] exynos: arch: add support for exynos5260 SoC
Oops. Thanks Jingoo Han. On 5 February 2014 11:01, Jingoo Han jg1@samsung.com wrote: On Wednesday, February 05, 2014 2:16 PM, Rahul Sharma wrote: This is re-spin of V2 which add arch-side support for exynos5260 SoC. V2: 1) Split up DT patch into SoC and Board patch. This series is based on Kukjin's for-next branch at http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git Pankaj Dubey (1): ARM: EXYNOS: initial board support for exynos5260 SoC Rahul Sharma (2): ARM: dts: add dts files for exynos5260 SoC ARM: dts: add dts files for xyref5260 board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 + arch/arm/boot/dts/exynos5260.dtsi | 317 + arch/arm/mach-exynos/Kconfig|9 + arch/arm/mach-exynos/common.c | 18 + arch/arm/mach-exynos/include/mach/map.h |1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/plat-samsung/include/plat/cpu.h|8 + arch/arm/plat-samsung/include/plat/map-s5p.h|1 + 10 files changed, 1033 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi mode change 100644 = 100755 arch/arm/mach-exynos/include/mach/map.h mode change 100644 = 100755 arch/arm/mach-exynos/mach-exynos5-dt.c mode change 100644 = 100755 arch/arm/plat-samsung/include/plat/cpu.h The mode of these three files should NOT be changed to 100755. Please fix it. Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/3] exynos: arch: add support for exynos5260 SoC
This is re-spin of V2 which add arch-side support for exynos5260 SoC. V2: 1) Split up DT patch into SoC and Board patch. This series is based on Kukjin's for-next branch at http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git Pankaj Dubey (1): ARM: EXYNOS: initial board support for exynos5260 SoC Rahul Sharma (2): ARM: dts: add dts files for exynos5260 SoC ARM: dts: add dts files for xyref5260 board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 + arch/arm/boot/dts/exynos5260.dtsi | 317 + arch/arm/mach-exynos/Kconfig|9 + arch/arm/mach-exynos/common.c | 18 + arch/arm/mach-exynos/include/mach/map.h |1 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/plat-samsung/include/plat/cpu.h|8 + arch/arm/plat-samsung/include/plat/map-s5p.h|1 + 10 files changed, 1033 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/3] ARM: dts: add dts files for xyref5260 board
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 +++
2 files changed, 106 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fa70ea2..c513a69 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
new file mode 100644
index 000..b4c9c35
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
@@ -0,0 +1,105 @@
+/*
+ * SAMSUNG XYREF5260 EVT0 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5260.dtsi
+
+/ {
+ model = SAMSUNG XYREF5260 EVT0 board based on EXYNOS5260;
+ compatible = samsung,xyref5260, samsung,exynos5260;
+
+ memory {
+ reg = 0x2000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: oscillator@0 {
+ compatible = fixed-clock;
+ reg = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+ };
+
+ pinctrl@1160 {
+ hdmi_hpd_irq: hdmi-hpd-irq {
+ samsung,pins = gpx3-7;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ serial@12C0 {
+ status = okay;
+ };
+
+ serial@12C1 {
+ status = okay;
+ };
+
+ serial@12C2 {
+ status = okay;
+ };
+
+ serial@1286 {
+ status = okay;
+ };
+
+ mmc0@1214 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ supports-hs200-mode; /* 200 Mhz */
+ fifo-depth = 0x40;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_rdqs sd0_clk sd0_cmd sd0_bus1 sd0_bus4
sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc2@1216 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x40;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+};
--
1.7.9.5
--
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[PATCH v2 2/3] ARM: dts: add dts files for exynos5260 SoC
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +
arch/arm/boot/dts/exynos5260.dtsi | 317
2 files changed, 889 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000..3f2c5c4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,572 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1160 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+
[PATCH v2 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Pankaj Dubey pankaj.du...@samsung.com
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/mach-exynos/Kconfig |9 +
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |1 +
6 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af..5c96248 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -91,6 +91,15 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5260
+ bool SAMSUNG EXYNOS5260
+ default y
+ depends on ARCH_EXYNOS5
+ select AUTO_ZRELADDR
+ select SAMSUNG_DMADEV
+ help
+ Enable EXYNOS5260 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 72ae5d3..4ee14ed 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5260[] = EXYNOS5260;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5260_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5260,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5260())
+ iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..bd6fa02 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5260_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 65a4646..18aee57 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5260,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..60687aa 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5260_SOC_ID 0xE526
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250,
[PATCH v2] pinctrl: exynos: add exynos5260 SoC specific data
From: Young-Gun Jang yg1004.j...@samsung.com
Adds pinctrl support for all platforms based on EXYNOS5260 SoC.
Acked-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Young-Gun Jang yg1004.j...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 82
drivers/pinctrl/pinctrl-samsung.c |2 +
drivers/pinctrl/pinctrl-samsung.h |1 +
4 files changed, 86 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677d..2b32783 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
- samsung,exynos4210-pinctrl: for Exynos4210 compatible pin-controller.
- samsung,exynos4x12-pinctrl: for Exynos4x12 compatible pin-controller.
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
+ - samsung,exynos5260-pinctrl: for Exynos5260 compatible pin-controller.
- samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 155b1b3..07c8130 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
},
};
+/* pin banks of exynos5260 pin-controller 0 */
+static struct samsung_pin_bank exynos5260_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, gpb1, 0x10),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0a0, gpb2, 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0c0, gpb3, 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, gpb4, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, gpb5, 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd0, 0x24),
+ EXYNOS_PIN_BANK_EINTG(7, 0x140, gpd1, 0x28),
+ EXYNOS_PIN_BANK_EINTG(5, 0x160, gpd2, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x180, gpe0, 0x30),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1a0, gpe1, 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, gpf0, 0x38),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1e0, gpf1, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x200, gpk0, 0x40),
+ EXYNOS_PIN_BANK_EINTW(8, 0xc00, gpx0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xc20, gpx1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xc40, gpx2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xc60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5260 pin-controller 1 */
+static struct samsung_pin_bank exynos5260_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpc0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, gpc1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, gpc2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpc3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, gpc4, 0x10),
+};
+
+/* pin banks of exynos5260 pin-controller 2 */
+static struct samsung_pin_bank exynos5260_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
+ * three gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5260_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = exynos5260-gpio-ctrl0,
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5260_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+
Re: [PATCH] spi: Make core DMA mapping functions generate scatterlists
On Sunday, February 02, 2014 at 02:52:52 PM, Mark Brown wrote:
Hi, thanks for preparing this patch!
I have just a few very minor nitpicks, ignore if you please.
[...]
+static int spi_map_buf(struct spi_master *master, struct device *dev,
+struct sg_table *sgt, void *buf, size_t len,
+enum dma_data_direction dir)
+{
+ const bool vmalloced_buf = is_vmalloc_addr(buf);
+ const int desc_len = vmalloced_buf ? PAGE_SIZE : master-max_dma_len;
You might want to rename this to sg_chunk_max_size or something, desc_len
doesn't make much sense here. The variable describes the maximum size of one
single scatterlist element.
+ const int sgs = DIV_ROUND_UP(len, desc_len);
Looking at this, the variables could generally use a more meaningful name. I
think it'd be clearer to call this num_sg_chunks or so ?
+ struct page *vm_page;
+ void *sg_buf;
+ size_t min;
+ int i, ret;
+
+ ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);
+ if (ret != 0)
+ return ret;
+
+ for (i = 0; i sgs; i++) {
+ min = min_t(size_t, len, desc_len);
+
+ if (vmalloced_buf) {
+ vm_page = vmalloc_to_page(buf);
Just curious, but shouldn't we check if buf != NULL right at the begining of
this function?
[...]
+static void spi_unmap_buf(struct spi_master *master, struct device *dev,
+ struct sg_table *sgt, enum dma_data_direction dir)
+{
+ if (sgt-orig_nents) {
I don't want to nag, but why not use if (!sgt-...) return; ? This would cut
down one level of indent.
+ dma_unmap_sg(dev, sgt-sgl, sgt-orig_nents, dir);
+ sg_free_table(sgt);
+ }
+}
+
[...]
--
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