Re: [PATCH 1/2] cpufreq: exynos: Use dev_err/info function instead of pr_err/info
On 18 April 2014 07:50, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch uses dev_err/info function to show accurate log message with
device name
instead of pr_err/info function.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/cpufreq/exynos-cpufreq.c | 21 -
drivers/cpufreq/exynos-cpufreq.h | 1 +
2 files changed, 13 insertions(+), 9 deletions(-)
This still looks fine even if we don't take the new driver ?
Acked-by: Viresh Kumar viresh.ku...@linaro.org
diff --git a/drivers/cpufreq/exynos-cpufreq.c
b/drivers/cpufreq/exynos-cpufreq.c
index f99cfe2..8b4bb4a 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -49,6 +49,7 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
unsigned int arm_volt, safe_arm_volt = 0;
unsigned int mpll_freq_khz = exynos_info-mpll_freq_khz;
+ struct device *dev = exynos_info-dev;
unsigned int old_freq;
int index, old_index;
int ret = 0;
@@ -90,8 +91,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
/* Firstly, voltage up to increase frequency */
ret = regulator_set_voltage(arm_regulator, arm_volt,
arm_volt);
if (ret) {
- pr_err(%s: failed to set cpu voltage to %d\n,
- __func__, arm_volt);
+ dev_err(dev, failed to set cpu voltage to %d\n,
+ arm_volt);
return ret;
}
}
@@ -100,8 +101,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
safe_arm_volt);
if (ret) {
- pr_err(%s: failed to set cpu voltage to %d\n,
- __func__, safe_arm_volt);
+ dev_err(dev, failed to set cpu voltage to %d\n,
+ safe_arm_volt);
return ret;
}
}
@@ -115,8 +116,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
ret = regulator_set_voltage(arm_regulator, arm_volt,
arm_volt);
if (ret) {
- pr_err(%s: failed to set cpu voltage to %d\n,
- __func__, arm_volt);
+ dev_err(dev, failed to set cpu voltage to %d\n,
+ arm_volt);
goto out;
}
}
@@ -163,6 +164,8 @@ static int exynos_cpufreq_probe(struct platform_device
*pdev)
if (!exynos_info)
return -ENOMEM;
+ exynos_info-dev = pdev-dev;
+
if (soc_is_exynos4210())
ret = exynos4210_cpufreq_init(exynos_info);
else if (soc_is_exynos4212() || soc_is_exynos4412())
@@ -176,13 +179,13 @@ static int exynos_cpufreq_probe(struct platform_device
*pdev)
goto err_vdd_arm;
if (exynos_info-set_freq == NULL) {
- pr_err(%s: No set_freq function (ERR)\n, __func__);
+ dev_err(pdev-dev, No set_freq function (ERR)\n);
goto err_vdd_arm;
}
arm_regulator = regulator_get(NULL, vdd_arm);
if (IS_ERR(arm_regulator)) {
- pr_err(%s: failed to get resource vdd_arm\n, __func__);
+ dev_err(pdev-dev, failed to get resource vdd_arm\n);
goto err_vdd_arm;
}
@@ -192,7 +195,7 @@ static int exynos_cpufreq_probe(struct platform_device
*pdev)
if (!cpufreq_register_driver(exynos_driver))
return 0;
- pr_err(%s: failed to register cpufreq driver\n, __func__);
+ dev_err(pdev-dev, failed to register cpufreq driver\n);
regulator_put(arm_regulator);
err_vdd_arm:
kfree(exynos_info);
diff --git a/drivers/cpufreq/exynos-cpufreq.h
b/drivers/cpufreq/exynos-cpufreq.h
index 3ddade8..b72ff10 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -34,6 +34,7 @@ struct apll_freq {
};
struct exynos_dvfs_info {
+ struct device *dev;
unsigned long mpll_freq_khz;
unsigned intpll_safe_idx;
struct clk *cpu_clk;
--
1.8.0
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[PATCH 0/4] Add support for Exynos5800 SoC
Exynos5800 is a derivative of Exynos5420 with higher
clock speeds and most other IP blocks remaining the same
except for a few.
Due to the similarities with 5420, following is done to
achieve maximum code re-use:
- Use the same 5420 clock file with few changes for adding
extra 5800 clocks.
- Re-use the 5420 dtsi by renaming it to exynos5-octa.
This series is re-based on the 5420 clock cleanup series
posted by Shaik [1].
[1] http://www.spinics.net/lists/arm-kernel/msg318493.html
Alim Akhtar (1):
clk: exynos5420: Add 5800 specific clocks
Arun Kumar K (3):
ARM: EXYNOS: Add 5800 SoC support
ARM: dts: Add 5800 dt files
ARM: dts: Add peach-pi board support
.../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
arch/arm/boot/dts/Makefile |3 +-
...5420-pinctrl.dtsi = exynos5-octa-pinctrl.dtsi} |0
arch/arm/boot/dts/exynos5-octa.dtsi| 732
arch/arm/boot/dts/exynos5420.dtsi | 713 +--
arch/arm/boot/dts/exynos5800-peach-pi.dts | 225 ++
arch/arm/boot/dts/exynos5800.dtsi | 24 +
arch/arm/mach-exynos/Kconfig |8 +
arch/arm/mach-exynos/exynos.c |1 +
arch/arm/mach-exynos/platsmp.c |2 +-
arch/arm/plat-samsung/include/plat/cpu.h | 11 +-
drivers/clk/samsung/clk-exynos5420.c | 276 ++--
include/dt-bindings/clock/exynos5420.h |4 +
13 files changed, 1230 insertions(+), 772 deletions(-)
rename arch/arm/boot/dts/{exynos5420-pinctrl.dtsi =
exynos5-octa-pinctrl.dtsi} (100%)
create mode 100644 arch/arm/boot/dts/exynos5-octa.dtsi
create mode 100644 arch/arm/boot/dts/exynos5800-peach-pi.dts
create mode 100644 arch/arm/boot/dts/exynos5800.dtsi
--
1.7.9.5
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[PATCH 1/4] ARM: EXYNOS: Add 5800 SoC support
Exynos5800 is an octa core SoC which is based on the 5420
platform. This patch adds the basic SoC support.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
arch/arm/mach-exynos/Kconfig |8
arch/arm/mach-exynos/exynos.c|1 +
arch/arm/mach-exynos/platsmp.c |2 +-
arch/arm/plat-samsung/include/plat/cpu.h | 11 ++-
4 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18..84f2b8e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -108,6 +108,14 @@ config SOC_EXYNOS5440
help
Enable EXYNOS5440 SoC support
+config SOC_EXYNOS5800
+ bool SAMSUNG EXYNOS5800
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ help
+ Enable EXYNOS5800 SoC support
+
endmenu
endif
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907..2bda44d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -378,6 +378,7 @@ static char const *exynos_dt_compat[] __initconst = {
samsung,exynos5250,
samsung,exynos5420,
samsung,exynos5440,
+ samsung,exynos5800,
NULL
};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..d14be39 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -47,7 +47,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
- else if (soc_is_exynos5420())
+ else if (soc_is_exynos5420() || soc_is_exynos5800())
boot_reg += 4;
return boot_reg;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8d..b1fe0b7 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -51,6 +51,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS5250_SOC_ID 0x4352
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
+#define EXYNOS5800_SOC_ID 0xE5422000
#define EXYNOS5_SOC_MASK 0xF000
#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -74,6 +75,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -160,6 +162,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
# define soc_is_exynos5420() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS5800)
+# define soc_is_exynos5800() is_samsung_exynos5800()
+#else
+# define soc_is_exynos5800() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS5440)
# define soc_is_exynos5440() is_samsung_exynos5440()
#else
@@ -168,7 +176,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
EXYNOS5_SOC_MASK)
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420() || \
+ soc_is_exynos5800())
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x,
__phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
--
1.7.9.5
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[PATCH 4/4] ARM: dts: Add peach-pi board support
Adds support for google peach-pi board having the
Exynos5800 SoC.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile|3 +-
arch/arm/boot/dts/exynos5800-peach-pi.dts | 225 +
2 files changed, 227 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos5800-peach-pi.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c17cf4b..6ed6467 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -77,7 +77,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
exynos5440-sd5v1.dtb \
- exynos5440-ssdk5440.dtb
+ exynos5440-ssdk5440.dtb \
+ exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
new file mode 100644
index 000..3ea6c8a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,225 @@
+/*
+ * Google Peach Pi Rev 10+ board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include include/dt-bindings/input/input.h
+#include exynos5800.dtsi
+
+/ {
+ model = Google Peach Pi Rev 10+;
+
+ compatible = google,pi-rev16,
+ google,pi-rev15, google,pi-rev14,
+ google,pi-rev13, google,pi-rev12,
+ google,pi-rev11, google,pi-rev10,
+ google,pi, google,peach, samsung,exynos5800,
+ samsung,exynos5;
+
+ memory {
+ reg = 0x2000 0xE000;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5420-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ pinctrl@1340 {
+ lid_irq: lid-irq {
+ samsung,pins = gpx3-4;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ power_key_irq: power-key-irq {
+ samsung,pins = gpx1-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ tpm_irq: tpm-irq {
+ samsung,pins = gpx1-0;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ pinctrl@1401 {
+ spi_flash_cs: spi-flash-cs {
+ samsung,pins = gpa2-5;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 3;
+ };
+
+ backlight_pwm: backlight-pwm {
+ samsung,pins = gpb2-0;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ gpio-keys {
+ compatible = gpio-keys;
+
+ pinctrl-names = default;
+ pinctrl-0 = power_key_irq lid_irq;
+
+ power {
+ label = Power;
+ gpios = gpx1 2 1;
+ linux,code = KEY_POWER;
+ gpio-key,wakeup;
+ };
+
+ lid-switch {
+ label = Lid;
+ gpios = gpx3 4 1;
+ linux,input-type = 5; /* EV_SW */
+ linux,code = 0; /* SW_LID */
+ debounce-interval = 1;
+ gpio-key,wakeup;
+ };
+ };
+
+ rtc@101E {
+ status = okay;
+ };
+
+ serial@12C3 {
+ status = okay;
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_bus4 sd0_bus8;
+
+ slot@0 {
+ reg = 0;
+ bus-width =
[PATCH 2/4] clk: exynos5420: Add 5800 specific clocks
From: Alim Akhtar alim.akh...@samsung.com
Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
drivers/clk/samsung/clk-exynos5420.c | 276
include/dt-bindings/clock/exynos5420.h |4 +
3 files changed, 224 insertions(+), 59 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index ca88c97..d54f42c 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -1,12 +1,13 @@
* Samsung Exynos5420 Clock Controller
The Exynos5420 clock controller generates and supplies clock to various
-controllers within the Exynos5420 SoC.
+controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
Required Properties:
- compatible: should be one of the following.
- samsung,exynos5420-clock - controller compatible with Exynos5420 SoC.
+ - samsung,exynos5800-clock - controller compatible with Exynos5800 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index ddf01c2..4b21451 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -59,15 +59,19 @@
#define SRC_TOP5 0x10214
#define SRC_TOP6 0x10218
#define SRC_TOP7 0x1021c
+#define SRC_TOP8 0x10220 /* 5800 specific */
+#define SRC_TOP9 0x10224 /* 5800 specific */
#define SRC_DISP10 0x1022c
#define SRC_MAU0x10240
#define SRC_FSYS 0x10244
#define SRC_PERIC0 0x10250
#define SRC_PERIC1 0x10254
#define SRC_ISP0x10270
+#define SRC_CAM0x10274 /* 5800 specific */
#define SRC_TOP10 0x10280
#define SRC_TOP11 0x10284
#define SRC_TOP12 0x10288
+#define SRC_TOP13 0x1028c
#define SRC_MASK_TOP2 0x10308
#define SRC_MASK_DISP100x1032c
#define SRC_MASK_MAU 0x10334
@@ -77,6 +81,8 @@
#define DIV_TOP0 0x10500
#define DIV_TOP1 0x10504
#define DIV_TOP2 0x10508
+#define DIV_TOP8 0x10520 /* 5800 specific */
+#define DIV_TOP9 0x10524 /* 5800 specific */
#define DIV_DISP10 0x1052c
#define DIV_MAU0x10544
#define DIV_FSYS0 0x10548
@@ -87,6 +93,7 @@
#define DIV_PERIC2 0x10560
#define DIV_PERIC3 0x10564
#define DIV_PERIC4 0x10568
+#define DIV_CAM0x10574 /* 5800 specific */
#define SCLK_DIV_ISP0 0x10580
#define SCLK_DIV_ISP1 0x10584
#define DIV2_RATIO00x10590
@@ -108,6 +115,7 @@
#define GATE_TOP_SCLK_ISP 0x10870
#define GATE_IP_GSCL0 0x10910
#define GATE_IP_GSCL1 0x10920
+#define GATE_IP_CAM0x10924 /* 5800 specific */
#define GATE_IP_MFC0x1092c
#define GATE_IP_DISP1 0x10928
#define GATE_IP_G3D0x10930
@@ -130,8 +138,14 @@
#define SRC_KFC0x28200
#define DIV_KFC0 0x28500
+/* Exynos5x SoC type */
+enum exynos5x_soc {
+ EXYNOS5420,
+ EXYNOS5800,
+};
+
/* list of PLLs */
-enum exynos5420_plls {
+enum exynos5x_plls {
apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
bpll, kpll,
nr_plls /* number of PLLs */
@@ -140,13 +154,13 @@ enum exynos5420_plls {
static void __iomem *reg_base;
#ifdef CONFIG_PM_SLEEP
-static struct samsung_clk_reg_dump *exynos5420_save;
+static struct samsung_clk_reg_dump *exynos5x_save;
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
-static unsigned long exynos5420_clk_regs[] __initdata = {
+static unsigned long exynos5x_clk_regs[] __initdata = {
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
@@ -235,16 +249,16 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
static int exynos5420_clk_suspend(void)
{
- samsung_clk_save(reg_base, exynos5420_save,
- ARRAY_SIZE(exynos5420_clk_regs));
+ samsung_clk_save(reg_base, exynos5x_save,
+ ARRAY_SIZE(exynos5x_clk_regs));
return 0;
}
static void exynos5420_clk_resume(void)
{
- samsung_clk_restore(reg_base, exynos5420_save,
-
[PATCH 3/4] ARM: dts: Add 5800 dt files
Most of the nodes of exynos5420 remains same for exynos5800.
So moving the common dt nodes to exynos5-octa.dtsi.
The pinctrl dtsi is completely re-used and is renamed to
exynos5-octa-pinctrl.dtsi.
Signed-off-by: Arun Kumar K arun...@samsung.com
---
...5420-pinctrl.dtsi = exynos5-octa-pinctrl.dtsi} |0
arch/arm/boot/dts/exynos5-octa.dtsi| 732
arch/arm/boot/dts/exynos5420.dtsi | 713 +--
arch/arm/boot/dts/exynos5800.dtsi | 24 +
4 files changed, 759 insertions(+), 710 deletions(-)
rename arch/arm/boot/dts/{exynos5420-pinctrl.dtsi =
exynos5-octa-pinctrl.dtsi} (100%)
create mode 100644 arch/arm/boot/dts/exynos5-octa.dtsi
create mode 100644 arch/arm/boot/dts/exynos5800.dtsi
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5-octa-pinctrl.dtsi
similarity index 100%
rename from arch/arm/boot/dts/exynos5420-pinctrl.dtsi
rename to arch/arm/boot/dts/exynos5-octa-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos5-octa.dtsi
b/arch/arm/boot/dts/exynos5-octa.dtsi
new file mode 100644
index 000..4b606ad
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5-octa.dtsi
@@ -0,0 +1,732 @@
+/*
+ * SAMSUNG EXYNOS5 Octa SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5 Octa SoC device nodes are listed in this file.
+ * EXYNOS5420 and EXYNOS5800 based board files can include this
+ * file and provide values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5420.h
+#include exynos5.dtsi
+#include exynos5-octa-pinctrl.dtsi
+
+#include dt-bindings/clock/exynos-audss-clk.h
+
+/ {
+ aliases {
+ mshc0 = mmc_0;
+ mshc1 = mmc_1;
+ mshc2 = mmc_2;
+ pinctrl0 = pinctrl_0;
+ pinctrl1 = pinctrl_1;
+ pinctrl2 = pinctrl_2;
+ pinctrl3 = pinctrl_3;
+ pinctrl4 = pinctrl_4;
+ i2c0 = i2c_0;
+ i2c1 = i2c_1;
+ i2c2 = i2c_2;
+ i2c3 = i2c_3;
+ i2c4 = hsi2c_4;
+ i2c5 = hsi2c_5;
+ i2c6 = hsi2c_6;
+ i2c7 = hsi2c_7;
+ i2c8 = hsi2c_8;
+ i2c9 = hsi2c_9;
+ i2c10 = hsi2c_10;
+ gsc0 = gsc_0;
+ gsc1 = gsc_1;
+ spi0 = spi_0;
+ spi1 = spi_1;
+ spi2 = spi_2;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x0;
+ clock-frequency = 18;
+ };
+
+ cpu1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x1;
+ clock-frequency = 18;
+ };
+
+ cpu2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x2;
+ clock-frequency = 18;
+ };
+
+ cpu3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0x3;
+ clock-frequency = 18;
+ };
+
+ cpu4: cpu@100 {
+ device_type = cpu;
+ compatible = arm,cortex-a7;
+ reg = 0x100;
+ clock-frequency = 10;
+ };
+
+ cpu5: cpu@101 {
+ device_type = cpu;
+ compatible = arm,cortex-a7;
+ reg = 0x101;
+ clock-frequency = 10;
+ };
+
+ cpu6: cpu@102 {
+ device_type = cpu;
+ compatible = arm,cortex-a7;
+ reg = 0x102;
+ clock-frequency = 10;
+ };
+
+ cpu7: cpu@103 {
+ device_type = cpu;
+ compatible = arm,cortex-a7;
+ reg = 0x103;
+ clock-frequency = 10;
+ };
+ };
+
+ clock: clock-controller@1001 {
+ compatible = samsung,exynos5420-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+ clock_audss: audss-clock-controller@381 {
+ compatible =
Re: [PATCH 1/2] cpufreq: exynos: Use dev_err/info function instead of pr_err/info
On 04/21/2014 03:05 PM, Viresh Kumar wrote: On 18 April 2014 07:50, Chanwoo Choi cw00.c...@samsung.com wrote: This patch uses dev_err/info function to show accurate log message with device name instead of pr_err/info function. Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/cpufreq/exynos-cpufreq.c | 21 - drivers/cpufreq/exynos-cpufreq.h | 1 + 2 files changed, 13 insertions(+), 9 deletions(-) This still looks fine even if we don't take the new driver ? Acked-by: Viresh Kumar viresh.ku...@linaro.org Thanks for your review. Best regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4] arm: exynos: generalize power register address calculation
Currently status/configuration power register values are hard-coded for cpu1.
Make it generic so that it is useful for SoC's with more than two cpus.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.org
---
changes in v4:
1: Dropped changes in platsmp.c and hotplug.c as those are taken care by
Tomasz Patches.
2. Converted ENYNOS_PMU_CPUNR macro to static inline function
changes in v3:
1. Move cpunr calculation to a macro
2. Changed printk format specifier from unsigned hex to unsigned decimal
Changes in v2:
1. Used existing macros for clusterid and cpuid calculation
arch/arm/mach-exynos/regs-pmu.h | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..f39e78c 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,13 @@
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+ (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
+#define S5P_ARM_CORE_STATUS(_cpunr) \
+ (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr))
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
#define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
@@ -313,4 +318,13 @@
#define EXYNOS5_OPTION_USE_RETENTION (1 4)
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int enynos_pmu_cpunr(unsigned int mpidr)
+{
+ return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
#endif /* __ASM_ARCH_REGS_PMU_H */
--
1.7.9.5
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[PATCH v2 1/2] v4l: Add resolution change event.
From: Pawel Osciak posc...@chromium.org
This event indicates that the decoder has reached a point in the stream,
at which the resolution changes. The userspace is expected to provide a new
set of CAPTURE buffers for the new format before decoding can continue.
The event can also be used for more generic events involving resolution
or format changes at runtime for all kinds of video devices.
Signed-off-by: Pawel Osciak posc...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../DocBook/media/v4l/vidioc-subscribe-event.xml | 16
include/uapi/linux/videodev2.h |6 ++
2 files changed, 22 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
index 5c70b61..0aec831 100644
--- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
+++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
@@ -155,6 +155,22 @@
/entry
/row
row
+ entryconstantV4L2_EVENT_SOURCE_CHANGE/constant/entry
+ entry5/entry
+ entry
+ paraThis event is triggered when a resolution or format change
+ is detected during runtime by the video device. It can be a
+ runtime resolution change triggered by a video decoder or the
+ format change happening on an HDMI connector. Application may
+ need to reinitialize buffers before proceeding further./para
+
+ paraThis event has a v4l2-event-source-change; associated
+ with it. This has significance only for v4l2 subdevs where the
+ structfieldpad_num/structfield field will be updated with
+ the pad number on which the event is triggered./para
+ /entry
+ /row
+ row
entryconstantV4L2_EVENT_PRIVATE_START/constant/entry
entry0x0800/entry
entryBase event number for driver-private events./entry
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 6ae7bbe..12e0614 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1733,6 +1733,7 @@ struct v4l2_streamparm {
#define V4L2_EVENT_EOS 2
#define V4L2_EVENT_CTRL3
#define V4L2_EVENT_FRAME_SYNC 4
+#define V4L2_EVENT_SOURCE_CHANGE 5
#define V4L2_EVENT_PRIVATE_START 0x0800
/* Payload for V4L2_EVENT_VSYNC */
@@ -1764,12 +1765,17 @@ struct v4l2_event_frame_sync {
__u32 frame_sequence;
};
+struct v4l2_event_source_change {
+ __u32 pad_num;
+};
+
struct v4l2_event {
__u32 type;
union {
struct v4l2_event_vsync vsync;
struct v4l2_event_ctrl ctrl;
struct v4l2_event_frame_syncframe_sync;
+ struct v4l2_event_source_change source_change;
__u8data[64];
} u;
__u32 pending;
--
1.7.9.5
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Re: [PATCH v2 1/2] v4l: Add resolution change event.
Hi Pawel, On Mon, Apr 21, 2014 at 2:58 PM, Pawel Osciak posc...@chromium.org wrote: Arun, I think it'd better if you attributed this patch to yourself, I'm not the author of it. I only wrote patch 2/2 in this series. Thanks, Pawel Sure I will change it. I kept your name as it was a rework of your patch from chrome tree. Will update the author name and post v3 if there are no other comments on this. Regards Arun -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] v4l: Add resolution change event.
Hi Arun,
Thank you for the patch.
On Monday 21 April 2014 14:56:01 Arun Kumar K wrote:
From: Pawel Osciak posc...@chromium.org
This event indicates that the decoder has reached a point in the stream,
at which the resolution changes. The userspace is expected to provide a new
set of CAPTURE buffers for the new format before decoding can continue.
The event can also be used for more generic events involving resolution
or format changes at runtime for all kinds of video devices.
Signed-off-by: Pawel Osciak posc...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../DocBook/media/v4l/vidioc-subscribe-event.xml | 16
include/uapi/linux/videodev2.h |6 ++
2 files changed, 22 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml index
5c70b61..0aec831 100644
--- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
+++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
@@ -155,6 +155,22 @@
/entry
/row
row
+ entryconstantV4L2_EVENT_SOURCE_CHANGE/constant/entry
+ entry5/entry
+ entry
+ paraThis event is triggered when a resolution or format change
+is detected during runtime by the video device. It can be a
+runtime resolution change triggered by a video decoder or the
+format change happening on an HDMI connector. Application may
+need to reinitialize buffers before proceeding further./para
+
+ paraThis event has a v4l2-event-source-change; associated
+ with it. This has significance only for v4l2 subdevs where the
+ structfieldpad_num/structfield field will be updated with
+ the pad number on which the event is triggered./para
+ /entry
+ /row
+ row
entryconstantV4L2_EVENT_PRIVATE_START/constant/entry
entry0x0800/entry
entryBase event number for driver-private events./entry
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 6ae7bbe..12e0614 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1733,6 +1733,7 @@ struct v4l2_streamparm {
#define V4L2_EVENT_EOS 2
#define V4L2_EVENT_CTRL 3
#define V4L2_EVENT_FRAME_SYNC4
+#define V4L2_EVENT_SOURCE_CHANGE 5
#define V4L2_EVENT_PRIVATE_START 0x0800
/* Payload for V4L2_EVENT_VSYNC */
@@ -1764,12 +1765,17 @@ struct v4l2_event_frame_sync {
__u32 frame_sequence;
};
+struct v4l2_event_source_change {
+ __u32 pad_num;
I would call the field just pad,
+};
+
struct v4l2_event {
__u32 type;
union {
struct v4l2_event_vsync vsync;
struct v4l2_event_ctrl ctrl;
struct v4l2_event_frame_syncframe_sync;
+ struct v4l2_event_source_change source_change;
__u8data[64];
This looks pretty good to me, but I'm a bit concerned about future
compatibility. We might need to report more information to userspace, and in
particular what has been changed at the source (resolution, format, ...). In
order to do so, we'll need to add a flag field to v4l2_event_source_change.
The next __u32 right after the source_change field must thus be zeroed. I see
two ways of doing so:
- zeroing the whole data array before setting event-specific data
- adding a reserved must-be-zeroed field to v4l2_event_source_change
I like the former better as it's more generic, but we then need to ensure that
all drivers zero the whole data field correctly. Adding a new
v4l2_event_init() function would help with that.
} u;
__u32 pending;
--
Regards,
Laurent Pinchart
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[PATCH 2/4] driver: cpuidle: cpuidle-big-little: init driver for Exynos5420
Add samsung,exynos5420 compatible string to initialize generic big-little cpuidle driver for Exynos5420. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Chander Kashyap k.chan...@samsung.org --- drivers/cpuidle/cpuidle-big_little.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c index b45fc62..d0fac53 100644 --- a/drivers/cpuidle/cpuidle-big_little.c +++ b/drivers/cpuidle/cpuidle-big_little.c @@ -170,7 +170,8 @@ static int __init bl_idle_init(void) /* * Initialize the driver just for a compliant set of machines */ - if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7)) + if (!of_machine_is_compatible(arm,vexpress,v2p-ca15_a7) + (!of_machine_is_compatible(samsung,exynos5420))) return -ENODEV; /* * For now the differentiation between little and big cores -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/4] add cpuidle support for Exynos5420
Exynos5420 is a big-little Soc from Samsung. It has 4 A15 and 4 A7 cores. This patchset adds cpuidle support for Exynos5420 SoC based on generic big.little cpuidle driver. Tested on SMDK5420. This patch set depends on: 1. [PATCH 0/5] MCPM backend for Exynos5420 http://www.spinics.net/lists/arm-kernel/msg321666.html 2. [PATCH v4] arm: exynos: generalize power register address calculation http://www.spinics.net/lists/arm-kernel/msg324024.html Chander Kashyap (4): cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver driver: cpuidle: cpuidle-big-little: init driver for Exynos5420 exynos: cpuidle: do not allow cpuidle registration for Exynos5420 mcpm: exynos: populate suspend and powered_up callbacks arch/arm/mach-exynos/cpuidle.c |3 ++ arch/arm/mach-exynos/mcpm-exynos.c | 53 ++ drivers/cpuidle/Kconfig.arm |2 +- drivers/cpuidle/cpuidle-big_little.c |3 +- 4 files changed, 59 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] v4l: Add resolution change event.
Hi Laurent,
Thank you for the review.
On Mon, Apr 21, 2014 at 3:54 PM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
Hi Arun,
Thank you for the patch.
On Monday 21 April 2014 14:56:01 Arun Kumar K wrote:
From: Pawel Osciak posc...@chromium.org
This event indicates that the decoder has reached a point in the stream,
at which the resolution changes. The userspace is expected to provide a new
set of CAPTURE buffers for the new format before decoding can continue.
The event can also be used for more generic events involving resolution
or format changes at runtime for all kinds of video devices.
Signed-off-by: Pawel Osciak posc...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../DocBook/media/v4l/vidioc-subscribe-event.xml | 16
include/uapi/linux/videodev2.h |6 ++
2 files changed, 22 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml index
5c70b61..0aec831 100644
--- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
+++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
@@ -155,6 +155,22 @@
/entry
/row
row
+ entryconstantV4L2_EVENT_SOURCE_CHANGE/constant/entry
+ entry5/entry
+ entry
+ paraThis event is triggered when a resolution or format change
+is detected during runtime by the video device. It can be a
+runtime resolution change triggered by a video decoder or the
+format change happening on an HDMI connector. Application may
+need to reinitialize buffers before proceeding further./para
+
+ paraThis event has a v4l2-event-source-change; associated
+ with it. This has significance only for v4l2 subdevs where the
+ structfieldpad_num/structfield field will be updated with
+ the pad number on which the event is triggered./para
+ /entry
+ /row
+ row
entryconstantV4L2_EVENT_PRIVATE_START/constant/entry
entry0x0800/entry
entryBase event number for driver-private events./entry
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 6ae7bbe..12e0614 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1733,6 +1733,7 @@ struct v4l2_streamparm {
#define V4L2_EVENT_EOS 2
#define V4L2_EVENT_CTRL 3
#define V4L2_EVENT_FRAME_SYNC4
+#define V4L2_EVENT_SOURCE_CHANGE 5
#define V4L2_EVENT_PRIVATE_START 0x0800
/* Payload for V4L2_EVENT_VSYNC */
@@ -1764,12 +1765,17 @@ struct v4l2_event_frame_sync {
__u32 frame_sequence;
};
+struct v4l2_event_source_change {
+ __u32 pad_num;
I would call the field just pad,
Ok.
+};
+
struct v4l2_event {
__u32 type;
union {
struct v4l2_event_vsync vsync;
struct v4l2_event_ctrl ctrl;
struct v4l2_event_frame_syncframe_sync;
+ struct v4l2_event_source_change source_change;
__u8data[64];
This looks pretty good to me, but I'm a bit concerned about future
compatibility. We might need to report more information to userspace, and in
particular what has been changed at the source (resolution, format, ...). In
order to do so, we'll need to add a flag field to v4l2_event_source_change.
Ok a flag can be added with bitfields for reporting specific event type.
The next __u32 right after the source_change field must thus be zeroed. I see
two ways of doing so:
- zeroing the whole data array before setting event-specific data
- adding a reserved must-be-zeroed field to v4l2_event_source_change
I like the former better as it's more generic, but we then need to ensure that
all drivers zero the whole data field correctly. Adding a new
v4l2_event_init() function would help with that.
Is that a good idea to have an init() function just for zeroing the data field?
If this is agreed upon, I can add this, but it can be easily missed
out by drivers.
Also how about the drivers already using the v4l2_event. Should we
update those drivers too with v4l2_event_init() ?
Regards
Arun
} u;
__u32 pending;
--
Regards,
Laurent Pinchart
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[PATCH 3/4] exynos: cpuidle: do not allow cpuidle registration for Exynos5420
Exynos5420 is big.Little Soc. It uses cpuidle-big-litle generic cpuidle driver. Hence do not allow exynos cpuidle driver registration for Exynos5420. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Chander Kashyap k.chan...@samsung.com --- arch/arm/mach-exynos/cpuidle.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index c57cae0..242f75d 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -219,6 +219,9 @@ static int exynos_cpuidle_probe(struct platform_device *pdev) int cpu_id, ret; struct cpuidle_device *device; + if (soc_is_exynos5420()) + return -ENODEV; + if (soc_is_exynos5250()) exynos5_core_down_clk(); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] mcpm: exynos: populate suspend and powered_up callbacks
In order to support cpuidle through mcpm, suspend and powered-up
callbacks are required in mcpm platform code.
Hence populate the same callbacks.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/mcpm-exynos.c | 53
1 file changed, 53 insertions(+)
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index 46d4968..16af0bd 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -318,10 +318,63 @@ static int exynos_power_down_finish(unsigned int cpu,
unsigned int cluster)
return 0; /* success: the CPU is halted */
}
+static void enable_coherency(void)
+{
+ unsigned long v, u;
+
+ asm volatile(
+ mrcp15, 0, %0, c1, c0, 1\n
+ orr%0, %0, %2\n
+ ldr%1, [%3]\n
+ and%1, %1, #0\n
+ orr%0, %0, %1\n
+ mcrp15, 0, %0, c1, c0, 1\n
+ : =r (v), =r (u)
+ : Ir (0x40), Ir (S5P_INFORM0)
+ : cc);
+}
+
+void exynos_powered_up(void)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ arch_spin_lock(bl_lock);
+ if (cpu_use_count[cpu][cluster] == 0)
+ cpu_use_count[cpu][cluster] = 1;
+ arch_spin_unlock(bl_lock);
+}
+
+static void exynos_suspend(u64 residency)
+{
+ unsigned int mpidr, cpunr;
+
+ mpidr = read_cpuid_mpidr();
+ cpunr = enynos_pmu_cpunr(mpidr);
+
+ __raw_writel(virt_to_phys(mcpm_entry_point), REG_ENTRY_ADDR);
+
+ exynos_power_down();
+
+ /*
+* Execution reaches here only if cpu did not power down.
+* Hence roll back the changes done in exynos_power_down function.
+ */
+ __raw_writel(EXYNOS_CORE_LOCAL_PWR_EN,
+ EXYNOS_ARM_CORE_CONFIGURATION(cpunr));
+ set_cr(get_cr() | CR_C);
+ enable_coherency();
+}
+
static const struct mcpm_platform_ops exynos_power_ops = {
.power_up = exynos_power_up,
.power_down = exynos_power_down,
.power_down_finish = exynos_power_down_finish,
+ .suspend= exynos_suspend,
+ .powered_up = exynos_powered_up,
};
static void __init exynos_mcpm_usage_count_init(void)
--
1.7.9.5
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[PATCH 1/4] cpuidle: config: Add SOC_EXYNOS5420 entry to select cpuidle-big-little driver
Exynos5420 is a big-little SoC from Samsung. It has 4 A15 and 4 A7 cores. In order to use generic cpuidle-big-little driver, this patch adds Exynos5420 specific check to initialize generic cpuidle driver. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Chander Kashyap k.chan...@samsung.com --- drivers/cpuidle/Kconfig.arm |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 97ccc31..5244d87 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -4,7 +4,7 @@ config ARM_BIG_LITTLE_CPUIDLE bool Support for ARM big.LITTLE processors - depends on ARCH_VEXPRESS_TC2_PM + depends on ARCH_VEXPRESS_TC2_PM || SOC_EXYNOS5420 select ARM_CPU_SUSPEND select CPU_IDLE_MULTIPLE_DRIVERS help -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] usb: ohci-exynos: Make provision for vdd regulators
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for smdk5250,
certain perripherals will now need to ensure that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ohci-exynos.c | 47
1 file changed, 47 insertions(+)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 68588d8..e2e72a8 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -18,6 +18,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/regulator/consumer.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
#include linux/usb.h
@@ -37,6 +38,8 @@ struct exynos_ohci_hcd {
struct clk *clk;
struct usb_phy *phy;
struct usb_otg *otg;
+ struct regulator *vdd33;
+ struct regulator *vdd10;
};
static void exynos_ohci_phy_enable(struct platform_device *pdev)
@@ -98,6 +101,28 @@ static int exynos_ohci_probe(struct platform_device *pdev)
exynos_ohci-otg = phy-otg;
}
+ exynos_ohci-vdd33 = devm_regulator_get(pdev-dev, vdd33);
+ if (IS_ERR(exynos_ohci-vdd33)) {
+ err = PTR_ERR(exynos_ohci-vdd33);
+ goto fail_regulator1;
+ }
+ err = regulator_enable(exynos_ohci-vdd33);
+ if (err) {
+ dev_err(pdev-dev, Failed to enable VDD33 supply\n);
+ goto fail_regulator1;
+ }
+
+ exynos_ohci-vdd10 = devm_regulator_get(pdev-dev, vdd10);
+ if (IS_ERR(exynos_ohci-vdd10)) {
+ err = PTR_ERR(exynos_ohci-vdd10);
+ goto fail_regulator2;
+ }
+ err = regulator_enable(exynos_ohci-vdd10);
+ if (err) {
+ dev_err(pdev-dev, Failed to enable VDD10 supply\n);
+ goto fail_regulator2;
+ }
+
skip_phy:
exynos_ohci-clk = devm_clk_get(pdev-dev, usbhost);
@@ -154,6 +179,10 @@ fail_add_hcd:
fail_io:
clk_disable_unprepare(exynos_ohci-clk);
fail_clk:
+ regulator_disable(exynos_ohci-vdd10);
+fail_regulator2:
+ regulator_disable(exynos_ohci-vdd33);
+fail_regulator1:
usb_put_hcd(hcd);
return err;
}
@@ -172,6 +201,9 @@ static int exynos_ohci_remove(struct platform_device *pdev)
clk_disable_unprepare(exynos_ohci-clk);
+ regulator_disable(exynos_ohci-vdd10);
+ regulator_disable(exynos_ohci-vdd33);
+
usb_put_hcd(hcd);
return 0;
@@ -208,6 +240,9 @@ static int exynos_ohci_suspend(struct device *dev)
clk_disable_unprepare(exynos_ohci-clk);
+ regulator_disable(exynos_ohci-vdd10);
+ regulator_disable(exynos_ohci-vdd33);
+
spin_unlock_irqrestore(ohci-lock, flags);
return 0;
@@ -218,6 +253,18 @@ static int exynos_ohci_resume(struct device *dev)
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
struct platform_device *pdev= to_platform_device(dev);
+ int ret;
+
+ ret = regulator_enable(exynos_ohci-vdd33);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD33 supply\n);
+ return ret;
+ }
+ ret = regulator_enable(exynos_ohci-vdd10);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD10 supply\n);
+ return ret;
+ }
clk_prepare_enable(exynos_ohci-clk);
--
1.7.10.4
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[PATCH 3/3] usb: dwc3-exynos: Make provision for vdd regulators
Facilitate getting required 3.3V and 1.0V VDD supply for
DWC3 controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for smdk5250,
certain perripherals will now need to ensure that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Anton Tikhomirov av.tikhomi...@samsung.com
---
Based on 'usb-next' branch of Greg's USB tree.
Also cleanly applies on 'next' branch of Balbi's USB tree.
drivers/usb/dwc3/dwc3-exynos.c | 51 ++--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 28c8ad7..c9d9102 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -27,6 +27,7 @@
#include linux/usb/usb_phy_gen_xceiv.h
#include linux/of.h
#include linux/of_platform.h
+#include linux/regulator/consumer.h
struct dwc3_exynos {
struct platform_device *usb2_phy;
@@ -34,6 +35,8 @@ struct dwc3_exynos {
struct device *dev;
struct clk *clk;
+ struct regulator*vdd33;
+ struct regulator*vdd10;
};
static int dwc3_exynos_register_phys(struct dwc3_exynos *exynos)
@@ -144,20 +147,46 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
clk_prepare_enable(exynos-clk);
+ exynos-vdd33 = devm_regulator_get(dev, vdd33);
+ if (IS_ERR(exynos-vdd33)) {
+ ret = PTR_ERR(exynos-vdd33);
+ goto err2;
+ }
+ ret = regulator_enable(exynos-vdd33);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD33 supply\n);
+ goto err2;
+ }
+
+ exynos-vdd10 = devm_regulator_get(dev, vdd10);
+ if (IS_ERR(exynos-vdd10)) {
+ ret = PTR_ERR(exynos-vdd10);
+ goto err3;
+ }
+ ret = regulator_enable(exynos-vdd10);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD10 supply\n);
+ goto err3;
+ }
+
if (node) {
ret = of_platform_populate(node, NULL, NULL, dev);
if (ret) {
dev_err(dev, failed to add dwc3 core\n);
- goto err2;
+ goto err4;
}
} else {
dev_err(dev, no device node, failed to add dwc3 core\n);
ret = -ENODEV;
- goto err2;
+ goto err4;
}
return 0;
+err4:
+ regulator_disable(exynos-vdd10);
+err3:
+ regulator_disable(exynos-vdd33);
err2:
clk_disable_unprepare(clk);
err1:
@@ -174,6 +203,9 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
clk_disable_unprepare(exynos-clk);
+ regulator_disable(exynos-vdd33);
+ regulator_disable(exynos-vdd10);
+
return 0;
}
@@ -192,12 +224,27 @@ static int dwc3_exynos_suspend(struct device *dev)
clk_disable(exynos-clk);
+ regulator_disable(exynos-vdd33);
+ regulator_disable(exynos-vdd10);
+
return 0;
}
static int dwc3_exynos_resume(struct device *dev)
{
struct dwc3_exynos *exynos = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(exynos-vdd33);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD33 supply\n);
+ return ret;
+ }
+ ret = regulator_enable(exynos-vdd10);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD10 supply\n);
+ return ret;
+ }
clk_enable(exynos-clk);
--
1.7.10.4
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[PATCH 2/3] usb: ehci-exynos: Make provision for vdd regulators
Facilitate getting required 3.3V and 1.0V VDD supply for
EHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for smdk5250,
certain perripherals will now need to ensure that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ehci-exynos.c | 47
1 file changed, 47 insertions(+)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index d1d8c47..a3ca8cc 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -20,6 +20,7 @@
#include linux/of.h
#include linux/of_gpio.h
#include linux/platform_device.h
+#include linux/regulator/consumer.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
#include linux/usb.h
@@ -46,6 +47,8 @@ struct exynos_ehci_hcd {
struct clk *clk;
struct usb_phy *phy;
struct usb_otg *otg;
+ struct regulator *vdd33;
+ struct regulator *vdd10;
};
#define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)-priv)
@@ -112,6 +115,28 @@ static int exynos_ehci_probe(struct platform_device *pdev)
exynos_ehci-otg = phy-otg;
}
+ exynos_ehci-vdd33 = devm_regulator_get(pdev-dev, vdd33);
+ if (IS_ERR(exynos_ehci-vdd33)) {
+ err = PTR_ERR(exynos_ehci-vdd33);
+ goto fail_regulator1;
+ }
+ err = regulator_enable(exynos_ehci-vdd33);
+ if (err) {
+ dev_err(pdev-dev, Failed to enable VDD33 supply\n);
+ goto fail_regulator1;
+ }
+
+ exynos_ehci-vdd10 = devm_regulator_get(pdev-dev, vdd10);
+ if (IS_ERR(exynos_ehci-vdd10)) {
+ err = PTR_ERR(exynos_ehci-vdd10);
+ goto fail_regulator2;
+ }
+ err = regulator_enable(exynos_ehci-vdd10);
+ if (err) {
+ dev_err(pdev-dev, Failed to enable VDD10 supply\n);
+ goto fail_regulator2;
+ }
+
skip_phy:
exynos_ehci-clk = devm_clk_get(pdev-dev, usbhost);
@@ -178,6 +203,10 @@ fail_add_hcd:
fail_io:
clk_disable_unprepare(exynos_ehci-clk);
fail_clk:
+ regulator_disable(exynos_ehci-vdd10);
+fail_regulator2:
+ regulator_disable(exynos_ehci-vdd33);
+fail_regulator1:
usb_put_hcd(hcd);
return err;
}
@@ -197,6 +226,9 @@ static int exynos_ehci_remove(struct platform_device *pdev)
clk_disable_unprepare(exynos_ehci-clk);
+ regulator_disable(exynos_ehci-vdd10);
+ regulator_disable(exynos_ehci-vdd33);
+
usb_put_hcd(hcd);
return 0;
@@ -221,6 +253,9 @@ static int exynos_ehci_suspend(struct device *dev)
clk_disable_unprepare(exynos_ehci-clk);
+ regulator_disable(exynos_ehci-vdd10);
+ regulator_disable(exynos_ehci-vdd33);
+
return rc;
}
@@ -228,6 +263,18 @@ static int exynos_ehci_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ehci_hcd *exynos_ehci = to_exynos_ehci(hcd);
+ int ret;
+
+ ret = regulator_enable(exynos_ehci-vdd33);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD33 supply\n);
+ return ret;
+ }
+ ret = regulator_enable(exynos_ehci-vdd10);
+ if (ret) {
+ dev_err(dev, Failed to enable VDD10 supply\n);
+ return ret;
+ }
clk_prepare_enable(exynos_ehci-clk);
--
1.7.10.4
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[RFC v2 PATCH v2 04/14] ARM: dts: sysreg: add exynos5 compatible to DT bindings
This patch adds relevant to exynos5 compatible for exynos5 SoCs. Changelog v2: - Changes title and description (commented by Sachin Kamat) Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/arm/samsung/sysreg.txt |1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt index 0ab3251..fd71581 100644 --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt @@ -3,6 +3,7 @@ SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) Properties: - compatible : should contain samsung,chip name-sysreg, syscon; For Exynos4 SoC series it should be samsung,exynos4-sysreg, syscon; + For Exynos5 SoC series it should be samsung,exynos5-sysreg, syscon; - reg : offset and length of the register set. Example: -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 PATCH 00/14] drm/exynos: support MIPI DSI command mode display
This patch series includes the followings: - FIMD I80 interface - DSI command mode interface for Exynos5420 SoC - S6E3FA0 command mode type panel driver - Some bugs modification The patch series is based on exynos-drm-next branch. Previous patch set, RFC v1: http://www.spinics.net/lists/dri-devel/msg57513.html Changelog v2: - Moves panel delays and size DT properties to panel probe routine. - Moves CPU timings relevant DT properties from FIMD to panel DT. Thank you. Best regards YJ YoungJun Cho (14): drm/exynos: dsi: move the Eot packets configuration point drm/exynos: dsi: delay setting clocks after reset drm/exynos: use wait_event_timeout() for safety usage ARM: dts: sysreg: add exynos5 compatible to DT bindings ARM: dts: samsung-fimd: add I80 specific properties drm/exynos: support MIPI DSI command mode ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5420 ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register node ARM: dts: exynos5: add system register support ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/arm/samsung/sysreg.txt |1 + .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 63 +++ .../devicetree/bindings/video/exynos_dsim.txt |4 +- .../devicetree/bindings/video/samsung-fimd.txt |2 + arch/arm/boot/dts/exynos4.dtsi |1 + arch/arm/boot/dts/exynos5.dtsi |6 + arch/arm/boot/dts/exynos5420.dtsi | 21 + drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 16 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h |2 + drivers/gpu/drm/exynos/exynos_drm_drv.h|2 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 121 - drivers/gpu/drm/exynos/exynos_drm_fimd.c | 280 -- drivers/gpu/drm/panel/Kconfig |7 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 include/drm/drm_mipi_dsi.h |2 + include/drm/drm_panel.h|7 + include/video/samsung_fimd.h |3 +- 19 files changed, 1038 insertions(+), 71 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 PATCH v2 07/14] ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings
This patch adds relevant to exynos5420 compatible for exynos5420 SoC support. Changelog v2: - Changes title, description and fixes typo (commented by Sachin Kamat) Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/exynos_dsim.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 33b5730..29bf3b2 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -1,7 +1,9 @@ Exynos MIPI DSI Master Required properties: - - compatible: samsung,exynos4210-mipi-dsi + - compatible: value should be one of the following + samsung,exynos4210-mipi-dsi /* for Exynos4 SoCs */ + samsung,exynos5420-mipi-dsi /* for Exynos5420 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 PATCH 08/14] drm/exynos: dsi: add driver data to support Exynos5420
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 101 ---
1 file changed, 80 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 179f2fa..fcd577f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include linux/clk.h
#include linux/irq.h
+#include linux/of_device.h
#include linux/phy/phy.h
#include linux/regulator/consumer.h
@@ -54,9 +55,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) 0xf) 0)
@@ -233,6 +237,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -262,11 +272,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = samsung,exynos4210-mipi-dsi,
+ .data = exynos4_dsi_driver_data },
+ { .compatible = samsung,exynos5420-mipi-dsi,
+ .data = exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, pdev-dev);
+
+ return (struct exynos_dsi_driver_data *)of_id-data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(dsi-completed, msecs_to_jiffies(300)))
@@ -340,14 +378,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi-driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -368,18 +401,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
failed to find PLL PMS for requested frequency\n);
return -EFAULT;
}
+ dev_dbg(dsi-dev, PLL freq %lu, (p %d, m %d, s %d)\n, fout, p, m, s);
- for (band = 0; band ARRAY_SIZE(freq_bands); ++band)
- if (fout freq_bands[band])
- break;
+ writel(500, dsi-reg_base + driver_data-plltmr_reg);
+
+ reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
+
+ if (driver_data-has_freqband) {
+ static const unsigned long freq_bands[] = {
+ 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
+ 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
+ 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
+ 770 * MHZ, 870 * MHZ, 950 * MHZ,
+ };
+ int band;
- dev_dbg(dsi-dev, PLL freq %lu, (p %d, m %d, s %d), band %d\n, fout,
- p, m,
[RFC v2 PATCH 03/14] drm/exynos: use wait_event_timeout() for safety usage
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e930d4f..1419d11 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,9 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc-pending_flip_queue,
- atomic_read(exynos_crtc-pending_flip) == 0);
+ wait_event_timeout(exynos_crtc-pending_flip_queue,
+ !atomic_read(exynos_crtc-pending_flip),
+ HZ/20);
drm_vblank_off(crtc-dev, exynos_crtc-pipe);
}
--
1.7.9.5
--
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[RFC v2 PATCH v3 05/14] ARM: dts: samsung-fimd: add I80 specific properties
In case of using CPU interface panel, the relevant registers should be set. So this patch adds relevant dt bindings. Changelog v2: - Changes samsung,sysreg-phandle to samsung,sysreg Changelog v3: - Moves CPU timings relevant properties to panel DT (commented by Laurent Pinchart, Andrzej Hajda) Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/video/samsung-fimd.txt |2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..6bf93e9 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,8 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- vidout-i80-ldi: boolean to support i80 interface instead of rgb one The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 PATCH 11/14] ARM: dts: exynos4: add system register node
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/boot/dts/exynos4.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 3d14cdb..a10aa50 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -528,6 +528,7 @@ clocks = clock 140, clock 283; clock-names = sclk_fimd, fimd; samsung,power-domain = pd_lcd0; + samsung,sysreg = sys_reg; status = disabled; }; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC v2 PATCH 01/14] drm/exynos: dsi: move the Eot packets configuration point
This configuration could be used in MIPI DSI command mode also.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index eb73e3b..956e5f3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -472,8 +472,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
if (!(dsi-mode_flags MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi-mode_flags MIPI_DSI_MODE_VIDEO_BURST)
@@ -490,6 +488,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi-mode_flags MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi-format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.7.9.5
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[RFC v2 PATCH v3 10/14] drm/panel: add S6E3FA0 driver
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Changelog v3:
- Moves CPU timings relevant properties from FIMD DT
(commented by Laurent Pinchart, Andrzej Hajda)
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig |7 +
drivers/gpu/drm/panel/Makefile|1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 +
3 files changed, 577 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E3FA0
+ tristate S6E3FA0 DSI command mode panel
+ depends on DRM DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..1282678
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,569 @@
+/*
+ * MIPI-DSI based s6e3fa0 AMOLED LCD 5.7 inch panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho yj44@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include drm/drmP.h
+#include drm/drm_mipi_dsi.h
+#include drm/drm_panel.h
+
+#include linux/gpio.h
+#include linux/of_gpio.h
+#include linux/regulator/consumer.h
+
+#include video/mipi_display.h
+#include video/of_videomode.h
+#include video/videomode.h
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct gpio_desc*det_gpio;
+ struct gpio_desc*te_gpio;
+ struct videomodevm;
+ struct drm_panel_cpu_timingscpu_timings;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+ {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+ {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+ {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
+ {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
+ {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
+ {0x55, 0x49}, {0x56, 0x4a}, {0x57, 0x4b}, {0x58, 0x4c}, {0x59, 0x4d},
+ {0x5a, 0x4e}, {0x5b, 0x4f}, {0x5c, 0x50}, {0x5d, 0x51}, {0x5e, 0x52},
+ {0x5f, 0x53}, {0x60, 0x54}, {0x61, 0x55}, {0x62, 0x56}, {0x63,
[RFC v2 PATCH v2 06/14] drm/exynos: support MIPI DSI command mode
This patch adds I80 interface for FIMD to support command mode panel.
For this, the below features are added:
- Sets display interface mode relevant registers properly according to the
interface type from DT
- Adds drm_panel_cpu_timings structure
. The command mode panel sets them as the private attributes in struct
drm_display_mode and FIMD gets them by fimd_mode_set().
- Adds TE interrupt handler
. FIMD driver should know TE signal from lcd panel to avoid tearing issue.
- Adds trigger feature
. In case of command mode panel, FIMD should set trigger bit,
so that image data has to be transferred to display bus or lcd panel.
Changelog v2:
- Moves CPU timings relevant properties to panel DT
(commented by Laurent Pinchart, Andrzej Hajda)
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/Kconfig |1 +
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 ++
drivers/gpu/drm/exynos/exynos_drm_crtc.h |2 +
drivers/gpu/drm/exynos/exynos_drm_drv.h |2 +
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 ++
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 280 +-
include/drm/drm_mipi_dsi.h |2 +
include/drm/drm_panel.h |7 +
include/video/samsung_fimd.h |3 +-
9 files changed, 277 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 5bf5bca..f4d34f0 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool Exynos DRM FIMD
depends on DRM_EXYNOS !FB_S3C !ARCH_MULTIPLATFORM
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 1419d11..d902d64 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -491,3 +491,14 @@ void exynos_drm_crtc_complete_scanout(struct
drm_framebuffer *fb)
manager-ops-wait_for_vblank(manager);
}
}
+
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)-manager;
+ int ret = 0;
+
+ if (manager-ops-te_handler)
+ ret = manager-ops-te_handler(manager);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index c27b66c..8482df2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -32,4 +32,6 @@ void exynos_drm_crtc_plane_commit(struct drm_crtc *crtc, int
zpos);
void exynos_drm_crtc_plane_enable(struct drm_crtc *crtc, int zpos);
void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc, int zpos);
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 4c5cf68..7cb0baf 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -186,6 +186,7 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: call driver specific TE handler callback.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -207,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ int (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 2cf1f0b..179f2fa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -23,6 +23,7 @@
#include video/mipi_display.h
#include video/videomode.h
+#include exynos_drm_crtc.h
#include exynos_drm_drv.h
/* returns true iff both arguments logically differs */
@@ -1032,10 +1033,22 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret 0) ? ret : xfer.rx_done;
}
+static int exynos_dsi_host_te_handler(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi-encoder;
+
+ if (!(dsi-state DSIM_STATE_ENABLED))
+ return -EPERM;
+
+ return exynos_drm_crtc_te_handler(encoder-crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
[RFC v2 PATCH v4 09/14] ARM: dts: s6e3fa0: add DT bindings
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by Sachin Kamat)
Changelog v3:
- Removes optional delay, size properties (commented by Laurent Pinchart)
- Adds OLED detection, TE gpio properties
Changelog v4:
- Moves CPU timings relevant properties from FIMD DT
(commeted by Laurent Pinchart, Andrzej Hajda)
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 63
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..9eeb38b
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,63 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+ - compatible: samsung,s6e3fa0
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpio: a GPIO spec for the reset pin
+ - det-gpio: a GPIO spec for the OLED detection pin
+ - te-gpio: a GPIO spec for the TE pin
+ - display-timings: timings for the connected panel as described by [1]
+ - cpu-timings: CPU interface timings for the connected panel, and it contains
+following optional properties.
+ - cs-setup: clock cycles for the active period of address signal
+enable until chip select is enable in CPU interface
+ - wr-setup: clock cycles for the active period of CS signal enable
+until write signal is enable in CPU interface
+ - wr-act: clock cycles for the active period of CS enable in CPU
+interface
+ - wr-hold: clock cycles for the active period of CS disable until
+write signal is disable in CPU interface
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [2]. This
+node should describe panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel@0 {
+ compatible = samsung,s6e3fa0;
+ reg = 0;
+ vdd3-supply = vcclcd_reg;
+ vci-supply = vlcd_reg;
+ reset-gpio = gpy7 4 0;
+ det-gpio = gpg0 6 0;
+ te-gpio = gpd1 7 0;
+
+ display-timings {
+ timing0: timing-0 {
+ clock-frequency = 0;
+ hactive = 1080;
+ vactive = 1920;
+ hfront-porch = 2;
+ hback-porch = 2;
+ hsync-len = 1;
+ vfront-porch = 1;
+ vback-porch = 4;
+ vsync-len = 1;
+ };
+ };
+
+ cpu-timings {
+ cs-setup = 0;
+ wr-setup = 0;
+ wr-act = 1;
+ wr-hold = 0;
+ };
+ };
--
1.7.9.5
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[RFC v2 PATCH 14/14] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Changelog v2:
- Uses clock macros instead of numbers (commented by Sachin Kamat)
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index f0184c7..f1030f5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -17,6 +17,7 @@
#include exynos5420-pinctrl.dtsi
#include dt-bindings/clk/exynos-audss-clk.h
+#include dt-bindings/clock/exynos5420.h
/ {
compatible = samsung,exynos5420;
@@ -422,6 +423,20 @@
#phy-cells = 1;
};
+ dsi@1450 {
+ compatible = samsung,exynos5420-mipi-dsi;
+ reg = 0x1450 0x1;
+ interrupts = 0 82 0;
+ samsung,power-domain = disp_pd;
+ phys = mipi_phy 1;
+ phy-names = dsim;
+ clocks = clock CLK_DSIM1, clock CLK_SCLK_MIPI1;
+ clock-names = bus_clk, pll_clk;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock 147, clock 421;
--
1.7.9.5
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[RFC v2 PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset
Some phy control registers are not kept after software reset.
So this patch makes the clocks containing phy control to be set
after software reset.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 956e5f3..2cf1f0b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
static int exynos_dsi_init(struct exynos_dsi *dsi)
{
- exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
enable_irq(dsi-irq);
exynos_dsi_wait_for_reset(dsi);
+ exynos_dsi_enable_clock(dsi);
exynos_dsi_init_link(dsi);
return 0;
--
1.7.9.5
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[RFC v2 PATCH 13/14] ARM: dts: exynos5420: add mipi-phy node
This patch adds mipi-phy node for MIPI-DSI device.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 8db792b..f0184c7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -416,6 +416,12 @@
phy-names = dp;
};
+ mipi_phy: video-phy@10040714 {
+ compatible = samsung,s5pv210-mipi-video-phy;
+ reg = 0x10040714 12;
+ #phy-cells = 1;
+ };
+
fimd@1440 {
samsung,power-domain = disp_pd;
clocks = clock 147, clock 421;
--
1.7.9.5
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[RFC v2 PATCH 12/14] ARM: dts: exynos5: add system register support
This patch adds sysreg device node, and sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 258dca4..f938bbb 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -88,12 +88,18 @@
status = disabled;
};
+ sys_reg: syscon@1005 {
+ compatible = samsung,exynos5-sysreg, syscon;
+ reg = 0x1005 0x500;
+ };
+
fimd@1440 {
compatible = samsung,exynos5250-fimd;
interrupt-parent = combiner;
reg = 0x1440 0x4;
interrupt-names = fifo, vsync, lcd_sys;
interrupts = 18 4, 18 5, 18 6;
+ samsung,sysreg = sys_reg;
status = disabled;
};
--
1.7.9.5
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Re: [PATCH 0/4] Add support for Exynos5800 SoC
[from the right account and without html formatting this time] On Sun, Apr 20, 2014 at 11:45 PM, Arun Kumar K arun...@samsung.com wrote: Exynos5800 is a derivative of Exynos5420 with higher clock speeds and most other IP blocks remaining the same except for a few. Due to the similarities with 5420, following is done to achieve maximum code re-use: - Use the same 5420 clock file with few changes for adding extra 5800 clocks. - Re-use the 5420 dtsi by renaming it to exynos5-octa. Nack, this is a bad idea. You're not converting over 5410, which is also marketed as an exynos octa chip. There's definitely no guarantee that future octa-core chips will fit into this naming scheme either. Just call it 5422 like you did in the Chrome OS code base. It is after all the product name that is fused in as chip id on these parts, and all the other naming falls out much better from that. No more soc_is_5420 || soc_is_5800, since you can add a soc_is_542x. Etc. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/4] ARM: dts: Add 5800 dt files
On Sun, Apr 20, 2014 at 11:45 PM, Arun Kumar K arun...@samsung.com wrote: Most of the nodes of exynos5420 remains same for exynos5800. So moving the common dt nodes to exynos5-octa.dtsi. The pinctrl dtsi is completely re-used and is renamed to exynos5-octa-pinctrl.dtsi. Again, naming here doesn't work. Also, if all you need to revise are a few properties, then you should just include 5420.dtsi in the 5422.dtsi file, and override, instead of adding another layer of indireciton. The multiple layers of includes and modifications makes it very hard to figure out where to find a specific definition for a platform, and I don't think we should encourage more use of it. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] serial: samsung: Change barrier() to cpu_relax() in console output
The two functions to write out to the console (one used in normal console mode and one in polling console mode) were slightly different. One used a barrier() in its loop and the other a cpu_relax(). The barrier() really doesn't do anything since we're using rd_regl() to read the port anyway. Switch it to cpu_relax() to make things consistent. No known bugs / issues are fixed by this change--it just makes things more consistent. Signed-off-by: Doug Anderson diand...@chromium.org --- drivers/tty/serial/samsung.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 12442748..1f5505e 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1466,7 +1466,7 @@ s3c24xx_serial_console_putchar(struct uart_port *port, int ch) unsigned int ufcon = rd_regl(port, S3C2410_UFCON); while (!s3c24xx_serial_console_txrdy(port, ufcon)) - barrier(); + cpu_relax(); wr_regb(port, S3C2410_UTXH, ch); } -- 1.9.1.423.g4596e3a -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] serial: samsung: don't check config for every character
The s3c24xx_serial_console_putchar() is _only_ ever used by
s3c24xx_serial_console_write() and is called in a loop (indirectly
through uart_console_write()). There's no reason to call
s3c24xx_port_configured() for every iteration through the loop. Move
it outside the loop.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/tty/serial/samsung.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index a8e8b79..12442748 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1464,11 +1464,6 @@ static void
s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
{
unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
- unsigned int ucon = rd_regl(port, S3C2410_UCON);
-
- /* not possible to xmit on unconfigured port */
- if (!s3c24xx_port_configured(ucon))
- return;
while (!s3c24xx_serial_console_txrdy(port, ufcon))
barrier();
@@ -1479,6 +1474,12 @@ static void
s3c24xx_serial_console_write(struct console *co, const char *s,
unsigned int count)
{
+ unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
+
+ /* not possible to xmit on unconfigured port */
+ if (!s3c24xx_port_configured(ucon))
+ return;
+
uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
}
--
1.9.1.423.g4596e3a
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[PATCH 1/3] serial: samsung: Use the passed in port, fixing kgdb w/ no console
The two functions in the samsung serial driver used for writing
characters out to the port were inconsistent about whether they used
the passed in port or the global cons_uart. There was no reason
to use the global and the use of the global in
s3c24xx_serial_put_poll_char() caused a crash in the case where you
used the serial port for kgdboc but not for console.
Fix it so we used the passed in variable.
Note that this doesn't fix all problems with the samsung serial
driver. Specifically:
* s3c24xx_serial_console_putchar() is still 99% identical to
s3c24xx_serial_put_poll_char() (the function signature is different,
but that's about it). A future patch will make them slightly less
identical and judging by other serial drivers we may need yet more
differences eventually.
* The samsung serial driver still doesn't allow you to have more than
one console port since it still uses the global cons_uart in
s3c24xx_serial_console_write().
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/tty/serial/samsung.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 23f4596..a8e8b79 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1446,8 +1446,8 @@ static int s3c24xx_serial_get_poll_char(struct uart_port
*port)
static void s3c24xx_serial_put_poll_char(struct uart_port *port,
unsigned char c)
{
- unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
- unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
+ unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
+ unsigned int ucon = rd_regl(port, S3C2410_UCON);
/* not possible to xmit on unconfigured port */
if (!s3c24xx_port_configured(ucon))
@@ -1455,7 +1455,7 @@ static void s3c24xx_serial_put_poll_char(struct uart_port
*port,
while (!s3c24xx_serial_console_txrdy(port, ufcon))
cpu_relax();
- wr_regb(cons_uart, S3C2410_UTXH, c);
+ wr_regb(port, S3C2410_UTXH, c);
}
#endif /* CONFIG_CONSOLE_POLL */
@@ -1463,8 +1463,8 @@ static void s3c24xx_serial_put_poll_char(struct uart_port
*port,
static void
s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
{
- unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
- unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
+ unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
+ unsigned int ucon = rd_regl(port, S3C2410_UCON);
/* not possible to xmit on unconfigured port */
if (!s3c24xx_port_configured(ucon))
@@ -1472,7 +1472,7 @@ s3c24xx_serial_console_putchar(struct uart_port *port,
int ch)
while (!s3c24xx_serial_console_txrdy(port, ufcon))
barrier();
- wr_regb(cons_uart, S3C2410_UTXH, ch);
+ wr_regb(port, S3C2410_UTXH, ch);
}
static void
--
1.9.1.423.g4596e3a
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[PATCH v2] serial_core: Commonalize crlf when working w/ a non open console port
In (efe2f29 kgdboc,kdb: Allow kdb to work on a non open console port)
support was added to directly use the write_char functions when
doing kdb over a non-open console port. This is great, but it ends up
bypassing the normal code in uart_console_write() that adds a carriage
return before any newlines.
There appears to have been a trend to add this support directly in
some console driver's poll_put_char() functions. This had a few side
effects, including:
- In this case we were doing LFCR, not CRLF. This was fixed in
uart_console_write() back in (d358788 [SERIAL] kernel console should
send CRLF not LFCR)
- Not all serial drivers had the LFCR code in their poll_put_char()
functions. In my case I was running serial/samsung.c which lacked
it.
I've moved the handling to uart_poll_put_char() to fix the above
problems. Now when I use kdb (and don't point console= to the same
UART) I no longer get:
[0]kdb
[0]kdb
[0]kdb
Signed-off-by: Doug Anderson diand...@chromium.org
---
Changes in v2:
- Moved from kdb to serial_core
drivers/tty/serial/8250/8250_core.c | 5 -
drivers/tty/serial/pch_uart.c | 5 -
drivers/tty/serial/pxa.c| 5 -
drivers/tty/serial/serial_core.c| 3 +++
drivers/tty/serial/serial_txx9.c| 5 -
5 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_core.c
b/drivers/tty/serial/8250/8250_core.c
index 81f909c..ffee982 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -1926,13 +1926,8 @@ static void serial8250_put_poll_char(struct uart_port
*port,
wait_for_xmitr(up, BOTH_EMPTY);
/*
* Send the character out.
-* If a LF, also do CR...
*/
serial_port_out(port, UART_TX, c);
- if (c == 10) {
- wait_for_xmitr(up, BOTH_EMPTY);
- serial_port_out(port, UART_TX, 13);
- }
/*
* Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 0931b3f..11e631d 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -1588,13 +1588,8 @@ static void pch_uart_put_poll_char(struct uart_port
*port,
wait_for_xmitr(priv, UART_LSR_THRE);
/*
* Send the character out.
-* If a LF, also do CR...
*/
iowrite8(c, priv-membase + PCH_UART_THR);
- if (c == 10) {
- wait_for_xmitr(priv, UART_LSR_THRE);
- iowrite8(13, priv-membase + PCH_UART_THR);
- }
/*
* Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index f9f20f3..9e7ee39 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -711,13 +711,8 @@ static void serial_pxa_put_poll_char(struct uart_port
*port,
wait_for_xmitr(up);
/*
* Send the character out.
-* If a LF, also do CR...
*/
serial_out(up, UART_TX, c);
- if (c == 10) {
- wait_for_xmitr(up);
- serial_out(up, UART_TX, 13);
- }
/*
* Finally, wait for transmitter to become empty
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index f26834d..5dba976 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2236,6 +2236,9 @@ static void uart_poll_put_char(struct tty_driver *driver,
int line, char ch)
return;
port = state-uart_port;
+
+ if (ch == '\n')
+ port-ops-poll_put_char(port, '\r');
port-ops-poll_put_char(port, ch);
}
#endif
diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
index 90a080b..60f49b9 100644
--- a/drivers/tty/serial/serial_txx9.c
+++ b/drivers/tty/serial/serial_txx9.c
@@ -535,13 +535,8 @@ static void serial_txx9_put_poll_char(struct uart_port
*port, unsigned char c)
wait_for_xmitr(up);
/*
* Send the character out.
-* If a LF, also do CR...
*/
sio_out(up, TXX9_SITFIFO, c);
- if (c == 10) {
- wait_for_xmitr(up);
- sio_out(up, TXX9_SITFIFO, 13);
- }
/*
* Finally, wait for transmitter to become empty
--
1.9.1.423.g4596e3a
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Re: [RESEND PATCH 6/7] i2c: ChromeOS EC tunnel driver
On 04/17/2014 12:36 PM, Doug Anderson wrote: On ARM Chromebooks we have a few devices that are accessed by both the AP (the main Application Processor) and the EC (the Embedded Controller). These are: * The battery (sbs-battery). * The power management unit tps65090. ... On the Samsung ARM Chromebook 2 the scheme is changed yet again, now: * The AP/EC comms are now using SPI for faster speeds. * The EC's i2c bus is exposed to the AP through a full i2c tunnel. ... This driver supports the scheme used by the Samsung ARM Chromebook 2. Future patches to this driver could add support for the battery tunnel on the HP Chromebook 11 (and perhaps could even be used to access tps65090 on the HP Chromebook 11 instead of using a special driver, but I haven't researched that enough). diff --git a/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt b/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt +I2C bus that tunnels through the ChromeOS EC (cros-ec) +== +On some ChromeOS board designs we've got a connection to the EC (embedded +controller) but no direct connection to some devices on the other side of +the EC (like a battery and PMIC). To get access to those devices we need +to tunnel our i2c commands through the EC. + +The node for this device should be under a cros-ec node like google,cros-ec-spi +or google,cros-ec-i2c. + + +Required properties: +- compatible: google,cros-ec-i2c-tunnel +- google,remote-bus: The EC bus we'd like to talk to. It's probably worth mentioning here that the node represents a single I2C bus, and hence is expected to contain child nodes representing I2C devices. Perhaps: Optional child nodes: - One node per I2C device connected to the tunnelled I2C bus. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/7] ARM: tegra: Add the EC i2c tunnel to tegra124-venice2
On 04/17/2014 11:59 AM, Doug Anderson wrote:
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
The series,
Tested-by: Stephen Warren swar...@nvidia.com
I can apply this one patch once the other patches in the series are
acked or applied (in order to make sure the DT binding is acceptable to
others).
I guess I'll send separate patches for tegra_defconfig and
multi_v7_defconfig to add the required options once I've applied this,
unless you beat me to it.
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
aliases {
+ i2c20 = /spi@0,7000d400/cros-ec@0/i2c-tunnel;
Is that needed? I'd prefer not to add it unless there's a specific
reason. I don't think I2C buses need specific names, do they?
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Re: [PATCH] usb: ohci-exynos: Add facility to use phy provided by the generic phy framework
On Thu, Apr 10, 2014 at 6:54 PM, Vivek Gautam gautam.vi...@samsung.com wrote: Add support to consume phy provided by Generic phy framework. Keeping the support for older usb-phy intact right now, in order to prevent any functionality break in absence of relevant device tree side change for ohci-exynos. Once we move to new phy in the device nodes for ohci, we can remove the support for older phys. Any comments on this please. I think whatever the approach we follow, that can be common to both ehci-exynos[1], and ohci-exynos, since both are needed to move to the new generic phy framework, keeping support for older usb-phy so as to have smooth transition, in order to avoid any regression. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com Cc: Jingoo Han jg1@samsung.com Cc: Alan Stern st...@rowland.harvard.edu --- Based on 'usb-next' branch of Greg's usb tree. Tested with local dt patches, similar to ehci dt changes posted by Kamil[1]. Tested on Exynos5250 smdk. [1] [PATCH v6 4/8] dts: Add usb2phy to Exynos 5250 https://lkml.org/lkml/2014/1/29/302 .../devicetree/bindings/usb/exynos-usb.txt | 14 drivers/usb/host/ohci-exynos.c | 79 ++-- 2 files changed, 85 insertions(+), 8 deletions(-) [snip] -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/7] ARM: tegra: Add the EC i2c tunnel to tegra124-venice2
Stephen,
On Mon, Apr 21, 2014 at 11:18 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 04/17/2014 11:59 AM, Doug Anderson wrote:
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
The series,
Tested-by: Stephen Warren swar...@nvidia.com
I can apply this one patch once the other patches in the series are
acked or applied (in order to make sure the DT binding is acceptable to
others).
Sounds good. If I don't get any feedback (positive or negative) in
the next few days I'll resend with your Tested-by.
I guess I'll send separate patches for tegra_defconfig and
multi_v7_defconfig to add the required options once I've applied this,
unless you beat me to it.
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
aliases {
+ i2c20 = /spi@0,7000d400/cros-ec@0/i2c-tunnel;
Is that needed? I'd prefer not to add it unless there's a specific
reason. I don't think I2C buses need specific names, do they?
It is not strictly needed, but from a usability standpoint it is
terribly helpful. It serves to make it obvious to someone looking at
the device that it's _not_ an i2c bus associated with the main SoC.
If you don't include a number I believe that the i2c core will pick
the first available number.
It seems worth it to save a few people a few hours of head scratching.
...but this is your dts and if you think it's a terrible idea then
I'll remove it. It looks to be less critical on tegra than it is on
exynos (which has ~9 i2c busses, they are numbered in the user manual,
and if you have one set to disable in the dts then the tunnel will
end up getting a very confusing number).
-Doug
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Re: [PATCH 7/7] ARM: tegra: Add the EC i2c tunnel to tegra124-venice2
On 04/21/2014 01:35 PM, Doug Anderson wrote:
Stephen,
On Mon, Apr 21, 2014 at 11:18 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 04/17/2014 11:59 AM, Doug Anderson wrote:
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
aliases {
+ i2c20 = /spi@0,7000d400/cros-ec@0/i2c-tunnel;
Is that needed? I'd prefer not to add it unless there's a specific
reason. I don't think I2C buses need specific names, do they?
It is not strictly needed, but from a usability standpoint it is
terribly helpful. It serves to make it obvious to someone looking at
the device that it's _not_ an i2c bus associated with the main SoC.
If you don't include a number I believe that the i2c core will pick
the first available number.
It seems worth it to save a few people a few hours of head scratching.
...but this is your dts and if you think it's a terrible idea then
I'll remove it. It looks to be less critical on tegra than it is on
exynos (which has ~9 i2c busses, they are numbered in the user manual,
and if you have one set to disable in the dts then the tunnel will
end up getting a very confusing number).
My opinion is that the in-kernel I2C bus numbering is an entirely
unrelated numbering space to the HW controller numbering space precisely
because of issues like that. DT aliases are more useful for user-visible
port numbering (e.g. HDMI 0, 1 connectors on a case) than purely
internal details like this. So, I would leave it out.
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Re: [PATCH v2 1/2] v4l: Add resolution change event.
Hi Arun,
On Monday 21 April 2014 17:19:26 Arun Kumar K wrote:
On Mon, Apr 21, 2014 at 3:54 PM, Laurent Pinchart wrote:
On Monday 21 April 2014 14:56:01 Arun Kumar K wrote:
From: Pawel Osciak posc...@chromium.org
This event indicates that the decoder has reached a point in the stream,
at which the resolution changes. The userspace is expected to provide a
new
set of CAPTURE buffers for the new format before decoding can continue.
The event can also be used for more generic events involving resolution
or format changes at runtime for all kinds of video devices.
Signed-off-by: Pawel Osciak posc...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
.../DocBook/media/v4l/vidioc-subscribe-event.xml | 16
include/uapi/linux/videodev2.h |6 ++
2 files changed, 22 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml index
5c70b61..0aec831 100644
--- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
+++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
@@ -155,6 +155,22 @@
/entry
/row
row
+ entryconstantV4L2_EVENT_SOURCE_CHANGE/constant/entry
+ entry5/entry
+ entry
+ paraThis event is triggered when a resolution or format
change +is detected during runtime by the video device. It
can be a +runtime resolution change triggered by a video
decoder or the +format change happening on an HDMI
connector. Application may +need to reinitialize buffers
before proceeding further./para +
+ paraThis event has a v4l2-event-source-change;
associated
+ with it. This has significance only for v4l2 subdevs where
the
+ structfieldpad_num/structfield field will be updated with
+ the pad number on which the event is triggered./para
+ /entry
+ /row
+ row
entryconstantV4L2_EVENT_PRIVATE_START/constant/entry
entry0x0800/entry
entryBase event number for driver-private events./entry
diff --git a/include/uapi/linux/videodev2.h
b/include/uapi/linux/videodev2.h index 6ae7bbe..12e0614 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1733,6 +1733,7 @@ struct v4l2_streamparm {
#define V4L2_EVENT_EOS 2
#define V4L2_EVENT_CTRL 3
#define V4L2_EVENT_FRAME_SYNC4
+#define V4L2_EVENT_SOURCE_CHANGE 5
#define V4L2_EVENT_PRIVATE_START 0x0800
/* Payload for V4L2_EVENT_VSYNC */
@@ -1764,12 +1765,17 @@ struct v4l2_event_frame_sync {
__u32 frame_sequence;
};
+struct v4l2_event_source_change {
+ __u32 pad_num;
I would call the field just pad,
Ok.
+};
+
struct v4l2_event {
__u32 type;
union {
struct v4l2_event_vsync vsync;
struct v4l2_event_ctrl ctrl;
struct v4l2_event_frame_syncframe_sync;
+ struct v4l2_event_source_change source_change;
__u8data[64];
This looks pretty good to me, but I'm a bit concerned about future
compatibility. We might need to report more information to userspace, and
in particular what has been changed at the source (resolution, format,
...). In order to do so, we'll need to add a flag field to
v4l2_event_source_change.
Ok a flag can be added with bitfields for reporting specific event type.
I don't think we need to add it now. Just making sure it can be added later
without breaking the userspace API would be enough for me.
The next __u32 right after the source_change field must thus be zeroed. I
see two ways of doing so:
- zeroing the whole data array before setting event-specific data
- adding a reserved must-be-zeroed field to v4l2_event_source_change
I like the former better as it's more generic, but we then need to ensure
that all drivers zero the whole data field correctly. Adding a new
v4l2_event_init() function would help with that.
Is that a good idea to have an init() function just for zeroing the data
field? If this is agreed upon, I can add this, but it can be easily missed
out by drivers.
I'm not sure. On one hand it would be easier to catch missing calls if we use
a dedicated function, as the function could set an initialized flag in the
event structure that would be checked by v4l2_event_queue. On the other hand,
that might be overengineering, and we could just manually check that all
drivers memset the structure to 0 before initializing fields. In both cases
the goal is to make sure that the structure is
[PATCH V2 1/9] drm/exynos: dp: support hotplug detection via GPIO
From: Andrew Bresticker abres...@chromium.org
Certain bridge chips use a GPIO to indicate the cable status instead
of the I_DP_HPD pin. This adds an optional device-tree property,
samsung,hpd-gpio, to the exynos-dp controller which indicates that
the specified GPIO should be used for hotplug detection.
The GPIO is then set up as an edge-triggered interrupt where the
rising edge indicates hotplug-in and the falling edge indicates hotplug-out.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Address reiew comments from Jingoo Han
.../devicetree/bindings/video/exynos_dp.txt|4 ++
drivers/gpu/drm/exynos/exynos_dp_core.c| 32 --
drivers/gpu/drm/exynos/exynos_dp_core.h|1 +
drivers/gpu/drm/exynos/exynos_dp_reg.c | 44 ++--
4 files changed, 66 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt
b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 57ccdde..53dbccf 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -62,6 +62,10 @@ Optional properties for dp-controller:
-hsync-active-high:
HSYNC polarity configuration.
High if defined, Low if not defined
+ -samsung,hpd-gpio:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug
+ detection
Example:
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 1cc3981..18fd9c5 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -18,6 +18,8 @@
#include linux/interrupt.h
#include linux/delay.h
#include linux/of.h
+#include linux/of_gpio.h
+#include linux/gpio.h
#include linux/component.h
#include linux/phy/phy.h
#include video/of_display_timing.h
@@ -1226,6 +1228,7 @@ static int exynos_dp_bind(struct device *dev, struct
device *master, void *data)
struct drm_device *drm_dev = data;
struct resource *res;
struct exynos_dp_device *dp;
+ unsigned int irq_flags;
int ret = 0;
@@ -1265,7 +1268,30 @@ static int exynos_dp_bind(struct device *dev, struct
device *master, void *data)
if (IS_ERR(dp-reg_base))
return PTR_ERR(dp-reg_base);
- dp-irq = platform_get_irq(pdev, 0);
+ dp-hpd_gpio = of_get_named_gpio(dev-of_node, samsung,hpd-gpio, 0);
+
+ if (gpio_is_valid(dp-hpd_gpio)) {
+ /*
+* Set up the hotplug GPIO from the device tree as an interrupt.
+* Simply specifying a different interrupt in the device tree
+* doesn't work since we handle hotplug rather differently when
+* using a GPIO. We also need the actual GPIO specifier so
+* that we can get the current state of the GPIO.
+*/
+ ret = devm_gpio_request_one(pdev-dev, dp-hpd_gpio, GPIOF_IN,
+ hpd_gpio);
+ if (ret) {
+ dev_err(pdev-dev, failed to get hpd gpio\n);
+ return ret;
+ }
+ dp-irq = gpio_to_irq(dp-hpd_gpio);
+ irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+ } else {
+ dp-hpd_gpio = -ENODEV;
+ dp-irq = platform_get_irq(pdev, 0);
+ irq_flags = 0;
+ }
+
if (dp-irq == -ENXIO) {
dev_err(pdev-dev, failed to get irq\n);
return -ENODEV;
@@ -1277,8 +1303,8 @@ static int exynos_dp_bind(struct device *dev, struct
device *master, void *data)
exynos_dp_init_dp(dp);
- ret = devm_request_irq(pdev-dev, dp-irq, exynos_dp_irq_handler, 0,
- exynos-dp, dp);
+ ret = devm_request_irq(pdev-dev, dp-irq, exynos_dp_irq_handler,
+ irq_flags, exynos-dp, dp);
if (ret) {
dev_err(pdev-dev, failed to request irq\n);
return ret;
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h
b/drivers/gpu/drm/exynos/exynos_dp_core.h
index d6a900d..56fa43e 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -159,6 +159,7 @@ struct exynos_dp_device {
struct work_struct hotplug_work;
struct phy *phy;
int dpms_mode;
+ int hpd_gpio;
struct exynos_drm_panel_info panel;
};
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c
b/drivers/gpu/drm/exynos/exynos_dp_reg.c
index b70da50..79291a2 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++
[PATCH V2 4/9] drm/exynos: add exynos_dp_panel driver registration to drm driver
Register exynos_dp_panel before the list of exynos crtcs and
connectors are probed.
This is needed because exynos_dp_panel should be registered to
the drm_panel list via panel-exynos-dp probe, i.e much before
exynos_dp_bind calls of_drm_find_panel().
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Added platform_driver_unregister(exynos_dp_panel_driver) to
exynos_drm_platform_remove as per Jingoo Han's correction
drivers/gpu/drm/exynos/exynos_drm_drv.c | 15 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h |1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 1d653f8..2db7f67 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -530,12 +530,23 @@ static int exynos_drm_platform_probe(struct
platform_device *pdev)
goto err_unregister_ipp_drv;
#endif
+#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
+ ret = platform_driver_register(exynos_dp_panel_driver);
+ if (ret 0)
+ goto err_unregister_dp_panel;
+#endif
+
ret = component_master_add(pdev-dev, exynos_drm_ops);
if (ret 0)
DRM_DEBUG_KMS(re-tried by last sub driver probed later.\n);
return 0;
+#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
+ platform_driver_unregister(exynos_dp_panel_driver);
+err_unregister_dp_panel:
+#endif
+
#ifdef CONFIG_DRM_EXYNOS_IPP
err_unregister_ipp_drv:
platform_driver_unregister(ipp_driver);
@@ -587,6 +598,10 @@ err_unregister_fimd_drv:
static int exynos_drm_platform_remove(struct platform_device *pdev)
{
+#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
+ platform_driver_unregister(exynos_dp_panel_driver);
+#endif
+
#ifdef CONFIG_DRM_EXYNOS_IPP
exynos_platform_device_ipp_unregister();
platform_driver_unregister(ipp_driver);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index fc15fe6..b33050d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -368,4 +368,5 @@ extern struct platform_driver fimc_driver;
extern struct platform_driver rotator_driver;
extern struct platform_driver gsc_driver;
extern struct platform_driver ipp_driver;
+extern struct platform_driver exynos_dp_panel_driver;
#endif
--
1.7.9.5
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[PATCH V2 3/9] drm/panel: Add driver for exynos_dp based panels
This patch adds a simple driver to handle all the LCD and LED
powerup/down routines needed to support eDP/eDP-LVDS panels
supported on exynos boards.
The LCD and LED units are usually powered up via regulators,
and almost on all boards, we will have a BL_EN pin to enable/
disable the backlight. Sometimes, we can have LCD_EN switches
as well. The routines in this driver can be used to control
panel power sequence on such boards.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Added routine for post_disable, removed few unwanted headers.
Refactored a lot of code.
.../devicetree/bindings/panel/exynos-dp-panel.txt | 45
drivers/gpu/drm/panel/Kconfig |9 +
drivers/gpu/drm/panel/Makefile |1 +
drivers/gpu/drm/panel/panel-exynos-dp.c| 251
4 files changed, 306 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
create mode 100644 drivers/gpu/drm/panel/panel-exynos-dp.c
diff --git a/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
b/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
new file mode 100644
index 000..3fbca54
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
@@ -0,0 +1,45 @@
+exynos_DP_panel/DP_to_LVDS_panel
+
+Required properties:
+ - compatible: samsung,exynos-dp-panel
+
+Optional properties:
+ -samsung,lcd-en-gpio:
+ eDP panel LCD poweron GPIO.
+ Indicates which GPIO needs to be powered up as output
+ to powerup/enable the switch to the LCD panel.
+ -samsung,led-en-gpio:
+ eDP panel LED enable GPIO.
+ Indicates which GPIO needs to be powered up as output
+ to enable the backlight.
+ -samsung,panel-pre-enable-delay:
+ delay value in ms required for panel_pre_enable process
+ Delay in ms needed for the eDP panel LCD unit to
+ powerup, and delay needed between panel_VCC and
+ video_enable.
+ -samsung,panel-enable-delay:
+ delay value in ms required for panel_enable process
+ Delay in ms needed for the eDP panel backlight/LED unit
+ to powerup, and delay needed between video_enable and
+ BL_EN.
+ samsung,panel-disable-delay:
+ delay value in ms required for panel_disable process
+ Delay in ms needed for the eDP panel backlight/LED unit
+ powerdown, and delay needed between BL_DISABLE and
+ video_disable.
+ samsung,panel-post-disable-delay:
+ delay value in ms required for panel_post_disable process
+ Delay in ms needed for the eDP panel LCD unit to
+ to powerdown, and delay between video_disable and
+ panel_VCC going down.
+
+Example:
+
+ dp-panel {
+ compatible = samsung,exynos-dp-panel;
+ samsung,led-en-gpio = gpx3 0 1;
+ samsung,panel-pre-enable-delay = 40;
+ samsung,panel-enable-delay = 20;
+ samsung,panel-disable-delay = 20;
+ samsung,panel-post-disable-delay = 30;
+ };
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..ea9d5ac 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,13 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_EXYNOS_DP
+ tristate support for DP panels
+ depends on OF DRM_PANEL DRM_EXYNOS_DP
+ help
+ DRM panel driver for DP panels and LVDS connected via DP bridges
+ that need at most a regulator for LCD unit, a regulator for LED unit
+ and/or enable GPIOs for LCD or LED units. Delay values can also be
+ specified to support powerup and powerdown process.
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..30311a4 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_EXYNOS_DP) += panel-exynos-dp.o
diff --git a/drivers/gpu/drm/panel/panel-exynos-dp.c
b/drivers/gpu/drm/panel/panel-exynos-dp.c
new file mode 100644
index 000..5568d6a
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-exynos-dp.c
@@ -0,0 +1,251 @@
+/*
+ * Exynos DP panel driver
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Ajay Kumar ajaykumar...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the
[PATCH V2 8/9] drm/bridge: Add PS8622 bridge driver
This patch adds a drm_bridge driver for the PS8622 DisplayPort to LVDS
bridge chip.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Sean Paul seanp...@chromium.org
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Pushing V1 for this as V2 because this patch holds good in this series.
drivers/gpu/drm/bridge/Kconfig |7 +
drivers/gpu/drm/bridge/Makefile |1 +
drivers/gpu/drm/bridge/ps8622.c | 566 +++
include/drm/bridge/ps8622.h | 42 +++
4 files changed, 616 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ps8622.c
create mode 100644 include/drm/bridge/ps8622.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3bc6845..aba21fc 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -4,3 +4,10 @@ config DRM_PTN3460
select DRM_KMS_HELPER
select DRM_PANEL
---help---
+
+config DRM_PS8622
+ tristate Parade eDP/LVDS bridge
+ depends on DRM
+ select DRM_KMS_HELPER
+ select DRM_PANEL
+ ---help---
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index b4733e1..d1b5daa 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,3 +1,4 @@
ccflags-y := -Iinclude/drm
obj-$(CONFIG_DRM_PTN3460) += ptn3460.o
+obj-$(CONFIG_DRM_PS8622) += ps8622.o
diff --git a/drivers/gpu/drm/bridge/ps8622.c b/drivers/gpu/drm/bridge/ps8622.c
new file mode 100644
index 000..1e6b3ca
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ps8622.c
@@ -0,0 +1,566 @@
+/*
+ * Parade PS8622 eDP/LVDS bridge driver
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/backlight.h
+#include linux/delay.h
+#include linux/err.h
+#include linux/fb.h
+#include linux/gpio.h
+#include linux/i2c.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/pm.h
+#include linux/regulator/consumer.h
+#include drm/drm_panel.h
+
+#include drmP.h
+#include drm_crtc.h
+#include drm_crtc_helper.h
+
+struct ps8622_bridge {
+ struct drm_connector connector;
+ struct drm_bridge *bridge;
+ struct drm_encoder *encoder;
+ struct drm_panel *panel;
+ struct i2c_client *client;
+ struct regulator *v12;
+ struct backlight_device *bl;
+ struct mutex enable_mutex;
+
+ int gpio_slp_n;
+ int gpio_rst_n;
+
+ u8 max_lane_count;
+ u8 lane_count;
+
+ bool enabled;
+
+ struct drm_display_mode mode;
+};
+
+struct ps8622_device_data {
+ u8 max_lane_count;
+};
+
+static const struct ps8622_device_data ps8622_data = {
+ .max_lane_count = 1,
+};
+
+static const struct ps8622_device_data ps8625_data = {
+ .max_lane_count = 2,
+};
+
+/* Brightness scale on the Parade chip */
+#define PS8622_MAX_BRIGHTNESS 0xff
+
+/* Timings taken from the version 1.7 datasheet for the PS8622/PS8625 */
+#define PS8622_POWER_RISE_T1_MIN_US 10
+#define PS8622_POWER_RISE_T1_MAX_US 1
+#define PS8622_RST_HIGH_T2_MIN_US 3000
+#define PS8622_RST_HIGH_T2_MAX_US 3
+#define PS8622_PWMO_END_T12_MS 200
+#define PS8622_POWER_FALL_T16_MAX_US 1
+#define PS8622_POWER_OFF_T17_MS 500
+
+#if ((PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US) \
+ (PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US))
+#error T2.min + T1.max must be less than T2.max + T1.min
+#endif
+
+static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val)
+{
+ int ret;
+ struct i2c_adapter *adap = client-adapter;
+ struct i2c_msg msg;
+ u8 data[] = {reg, val};
+
+ msg.addr = client-addr + page;
+ msg.flags = 0;
+ msg.len = sizeof(data);
+ msg.buf = data;
+
+ ret = i2c_transfer(adap, msg, 1);
+ if (ret != 1)
+ pr_warn(PS8622 I2C write (0x%02x,0x%02x,0x%02x) failed: %d\n,
+ client-addr + page, reg, val, ret);
+ return !(ret == 1);
+}
+
+static int ps8622_send_config(struct ps8622_bridge *ps_bridge)
+{
+ struct i2c_client *cl = ps_bridge-client;
+ int err = 0;
+
+ /* wait 20ms after power ON */
+ usleep_range(2, 3);
+
+ err |= ps8622_set(cl, 0x02, 0xa1, 0x01); /* HPD low */
+ /* SW setting */
+ err |= ps8622_set(cl, 0x04, 0x14, 0x01); /* [1:0] SW output 1.2V voltage
+ * is lower to 96% */
[PATCH V2 2/9] drm/panel: add pre_enable and post_disable routines
Most of the panels need an init sequence as mentioned below:
-- poweron LCD unit/LCD_EN
-- start video data
-- poweron LED unit/BL_EN
And, a de-init sequence as mentioned below:
-- poweroff LED unit/BL_EN
-- stop video data
-- poweroff LCD unit/LCD_EN
With existing callbacks for drm panel, we cannot accomodate such panels,
since only two callbacks, i.e panel_enable and panel_disable are supported.
This patch adds:
-- pre_enable callback which can be called before
the actual video data is on, and then call the enable
callback after the video data is available.
-- post_disable callback which can be called after
the video data is off, and use disable callback
to do something before switching off the video data.
Now, we can easily map the above scenario as shown below:
poweron LCD unit/LCD_EN = pre_enable callback
poweron LED unit/BL_EN = enable callback
poweroff LED unit/BL_EN = disable callback
poweroff LCD unit/LCD_EN = post_disable callback
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Added post_disable callback
include/drm/drm_panel.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index c2ab77a..bf191df 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -31,7 +31,9 @@ struct drm_device;
struct drm_panel;
struct drm_panel_funcs {
+ int (*post_disable)(struct drm_panel *panel);
int (*disable)(struct drm_panel *panel);
+ int (*pre_enable)(struct drm_panel *panel);
int (*enable)(struct drm_panel *panel);
int (*get_modes)(struct drm_panel *panel);
};
@@ -46,6 +48,14 @@ struct drm_panel {
struct list_head list;
};
+static inline int drm_panel_post_disable(struct drm_panel *panel)
+{
+ if (panel panel-funcs panel-funcs-post_disable)
+ return panel-funcs-post_disable(panel);
+
+ return panel ? -ENOSYS : -EINVAL;
+}
+
static inline int drm_panel_disable(struct drm_panel *panel)
{
if (panel panel-funcs panel-funcs-disable)
@@ -54,6 +64,14 @@ static inline int drm_panel_disable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
}
+static inline int drm_panel_pre_enable(struct drm_panel *panel)
+{
+ if (panel panel-funcs panel-funcs-pre_enable)
+ return panel-funcs-pre_enable(panel);
+
+ return panel ? -ENOSYS : -EINVAL;
+}
+
static inline int drm_panel_enable(struct drm_panel *panel)
{
if (panel panel-funcs panel-funcs-enable)
--
1.7.9.5
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[PATCH V2 7/9] drm/bridge: ptn3460: add drm_panel controls
attach ptn3460 connector to drm_panel and support drm_panel routines,
if a valid drm_panel object is passed to ptn3460_init.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Address few coding style comments from Jingoo Han
drivers/gpu/drm/bridge/Kconfig |1 +
drivers/gpu/drm/bridge/ptn3460.c| 20 +++-
drivers/gpu/drm/exynos/exynos_dp_core.c | 16
include/drm/bridge/ptn3460.h|6 --
4 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 884923f..3bc6845 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -2,4 +2,5 @@ config DRM_PTN3460
tristate PTN3460 DP/LVDS bridge
depends on DRM
select DRM_KMS_HELPER
+ select DRM_PANEL
---help---
diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c
index f1d2afc..3920202 100644
--- a/drivers/gpu/drm/bridge/ptn3460.c
+++ b/drivers/gpu/drm/bridge/ptn3460.c
@@ -19,6 +19,7 @@
#include linux/i2c.h
#include linux/gpio.h
#include linux/delay.h
+#include drm/drm_panel.h
#include drmP.h
#include drm_edid.h
@@ -38,6 +39,7 @@ struct ptn3460_bridge {
struct i2c_client *client;
struct drm_encoder *encoder;
struct drm_bridge *bridge;
+ struct drm_panel *panel;
struct edid *edid;
int gpio_pd_n;
int gpio_rst_n;
@@ -126,6 +128,8 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
gpio_set_value(ptn_bridge-gpio_rst_n, 1);
}
+ drm_panel_pre_enable(ptn_bridge-panel);
+
/*
* There's a bug in the PTN chip where it falsely asserts hotplug before
* it is fully functional. We're forced to wait for the maximum start up
@@ -142,6 +146,10 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
static void ptn3460_enable(struct drm_bridge *bridge)
{
+ struct ptn3460_bridge *ptn_bridge = bridge-driver_private;
+
+ if (ptn_bridge-enabled)
+ drm_panel_enable(ptn_bridge-panel);
}
static void ptn3460_disable(struct drm_bridge *bridge)
@@ -153,6 +161,9 @@ static void ptn3460_disable(struct drm_bridge *bridge)
ptn_bridge-enabled = false;
+ drm_panel_disable(ptn_bridge-panel);
+ drm_panel_post_disable(ptn_bridge-panel);
+
if (gpio_is_valid(ptn_bridge-gpio_rst_n))
gpio_set_value(ptn_bridge-gpio_rst_n, 1);
@@ -198,6 +209,7 @@ int ptn3460_get_modes(struct drm_connector *connector)
power_off = !ptn_bridge-enabled;
ptn3460_pre_enable(ptn_bridge-bridge);
+ ptn3460_enable(ptn_bridge-bridge);
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
if (!edid) {
@@ -265,7 +277,8 @@ struct drm_connector_funcs ptn3460_connector_funcs = {
};
int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder,
- struct i2c_client *client, struct device_node *node)
+ struct i2c_client *client, struct device_node *node,
+ struct drm_panel *panel)
{
int ret;
struct drm_bridge *bridge;
@@ -324,6 +337,11 @@ int ptn3460_init(struct drm_device *dev, struct
drm_encoder *encoder,
goto err;
}
+ if (panel) {
+ ptn_bridge-panel = panel;
+ drm_panel_attach(ptn_bridge-panel, ptn_bridge-connector);
+ }
+
bridge-driver_private = ptn_bridge;
encoder-bridge = bridge;
ptn_bridge-connector.polled = DRM_CONNECTOR_POLL_HPD;
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index dbc5ccc..4853f31 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -989,13 +989,14 @@ static bool find_bridge(const char *compat, struct
bridge_init *bridge)
/* returns the number of bridges attached */
static int exynos_drm_attach_lcd_bridge(struct drm_device *dev,
- struct drm_encoder *encoder)
+ struct drm_encoder *encoder, struct drm_panel *panel)
{
struct bridge_init bridge;
int ret;
if (find_bridge(nxp,ptn3460, bridge)) {
- ret = ptn3460_init(dev, encoder, bridge.client, bridge.node);
+ ret = ptn3460_init(dev, encoder, bridge.client, bridge.node,
+ panel);
if (!ret)
return 1;
}
@@ -1012,9 +1013,16 @@ static int exynos_dp_create_connector(struct
exynos_drm_display *display,
dp-encoder = encoder;
/* Pre-empt DP connector creation if there's a bridge */
- ret = exynos_drm_attach_lcd_bridge(dp-drm_dev, encoder);
- if (ret)
+ ret = exynos_drm_attach_lcd_bridge(dp-drm_dev, encoder, dp-drm_panel);
+ if (ret) {
+ /*
+* Also set dp-drm_panel = NULL so that we
[PATCH V2 5/9] drm/exynos: dp: modify driver to support drm_panel
This patch attaches the dp connector to exynos_dp_panel, and adds
calls to drm_panel functions to control panel power sequence.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Addressed a comment from Jingoo Han. Also added post_disable
control to exynos_dp driver.
drivers/gpu/drm/exynos/Kconfig |1 +
drivers/gpu/drm/exynos/exynos_dp_core.c | 18 ++
drivers/gpu/drm/exynos/exynos_dp_core.h |1 +
3 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 5bf5bca..56af433 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -52,6 +52,7 @@ config DRM_EXYNOS_DP
bool EXYNOS DRM DP driver support
depends on DRM_EXYNOS ARCH_EXYNOS
default DRM_EXYNOS
+ select DRM_PANEL
help
This enables support for DP device.
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 18fd9c5..dbc5ccc 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -28,6 +28,7 @@
#include drm/drmP.h
#include drm/drm_crtc.h
#include drm/drm_crtc_helper.h
+#include drm/drm_panel.h
#include drm/bridge/ptn3460.h
#include exynos_drm_drv.h
@@ -1028,6 +1029,9 @@ static int exynos_dp_create_connector(struct
exynos_drm_display *display,
drm_sysfs_connector_add(connector);
drm_mode_connector_attach_encoder(connector, encoder);
+ if (dp-drm_panel)
+ drm_panel_attach(dp-drm_panel, dp-connector);
+
return 0;
}
@@ -1062,10 +1066,12 @@ static void exynos_dp_poweron(struct exynos_dp_device
*dp)
if (dp-dpms_mode == DRM_MODE_DPMS_ON)
return;
+ drm_panel_pre_enable(dp-drm_panel);
clk_prepare_enable(dp-clock);
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
enable_irq(dp-irq);
+ drm_panel_enable(dp-drm_panel);
}
static void exynos_dp_poweroff(struct exynos_dp_device *dp)
@@ -1073,10 +1079,12 @@ static void exynos_dp_poweroff(struct exynos_dp_device
*dp)
if (dp-dpms_mode != DRM_MODE_DPMS_ON)
return;
+ drm_panel_disable(dp-drm_panel);
disable_irq(dp-irq);
flush_work(dp-hotplug_work);
exynos_dp_phy_exit(dp);
clk_disable_unprepare(dp-clock);
+ drm_panel_post_disable(dp-drm_panel);
}
static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
@@ -1225,6 +1233,7 @@ static int exynos_dp_dt_parse_panel(struct
exynos_dp_device *dp)
static int exynos_dp_bind(struct device *dev, struct device *master, void
*data)
{
struct platform_device *pdev = to_platform_device(dev);
+ struct device_node *panel_node;
struct drm_device *drm_dev = data;
struct resource *res;
struct exynos_dp_device *dp;
@@ -1299,6 +1308,15 @@ static int exynos_dp_bind(struct device *dev, struct
device *master, void *data)
INIT_WORK(dp-hotplug_work, exynos_dp_hotplug);
+ panel_node = of_find_compatible_node(NULL, NULL,
+ samsung,exynos-dp-panel);
+ if (panel_node) {
+ dp-drm_panel = of_drm_find_panel(panel_node);
+ of_node_put(panel_node);
+ if (!dp-drm_panel)
+ return -ENODEV;
+ }
+
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h
b/drivers/gpu/drm/exynos/exynos_dp_core.h
index 56fa43e..9dc7991 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -148,6 +148,7 @@ struct exynos_dp_device {
struct drm_device *drm_dev;
struct drm_connectorconnector;
struct drm_encoder *encoder;
+ struct drm_panel*drm_panel;
struct clk *clock;
unsigned intirq;
void __iomem*reg_base;
--
1.7.9.5
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[PATCH V2 0/9] drm: exynos: few patches to enhance bridge chip support
This series is based on exynos-drm-next-todo branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git This set of drm patches are needed to support bridge chips and eDP/LVDS panels with exynos_dp. Bridge chip driver for parade DP to LVDS converter is also added. For testing, I have used exynos5250-snow, and exynos5420-peach-pit boards along with a few local arch side patches. Andrew Bresticker (1): [PATCH 1/9] drm/exynos: dp: support hotplug detection via GPIO Ajay Kumar (7): [PATCH 2/9] drm/panel: add pre_enable and post_disable routines [PATCH 3/9] drm/panel: Add driver for exynos_dp based panels [PATCH 4/9] drm/exynos: add exynos_dp_panel driver registration to drm driver [PATCH 5/9] drm/exynos: dp: modify driver to support drm_panel [PATCH 7/9] drm/bridge: ptn3460: add drm_panel controls [PATCH 8/9] drm/bridge: Add PS8622 bridge driver [PATCH 9/9] drm/exynos: Add ps8622 lvds bridge discovery to DP driver Rahul Sharma (1): [PATCH 6/9] drm/bridge: ptn3460: enable polling based detection Major changes since V1: Add post_disable callback and add bridge chip driver for parade DP to LVDS converter .../devicetree/bindings/panel/exynos-dp-panel.txt | 45 ++ .../devicetree/bindings/video/exynos_dp.txt|4 + drivers/gpu/drm/bridge/Kconfig |8 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/ps8622.c| 566 drivers/gpu/drm/bridge/ptn3460.c | 21 +- drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_dp_core.c| 75 ++- drivers/gpu/drm/exynos/exynos_dp_core.h|2 + drivers/gpu/drm/exynos/exynos_dp_reg.c | 44 +- drivers/gpu/drm/exynos/exynos_drm_drv.c| 15 + drivers/gpu/drm/exynos/exynos_drm_drv.h|1 + drivers/gpu/drm/panel/Kconfig |9 + drivers/gpu/drm/panel/Makefile |1 + drivers/gpu/drm/panel/panel-exynos-dp.c| 251 + include/drm/bridge/ps8622.h| 42 ++ include/drm/bridge/ptn3460.h |6 +- include/drm/drm_panel.h| 18 + 18 files changed, 1088 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/exynos-dp-panel.txt create mode 100644 drivers/gpu/drm/bridge/ps8622.c create mode 100644 drivers/gpu/drm/panel/panel-exynos-dp.c create mode 100644 include/drm/bridge/ps8622.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 9/9] drm/exynos: Add ps8622 lvds bridge discovery to DP driver
This patch adds ps8622 lvds bridge discovery code to the dp driver.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Pushing V1 for this as V2 because this patch holds good in this series.
drivers/gpu/drm/exynos/exynos_dp_core.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 4853f31..0006412 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -30,6 +30,7 @@
#include drm/drm_crtc_helper.h
#include drm/drm_panel.h
#include drm/bridge/ptn3460.h
+#include drm/bridge/ps8622.h
#include exynos_drm_drv.h
#include exynos_dp_core.h
@@ -999,7 +1000,15 @@ static int exynos_drm_attach_lcd_bridge(struct drm_device
*dev,
panel);
if (!ret)
return 1;
+ } else if (find_bridge(parade,ps8625, bridge)) {
+
+ ret = ps8622_init(dev, encoder, bridge.client, bridge.node,
+ panel);
+
+ if (!ret)
+ return 1;
}
+
return 0;
}
--
1.7.9.5
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Re: [RFC v2 PATCH v2 06/14] drm/exynos: support MIPI DSI command mode
Hi YoungJun, Thank you for the patch. On Monday 21 April 2014 21:28:33 YoungJun Cho wrote: This patch adds I80 interface for FIMD to support command mode panel. For this, the below features are added: - Sets display interface mode relevant registers properly according to the interface type from DT - Adds drm_panel_cpu_timings structure . The command mode panel sets them as the private attributes in struct drm_display_mode and FIMD gets them by fimd_mode_set(). - Adds TE interrupt handler . FIMD driver should know TE signal from lcd panel to avoid tearing issue. - Adds trigger feature . In case of command mode panel, FIMD should set trigger bit, so that image data has to be transferred to display bus or lcd panel. Changelog v2: - Moves CPU timings relevant properties to panel DT (commented by Laurent Pinchart, Andrzej Hajda) Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 ++ drivers/gpu/drm/exynos/exynos_drm_crtc.h |2 + drivers/gpu/drm/exynos/exynos_drm_drv.h |2 + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 ++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 280 ++- include/drm/drm_mipi_dsi.h |2 + include/drm/drm_panel.h |7 + Could you please split the DRM core changes into two separate standalone patches (as they're unrelated to each other) ? include/video/samsung_fimd.h |3 +- 9 files changed, 277 insertions(+), 44 deletions(-) [snip] -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add peach-pit board support
Arun,
On Sat, Apr 19, 2014 at 10:26 PM, Arun Kumar K arun...@samsung.com wrote:
Adds the google peach-pit board dts file which uses
exynos5420 SoC.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5420-peach-pit.dts | 225
2 files changed, 226 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5420-peach-pit.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..09bcb8d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-snow.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-smdk5420.dtb \
+ exynos5420-peach-pit.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
new file mode 100644
index 000..4d61a5e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -0,0 +1,225 @@
+/*
+ * Google Peach Pit Rev 6+ board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include exynos5420.dtsi
+
+/ {
+ model = Google Peach Pit Rev 6+;
+
+ compatible = google,pit-rev16,
+ google,pit-rev15, google,pit-rev14,
+ google,pit-rev13, google,pit-rev12,
+ google,pit-rev11, google,pit-rev10,
+ google,pit-rev9, google,pit-rev8,
+ google,pit-rev7, google,pit-rev6,
+ google,pit, google,peach, samsung,exynos5420;
+
+ memory {
+ reg = 0x2000 0x8000;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5420-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ pinctrl@1340 {
+ lid_irq: lid-irq {
+ samsung,pins = gpx3-4;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ power_key_irq: power-key-irq {
+ samsung,pins = gpx1-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ tpm_irq: tpm-irq {
+ samsung,pins = gpx1-0;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ pinctrl@1401 {
+ spi_flash_cs: spi-flash-cs {
+ samsung,pins = gpa2-5;
+ samsung,pin-function = 1;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 3;
+ };
+
+ backlight_pwm: backlight-pwm {
+ samsung,pins = gpb2-0;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+ };
+
+ gpio-keys {
+ compatible = gpio-keys;
+
+ pinctrl-names = default;
+ pinctrl-0 = power_key_irq lid_irq;
+
+ power {
+ label = Power;
+ gpios = gpx1 2 1;
We should probably make the final number GPIO_ACTIVE_LOW instead of 1.
You'll probably need to add this to the top:
#include dt-bindings/gpio/gpio.h
+ linux,code = 116; /* KEY_POWER */
I believe you can just use KEY_POWER instead of 116 now, though you might need:
#include dt-bindings/input/input.h
See tegra124-venice2.dts.
+ gpio-key,wakeup;
+ };
+
+ lid-switch {
+ label = Lid;
+ gpios = gpx3 4 1;
+ linux,input-type = 5; /* EV_SW */
+ linux,code = 0; /* SW_LID */
Similar here. Use #defines directly.
+ debounce-interval = 1;
+ gpio-key,wakeup;
+ };
+ };
+
+ rtc@101E {
+ status = okay;
+ };
+
+ serial@12C3 {
+ status = okay;
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+
Re: [RFC v2 PATCH v3 10/14] drm/panel: add S6E3FA0 driver
Hi YoungJun,
Thank you for the patch.
On Monday 21 April 2014 21:28:37 YoungJun Cho wrote:
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Changelog v3:
- Moves CPU timings relevant properties from FIMD DT
(commented by Laurent Pinchart, Andrzej Hajda)
Signed-off-by: YoungJun Cho yj44@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/gpu/drm/panel/Kconfig |7 +
drivers/gpu/drm/panel/Makefile|1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 ++
3 files changed, 577 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
[snip]
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c new file mode 100644
index 000..1282678
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,569 @@
[snip]
+static int s6e3fa0_get_modes(struct drm_panel *panel)
+{
+ struct drm_connector *connector = panel-connector;
+ struct s6e3fa0 *ctx = panel_to_s6e3fa0(panel);
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_create(connector-dev);
+ if (!mode) {
+ DRM_ERROR(failed to create a new display mode\n);
+ return 0;
+ }
+
+ drm_display_mode_from_videomode(ctx-vm, mode);
+ mode-width_mm = ctx-width_mm;
+ mode-height_mm = ctx-height_mm;
+ connector-display_info.width_mm = mode-width_mm;
+ connector-display_info.height_mm = mode-height_mm;
+
+ mode-type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ mode-private = (void *)ctx-cpu_timings;
Wouldn't it make sense to create a new get_interface_params (or similar)
operation for drm_panel to query interface configuration parameters instead of
shoving it in the mode private field ?
+ drm_mode_probed_add(connector, mode);
+
+ return 1;
+}
[snip]
--
Regards,
Laurent Pinchart
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[PATCH v4 2/8] cpufreq: Use cpufreq_for_each_* macros for frequency table iteration
The cpufreq core now supports the cpufreq_for_each_entry and
cpufreq_for_each_valid_entry macros helpers for iteration over the
cpufreq_frequency_table, so use them.
It should have no functional changes.
Signed-off-by: Stratos Karafotis strat...@semaphore.gr
---
drivers/cpufreq/acpi-cpufreq.c | 9 +++---
drivers/cpufreq/arm_big_little.c | 16 +--
drivers/cpufreq/cpufreq_stats.c | 24 ++--
drivers/cpufreq/dbx500-cpufreq.c | 8 ++
drivers/cpufreq/elanfreq.c | 9 +++---
drivers/cpufreq/exynos-cpufreq.c | 11 ---
drivers/cpufreq/exynos5440-cpufreq.c | 30 +--
drivers/cpufreq/freq_table.c | 56
drivers/cpufreq/longhaul.c | 13 -
drivers/cpufreq/pasemi-cpufreq.c | 10 +++
drivers/cpufreq/powernow-k6.c| 14 -
drivers/cpufreq/ppc_cbe_cpufreq.c| 9 +++---
drivers/cpufreq/s3c2416-cpufreq.c| 40 +++---
drivers/cpufreq/s3c64xx-cpufreq.c| 15 --
14 files changed, 117 insertions(+), 147 deletions(-)
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 000e4e0..b0c18ed 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -213,7 +213,7 @@ static unsigned extract_io(u32 value, struct
acpi_cpufreq_data *data)
static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data)
{
- int i;
+ struct cpufreq_frequency_table *pos;
struct acpi_processor_performance *perf;
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
@@ -223,10 +223,9 @@ static unsigned extract_msr(u32 msr, struct
acpi_cpufreq_data *data)
perf = data-acpi_data;
- for (i = 0; data-freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (msr == perf-states[data-freq_table[i].driver_data].status)
- return data-freq_table[i].frequency;
- }
+ cpufreq_for_each_entry(pos, data-freq_table)
+ if (msr == perf-states[pos-driver_data].status)
+ return pos-frequency;
return data-freq_table[0].frequency;
}
diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c
index bad2ed3..1f4d4e3 100644
--- a/drivers/cpufreq/arm_big_little.c
+++ b/drivers/cpufreq/arm_big_little.c
@@ -226,22 +226,22 @@ static inline u32 get_table_count(struct
cpufreq_frequency_table *table)
/* get the minimum frequency in the cpufreq_frequency_table */
static inline u32 get_table_min(struct cpufreq_frequency_table *table)
{
- int i;
+ struct cpufreq_frequency_table *pos;
uint32_t min_freq = ~0;
- for (i = 0; (table[i].frequency != CPUFREQ_TABLE_END); i++)
- if (table[i].frequency min_freq)
- min_freq = table[i].frequency;
+ cpufreq_for_each_entry(pos, table)
+ if (pos-frequency min_freq)
+ min_freq = pos-frequency;
return min_freq;
}
/* get the maximum frequency in the cpufreq_frequency_table */
static inline u32 get_table_max(struct cpufreq_frequency_table *table)
{
- int i;
+ struct cpufreq_frequency_table *pos;
uint32_t max_freq = 0;
- for (i = 0; (table[i].frequency != CPUFREQ_TABLE_END); i++)
- if (table[i].frequency max_freq)
- max_freq = table[i].frequency;
+ cpufreq_for_each_entry(pos, table)
+ if (pos-frequency max_freq)
+ max_freq = pos-frequency;
return max_freq;
}
diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c
index ecaaebf..0cd9b4d 100644
--- a/drivers/cpufreq/cpufreq_stats.c
+++ b/drivers/cpufreq/cpufreq_stats.c
@@ -182,11 +182,11 @@ static void cpufreq_stats_free_table(unsigned int cpu)
static int __cpufreq_stats_create_table(struct cpufreq_policy *policy)
{
- unsigned int i, j, count = 0, ret = 0;
+ unsigned int i, count = 0, ret = 0;
struct cpufreq_stats *stat;
unsigned int alloc_size;
unsigned int cpu = policy-cpu;
- struct cpufreq_frequency_table *table;
+ struct cpufreq_frequency_table *pos, *table;
table = cpufreq_frequency_get_table(cpu);
if (unlikely(!table))
@@ -205,12 +205,8 @@ static int __cpufreq_stats_create_table(struct
cpufreq_policy *policy)
stat-cpu = cpu;
per_cpu(cpufreq_stats_table, cpu) = stat;
- for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
- unsigned int freq = table[i].frequency;
- if (freq == CPUFREQ_ENTRY_INVALID)
- continue;
+ cpufreq_for_each_valid_entry(pos, table)
count++;
- }
alloc_size = count * sizeof(int) + count * sizeof(u64);
@@ -228,15 +224,11 @@ static int __cpufreq_stats_create_table(struct
cpufreq_policy *policy)
#ifdef
Re: [RFC v2 PATCH v2 06/14] drm/exynos: support MIPI DSI command mode
Hi Laurent, Thank you for the comment. On 04/22/2014 07:52 AM, Laurent Pinchart wrote: Hi YoungJun, Thank you for the patch. On Monday 21 April 2014 21:28:33 YoungJun Cho wrote: This patch adds I80 interface for FIMD to support command mode panel. For this, the below features are added: - Sets display interface mode relevant registers properly according to the interface type from DT - Adds drm_panel_cpu_timings structure . The command mode panel sets them as the private attributes in struct drm_display_mode and FIMD gets them by fimd_mode_set(). - Adds TE interrupt handler . FIMD driver should know TE signal from lcd panel to avoid tearing issue. - Adds trigger feature . In case of command mode panel, FIMD should set trigger bit, so that image data has to be transferred to display bus or lcd panel. Changelog v2: - Moves CPU timings relevant properties to panel DT (commented by Laurent Pinchart, Andrzej Hajda) Signed-off-by: YoungJun Cho yj44@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/gpu/drm/exynos/Kconfig |1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 ++ drivers/gpu/drm/exynos/exynos_drm_crtc.h |2 + drivers/gpu/drm/exynos/exynos_drm_drv.h |2 + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 ++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 280 ++- include/drm/drm_mipi_dsi.h |2 + include/drm/drm_panel.h |7 + Could you please split the DRM core changes into two separate standalone patches (as they're unrelated to each other) ? Ok, it could be split into core and driver ones. The DRM core changes are required to link with TE irq handler callback. I'll do it next patch set. Thank you. Best regards YJ include/video/samsung_fimd.h |3 +- 9 files changed, 277 insertions(+), 44 deletions(-) [snip] -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] ARM: dts: disable MDMA1 node for smdk5420 board
Seungwon Jeon wrote:
+ Javi Merino and Tushar Behera
This change is similar to commit 3da355c(ARM: dts: Disable MDMA1 node
for arndale-octa board). If MDMA1 region is configured with secure mode,
it makes the boot failure with the following.
Unhandled fault: imprecise external abort (0x1406) at 0x
If so, how about adding the 'disabled' status in 5420 dtsi file? Then if
'enabling' is required, we can enable in each board dt file...
- Kukjin
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6910485..9a48e3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -373,4 +373,10 @@
};
};
};
+
+ amba {
+ mdma1: mdma@11C1 {
+ status = disabled;
+ };
+ };
};
--
1.7.0.4
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Re: [PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver
On Wednesday, April 16, 2014 11:49 PM, Vivek Gautam wrote: On Wed, Apr 16, 2014 at 7:14 PM, Tomasz Figa t.f...@samsung.com wrote: On 15.04.2014 08:09, Vivek Gautam wrote: On Thu, Apr 10, 2014 at 5:09 PM, Vivek Gautam wrote: On Wed, Apr 9, 2014 at 7:03 PM, Tomasz Figa t.f...@samsung.com wrote: On 09.04.2014 13:49, Vivek Gautam wrote: So, USB30_SCLK_100M is the SCLK that we are talking in the driver. I don't see any reference to XXTI in the USB 3.0 DRD controller chapter (in both Exynos5250 and 5420) In addition to this there's one more point to be noticed here. On Exynos5420 system, the sclk_usbphy300 (which is the sclk_usbphy30 for USB DRD channel 0), is also the PICO phy clock, i.e. USB 2.0 phy clock. So we should add a similar clk_get() for this clock in the phy-exynos5250-usb2 driver too, to support Exynos5420. Is something clear from the above block diagram ? (although the diagram looks weird - space and tabs problem :-( ) Basically there's the clock USB30_SCLK_100M which is going into the USB 3.0 DRD PHY controller. And this is the only sclk mentioned in the block diagram for USB 3.0 DRD controller in Exynos5420. Same is not there in the block diagram in Exynos5250 UM. From what I can see in the documentation, there are 4 USB 3.0 related clocks generated in CMU: - sclk_usbphy300, - sclk_usbphy301, - sclk_usbdrd300, - sclk_usbdrd301, They are all rated to max. 24 MHz and the recommended operating frequency is 24 MHz, so it looks exactly like USB PHY reference, which is usually a 24 MHz clock. To me, this looks like on Exynos5420 a separate special clock path is used instead of xusbxti as reference of USB 3.0 PHY and so the sclk should be simply passed as the ref clock. Ok, i will clear on this with the hardware engineer also once. May be Jingoo can help me with this. Jingoo, Can you please enquire about the clock path of usbphy30 reference clocks on Exynos5420. As mentioned by Tomasz above, we have sclk_usbphy300 and sclk_usbphy301 as the reference clocks for USB3.0 DRD phy. *Also* sclk_usbphy300 is used for Pico phy (which is the USb 2.0 phy used by ehci/ohci controller on Exynos5420). It will be of great help. Hi Vevek, Tomasz Long time no see. I asked USB S/W engineer and USB H/W engineer. There are two USB3.0 on Exynos5420; thus there are two sclks such as 'sclk_usbphy300 and sclk_usbphy301'. As Tomasz mentioned, 'sclk_usbphy300 and sclk_usbphy301' can be used instead of 'xusbxti' as reference of USB 3.0 PHY. However, on Exynos5420, ONLY 'sclk_usbphy300' can be used for USB2.0 pico phy. (so, '301' CANNOT support USB2.0 pico phy.) Best regards, Jingoo Han -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Jingoo, On Tue, Apr 22, 2014 at 7:48 AM, Jingoo Han jg1@samsung.com wrote: On Wednesday, April 16, 2014 11:49 PM, Vivek Gautam wrote: On Wed, Apr 16, 2014 at 7:14 PM, Tomasz Figa t.f...@samsung.com wrote: On 15.04.2014 08:09, Vivek Gautam wrote: On Thu, Apr 10, 2014 at 5:09 PM, Vivek Gautam wrote: On Wed, Apr 9, 2014 at 7:03 PM, Tomasz Figa t.f...@samsung.com wrote: On 09.04.2014 13:49, Vivek Gautam wrote: So, USB30_SCLK_100M is the SCLK that we are talking in the driver. I don't see any reference to XXTI in the USB 3.0 DRD controller chapter (in both Exynos5250 and 5420) In addition to this there's one more point to be noticed here. On Exynos5420 system, the sclk_usbphy300 (which is the sclk_usbphy30 for USB DRD channel 0), is also the PICO phy clock, i.e. USB 2.0 phy clock. So we should add a similar clk_get() for this clock in the phy-exynos5250-usb2 driver too, to support Exynos5420. Is something clear from the above block diagram ? (although the diagram looks weird - space and tabs problem :-( ) Basically there's the clock USB30_SCLK_100M which is going into the USB 3.0 DRD PHY controller. And this is the only sclk mentioned in the block diagram for USB 3.0 DRD controller in Exynos5420. Same is not there in the block diagram in Exynos5250 UM. From what I can see in the documentation, there are 4 USB 3.0 related clocks generated in CMU: - sclk_usbphy300, - sclk_usbphy301, - sclk_usbdrd300, - sclk_usbdrd301, They are all rated to max. 24 MHz and the recommended operating frequency is 24 MHz, so it looks exactly like USB PHY reference, which is usually a 24 MHz clock. To me, this looks like on Exynos5420 a separate special clock path is used instead of xusbxti as reference of USB 3.0 PHY and so the sclk should be simply passed as the ref clock. Ok, i will clear on this with the hardware engineer also once. May be Jingoo can help me with this. Jingoo, Can you please enquire about the clock path of usbphy30 reference clocks on Exynos5420. As mentioned by Tomasz above, we have sclk_usbphy300 and sclk_usbphy301 as the reference clocks for USB3.0 DRD phy. *Also* sclk_usbphy300 is used for Pico phy (which is the USb 2.0 phy used by ehci/ohci controller on Exynos5420). It will be of great help. Hi Vevek, Tomasz Long time no see. I asked USB S/W engineer and USB H/W engineer. There are two USB3.0 on Exynos5420; thus there are two sclks such as 'sclk_usbphy300 and sclk_usbphy301'. As Tomasz mentioned, 'sclk_usbphy300 and sclk_usbphy301' can be used instead of 'xusbxti' as reference of USB 3.0 PHY. Thank you so much for getting this information. I can re-spin the patch. :-) However, on Exynos5420, ONLY 'sclk_usbphy300' can be used for USB2.0 pico phy. (so, '301' CANNOT support USB2.0 pico phy.) True, for USB 2.0 pico phy, only sclk_usbphy300 can be used. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: disable MDMA1 node for smdk5420 board
On 22 April 2014 07:48, Kukjin Kim kgene@samsung.com wrote:
Seungwon Jeon wrote:
+ Javi Merino and Tushar Behera
This change is similar to commit 3da355c(ARM: dts: Disable MDMA1 node
for arndale-octa board). If MDMA1 region is configured with secure mode,
it makes the boot failure with the following.
Unhandled fault: imprecise external abort (0x1406) at 0x
If so, how about adding the 'disabled' status in 5420 dtsi file? Then if
'enabling' is required, we can enable in each board dt file...
That should be okay. While at it, we can remove the node disabling
code from Arndale-Octa board DTS file.
- Kukjin
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6910485..9a48e3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -373,4 +373,10 @@
};
};
};
+
+ amba {
+ mdma1: mdma@11C1 {
+ status = disabled;
+ };
+ };
};
--
1.7.0.4
--
Tushar Behera
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[PATCH] ARM: dts: Remove mau_pd node for Exynos5420
MAU powerdomain provides clocks for Audio sub-system block. This block
comprises of the I2S audio controller, audio DMA blocks and Audio
sub-system clock registers.
Right now, there is no way to hook up power-domains with clock providers.
During late boot when this power-domain gets disabled, we get following
external abort.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
arch/arm/boot/dts/exynos5420.dtsi |5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..68e0f24 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -219,11 +219,6 @@
reg = 0x100440C0 0x20;
};
- mau_pd: power-domain@100440E0 {
- compatible = samsung,exynos4210-pd;
- reg = 0x100440E0 0x20;
- };
-
g2d_pd: power-domain@10044100 {
compatible = samsung,exynos4210-pd;
reg = 0x10044100 0x20;
--
1.7.9.5
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Re: [PATCH] ARM: dts: Add peach-pit board support
On 20 April 2014 10:56, Arun Kumar K arun...@samsung.com wrote:
Adds the google peach-pit board dts file which uses
exynos5420 SoC.
Signed-off-by: Arun Kumar K arun...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5420-peach-pit.dts | 225
2 files changed, 226 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5420-peach-pit.dts
[ snip ]
+ pinctrl@1340 {
+ lid_irq: lid-irq {
+ samsung,pins = gpx3-4;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ power_key_irq: power-key-irq {
+ samsung,pins = gpx1-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ tpm_irq: tpm-irq {
+ samsung,pins = gpx1-0;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+ };
+
If you plan to respin, please consider keeping the above entries
sorted based on the pin numbers.
tpm_irq
power_key_irq
lid_irq
--
Tushar Behera
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