Re: [PATCH 12/16] i2c: i2c-s3c2410: Drop class based scanning to improve bootup time
Hi Wolfram, On Thu, Jul 10, 2014 at 5:16 PM, Wolfram Sang w...@the-dreams.de wrote: This driver has been flagged to drop class based instantiation. The removal improves boot-up time and is unneeded for embedded controllers. Users have been warned to switch for some time now, so we can actually do the removal. Keep the DEPRECATED flag, so the core can inform users that the behaviour finally changed now. After another transition period, this flag can go, too. While we are here, remove the indentation for the array setup because such things always break after some time. Signed-off-by: Wolfram Sang w...@the-dreams.de --- drivers/i2c/busses/i2c-s3c2410.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index e828a1dba0e5..6252c051525a 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -1128,11 +1128,11 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev) s3c24xx_i2c_parse_dt(pdev-dev.of_node, i2c); strlcpy(i2c-adap.name, s3c2410-i2c, sizeof(i2c-adap.name)); - i2c-adap.owner = THIS_MODULE; - i2c-adap.algo= s3c24xx_i2c_algorithm; + i2c-adap.owner = THIS_MODULE; + i2c-adap.algo = s3c24xx_i2c_algorithm; i2c-adap.retries = 2; - i2c-adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED; - i2c-tx_setup = 50; + i2c-adap.class = I2C_CLASS_DEPRECATED; + i2c-tx_setup = 50; init_waitqueue_head(i2c-wait); -- Tested on Exynos 5250 boards. Tested-by: Sachin Kamat sachin.ka...@samsung.com -- Regards, Sachin. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/4] ARM: Exynos: PMU cleanup and refactoring for using DT
Hello Pankaj, On 9 July 2014 09:30, Pankaj Dubey pankaj.du...@samsung.com wrote: This patch series, modifies Exynos Power Management Unit (PMU) related code for converting it into a platform_driver. This is also preparation for moving PMU related code out of machine folder into a either drivers/mfd, or drivers/power or some other suitable place so that ARM64 based SoC can utilize common piece of code. These patches are created on top of Kukjin Kim's for-next. I have tested this patches on Exynos5250 Snow board for system boot and S2R. This patch series depends on following two patch series: [1]: mfd: syscon: Decouple syscon interface from syscon devices. https://lkml.org/lkml/2014/6/24/188 [2]: Cleanup patches for mach-exynos. http://www.spinics.net/lists/arm-kernel/msg341474.html With the above mentioned patches + this series I was able to add PMU registers using syscon in the DTS node for DP and ADC. and access the PMU registers in the respective drivers using syscon API. Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Patch v6 and discussion can be found here: https://lkml.org/lkml/2014/7/7/22 Change since v6: - Removed NULL check for pmu_data in pmu.c. - Moved pmu_raw_readl and pmu_raw_writel inline helper function into common.h. Change Since v5: - Squashed patch Move mach/map.h inclusion from regs-pmu.h to platsmp.c into patch Refactored code for using PMU address via DT. - Addressed review comments from Tomasz Figa. - Using init_irq machine function to initialize PMU mapping instead of init_time. - Rebased on latest Kukjin Kim's for-next branch. Changes Since v4: - Splitted patch series in two parts. Part 1 has code cleanup under mach-exynos and posted as separate patch [2]. Current patchset is part 2 which modified exynos pmu implementation for making it platform driver. - Removed dependency over early_syscon API. - Removed usage of regmap read/write APIs. - Modified probe function to register exynos pmu as syscon provider using Tomasz Figa's syscon patch [1]. - Address various other review comments from Tomasz Figa. - Removed signed-off-by of Young-Gun Jang yg1004.j...@samsung.com, as this id is no more valid. Taking ownership of all his patches. Changes Since v3: - Optimized exynos_pmu_probe function by removing exynos_pmu_data_init as suggested by Vikas Sajjan. - Modified syscon_early_regmap_lookup_by_phandle and syscon_regmap_lookup_by_phandle function call to pass property as NULL. Changes Since v2: - Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches. - Removed early mapping of PMU base address from exynos.c and removed get_exynos_pmuaddr function. Instead of this added code in platsmp.c to get PMU base address using of_iomap as suggested by Tomasz Figa. - Converted PMU implementation into platform_driver by using static platform_device method. Changes Since v1: - Rebased on latest for-next of Kukjin Kim's tree. - Updated patch: Add support for mapping PMU base address via DT - Removed __initdata from declaration of exynos_pmu_base, as it caused kernel crash as pointed out by Vikas Sajjan. - Added support for Syscon initialization and getting PMU regmap handle as suggested by Sylwester. Since current implementation of early intialization [1] has limitation that early_syscon_init requires DT to be unflattened and system should be able to allocate memory, we can't use regmap handles for platsmp.c file as smp_secondary_init will be called before DT unflattening. So I have kept both method for accessing PMU base address. platsmp.c will use ioremmaped address where as rest other files can use regmap handle. - Updated patch: Refactored code for PMU register mapping via DT - Modified to use regmap_read/write when using regmap handle. - Added patch: Add device tree based initialization support for PMU. - Convert existing PMU implementation to be a device tree based before moving it to drivers/mfd folder. As suggested by Bartlomiej. - Dropped making a platform_driver for PMU, as currently PMU binding has two compatibility strings as samsung, exynosxxx-pmu, syscon, once we enable MFD_SYSCON config option, current syscon driver probe gets called and PMU probe never gets called. So modified PMU initialization code to scan DT and match against supported compatiblity string in driver code, and once we get matching node use that for accessing PMU regmap handle using syscon_early_regmap_lookup_by_phandle. If there is any better solution please suggest. Pankaj Dubey (4): ARM: EXYNOS: Add support for mapping PMU base address via DT ARM: EXYNOS: Refactored code for using PMU address via DT ARM: EXYNOS: Add platform driver support for Exynos PMU
Re: [PATCH v6 0/4] Adds PMU and S2R support for exynos5420
Hello Vikas, On 7 July 2014 18:25, Vikas Sajjan vikas.saj...@samsung.com wrote: Rebased on 1] Kukjin Kim's tree, for-next branch https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next 2] Pankaj Dubey's v6 PMU patchset http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg33660.html changes since v5: - Refactored pm.c to use DT based lookup as suggested by Tomasz Figa. changes since v4: - Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset changes since v3: Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz, Tomasz Figa and Alim Akhtar: - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h. - Merged exynos5420_set_core_flag function into powerdown_conf. - Removed XXTI_DURATION3 register setting. - Updated the commit message and ordered the clock registers in clock patch. - Removed the code for SYS_DISP1_BLK_CFG handling. - Modified SoC checks to A9 specific checks in PM code. - Updated some comments in the code and added macros for register offsets. - Fixed code which was changing pad retention code for older SoCs. changes since v2: - Addressed comments from Tomasz figa - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612 - dropped patch ARM: dts: Add node for GPIO keys on SMDK5420, will be sent separately. changes since v1: - Addressed comments from Tomasz figa. - restructured/consolidated as per Tomasz figa's PM consolidations for exynos Tested on Kukjin Kim's tree, for-next branch + 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html 2] http://www.spinics.net/lists/linux-samsung-soc/msg32923.html 3] https://www.mail-archive.com/linux-mmc@vger.kernel.org/msg26210.html (for eMMC S2R fail issue) on Exynos5420 based chromebook (peach-pit board) and Exynos5250 based chromebook (snow board). PS : Not tested on exynos4 based boards. Tested-by for exynos4 would be appreciated. Below procedures were followed to test S2R: Procedure A: 1. make multi_v7_defconfig 2 enable MCPM for 5420 3. enable S3C RTC 4. pass no_console_suspend in bootargs 5. echo +20 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state Procedure B: 1. make exynos_defconfig 2 enable MCPM for 5420 3 enable CONFIG_PL330_DMA 4. enable CONFIG_PM_RUNTIME 5. pass no_console_suspend in bootargs 6. echo +20 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state Could test with the given description on Exynos5420 based Peach PIT. S2R on Exynos5250 based Snow works fine too. With http://www.spinics.net/lists/linux-samsung-soc/msg33999.html S2R on Exynos5800 based Peach PI works fine. Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Abhilash Kesavan (2): arm: exynos5: Add PMU support for 5420 arm: exynos5: Add Suspend-to-RAM support for 5420 Vikas Sajjan (2): ARM: EXYNOS: Refactor the code to use DT based lookup clk: samsung: exynos5420: Setup clocks before system suspend arch/arm/mach-exynos/pm.c| 376 ++ arch/arm/mach-exynos/pmu.c | 288 ++ arch/arm/mach-exynos/regs-pmu.h | 230 + drivers/clk/samsung/clk-exynos5420.c | 29 +++ 4 files changed, 880 insertions(+), 43 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Shine bright, (: Nav :) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: exynos-audss: Keep the parent of mout_audss always enabled
On 06/13/2014 02:39 AM, Mike Turquette wrote: Quoting Tushar Behera (2014-06-12 00:29:23) On Wed, Jun 11, 2014 at 10:20 PM, Mike Turquette mturque...@linaro.org wrote: Quoting Tushar Behera (2014-06-10 22:32:17) When the output clock of AUDSS mux is disabled, we are getting kernel oops while doing a clk_get() on other clocks provided by AUDSS. Though user manual doesn't specify this dependency, we came across this issue while disabling the parent of AUDSS mux clocks. Hi Tushar, Can you help me understand better what the actual problem is? What is the root cause of the kernel oops? Currently AUDSS mux has two parents, XXTI crystal and MAU_EPLL clock. As per observation, when the output of AUDSS mux is gated, we are not able to do any operation on the clocks provided by MAU block (mostly the clocks used by ADMA and audio blocks). I tried to get a datasheet for Exynos 54xx but could not find it. I even looked at the public 5250 data sheet, but it is completely missing Chapter 34, Audio Subsystem, which apparently contains Figure 34-3, Clock names and clock tree diagram of MAUDIO_BLK. So without any clue about your hardware (not for lack of trying) I would guess that somewhere in the parent hierarchy you have an interface clock which must be enabled in order for you to touch the registers pertaining to the downstream audio clocks. Yes, right. As per observation, we need to keep the output of AUDSS mux enabled to access the registers present in MAU block. The right way to handle this requires two steps: 1) model your interface clock in the Linux clock framework if you haven't already (I assume it is a gate clock, or the child of a gate clock) The interface clock is already part of the clock framework. 2) the clk_ops callbacks for the affected audio clocks should wrap their operations (i.e. critical secion) with a clk_enable/clk_disable pair, where the clock being enables/disable is the interface clock mentioned above in #1 The CCF is reentrant, so you can do this by simply using the top-level clk.h API from within your clk_ops callbacks. Right now, the clocks are registered with clk_register_mux, clk_register_div and clk_register_gate calls which in turn set appropriate clk_ops callbacks. If I need to wrap the register access during these clk_ops callbacks with clk_enable/clk_disable of interface lock, I would have to reimplement the clk_ops callbacks in clk-exynos-audss driver. Is that the approach that you are suggesting? I might be totally wrong about the cause of the hang, but that's my best guess based on everyone's bug reports. There are 5 gate clocks within MAU block. While disabling the unused clocks, if CLK_MAU_EPLL is disabled first, then we are getting this system hang. Regards, Mike You mention calling clk_get on child clocks of the AUDSS mux fails, but I cannot imagine why. How can the enable/disable state of a clock affect the ability to clk_get other clocks? I might have a little vogue while updating the commit message (mentioning about clk_get which surely is only a s/w operation), but there is definitely some issue with handling those clocks under given scenario. I am on leave till end of this week, so I will update you more with the logs on Monday. Thanks, -- Tushar ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
The DT bindings in exynos-adc.txt applies to the ADC
driver (exynos-adc.c) developed based on IIO framework.
The bindings are more appropriate to be under
Documentation/devicetree/bindings/iio/adc/
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: devicet...@vger.kernel.org
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 82
.../devicetree/bindings/iio/adc/exynos-adc.txt | 82
2 files changed, 82 insertions(+), 82 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
deleted file mode 100644
index b87749a..000
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-Samsung Exynos Analog to Digital Converter bindings
-
-The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
-
-New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
- and future SoCs from Samsung
-2. Add ADC driver under iio/adc framework
-3. Also adds the Documentation for device tree bindings
-
-Required properties:
-- compatible: Must be samsung,exynos-adc-v1
- for exynos4412/5250 controllers.
- Must be samsung,exynos-adc-v2 for
- future controllers.
- Must be samsung,exynos3250-adc-v2 for
- for controllers compatible with ADC of
- Exynos3250.
-- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
-- interrupts: Contains the interrupt information for the timer. The
- format is being dependent on which interrupt controller
- the Samsung device uses.
-- #io-channel-cells = 1; As ADC has multiple outputs
-- clocks From common clock bindings: handles to clocks specified
- in clock-names property, in the same order.
-- clock-names From common clock bindings: list of clock input names
- used by ADC block:
- - adc : ADC bus clock
- - sclk_adc : ADC special clock (only for Exynos3250
- and compatible ADC block)
-- vdd-supply VDD input supply.
-
-Note: child nodes can be added for auto probing from device tree.
-
-Example: adding device info in dtsi file
-
-adc: adc@12D1 {
- compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
- interrupts = 0 106 0;
- #io-channel-cells = 1;
- io-channel-ranges;
-
- clocks = clock 303;
- clock-names = adc;
-
- vdd-supply = buck5_reg;
-};
-
-Example: adding device info in dtsi file for Exynos3250 with additional sclk
-
-adc: adc@126C {
- compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
- interrupts = 0 137 0;
- #io-channel-cells = 1;
- io-channel-ranges;
-
- clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
- clock-names = adc, sclk_adc;
-
- vdd-supply = buck5_reg;
-};
-
-Example: Adding child nodes in dts file
-
-adc@12D1 {
-
- /* NTC thermistor is a hwmon device */
- ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
- pullup-uv = 180;
- pullup-ohm = 47000;
- pulldown-ohm = 0;
- io-channels = adc 4;
- };
-};
-
-Note: Does not apply to ADC driver under arch/arm/plat-samsung/
-Note: The child node can be added under the adc node or separately.
diff --git a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
new file mode 100644
index 000..b87749a
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
@@ -0,0 +1,82 @@
+Samsung Exynos Analog to Digital Converter bindings
+
+The devicetree bindings are for the new ADC driver written for
+Exynos4 and upward SoCs from Samsung.
+
+New driver handles the following
+1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+ and future SoCs from Samsung
+2. Add ADC driver under iio/adc framework
+3. Also adds the Documentation for device tree bindings
+
+Required properties:
+- compatible: Must be samsung,exynos-adc-v1
+ for exynos4412/5250 controllers.
+ Must be samsung,exynos-adc-v2 for
+ future controllers.
+ Must be samsung,exynos3250-adc-v2 for
+ for controllers compatible with
[PATCH 0/4] iio: exynos-adc: use syscon instead of ioremap
This patch does the following 1. Use the syscon and Regmap API instead of ioremappaing the ADC_PHY register from PMU. 2. Moves the exynos-adc.txt from bindings/arm/samsung/ to bindings/iio/adc/. 3. Updates the Documentation in exynos-adc.txt with syscon phandle for the ADC nodes. 4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250, Exynos5420 with the syscon phandle. Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI by verifying sysfs entries provided by HWMON based NTC thermistors. Tested-By for Exynos3250, Exynos4x12 would be appreciated. Naveen Krishna Chatradhi (4): iio: exyno-adc: use syscon for PMU register access Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/ Documentation: dt-bindings: update exynos-adc.txt with syscon handle ARM: dts: exynos: Add sysreg phandle to ADC node .../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 -- .../devicetree/bindings/iio/adc/exynos-adc.txt | 87 arch/arm/boot/dts/exynos3250.dtsi |3 +- arch/arm/boot/dts/exynos4x12.dtsi |3 +- arch/arm/boot/dts/exynos5250.dtsi |3 +- arch/arm/boot/dts/exynos5420.dtsi |3 +- drivers/iio/adc/exynos_adc.c | 29 +-- 7 files changed, 115 insertions(+), 95 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] iio: exyno-adc: use syscon for PMU register access
This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-...@vger.kernel.org
---
drivers/iio/adc/exynos_adc.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index b63e882..60847ef 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -38,6 +38,8 @@
#include linux/iio/iio.h
#include linux/iio/machine.h
#include linux/iio/driver.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
/* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
@@ -79,11 +81,14 @@
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
+#define EXYNOS_ADCV1_PHY_OFFSET0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET0x0720
+
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
void __iomem*regs;
- void __iomem*enable_reg;
+ struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned intirq;
@@ -98,6 +103,7 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ int phy_offset;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -169,7 +175,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -183,7 +189,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V1_CON(info-regs));
con |= ADC_V1_CON_STANDBY;
@@ -208,6 +214,7 @@ static void exynos_adc_v1_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw= exynos_adc_v1_init_hw,
.exit_hw= exynos_adc_v1_exit_hw,
@@ -219,7 +226,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info-regs));
@@ -236,7 +243,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V2_CON1(info-regs));
con = ~ADC_CON_EN_START;
@@ -271,10 +278,12 @@ static void exynos_adc_v2_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
};
static struct exynos_adc_data const exynos3250_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.needs_sclk = true,
};
@@ -437,10 +446,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info-regs))
return PTR_ERR(info-regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info-enable_reg = devm_ioremap_resource(pdev-dev, mem);
- if (IS_ERR(info-enable_reg))
- return PTR_ERR(info-enable_reg);
+ info-pmu_map = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
+ samsung,syscon-phandle);
+ if (IS_ERR(info-pmu_map)) {
+ dev_err(pdev-dev, syscon regmap lookup failed.\n);
+ return PTR_ERR(info-pmu_map);
+ }
irq = platform_get_irq(pdev, 0);
if (irq 0) {
--
1.7.9.5
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[PATCH 4/4] ARM: dts: exynos: Add sysreg phandle to ADC node
Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.
This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-samsung-soc@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi |3 ++-
arch/arm/boot/dts/exynos4x12.dtsi |3 ++-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
arch/arm/boot/dts/exynos5420.dtsi |3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index c5e15db..51c9b0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -262,12 +262,13 @@
adc: adc@126C {
compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
clock-names = adc, sclk_adc;
clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..9a18d9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -114,13 +114,14 @@
adc: adc@126C {
compatible = samsung,exynos-adc-v1;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupt-parent = combiner;
interrupts = 10 3;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..6003777 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -762,12 +762,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100
interrupts = 0 106 0;
clocks = clock CLK_ADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..6979da8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -525,12 +525,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v2;
- reg = 0x12D1 0x100, 0x10040720 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
--
1.7.9.5
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Re: [PATCH 2/4] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
Hi Naveen, On Fri, Jul 11, 2014 at 2:36 PM, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote: The DT bindings in exynos-adc.txt applies to the ADC driver (exynos-adc.c) developed based on IIO framework. The bindings are more appropriate to be under Documentation/devicetree/bindings/iio/adc/ Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com To: devicet...@vger.kernel.org --- .../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 .../devicetree/bindings/iio/adc/exynos-adc.txt | 82 2 files changed, 82 insertions(+), 82 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt Tip: For only a file move or rename please use -M with git format-patch. That will make the patch concise. -- Regards, Sachin. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
Hello Sachin, On 11 July 2014 14:47, Sachin Kamat spk.li...@gmail.com wrote: Hi Naveen, On Fri, Jul 11, 2014 at 2:36 PM, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote: The DT bindings in exynos-adc.txt applies to the ADC driver (exynos-adc.c) developed based on IIO framework. The bindings are more appropriate to be under Documentation/devicetree/bindings/iio/adc/ Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com To: devicet...@vger.kernel.org --- .../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 .../devicetree/bindings/iio/adc/exynos-adc.txt | 82 2 files changed, 82 insertions(+), 82 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt Tip: For only a file move or rename please use -M with git format-patch. That will make the patch concise. Sure, Thanks. -- Regards, Sachin. -- Shine bright, (: Nav :) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 15/23] regulator: max77686: Setup DVS-related GPIOs on probe
On Fri, Jul 11, 2014 at 7:33 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Amit,
On 07/10/2014 12:08 PM, amit daniel kachhap wrote:
On Fri, Jul 4, 2014 at 3:25 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
MAX77686 PMIC support Dyamic Voltage Scaling (DVS) on a set
of Buck regulators. A number of GPIO are connected to these
lines and are requested by the mfd driver. Setup the GPIO
pins from the regulator driver.
If possible merge this patch with patch 8. Both are adding DVS
support. Put regmap_copy dependency patch in very beginning.
As Lee already said, I split the changes to minimize the cross-subsystem
churn.
Yes agreed. This comment doesn't hold.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/regulator/max77686.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/regulator/max77686.c b/drivers/regulator/max77686.c
index ef1af2d..ecce77a 100644
--- a/drivers/regulator/max77686.c
+++ b/drivers/regulator/max77686.c
@@ -435,6 +435,12 @@ static int max77686_pmic_dt_parse_pdata(struct
platform_device *pdev,
}
#endif /* CONFIG_OF */
+static inline bool max77686_is_dvs_buck(int id)
+{
+ /* BUCK 2,3 and 4 support DVS */
+ return (id = MAX77686_BUCK2 id = MAX77686_BUCK4);
I am just wondering if along with above check, SELB gpios (if present)
can be used to confirm if BUCK's are DVS based or not.
I don't know if SELB gpios being present or not should be used to determine
whether a BUCK includes the DVS feature. AFAIK boards could have some of these
lines hardwired and pulled high or low instead of using a GPIO.
As per the max77686 data sheet, selb2.3.4 uses logic high for no DVS
and logic low for DVS enabled.
So may be if DT is supplying selb gpios then the above checks can be
put otherwise not required.
Anyway from your other comments, since this patch series is not
handling complete DVS scenario.
So putting this check is not useful in this stage.
+}
+
static int max77686_pmic_probe(struct platform_device *pdev)
{
struct max77686_dev *iodev = dev_get_drvdata(pdev-dev.parent);
@@ -442,6 +448,9 @@ static int max77686_pmic_probe(struct platform_device
*pdev)
struct max77686_data *max77686;
int i, ret = 0;
struct regulator_config config = { };
+ unsigned int reg;
+ int buck_default_idx;
+ int buck_old_idx;
dev_dbg(pdev-dev, %s\n, __func__);
@@ -472,13 +481,34 @@ static int max77686_pmic_probe(struct platform_device
*pdev)
config.driver_data = max77686;
platform_set_drvdata(pdev, max77686);
+ buck_default_idx = pdata-buck_default_idx;
+ buck_old_idx = max77686_read_gpios(pdata);
+
for (i = 0; i MAX77686_REGULATORS; i++) {
struct regulator_dev *rdev;
+ int id = pdata-regulators[i].id;
config.init_data = pdata-regulators[i].initdata;
config.of_node = pdata-regulators[i].of_node;
max77686-opmode[i] = regulators[i].enable_mask;
+
+ if (max77686_is_dvs_buck(id)) {
+ /* Try to copy over data so we keep firmware
settings */
+ reg = regulators[i].vsel_reg;
+
+ ret = regmap_reg_copy(iodev-regmap,
+ reg + buck_default_idx,
+ reg + buck_old_idx);
+
+ if (ret)
+ dev_warn(pdev-dev, Copy err %d = %d
(%d)\n,
+reg + buck_old_idx,
+reg + buck_default_idx, ret);
+
+ regulators[i].vsel_reg += buck_default_idx;
+ }
+
rdev = devm_regulator_register(pdev-dev,
regulators[i], config);
if (IS_ERR(rdev)) {
@@ -488,6 +518,10 @@ static int max77686_pmic_probe(struct platform_device
*pdev)
}
}
+ ret = max77686_setup_gpios(iodev-dev);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.0.0.rc2
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Best regards,
Javier
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Re: [PATCH v7 08/24] mfd: max77686: Add Dynamic Voltage Scaling (DVS) support
On Fri, Jul 11, 2014 at 7:15 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Amit,
On 07/10/2014 11:59 AM, amit daniel kachhap wrote:
On Sat, Jul 5, 2014 at 1:54 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Some regulators on the MAX77686 PMIC have Dynamic Voltage Scaling
(DVS) support that allows output voltage to change dynamically.
For MAX77686, these regulators are Buck regulators 2, 3 and 4.
Each Buck output voltage is selected using a set of external
inputs: DVS1-3 and SELB2-4.
DVS registers can be used to configure the output voltages for each
Buck regulator and which one is active is controled by DVSx lines.
SELBx lines are used to control if individual Buck lines are ON or OFF.
This patch adds support to configure the DVSx and SELBx lines
from DT and to setup and read the GPIO lines connected to them.
The entire series looks nice. Few minor comments from my side. I guess
still one more version in needed as per other ppls comment.
You may add,
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Thanks.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Changes since v6:
- Add a comment that max77686_read_gpios() function can sleep.
Sugggested by Krzysztof Kozlowski
---
drivers/mfd/max77686.c | 119
+++
include/linux/mfd/max77686.h | 18 ---
2 files changed, 129 insertions(+), 8 deletions(-)
diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 8650832..d193873 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -32,8 +32,10 @@
#include linux/mfd/core.h
#include linux/mfd/max77686.h
#include linux/mfd/max77686-private.h
+#include linux/gpio/consumer.h
#include linux/err.h
#include linux/of.h
+#include linux/export.h
#define I2C_ADDR_RTC (0x0C 1)
@@ -101,9 +103,119 @@ static const struct of_device_id
max77686_pmic_dt_match[] = {
{},
};
+static void max77686_dt_parse_dvs_gpio(struct device *dev)
+{
+ struct max77686_platform_data *pd = dev_get_platdata(dev);
+ int i;
+
+ /*
+* NOTE: we don't consider GPIO errors fatal; board may have some
lines
+* directly pulled high or low and thus doesn't specify them.
+*/
+ for (i = 0; i ARRAY_SIZE(pd-buck_gpio_dvs); i++)
+ pd-buck_gpio_dvs[i] =
+ devm_gpiod_get_index(dev, max77686,pmic-buck-dvs,
i);
+
+ for (i = 0; i ARRAY_SIZE(pd-buck_gpio_selb); i++)
+ pd-buck_gpio_selb[i] =
+ devm_gpiod_get_index(dev,
max77686,pmic-buck-selb, i);
+}
+
+/**
+ * max77686_setup_gpios() - init DVS-related GPIOs
+ * @dev: device whose platform data contains the dvs GPIOs information
+ *
+ * This function claims / initalizations GPIOs related to DVS if they are
+ * defined. This may have the effect of switching voltages if the
+ * pdata-buck_default_idx does not match the boot time state of pins.
+ */
+int max77686_setup_gpios(struct device *dev)
+{
+ struct max77686_platform_data *pd = dev_get_platdata(dev);
+ int buck_default_idx = pd-buck_default_idx;
+ int ret;
+ int i;
+
+ /* Set all SELB high to avoid glitching while DVS is changing */
+ for (i = 0; i ARRAY_SIZE(pd-buck_gpio_selb); i++) {
+ struct gpio_desc *gpio = pd-buck_gpio_selb[i];
+
+ /* OK if some GPIOs aren't defined */
+ if (IS_ERR(gpio))
+ continue;
+
+ ret = gpiod_direction_output_raw(gpio, 1);
+ if (ret) {
+ dev_err(dev, can't set gpio[%d] dir: %d\n, i,
ret);
+ return ret;
+ }
+ }
+
+ /* Set our initial setting */
+ for (i = 0; i ARRAY_SIZE(pd-buck_gpio_dvs); i++) {
+ struct gpio_desc *gpio = pd-buck_gpio_dvs[i];
+
+ /* OK if some GPIOs aren't defined */
+ if (IS_ERR(gpio))
+ continue;
+
+ /* If a GPIO is valid, set it */
+ gpiod_direction_output(gpio, (buck_default_idx i) 1);
+ if (ret) {
+ dev_err(dev, can't set gpio[%d]: dir %d\n, i,
ret);
+ return ret;
+ }
+ }
+
+ /* Now set SELB low to take effect */
+ for (i = 0; i ARRAY_SIZE(pd-buck_gpio_selb); i++) {
+ struct gpio_desc *gpio = pd-buck_gpio_selb[i];
+
+ if (!IS_ERR(gpio))
+ gpiod_set_value(gpio, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(max77686_setup_gpios);
+
+/**
+ * max77686_read_gpios() - read the current state of the dvs GPIOs
+ * @pdata: platform data that contains the dvs GPIOs information
+
[PATCH 1/2] clk: exynos-audss: Simplify code to get clock names
Instead of getting the clock names individually, it would be good to put
the logic within a loop.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 33
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 13eae14c..ebfc5da 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -80,10 +80,14 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ struct clk *tmp;
+ const char *clk_name_ref[] = {
+ pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
+ const char *clk_name_actual[] = {
+ fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
const char *sclk_pcm_p = sclk_pcm0;
- struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
@@ -111,23 +115,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
else
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
- pll_ref = devm_clk_get(pdev-dev, pll_ref);
- pll_in = devm_clk_get(pdev-dev, pll_in);
- if (!IS_ERR(pll_ref))
- mout_audss_p[0] = __clk_get_name(pll_ref);
- if (!IS_ERR(pll_in))
- mout_audss_p[1] = __clk_get_name(pll_in);
+ for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
+ tmp = devm_clk_get(pdev-dev, clk_name_ref[i]);
+ if (!IS_ERR(tmp))
+ clk_name_actual[i] = __clk_get_name(tmp);
+ }
+
+ mout_audss_p[0] = clk_name_actual[0];
+ mout_audss_p[1] = clk_name_actual[1];
+ mout_i2s_p[1] = clk_name_actual[2];
+ mout_i2s_p[2] = clk_name_actual[3];
+ sclk_pcm_p = clk_name_actual[4];
+
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
- cdclk = devm_clk_get(pdev-dev, cdclk);
- sclk_audio = devm_clk_get(pdev-dev, sclk_audio);
- if (!IS_ERR(cdclk))
- mout_i2s_p[1] = __clk_get_name(cdclk);
- if (!IS_ERR(sclk_audio))
- mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, mout_i2s,
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
@@ -161,9 +165,6 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, lock);
- sclk_pcm_in = devm_clk_get(pdev-dev, sclk_pcm_in);
- if (!IS_ERR(sclk_pcm_in))
- sclk_pcm_p = __clk_get_name(sclk_pcm_in);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, sclk_pcm,
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
--
1.7.9.5
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[PATCH 0/2] clk: exynos-audss: Adapt to exising clock framework
The patchset is targetted as moving exising exynos-audss clock driver from being a module driver. The driver is now registered through CLK_OF_DECLARE and is inline with other Samsung clock drivers. The patches are tested on Exynos5800 based Peach-Pi board. More tests are welcome. Tushar Behera (2): clk: exynos-audss: Simplify code to get clock names clk: exynos-audss: Update as per existing framework drivers/clk/samsung/clk-exynos-audss.c | 268 1 file changed, 102 insertions(+), 166 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] clk: exynos-audss: Update as per existing framework
Change exynos-audss clock driver as per existing clock framework from
the existing module driver framework.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
drivers/clk/samsung/clk-exynos-audss.c | 239
1 file changed, 87 insertions(+), 152 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index ebfc5da..49f4163 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,26 +19,25 @@
#include dt-bindings/clock/exynos-audss-clk.h
+#include clk.h
+
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
-#define ASS_CLK_SRC 0x0
-#define ASS_CLK_DIV 0x4
-#define ASS_CLK_GATE 0x8
+#define ASS_CLK_SRC0x0
+#define ASS_CLK_DIV0x4
+#define ASS_CLK_GATE 0x8
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
- {ASS_CLK_SRC, 0},
- {ASS_CLK_DIV, 0},
- {ASS_CLK_GATE, 0},
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
};
static int exynos_audss_clk_suspend(void)
@@ -65,21 +64,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = samsung,exynos4210-audss-clock,
- .data = (void *)TYPE_EXYNOS4210, },
- { .compatible = samsung,exynos5250-audss-clock,
- .data = (void *)TYPE_EXYNOS5250, },
- { .compatible = samsung,exynos5420-audss-clock,
- .data = (void *)TYPE_EXYNOS5420, },
- {},
-};
-
-/* register exynos_audss clocks */
-static int exynos_audss_clk_probe(struct platform_device *pdev)
+static void __init exynos_audss_clk_init(struct device_node *np,
+ enum exynos_audss_clk_type variant)
{
- int i, ret = 0;
- struct resource *res;
+ int i;
struct clk *tmp;
const char *clk_name_ref[] = {
pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
@@ -87,163 +75,110 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
- const char *sclk_pcm_p = sclk_pcm0;
- const struct of_device_id *match;
- enum exynos_audss_clk_type variant;
-
- match = of_match_node(exynos_audss_clk_of_match, pdev-dev.of_node);
- if (!match)
- return -EINVAL;
- variant = (enum exynos_audss_clk_type)match-data;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- reg_base = devm_ioremap_resource(pdev-dev, res);
- if (IS_ERR(reg_base)) {
- dev_err(pdev-dev, failed to map audss registers\n);
- return PTR_ERR(reg_base);
- }
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
- return -ENOMEM;
-
- clk_data.clks = clk_table;
- if (variant == TYPE_EXYNOS5420)
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- else
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
+ char sclk_pcm_p[32];
+
+ struct samsung_mux_clock exynos_audss_mux_clks[] = {
+ MUX(EXYNOS_MOUT_AUDSS, mout_audss, mout_audss_p,
+ ASS_CLK_SRC, 0, 1),
+ MUX(EXYNOS_MOUT_I2S, mout_i2s, mout_i2s_p,
+ ASS_CLK_SRC, 2, 2),
+ };
+
+ struct samsung_div_clock exynos_audss_div_clks[] = {
+ DIV(EXYNOS_DOUT_SRP, dout_srp, mout_audss,
+ ASS_CLK_DIV, 0, 4),
+ DIV(EXYNOS_DOUT_AUD_BUS, dout_aud_bus, dout_srp,
+ ASS_CLK_DIV, 4, 4),
+ DIV(EXYNOS_DOUT_I2S, dout_i2s, mout_i2s, ASS_CLK_DIV, 8, 4),
+ };
+
+ struct samsung_gate_clock exynos_audss_gate_clks[] = {
+ GATE(EXYNOS_SRP_CLK, srp_clk, dout_srp,
+ ASS_CLK_GATE, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_I2S_BUS, i2s_bus, dout_aud_bus,
+ ASS_CLK_GATE, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_I2S, sclk_i2s, dout_i2s,
+ ASS_CLK_GATE, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_PCM_BUS, pcm_bus, sclk_pcm,
+ ASS_CLK_GATE, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_PCM, sclk_pcm, sclk_pcm_p,
+ ASS_CLK_GATE, 5, CLK_SET_RATE_PARENT, 0),
+ };
+
+
Re: [PATCH v7 08/24] mfd: max77686: Add Dynamic Voltage Scaling (DVS) support
Hi Javier, On 11.07.2014 03:45, Javier Martinez Canillas wrote: On 07/10/2014 11:59 AM, amit daniel kachhap wrote: On Sat, Jul 5, 2014 at 1:54 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: [snip] @@ -111,6 +223,13 @@ static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device return NULL; dev-platform_data = pd; + + /* Read default index and ignore errors, since default is 0 */ + of_property_read_u32(np, max77686,pmic-buck-default-dvs-idx, +pd-buck_default_idx); Any error checking code here. Say if pmic-buck-default-dvs-idx exceed 8? I'm not a DT expert but AFAIK the kernel should expect the data in a FDT to be correct and should not validate it on runtime. There is work-in-progress to add a proper schema checking for DTS to the dtc so on build time it can be validated that a DTS is valid. AFAIU the only thing that the kernel should check is if a required property does not exist. I'd disagree on this. IMHO schema (if it progresses further, as unfortunately I can't find time to dedicate to it and looks like it's similar for other people that used to be involved) should be focused on structural checks, i.e. proper layout of nodes and properties, basic data types and so, to figure out common errors earlier than at boot-up time. On kernel side this should be treated in the same way as platform data. I agree that some existing drivers do little to validate incoming data, but I believe it is a good practice to validate things that the driver has no control over, especially when it's about a PMIC, when invalid data can have quite serious effects and detecting even some of them (e.g. value to big, which would overflow in target bit field) might prevent a failure. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] clk: exynos-audss: Adapt to exising clock framework
Hi Tushar, On 11.07.2014 11:37, Tushar Behera wrote: The patchset is targetted as moving exising exynos-audss clock driver from being a module driver. The driver is now registered through CLK_OF_DECLARE and is inline with other Samsung clock drivers. I'm afraid I have to NAK this series or at least the part converting the driver back to use CLK_OF_DECLARE(). We have deliberately made this driver a platform driver, because this is how drivers should be modeled in Linux kernel whenever possible. CLK_OF_DECLARE() should be only considered a hack to work around late initialization of driver model. Reverting this change without a good reason (and you haven't provided such) is just going backwards. Rest of this series is actually quite nice, though, as reusing Samsung clock helpers reduces the line count significantly, so if you could rework this to keep this driver a platform driver then we could get something I could ack. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/2] clk: exynos-audss: Adapt to exising clock framework
On 07/11/2014 03:21 PM, Tomasz Figa wrote: Hi Tushar, On 11.07.2014 11:37, Tushar Behera wrote: The patchset is targetted as moving exising exynos-audss clock driver from being a module driver. The driver is now registered through CLK_OF_DECLARE and is inline with other Samsung clock drivers. I'm afraid I have to NAK this series or at least the part converting the driver back to use CLK_OF_DECLARE(). Considering the more prevalent usage of CLK_OF_DECLARE() in drivers/clk led me into thinking it was the normal way for the clock drivers. Keeping only one clock driver using a different approach looked odd to me. Anyways, I don't have any other reason to pursue this case. We have deliberately made this driver a platform driver, because this is how drivers should be modeled in Linux kernel whenever possible. CLK_OF_DECLARE() should be only considered a hack to work around late initialization of driver model. Reverting this change without a good reason (and you haven't provided such) is just going backwards. Rest of this series is actually quite nice, though, as reusing Samsung clock helpers reduces the line count significantly, so if you could rework this to keep this driver a platform driver then we could get something I could ack. Sure. There are still some valid cleanups even if we plan to retain the platform driver infrastructure. I will split and repost. Best regards, Tomasz -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 08/24] mfd: max77686: Add Dynamic Voltage Scaling (DVS) support
Hello Tomasz, On 07/11/2014 11:43 AM, Tomasz Figa wrote: Hi Javier, On 11.07.2014 03:45, Javier Martinez Canillas wrote: On 07/10/2014 11:59 AM, amit daniel kachhap wrote: On Sat, Jul 5, 2014 at 1:54 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: [snip] @@ -111,6 +223,13 @@ static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device return NULL; dev-platform_data = pd; + + /* Read default index and ignore errors, since default is 0 */ + of_property_read_u32(np, max77686,pmic-buck-default-dvs-idx, +pd-buck_default_idx); Any error checking code here. Say if pmic-buck-default-dvs-idx exceed 8? I'm not a DT expert but AFAIK the kernel should expect the data in a FDT to be correct and should not validate it on runtime. There is work-in-progress to add a proper schema checking for DTS to the dtc so on build time it can be validated that a DTS is valid. AFAIU the only thing that the kernel should check is if a required property does not exist. I'd disagree on this. IMHO schema (if it progresses further, as unfortunately I can't find time to dedicate to it and looks like it's similar for other people that used to be involved) should be focused on structural checks, i.e. proper layout of nodes and properties, basic data types and so, to figure out common errors earlier than at boot-up time. On kernel side this should be treated in the same way as platform data. I agree that some existing drivers do little to validate incoming data, but I believe it is a good practice to validate things that the driver has no control over, especially when it's about a PMIC, when invalid data can have quite serious effects and detecting even some of them (e.g. value to big, which would overflow in target bit field) might prevent a failure. Thanks a lot for the clarification and I completely agree with your explanation. I'll add proper validation for the data obtained by DT then. It would be nice if this was documented somewhere (or maybe I missed it). Best regards, Tomasz Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] mmc: dw_mmc: change to use recommended reset procedure
On Fri, July 11, 2014, Sonny Rao wrote:
On Thu, Jul 10, 2014 at 5:28 AM, Seungwon Jeon tgih@samsung.com wrote:
Hi Sonny,
I have missed this patch.
You finally choose to take extra interrupt handling.
If it is not harm, it's fine.
Hi, thanks for coming back to it. Based on my tracing, the interrupt
seems to be okay and is just ignored.
-static inline bool dw_mci_fifo_reset(struct dw_mci *host)
+static inline bool dw_mci_reset(struct dw_mci *host)
inline is no needed anymore.
{
+ u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
+ bool ret = false;
+
/*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
@@ -2334,15 +2330,59 @@ static inline bool dw_mci_fifo_reset(struct dw_mci
*host)
host-sg = NULL;
}
- return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
-}
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
-{
- return dw_mci_ctrl_reset(host,
- SDMMC_CTRL_FIFO_RESET |
- SDMMC_CTRL_RESET |
- SDMMC_CTRL_DMA_RESET);
+ if (dw_mci_ctrl_reset(host, flags)) {
+ /*
+ * In all cases we clear the RAWINTS register to clear any
+ * interrupts.
+ */
+ mci_writel(host, RINTSTS, 0x);
+
+ /* if using dma we wait for dma_req to clear */
+ if (host-use_dma) {
+ unsigned long timeout = jiffies +
msecs_to_jiffies(500);
+ u32 status;
+ do {
+ status = mci_readl(host, STATUS);
+ if (!(status SDMMC_STATUS_DMA_REQ))
+ break;
+ cpu_relax();
+ } while (time_before(jiffies, timeout));
+
+ if (status SDMMC_STATUS_DMA_REQ) {
+ dev_err(host-dev,
+ %s: Timeout waiting for dma_req to
+ clear during reset, __func__);
+ goto ciu_out;
+ }
+
+ /* when using DMA next we reset the fifo again */
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
+ goto ciu_out;
+ }
+ } else {
+ /* if the controller reset bit did clear, then set clock
regs */
+ if (!(mci_readl(host, CTRL) SDMMC_CTRL_RESET)) {
+ dev_err(host-dev, %s: fifo/dma reset bits didn't
+ clear but ciu was reset, doing clock
update.,
+ __func__);
+ goto ciu_out;
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_MMC_DW_IDMAC))
+ /* It is also recommended that we reset and reprogram idmac
*/
+ dw_mci_idmac_reset(host);
+
+ ret = true;
+
+ciu_out:
+ /* After a CTRL reset we need to have CIU set clock registers */
+ mci_send_cmd(host-cur_slot, SDMMC_CMD_UPD_CLK, 0);
+
+ return ret;
}
#ifdef CONFIG_OF
@@ -2555,7 +2595,7 @@ int dw_mci_probe(struct dw_mci *host)
}
/* Reset all blocks */
- if (!dw_mci_ctrl_all_reset(host))
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
return -ENODEV;
host-dma_ops = host-pdata-dma_ops;
@@ -2744,7 +2784,7 @@ int dw_mci_resume(struct dw_mci *host)
}
}
- if (!dw_mci_ctrl_all_reset(host)) {
+ if (!dw_mci_reset(host)) {
Do you have any reason to use dw_mci_reset() unlike doing on probing?
I really wanted to use dw_mci_reset() everwhere, including probe,
because that would be simplest, where there is just one reset function
always, but the host structure is not completely set up at probe time,
so the code in dw_mci_reset() where we try to send a command to update
clock fails, so that's why I had to just do a reset.
Yes, if we can keep one interface, it would be good.
But can you check below?
Did you see the kernel panic on probing with host-cur_slot is NULL?
If right, resume seems not different from probe in case of removable type.
And dw_mci_idmac_reset() is redundant when dw_mci_reset() is used at resume.
I think dw_mci_ctrl_reset() can be also used at resume like at probe for simple
way.
For safety's sake, host-cur_slot should be guaranteed it's not NULL.
Thanks,
Seungwon Jeon
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Re: [PATCH 2/2] clk: exynos-audss: Update as per existing framework
Hi Tushar, On 11/07/14 11:37, Tushar Behera wrote: Change exynos-audss clock driver as per existing clock framework from the existing module driver framework. Can you explain what's the actual issue you're trying to solve with that patch ? What's the problem with this driver being a platform driver ? It feels we're moving in circles here, see commit b37a4224104568198b93fb9831224cfe7d83fff8 Author: Andrew Bresticker abres...@chromium.org Date: Wed Sep 25 14:12:47 2013 -0700 clk: exynos-audss: convert to platform device The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by: Andrew Bresticker abres...@chromium.org Acked-by: Tomasz Figa t.f...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com Acked-by: Mike Turquette mturque...@linaro.org Acked-by: Kukjin Kim kgene@samsung.com Signed-off-by: Tomasz Figa t.f...@samsung.com I realize of_clk_init() now handles better clock provider dependencies, nevertheless do we really need all this churn ? -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v5] spi: s3c64xx: fix broken cs_gpios usage in the driver
Hello Naveen and Mark,
On Mon, Jul 7, 2014 at 1:22 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
On Mon, Jul 7, 2014 at 10:31 AM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
Hence, spi-s3c64xx.c is broken since Jun 21 11:26:12 2013 and
considering the time with no compliants about the breakage.
I'm not clear what the breakage is? Some boards are broken but what's
the driver issue?
ToT was broken for few boards
exynos4412-trats2.dts, exynos4210-smdkv310.dts and exynos5250-smdk5250.dts
With some DTS changes SPI works well, spi-s3c64xx.c driver had no issues.
Correct me if I'm wrong but I think that the driver does have issues
since the commit mentioned (3146bee) broke DT backward compatibility.
No, you're not answering my question - to repeat, what is the breakage?
As far as I understand, the breakage is that any DTS that followed the
DT binding documented in
Documentation/devicetree/bindings/spi/spi-samsung.txt is not working
with the current driver. So is not that some boards are broken, is
that the driver is broken and it has been broken for more than a year
(the commit date is Jun 21 2013).
The Documentation/devicetree/bindings/spi/spi-samsung.txt
describes cs-gpio as a controller specific property.
The dts entries for SPI in exynos4412-trats2.dts, exynos4210-smdkv310.dts
and exynos5250-smdk5250.dts boards have the cs-gpio property defined
under controller-data node, which is inside the SPI device node
spi_1 {
controller-data {
cs-gpio = ;
};
};
But, _probe() of spi-s3c64xx.c driver looks for cs-gpio in the SPI
device node and
sets a flag sdd-cs_gpio = false (If the property is not available)
spi_1 {
cs-gpio = ;
};
the sdd-cs_gpio flag is checked before actually getting the gpios
from the controller-data node
if (sdd-cs_gpio)
cs-line = of_get_named_gpio(data_np, cs-gpio, 0);
I think that if changing the binding is not possible, at least we
should document this new cs-gpio property that is looked in the top
level SPI node after commit 3146bee and also revert the default in
order to allow DTs using the old binding to keep working.
By default not having the cs-gpio property in the SPI dev node
should mean that the cs-gpio property in the controller-data node
should be used to signal the chip-select and having the cs-gpio
property in the SPI node should mean that the native chip select
should be used instead of a GPIO. That preserves the old DT binding
semantic while making the GPIO to be optional.
Of course in that case the property name does not make too much sense,
so probably should be changed to cs-native or something like that.
But I still don't understand why this is needed in the first place
since according to Documentation/devicetree/bindings/spi/spi-bus.txt
you can use the cs-gpios property to specify that a native chip-select
will be used instead of a GPIO by doing:
cs-gpios = gpio1 0 0 0
cs0 : gpio1 0 0
cs1 : native
Hence, SPI was failing on those boards.
1. As the SPI core and several drivers were changed to work with
DT property cs-gpios (plural) defined under SPI node.
2. Since the commit 3146beec21b64f4551fcf0ac148381d54dc41b1b
spi: s3c64xx: Added provision for dedicated cs pin
Dated: Fri Jun 21 11:26:12 2013 +0530
For the above 2 reasons, It was decided to drop the backward compatibility
of using cs-gpio(singular) in controller-data.
Instead, start supporting cs-gpios(plural) in the SPI node.
Right, since the DT binding has been broken for a year and because is
not consistent with the bindings used by all other SPI drivers, many
agreed that it was one of the exceptional cases where the DT binding
can be rethought and changed to use the generic cs-gpios property
already supported by SPI core. It breaks backward compatibility that's
true but the DT binding has been broken anyways and nobody noticed
before.
The other option is what I said above, fixing the DT binding
compatibility breakage while keeping the custom binding for this SPI
driver.
Also I'd need to check but are you sure that GPIO 0 is not valid?
gpio_is_valid() returns true for
number = 0 number ARCH_NR_GPIOS
Right, so this means that any board that is using the internal chip
select with zero as default in their platform data is broken by this
change.
I think this problem could be present in other SPI drivers as well? So
maybe the right fix for this is to convert the SPI core gpio handling
to use the new descriptor-based gpio API instead of the integer-base
one?
using gpio_is_valid() to sdd-cs_gpio flag every where to check for the
validity was a review comment.
Which seems to fail for internal chip select with zero.
I can submit another version withsdd-cs_gpio flag for this purpose.
--
Thanks Regards,
(: Nav :)
--
Any more opinions on this issue?
It would be great if we can move this forward since there are other
series that
[PATCH V2 1/3] clk: exynos-audss: Simplify code to get clock names
Instead of getting the clock names individually, it would be good to put
the logic within a loop.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changes for V2:
* Calling clk_put as soon as the clock is not required anymore
drivers/clk/samsung/clk-exynos-audss.c | 35 +---
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 13eae14c..1a5294c 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -80,10 +80,14 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ struct clk *tmp;
+ const char *clk_name_ref[] = {
+ pll_ref, pll_in, cdclk, sclk_audio, sclk_pcm_in };
+ const char *clk_name_actual[] = {
+ fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
const char *sclk_pcm_p = sclk_pcm0;
- struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
@@ -111,23 +115,25 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
else
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
- pll_ref = devm_clk_get(pdev-dev, pll_ref);
- pll_in = devm_clk_get(pdev-dev, pll_in);
- if (!IS_ERR(pll_ref))
- mout_audss_p[0] = __clk_get_name(pll_ref);
- if (!IS_ERR(pll_in))
- mout_audss_p[1] = __clk_get_name(pll_in);
+ for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
+ tmp = clk_get(pdev-dev, clk_name_ref[i]);
+ if (!IS_ERR(tmp)) {
+ clk_name_actual[i] = __clk_get_name(tmp);
+ clk_put(tmp);
+ }
+ }
+
+ mout_audss_p[0] = clk_name_actual[0];
+ mout_audss_p[1] = clk_name_actual[1];
+ mout_i2s_p[1] = clk_name_actual[2];
+ mout_i2s_p[2] = clk_name_actual[3];
+ sclk_pcm_p = clk_name_actual[4];
+
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, lock);
- cdclk = devm_clk_get(pdev-dev, cdclk);
- sclk_audio = devm_clk_get(pdev-dev, sclk_audio);
- if (!IS_ERR(cdclk))
- mout_i2s_p[1] = __clk_get_name(cdclk);
- if (!IS_ERR(sclk_audio))
- mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, mout_i2s,
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
@@ -161,9 +167,6 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, lock);
- sclk_pcm_in = devm_clk_get(pdev-dev, sclk_pcm_in);
- if (!IS_ERR(sclk_pcm_in))
- sclk_pcm_p = __clk_get_name(sclk_pcm_in);
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, sclk_pcm,
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, lock);
--
1.7.9.5
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[PATCH V2 2/3] clk: samsung: Add API to unregister clocks
Added an API to unregister all the clocks defined within a context. This
is helpful in case where the clock is registered through a platform
driver and we want to unregister the clocks during remove callback.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changelog:
This is new patch required because of changes to patch 3/3.
drivers/clk/samsung/clk.c | 19 +++
drivers/clk/samsung/clk.h |2 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 49629c7..b9310b9 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -83,6 +83,25 @@ struct samsung_clk_provider *__init samsung_clk_init(struct
device_node *np,
return ctx;
}
+/* API to remove a clock provider */
+void samsung_clk_exit(struct device_node *np, struct samsung_clk_provider *ctx)
+{
+ int i;
+
+ if (np)
+ of_clk_del_provider(np);
+
+ if (!ctx)
+ return;
+
+ for (i = 0; i ctx-clk_data.clk_num; i++)
+ if (!IS_ERR(ctx-clk_data.clks[i]))
+ clk_unregister(ctx-clk_data.clks[i]);
+
+ kfree(ctx-clk_data.clks);
+ kfree(ctx);
+}
+
/* add a clock instance to the clock lookup table used for dt based lookup */
void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
unsigned int id)
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 9693b80..8ecc85a 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -327,6 +327,8 @@ struct samsung_pll_clock {
extern struct samsung_clk_provider *__init samsung_clk_init(
struct device_node *np, void __iomem *base,
unsigned long nr_clks);
+extern void samsung_clk_exit(struct device_node *np,
+ struct samsung_clk_provider *ctx);
extern void __init samsung_clk_of_register_fixed_ext(
struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
--
1.7.9.5
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[PATCH V2 3/3] clk: exynos-audss: Use samsung clock APIs to register/unregister clocks
Using samsung clock APIs to register/unregister clocks will save some
lines of code.
Signed-off-by: Tushar Behera tusha...@samsung.com
---
Changes of v2:
* Retain platform driver structure.
drivers/clk/samsung/clk-exynos-audss.c | 146
1 file changed, 56 insertions(+), 90 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 1a5294c..2b90967 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,16 +19,16 @@
#include dt-bindings/clock/exynos-audss-clk.h
+#include clk.h
+
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
TYPE_EXYNOS5250,
TYPE_EXYNOS5420,
};
-static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
+static struct samsung_clk_provider *ctx;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
@@ -78,7 +78,7 @@ static const struct of_device_id exynos_audss_clk_of_match[]
= {
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- int i, ret = 0;
+ int i;
struct resource *res;
struct clk *tmp;
const char *clk_name_ref[] = {
@@ -87,14 +87,51 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
fin_pll, fout_epll, cdclk0, sclk_audio0, sclk_pcm0};
const char *mout_audss_p[] = {fin_pll, fout_epll};
const char *mout_i2s_p[] = {mout_audss, cdclk0, sclk_audio0};
- const char *sclk_pcm_p = sclk_pcm0;
+ char sclk_pcm_p[32];
const struct of_device_id *match;
enum exynos_audss_clk_type variant;
+ struct samsung_mux_clock exynos_audss_mux_clks[] = {
+ MUX(EXYNOS_MOUT_AUDSS, mout_audss, mout_audss_p,
+ ASS_CLK_SRC, 0, 1),
+ MUX(EXYNOS_MOUT_I2S, mout_i2s, mout_i2s_p,
+ ASS_CLK_SRC, 2, 2),
+ };
+
+ struct samsung_div_clock exynos_audss_div_clks[] = {
+ DIV(EXYNOS_DOUT_SRP, dout_srp, mout_audss,
+ ASS_CLK_DIV, 0, 4),
+ DIV(EXYNOS_DOUT_AUD_BUS, dout_aud_bus, dout_srp,
+ ASS_CLK_DIV, 4, 4),
+ DIV(EXYNOS_DOUT_I2S, dout_i2s, mout_i2s, ASS_CLK_DIV, 8, 4),
+ };
+
+ struct samsung_gate_clock exynos_audss_gate_clks[] = {
+ GATE(EXYNOS_SRP_CLK, srp_clk, dout_srp,
+ ASS_CLK_GATE, 0, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_I2S_BUS, i2s_bus, dout_aud_bus,
+ ASS_CLK_GATE, 2, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_I2S, sclk_i2s, dout_i2s,
+ ASS_CLK_GATE, 3, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_PCM_BUS, pcm_bus, sclk_pcm,
+ ASS_CLK_GATE, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(EXYNOS_SCLK_PCM, sclk_pcm, sclk_pcm_p,
+ ASS_CLK_GATE, 5, CLK_SET_RATE_PARENT, 0),
+ };
+
+ struct samsung_gate_clock exynos5420_audss_gate_clks[] = {
+ GATE(EXYNOS_ADMA, adma, dout_srp,
+ ASS_CLK_GATE, 9, CLK_SET_RATE_PARENT, 0),
+ };
+
+ int nr_clks = EXYNOS_AUDSS_MAX_CLKS;
+
match = of_match_node(exynos_audss_clk_of_match, pdev-dev.of_node);
if (!match)
return -EINVAL;
variant = (enum exynos_audss_clk_type)match-data;
+ if (variant != TYPE_EXYNOS5420)
+ nr_clks--;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(pdev-dev, res);
@@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(pdev-dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
+ ctx = samsung_clk_init(pdev-dev.of_node, reg_base, nr_clks);
+ if (!ctx) {
+ dev_err(pdev-dev, failed to get clock provier context\n);
return -ENOMEM;
-
- clk_data.clks = clk_table;
- if (variant == TYPE_EXYNOS5420)
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- else
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
+ }
for (i = 0; i ARRAY_SIZE(clk_name_ref); i++) {
tmp = clk_get(pdev-dev, clk_name_ref[i]);
@@ -127,69 +158,20 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
mout_audss_p[1] = clk_name_actual[1];
mout_i2s_p[1] = clk_name_actual[2];
mout_i2s_p[2] = clk_name_actual[3];
- sclk_pcm_p = clk_name_actual[4];
-
- clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, mout_audss,
-
[PATCH V2 0/3] clk: exynos-audss: Adapt to exising clock framework
Generic cleanup and usage of samsung clock register/unregister APIs. The patches are tested on Exynos5800 based Peach-Pi board. More tests are welcome. Tushar Behera (3): clk: exynos-audss: Simplify code to get clock names clk: samsung: Add API to unregister clocks clk: exynos-audss: Use samsung clock APIs to register/unregister clocks drivers/clk/samsung/clk-exynos-audss.c | 179 +--- drivers/clk/samsung/clk.c | 19 drivers/clk/samsung/clk.h |2 + 3 files changed, 95 insertions(+), 105 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] clk: exynos-audss: Update as per existing framework
On 07/11/2014 04:10 PM, Sylwester Nawrocki wrote: Hi Tushar, On 11/07/14 11:37, Tushar Behera wrote: Change exynos-audss clock driver as per existing clock framework from the existing module driver framework. Can you explain what's the actual issue you're trying to solve with that patch ? What's the problem with this driver being a platform driver ? It feels we're moving in circles here, see commit b37a4224104568198b93fb9831224cfe7d83fff8 Author: Andrew Bresticker abres...@chromium.org Date: Wed Sep 25 14:12:47 2013 -0700 clk: exynos-audss: convert to platform device The Exynos AudioSS clock controller will later be modified to allow input clocks to be specified via device-tree in order to support multiple Exynos SoCs. This will introduce a dependency on the core SoC clock controller being initialized first so that the AudioSS driver can look up its input clocks, but the order in which clock providers are probed in of_clk_init() is not guaranteed. Since deferred probing is not supported in of_clk_init() and the AudioSS block is not the core controller, we can initialize it later as a platform device. Signed-off-by: Andrew Bresticker abres...@chromium.org Acked-by: Tomasz Figa t.f...@samsung.com Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com Acked-by: Mike Turquette mturque...@linaro.org Acked-by: Kukjin Kim kgene@samsung.com Signed-off-by: Tomasz Figa t.f...@samsung.com I realize of_clk_init() now handles better clock provider dependencies, nevertheless do we really need all this churn ? I have sent v2 of the patchset while retaining the platform driver infrastructure. Awaiting your review comments on that. -- Thanks, Sylwester Thanks, -- Tushar Behera -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] devicetree: Add generic IOMMU device tree bindings
On Thu, Jul 10, 2014 at 11:32:16PM +0100, Olav Haugan wrote: On 7/9/2014 3:54 AM, Will Deacon wrote: On Wed, Jul 09, 2014 at 02:07:38AM +0100, Olav Haugan wrote: So how does an algorithm figure this out in both my examples? The algorithm would have to know about both (all) bus masters and their stream IDs for a specific SMMU. If the algorithm operates on the set of stream IDs for one bus master at a time the algorithm has no way of knowing which bits can be ignored since it doesn't know the value of the other stream IDs for the other bus masters and thus could potentially create a mask that could cause a stream ID to match in two different entries. Complete knowledge of the system topology (i.e. all bus masters) is a requirement for being able to configure the SMMU correctly if you want to guarantee that you don't have SMR aliasing issues. So you agree that an algorithm needs to know about all the bus masters/stream IDs for a specific IOMMU before it can figure out the StreamID masks and how many SMRs can be allocated to a specific bus master? Andreas's algorithm does not know about the other bus masters/stream IDs. It operates on one bus master at a time. Right, but it can certainly be improved. There are certain things you can do without complete knowledge, as I mentioned previously (if you can have densely packed power-of-2 aligned/sized regions). I am not familiar with Andreas's proposal. Do you have a link? http://marc.info/?l=linux-arm-kernelm=139110598005846w=2 Unless I am mistaken the algorithm works on one bus master at a time. I don't think that will work. IIRC, it works for densely packed SIDs on the master, so it tries to build up power-of-2 sized groups for that master then mops up the rest with individual entries. I ran the algorithm through a few trivial cases: 1) Stream IDs: 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28 Number of SMRs: 9 In this case the algorithm decided to set mask to 0 for all entries using up 8 of the SMRs. Well think about what it's doing... we don't know about SID 0x20, for example so there's not much it can do. 2) Same Stream IDs but only 2 SMRs. The algorithm gave an error saying I did not have enough SMRs. There's a reason this didn't get merged, and it would be great if you could try to improve the situation ;). Will -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: samsung-i2s: Maintain CDCLK settings across i2s_{shutdown/startup}
On Thu, Jul 10, 2014 at 06:11:13PM +0200, Sylwester Nawrocki wrote: Currently configuration of the CDCLK pad is being overwritten in the i2s_shutdown() callback in order to gate the SoC output clock. Applied, thanks. signature.asc Description: Digital signature
[PATCH] ARM: EXYNOS: Fix build with PM_SLEEP=n
Fix building of exynos defconfig with disabled PM_SLEEP:
CONFIG_PM_SLEEP=n
CONFIG_PM_SLEEP_SMP=n
CONFIG_SUSPEND=n
The build error messages:
arch/arm/mach-exynos/built-in.o: In function `exynos_boot_secondary':
arch/arm/mach-exynos/platsmp.c:111: undefined reference to
`exynos_cpu_power_state'
arch/arm/mach-exynos/platsmp.c:112: undefined reference to `exynos_cpu_power_up'
arch/arm/mach-exynos/platsmp.c:116: undefined reference to
`exynos_cpu_power_state'
make: *** [vmlinux] Error 1
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/mach-exynos/common.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f8daa9cc5617..966ecf195265 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -149,9 +149,15 @@ struct exynos_pmu_conf {
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+#ifdef CONFIG_PM_SLEEP
extern void exynos_cpu_power_down(int cpu);
extern void exynos_cpu_power_up(int cpu);
extern int exynos_cpu_power_state(int cpu);
+#else
+extern inline void exynos_cpu_power_down(int cpu) {}
+extern inline void exynos_cpu_power_up(int cpu) {}
+extern inline int exynos_cpu_power_state(int cpu) { return 0; }
+#endif
extern void exynos_cluster_power_down(int cluster);
extern void exynos_cluster_power_up(int cluster);
extern int exynos_cluster_power_state(int cluster);
--
1.9.1
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[PATCH 4/4] ASoC: samsung: remove unused DMA data
The s3c_dma_client structures and the 'ch' and 'ops' members in
s3c_dma_params were only used by the legacy DMA driver and serve
no function any more. This removes any reference to them.
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Heiko Stuebner he...@sntech.de
Cc: Sangbeom Kim sbki...@samsung.com
Cc: Ben Dooks ben-li...@fluff.org
Cc: Kukjin Kim kgene@samsung.com
Cc: linux-samsung-soc@vger.kernel.org
---
sound/soc/samsung/ac97.c| 15 ---
sound/soc/samsung/dma.h | 7 ---
sound/soc/samsung/i2s.c | 6 --
sound/soc/samsung/pcm.c | 12
sound/soc/samsung/s3c-i2s-v2.c | 2 --
sound/soc/samsung/s3c2412-i2s.c | 4
sound/soc/samsung/s3c24xx-i2s.c | 4
sound/soc/samsung/spdif.c | 5 -
8 files changed, 55 deletions(-)
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 2aa24d052a4a..e1615113fd84 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -38,30 +38,15 @@ struct s3c_ac97_info {
};
static struct s3c_ac97_info s3c_ac97;
-static struct s3c_dma_client s3c_dma_client_out = {
- .name = AC97 PCMOut
-};
-
-static struct s3c_dma_client s3c_dma_client_in = {
- .name = AC97 PCMIn
-};
-
-static struct s3c_dma_client s3c_dma_client_micin = {
- .name = AC97 MicIn
-};
-
static struct s3c_dma_params s3c_ac97_pcm_out = {
- .client = s3c_dma_client_out,
.dma_size = 4,
};
static struct s3c_dma_params s3c_ac97_pcm_in = {
- .client = s3c_dma_client_in,
.dma_size = 4,
};
static struct s3c_dma_params s3c_ac97_mic_in = {
- .client = s3c_dma_client_micin,
.dma_size = 4,
};
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index 070ab0f09609..0e85dcfec023 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -14,17 +14,10 @@
#include sound/dmaengine_pcm.h
-struct s3c_dma_client {
- char *name;
-};
-
struct s3c_dma_params {
- struct s3c_dma_client *client; /* stream identifier */
int channel;/* Channel ID */
dma_addr_t dma_addr;
int dma_size; /* Size of the DMA transfer */
- unsigned ch;
- struct samsung_dma_ops *ops;
char *ch_name;
struct snd_dmaengine_dai_dma_data dma_data;
};
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 5f9b255a8b38..db8b29a0d106 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -1212,11 +1212,7 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
pri_dai-dma_playback.dma_addr = regs_base + I2STXD;
pri_dai-dma_capture.dma_addr = regs_base + I2SRXD;
- pri_dai-dma_playback.client =
- (struct s3c_dma_client *)pri_dai-dma_playback;
pri_dai-dma_playback.ch_name = tx;
- pri_dai-dma_capture.client =
- (struct s3c_dma_client *)pri_dai-dma_capture;
pri_dai-dma_capture.ch_name = rx;
pri_dai-dma_playback.dma_size = 4;
pri_dai-dma_capture.dma_size = 4;
@@ -1234,8 +1230,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
goto err;
}
sec_dai-dma_playback.dma_addr = regs_base + I2STXDS;
- sec_dai-dma_playback.client =
- (struct s3c_dma_client *)sec_dai-dma_playback;
sec_dai-dma_playback.ch_name = tx-sec;
if (!np) {
diff --git a/sound/soc/samsung/pcm.c b/sound/soc/samsung/pcm.c
index 4c5f97fe45c8..bac034b15a27 100644
--- a/sound/soc/samsung/pcm.c
+++ b/sound/soc/samsung/pcm.c
@@ -131,32 +131,20 @@ struct s3c_pcm_info {
struct s3c_dma_params *dma_capture;
};
-static struct s3c_dma_client s3c_pcm_dma_client_out = {
- .name = PCM Stereo out
-};
-
-static struct s3c_dma_client s3c_pcm_dma_client_in = {
- .name = PCM Stereo in
-};
-
static struct s3c_dma_params s3c_pcm_stereo_out[] = {
[0] = {
- .client = s3c_pcm_dma_client_out,
.dma_size = 4,
},
[1] = {
- .client = s3c_pcm_dma_client_out,
.dma_size = 4,
},
};
static struct s3c_dma_params s3c_pcm_stereo_in[] = {
[0] = {
- .client = s3c_pcm_dma_client_in,
.dma_size = 4,
},
[1] = {
- .client = s3c_pcm_dma_client_in,
.dma_size = 4,
},
};
diff --git a/sound/soc/samsung/s3c-i2s-v2.c b/sound/soc/samsung/s3c-i2s-v2.c
index de6c321b8b68..df65c5b494b1 100644
--- a/sound/soc/samsung/s3c-i2s-v2.c
+++ b/sound/soc/samsung/s3c-i2s-v2.c
@@ -22,8 +22,6 @@
#include sound/soc.h
#include sound/pcm_params.h
-#include mach/dma.h
-
#include regs-i2s-v2.h
#include s3c-i2s-v2.h
#include dma.h
diff --git a/sound/soc/samsung/s3c2412-i2s.c
[PATCH 3/4] ASoC: samsung: s3c24xx dmaengine follow-up
Commit ae602456e83c92 (ASoC: samsung: drop support for legacy
S3C24XX DMA API) removed the old code for the samsung specific
DMA interfaces, now that everybody can use dmaengine.
This picks up the few remaining pieces left over by that patch:
The most important one is the removal of the dma_data-ops-started()
calls in ac97. My understanding is that these are only required
for drivers that do not support cyclic transfers, which the new dma
engine driver now does, so we can simply remove them. This would also
fix at least one bug in the ac97 driver on newer machines, which
currently gives us a NULL pointer dereference from trying to call
dma_data-ops-started().
Further, we must no longer 'select' S3C2410_DMA, which conflicts
with the dmaengine driver. The SND_S3C_DMA symbol is now
useless, because it is always selected, so we can remove it
and build the dmaengine support unconditionally.
Finally, we should not 'select' S3C24XX_DMAC or S3C64XX_PL080,
which may have additional dependencies. This replaces it with
'depends on', to be more conservative.
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Heiko Stuebner he...@sntech.de
Cc: Sangbeom Kim sbki...@samsung.com
Cc: Ben Dooks ben-li...@fluff.org
Cc: Kukjin Kim kgene@samsung.com
Cc: linux-samsung-soc@vger.kernel.org
---
sound/soc/samsung/Kconfig | 10 ++
sound/soc/samsung/Makefile | 2 +-
sound/soc/samsung/ac97.c | 17 -
3 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 7622af82ac4f..afcf95c6e212 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,18 +1,14 @@
config SND_SOC_SAMSUNG
tristate ASoC support for Samsung
depends on PLAT_SAMSUNG
- select S3C24XX_DMAC if ARCH_S3C24XX
- select S3C64XX_PL080 if ARCH_S3C64XX
- select SND_S3C_DMA
+ depends on S3C64XX_PL080 || !ARCH_S3C64XX
+ depends on S3C24XX_DMAC || !ARCH_S3C24XX
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for codecs attached to
the Samsung SoCs' Audio interfaces. You will also need to
select the audio interfaces to support below.
-config SND_S3C_DMA
- tristate
-
config SND_S3C24XX_I2S
tristate
@@ -77,7 +73,6 @@ config SND_SOC_SAMSUNG_SMDK_WM8994
config SND_SOC_SAMSUNG_SMDK2443_WM9710
tristate SoC AC97 Audio support for SMDK2443 - WM9710
depends on SND_SOC_SAMSUNG MACH_SMDK2443
- select S3C2410_DMA
select AC97_BUS
select SND_SOC_AC97_CODEC
select SND_SAMSUNG_AC97
@@ -88,7 +83,6 @@ config SND_SOC_SAMSUNG_SMDK2443_WM9710
config SND_SOC_SAMSUNG_LN2440SBC_ALC650
tristate SoC AC97 Audio support for LN2440SBC - ALC650
depends on SND_SOC_SAMSUNG ARCH_S3C24XX
- select S3C2410_DMA
select AC97_BUS
select SND_SOC_AC97_CODEC
select SND_SAMSUNG_AC97
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index e8d9ccdc41fd..91505ddaaf95 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -9,7 +9,7 @@ snd-soc-samsung-spdif-objs := spdif.o
snd-soc-pcm-objs := pcm.o
snd-soc-i2s-objs := i2s.o
-obj-$(CONFIG_SND_S3C_DMA) += snd-soc-s3c-dma.o
+obj-$(CONFIG_SND_SOC_SAMSUNG) += snd-soc-s3c-dma.o
obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o
obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o
obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 68d9303047e8..2aa24d052a4a 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -19,7 +19,6 @@
#include sound/soc.h
-#include mach/dma.h
#include regs-ac97.h
#include linux/platform_data/asoc-s3c.h
@@ -225,9 +224,6 @@ static int s3c_ac97_trigger(struct snd_pcm_substream
*substream, int cmd,
struct snd_soc_dai *dai)
{
u32 ac_glbctrl;
- struct snd_soc_pcm_runtime *rtd = substream-private_data;
- struct s3c_dma_params *dma_data =
- snd_soc_dai_get_dma_data(rtd-cpu_dai, substream);
ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
if (substream-stream == SNDRV_PCM_STREAM_CAPTURE)
@@ -253,11 +249,6 @@ static int s3c_ac97_trigger(struct snd_pcm_substream
*substream, int cmd,
writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
- if (!dma_data-ops)
- dma_data-ops = samsung_dma_get_ops();
-
- dma_data-ops-started(dma_data-channel);
-
return 0;
}
@@ -265,9 +256,6 @@ static int s3c_ac97_mic_trigger(struct snd_pcm_substream
*substream,
int cmd, struct snd_soc_dai *dai)
{
u32 ac_glbctrl;
- struct snd_soc_pcm_runtime *rtd = substream-private_data;
- struct s3c_dma_params *dma_data =
- snd_soc_dai_get_dma_data(rtd-cpu_dai, substream);
ac_glbctrl =
Re: [PATCH 8/9] Documentation: devicetree: Document sclk-jpeg clock for exynos3250 SoC
On 07/07/14 18:32, Jacek Anaszewski wrote: JPEG IP on Exynos3250 SoC requires enabling two clock gates for its operation. This patch documents this requirement. Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Cc: Rob Herring robh...@kernel.org Cc: Pawel Moll pawel.m...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Ian Campbell ijc+devicet...@hellion.org.uk Cc: Kumar Gala ga...@codeaurora.org Cc: devicet...@vger.kernel.org --- .../bindings/media/exynos-jpeg-codec.txt |9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt index 937b755..20cd150 100644 --- a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt +++ b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt @@ -3,9 +3,12 @@ Samsung S5P/EXYNOS SoC series JPEG codec Required properties: - compatible : should be one of: - samsung,s5pv210-jpeg, samsung,exynos4210-jpeg; + samsung,s5pv210-jpeg, samsung,exynos4210-jpeg, + samsung,exynos3250-jpeg; - reg: address and length of the JPEG codec IP register set; - interrupts : specifies the JPEG codec IP interrupt; - clocks : should contain the JPEG codec IP gate clock specifier, from the - common clock bindings; -- clock-names: should contain jpeg entry. + common clock bindings; for Exynos3250 SoC special clock gate + should be defined as the second element of the clocks array Entries in the clocks and clock-names can be in any order, the only requirement normally is that they match. I would rephrase this to something along the lines of: - clocks : should contain the JPEG codec IP gate clock specifier and for the Exynos3250 SoC additionally the SCLK_JPEG entry; from the common clock bindings; +- clock-names: should contain jpeg entry and additionally sclk-jpeg entry + for Exynos3250 SoC -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v5] spi: s3c64xx: fix broken cs_gpios usage in the driver
On Fri, Jul 11, 2014 at 01:04:07PM +0200, Javier Martinez Canillas wrote: Hello Naveen and Mark, On Mon, Jul 7, 2014 at 1:22 PM, Javier Martinez Canillas jav...@dowhile0.org wrote: On Mon, Jul 7, 2014 at 10:31 AM, Naveen Krishna Ch naveenkrishna...@gmail.com wrote: Please delete irrelevant context from your replies, this mail is over a hundred lines long and has only three lines of new content. Any more opinions on this issue? It would be great if we can move this forward since there are other series that depend on these fixes. Well, the bug with making a GPIO chip select mandatory needs to be fixed. signature.asc Description: Digital signature
Re: [PATCH 1/9] s5p-jpeg: Add support for Exynos3250 SoC
On 07/07/14 18:32, Jacek Anaszewski wrote:
+void exynos3250_jpeg_dec_scaling_ratio(void __iomem *regs,
+ unsigned int sratio)
+{
+ switch (sratio) {
+ case 1:
+ sratio = EXYNOS3250_DEC_SCALE_FACTOR_8_8;
+ break;
+ case 2:
+ sratio = EXYNOS3250_DEC_SCALE_FACTOR_4_8;
+ break;
+ case 4:
+ sratio = EXYNOS3250_DEC_SCALE_FACTOR_2_8;
+ break;
+ case 8:
+ sratio = EXYNOS3250_DEC_SCALE_FACTOR_1_8;
+ break;
+ }
Missing the 'default' case ?
+ writel(sratio EXYNOS3250_DEC_SCALE_FACTOR_MASK,
+ regs + EXYNOS3250_DEC_SCALING_RATIO);
+}
--
Regards,
Sylwester
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Re: [PATCH 9/9] ARM: dts: exynos3250: add JPEG codec device node
On 07/07/14 18:32, Jacek Anaszewski wrote:
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..351871a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -206,6 +206,18 @@
interrupts = 0 240 0;
};
+ jpeg-codec@1183 {
+ compatible = samsung,exynos3250-jpeg;
+ reg = 0x1183 0x1000;
+ interrupts = 0 171 0;
+ clocks = cmu CLK_JPEG, cmu CLK_SCLK_JPEG;
+ clock-names = jpeg, sclk-jpeg;
+ samsung,power-domain = pd_cam;
+ assigned-clock-parents = cmu CLK_MOUT_CAM_BLK cmu
CLK_DIV_MPLL_PRE,
+ cmu CLK_SCLK_JPEG cmu;
+ assigned-clock-rates = cmu CLK_SCLK_JPEG 15000;
There is no support for the assigned-clock-parents/assigned-clock-rates
in mainline yet unfortunately. I would suggest removing these two properties
for now. And please send this patch to relevant maintainer, i.e. Kukjin Kim.
+ };
Thanks,
Sylwester
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[PATCH v3] ARM: dts: exynos3250 add MFC codec device node
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Kukjin Kim kgene@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 351871a..01bf5fa 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -283,6 +283,17 @@
status = disabled;
};
+ codec@1340 {
+ compatible = samsung,mfc-v7;
+ reg = 0x1340 0x1;
+ interrupts = 0 102 0;
+ clock-names = mfc, sclk-mfc;
+ clocks = cmu CLK_MFC, cmu CLK_SCLK_MFC;
+ #address-cells = 1;
+ #size-cells = 0;
+ samsung,power-domain = pd_mfc;
+ };
+
serial_0: serial@1380 {
compatible = samsung,exynos4210-uart;
reg = 0x1380 0x100;
--
1.7.9.5
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Re: [PATCH] mmc: dw_mmc: change to use recommended reset procedure
On Fri, Jul 11, 2014 at 3:20 AM, Seungwon Jeon tgih@samsung.com wrote:
On Fri, July 11, 2014, Sonny Rao wrote:
On Thu, Jul 10, 2014 at 5:28 AM, Seungwon Jeon tgih@samsung.com wrote:
Hi Sonny,
I have missed this patch.
You finally choose to take extra interrupt handling.
If it is not harm, it's fine.
Hi, thanks for coming back to it. Based on my tracing, the interrupt
seems to be okay and is just ignored.
-static inline bool dw_mci_fifo_reset(struct dw_mci *host)
+static inline bool dw_mci_reset(struct dw_mci *host)
inline is no needed anymore.
{
+ u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
+ bool ret = false;
+
/*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
@@ -2334,15 +2330,59 @@ static inline bool dw_mci_fifo_reset(struct
dw_mci *host)
host-sg = NULL;
}
- return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
-}
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
-{
- return dw_mci_ctrl_reset(host,
- SDMMC_CTRL_FIFO_RESET |
- SDMMC_CTRL_RESET |
- SDMMC_CTRL_DMA_RESET);
+ if (dw_mci_ctrl_reset(host, flags)) {
+ /*
+ * In all cases we clear the RAWINTS register to clear any
+ * interrupts.
+ */
+ mci_writel(host, RINTSTS, 0x);
+
+ /* if using dma we wait for dma_req to clear */
+ if (host-use_dma) {
+ unsigned long timeout = jiffies +
msecs_to_jiffies(500);
+ u32 status;
+ do {
+ status = mci_readl(host, STATUS);
+ if (!(status SDMMC_STATUS_DMA_REQ))
+ break;
+ cpu_relax();
+ } while (time_before(jiffies, timeout));
+
+ if (status SDMMC_STATUS_DMA_REQ) {
+ dev_err(host-dev,
+ %s: Timeout waiting for dma_req to
+ clear during reset, __func__);
+ goto ciu_out;
+ }
+
+ /* when using DMA next we reset the fifo again */
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
+ goto ciu_out;
+ }
+ } else {
+ /* if the controller reset bit did clear, then set clock
regs */
+ if (!(mci_readl(host, CTRL) SDMMC_CTRL_RESET)) {
+ dev_err(host-dev, %s: fifo/dma reset bits didn't
+ clear but ciu was reset, doing clock
update.,
+ __func__);
+ goto ciu_out;
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_MMC_DW_IDMAC))
+ /* It is also recommended that we reset and reprogram idmac
*/
+ dw_mci_idmac_reset(host);
+
+ ret = true;
+
+ciu_out:
+ /* After a CTRL reset we need to have CIU set clock registers */
+ mci_send_cmd(host-cur_slot, SDMMC_CMD_UPD_CLK, 0);
+
+ return ret;
}
#ifdef CONFIG_OF
@@ -2555,7 +2595,7 @@ int dw_mci_probe(struct dw_mci *host)
}
/* Reset all blocks */
- if (!dw_mci_ctrl_all_reset(host))
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
return -ENODEV;
host-dma_ops = host-pdata-dma_ops;
@@ -2744,7 +2784,7 @@ int dw_mci_resume(struct dw_mci *host)
}
}
- if (!dw_mci_ctrl_all_reset(host)) {
+ if (!dw_mci_reset(host)) {
Do you have any reason to use dw_mci_reset() unlike doing on probing?
I really wanted to use dw_mci_reset() everwhere, including probe,
because that would be simplest, where there is just one reset function
always, but the host structure is not completely set up at probe time,
so the code in dw_mci_reset() where we try to send a command to update
clock fails, so that's why I had to just do a reset.
Yes, if we can keep one interface, it would be good.
But can you check below?
Did you see the kernel panic on probing with host-cur_slot is NULL?
Yes, I think that was the one.
If right, resume seems not different from probe in case of removable type.
And dw_mci_idmac_reset() is redundant when dw_mci_reset() is used at resume.
I think dw_mci_ctrl_reset() can be also used at resume like at probe for
simple way.
For safety's sake, host-cur_slot should be guaranteed it's not NULL.
Ok, I didn't try on removable, but I can change it to match probe,
thanks for looking at this.
Thanks,
[PATCHv5] mmc: dw_mmc: change to use recommended reset procedure
This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys Mobile storage host databook.
Signed-off-by: Sonny Rao sonny...@chromium.org
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
v2: Add Generic DMA support
per the documentation, move interrupt clear before wait
make the test for DMA host-use_dma rather than host-using_dma
add proper return values (although it appears no caller checks)
v3: rename fifo reset function, and change callers
use this combined reset function in dw_mci_resume()
just one caller left (probe), so get rid of dw_mci_ctrl_all_reset()
use DMA reset bit for all systems which use DMA
remove extra IDMAC reset in dw_mci_work_routine_card()
do CIU clock update in error path, if CIU reset cleared
v4: remove comment about FIFO reset in dw_mci_work_routine_card()
move down error message when control reset clears but others don't
and clarify the error stating that we will still update clocks
make flags for all reset bits a macro
v5: don't use dw_mci_reset() in dw_mci_resume() and instead match what
is done in dw_mci_probe() and don't force inline dw_mci_resume()
---
drivers/mmc/host/dw_mmc.c | 86 ++-
drivers/mmc/host/dw_mmc.h | 5 +++
2 files changed, 68 insertions(+), 23 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 55cd110..db25494 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = {
0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
};
-static inline bool dw_mci_fifo_reset(struct dw_mci *host);
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
+static bool dw_mci_reset(struct dw_mci *host);
#if defined(CONFIG_DEBUG_FS)
static int dw_mci_req_show(struct seq_file *s, void *v)
@@ -1254,7 +1253,7 @@ static int dw_mci_data_complete(struct dw_mci *host,
struct mmc_data *data)
* After an error, there may be data lingering
* in the FIFO
*/
- dw_mci_fifo_reset(host);
+ dw_mci_reset(host);
} else {
data-bytes_xfered = data-blocks * data-blksz;
data-error = 0;
@@ -1371,7 +1370,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* CMD error in data command */
if (mrq-cmd-error mrq-data)
- dw_mci_fifo_reset(host);
+ dw_mci_reset(host);
host-cmd = NULL;
host-data = NULL;
@@ -1982,14 +1981,8 @@ static void dw_mci_work_routine_card(struct work_struct
*work)
}
/* Power down slot */
- if (present == 0) {
- /* Clear down the FIFO */
- dw_mci_fifo_reset(host);
-#ifdef CONFIG_MMC_DW_IDMAC
- dw_mci_idmac_reset(host);
-#endif
-
- }
+ if (present == 0)
+ dw_mci_reset(host);
spin_unlock_bh(host-lock);
@@ -2323,8 +2316,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32
reset)
return false;
}
-static inline bool dw_mci_fifo_reset(struct dw_mci *host)
+static bool dw_mci_reset(struct dw_mci *host)
{
+ u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
+ bool ret = false;
+
/*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
@@ -2334,15 +2330,59 @@ static inline bool dw_mci_fifo_reset(struct dw_mci
*host)
host-sg = NULL;
}
- return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
-}
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
-{
- return dw_mci_ctrl_reset(host,
-SDMMC_CTRL_FIFO_RESET |
-SDMMC_CTRL_RESET |
-SDMMC_CTRL_DMA_RESET);
+ if (dw_mci_ctrl_reset(host, flags)) {
+ /*
+* In all cases we clear the RAWINTS register to clear any
+* interrupts.
+*/
+ mci_writel(host, RINTSTS, 0x);
+
+ /* if using dma we wait for dma_req to clear */
+ if (host-use_dma) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(500);
+ u32 status;
+ do {
+ status = mci_readl(host, STATUS);
+ if (!(status SDMMC_STATUS_DMA_REQ))
+ break;
+ cpu_relax();
+
