Re: [RFC 1/2] clk: Allow overriding generic ops for clocks
On pon, 2014-11-24 at 17:34 -0800, Mike Turquette wrote:
Quoting Krzysztof Kozlowski (2014-11-24 07:18:31)
For clocks depending on some other clock domain one may want to perform
specific ops before actual enable/disable of gate clock. Allow such case
by accepting supplied ops in new exported function:
clk_register_gate_ops().
If you are not going to use the gate_ops, why use the gate clock at all?
You can create a platform-specific clock type which uses the ops you
specify.
Actually I want to use gate_ops (and as much as possible from current
code) but I need to encapsulate gate_ops calls in other enable/disable
of other clock. In 2nd patch:
+static int audss_clk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ if (!IS_ERR(pll_in))
+ clk_prepare_enable(pll_in);
+ ret = clk_gate_ops.enable(hw);
+ if (!IS_ERR(pll_in))
+ clk_disable_unprepare(pll_in);
+
+ return ret;
+}
Other idea is to add some kind of dependency between clocks... but
wait... there is already parent-child dependency. However these audss
clocks need two parents :)
Best regards,
Krzysztof
Regards,
Mike
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
drivers/clk/clk-gate.c | 16 +---
include/linux/clk-provider.h | 5 +
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 51fd87fb7ba6..51802af2d9e7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -117,11 +117,12 @@ EXPORT_SYMBOL_GPL(clk_gate_ops);
* @bit_idx: which bit in the register controls gating of this clock
* @clk_gate_flags: gate-specific flags for this clock
* @lock: shared register lock for this clock
+ * @ops: clk_ops to use for this clock
*/
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate_ops(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
- u8 clk_gate_flags, spinlock_t *lock)
+ u8 clk_gate_flags, spinlock_t *lock, const struct clk_ops
*ops)
{
struct clk_gate *gate;
struct clk *clk;
@@ -142,7 +143,7 @@ struct clk *clk_register_gate(struct device *dev, const
char *name,
}
init.name = name;
- init.ops = clk_gate_ops;
+ init.ops = ops;
init.flags = flags | CLK_IS_BASIC;
init.parent_names = (parent_name ? parent_name: NULL);
init.num_parents = (parent_name ? 1 : 0);
@@ -161,4 +162,13 @@ struct clk *clk_register_gate(struct device *dev,
const char *name,
return clk;
}
+EXPORT_SYMBOL_GPL(clk_register_gate_ops);
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ return clk_register_gate_ops(dev, name, parent_name, flags, reg,
bit_idx, clk_gate_flags, lock, clk_gate_ops);
+}
EXPORT_SYMBOL_GPL(clk_register_gate);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index be21af149f11..6cfc77a9f339 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -290,11 +290,16 @@ struct clk_gate {
#define CLK_GATE_HIWORD_MASK BIT(1)
extern const struct clk_ops clk_gate_ops;
+struct clk *clk_register_gate_ops(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock, const struct clk_ops
*ops);
struct clk *clk_register_gate(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
+
struct clk_div_table {
unsigned intval;
unsigned intdiv;
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Re: [PATCH v4 0/5] exynos: Move pmu driver to driver/soc folder and add exynos7 support
On Mon, Nov 24, 2014 at 6:50 PM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Monday, November 24, 2014 07:36:10 AM Amit Daniel Kachhap wrote:
This patch series [1 - 5] performs,
1) Moves pmu driver to driver/soc/samsung folder. This is needed as exynos7
is
an arm64 based platform and hence PMU driver should be in driver folder.
Some discussion happened about this in the v1 version. Finally adding it
in
driver/soc folder as it too SoC specific and not a general driver.
Entire discussion can be found here (A).
2) Add exynos7 PMU support.
Some months ago (when the work on moving PMU driver out of mach-exynos
started) I asked how much code would be shared between arm32 and arm64
SoCs. Now it seems that the code in question is minimal so I still
wonder whether it is really worth to have a common driver (please note
that in case of arm32 kernel all arm64 PMU code is just a dead code,
similarly for arm64 kernel and arm32 PMU code). Would it be possible
to do the analysis of the additional source code needed vs saved code
in the resulting binary for the case of having separate drivers?
yes your suggestion is good. It may done by keeping the data pmu_config[]
arrays in .h file under CONFIG_ARM(or CONFIG_ARM64) and NULL for non required
platforms. Keep them in 2 separate files may be confusing.
Could you also please take a look into fixing patch #4 to be compatible
with http://lkml.iu.edu/hypermail/linux/kernel/1407.1/00298.html ?
This patch makes sense. Thanks for pointing out.
(It seems that just adding separate struct exynos_pmu_conf_extra for
-pmu_config_extra shold be okay.)
Yes right struct exynos_pmu_conf_extra should work for exynos7.
I think both of the above optimizations may go as a separate patch.
Regards,
Amit D
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
3) Enables the driver for 32bit arm exynos platforms.
Changes from V3:
* Fixed Kconfig as per Russell feedback
* Rebased the series against Pankaj SoC restart consolidation patches (D) as
per
Kukjin request.
* Link to V3 can be found here (C)
Changes from V2:
* Added review comment changes suggested by Pankaj.
* Removed mfd client support in this patch series. This will be added later
in
the power domain patch series.
* Link to V2 can be found here (B)
Changes from V1:
* Move pmu driver in driver/soc/samsung folder
* Removed the power domain features. They will posted as a separate series.
* Added exynos7 PMU support.
* Link to v1 can be found here (A)
This complete patch series is rebased on Kukjin for-next tree.
(A) - http://www.spinics.net/lists/linux-samsung-soc/msg38442.html
(B) - http://www.spinics.net/lists/arm-kernel/msg375910.html
(C) - http://www.spinics.net/lists/linux-samsung-soc/msg39237.html
(D) - http://www.spinics.net/lists/linux-samsung-soc/msg39095.html
Amit Daniel Kachhap (5):
ARM: EXYNOS: Move pmu specific header files under linux/soc/samsung
drivers: soc: Add support for Exynos PMU driver
driver: soc: exynos-pmu: Add an API to be called after wakeup
drivers: soc: exynos-pmu: Add support for Exynos7
arm: exynos: Select SOC_SAMSUNG config option
.../devicetree/bindings/arm/samsung/pmu.txt|1 +
arch/arm/mach-exynos/Kconfig |1 +
arch/arm/mach-exynos/Makefile |2 +-
arch/arm/mach-exynos/exynos.c |2 +-
arch/arm/mach-exynos/mcpm-exynos.c |2 +-
arch/arm/mach-exynos/platsmp.c |2 +-
arch/arm/mach-exynos/pm.c |4 +-
arch/arm/mach-exynos/suspend.c |4 +-
drivers/soc/Kconfig|1 +
drivers/soc/Makefile |1 +
drivers/soc/samsung/Kconfig| 20 +
drivers/soc/samsung/Makefile |1 +
.../pmu.c = drivers/soc/samsung/exynos-pmu.c | 442
+++-
.../linux/soc/samsung}/exynos-pmu.h|1 +
.../linux/soc/samsung/exynos-regs-pmu.h| 273
15 files changed, 744 insertions(+), 13 deletions(-)
create mode 100644 drivers/soc/samsung/Kconfig
create mode 100644 drivers/soc/samsung/Makefile
rename arch/arm/mach-exynos/pmu.c = drivers/soc/samsung/exynos-pmu.c (64%)
rename {arch/arm/mach-exynos = include/linux/soc/samsung}/exynos-pmu.h
(89%)
rename arch/arm/mach-exynos/regs-pmu.h =
include/linux/soc/samsung/exynos-regs-pmu.h (63%)
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Re: [PATCH RFC v2 06/12] driver: soc: exynos-pmu: Add exynos7 power domain on/off ops
On Tue, Nov 25, 2014 at 1:00 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 24 November 2014 at 14:04, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This patch uses the restructuring done in PD handlers and adds PD
on/off/status handlers for exynos7. In this SoC, some extra settings
need to be done prior to turning on/off power domains. Some of those
settings are also different from different power domains so is uses
the power domain compatible name feature to distinguish between power
domains.
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
drivers/soc/samsung/exynos-pmu.c| 105
+++
include/linux/soc/samsung/exynos-regs-pmu.h | 17 +
2 files changed, 122 insertions(+)
diff --git a/drivers/soc/samsung/exynos-pmu.c
b/drivers/soc/samsung/exynos-pmu.c
index e690f65..b9631d5 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -1202,6 +1202,104 @@ static void exynos7_pmu_init(void)
}
}
+static int exynos7_pd_extraconf_base(const char *pd_name)
+{
+ if (!pd_name)
+ return -EINVAL;
+
+ if (!strcmp(samsung,exynos7-pd-mfc, pd_name))
+ return EXYNOS7_CLKRUN_CMU_MFC_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-hevc, pd_name))
+ return EXYNOS7_CLKRUN_CMU_HEVC_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-mscl, pd_name))
+ return EXYNOS7_CLKRUN_CMU_MSCL_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-g2d, pd_name))
+ return EXYNOS7_CLKRUN_CMU_G2D_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-fsys0, pd_name))
+ return EXYNOS7_CLKRUN_CMU_FSYS0_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-fsys1, pd_name))
+ return EXYNOS7_CLKRUN_CMU_FSYS1_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-aud, pd_name))
+ return EXYNOS7_CLKRUN_CMU_AUD_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-disp, pd_name))
+ return EXYNOS7_CLKRUN_CMU_DISP_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-vpp, pd_name))
+ return EXYNOS7_CLKRUN_CMU_VPP_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-vpp, pd_name))
+ return EXYNOS7_CLKRUN_CMU_VPP_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-isp0, pd_name))
+ return EXYNOS7_CLKRUN_CMU_ISP0_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-isp1, pd_name))
+ return EXYNOS7_CLKRUN_CMU_ISP1_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-cam0, pd_name))
+ return EXYNOS7_CLKRUN_CMU_CAM0_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-cam1, pd_name))
+ return EXYNOS7_CLKRUN_CMU_CAM1_SYS_PWR_REG;
+ else if (!strcmp(samsung,exynos7-pd-g3d, pd_name))
+ return EXYNOS7_CLKRUN_CMU_CAM1_SYS_PWR_REG;
I think we should move away from using strings to find a matching PM
domain. Instead we should use a enum/define pointing to the PM domain
in an array of PM domains, or similar.
Thanks for looking into the series.
Here pd names are compatible string from the pd DT nodes. I think
compatible names are
used in many places like searching for platform data in DT based probe etc.
yes enum can also be used to locate the PM domain. Will check.
The UX500 SOC initial support for PM domains is queued for 3.19 and is
currently available in linux-next. You may want to get some
inspiration from that approach.
ok will check them.
+
+ pr_err(%s: Unsupported power domain\n, pd_name);
+ return 0;
+}
+
+static int exynos7_pd_powerdown(const char *pd_name, void __iomem *pd_addr)
+{
Considering the suggestion above and to move away from using strings
like this; this function could take a pointer to the PM domain instead
of a string and the __iomem, right!?
Actually in our case there are 2 files, pm-domain.c and exynos-pmu.c.
I thought of abstracting out generic PD related stuffs from
exynos-pmu.c file so this function
takes these type of arguments.
+ int off_base = exynos7_pd_extraconf_base(pd_name);
+
+ if (!off_base)
+ return -EINVAL;
+
+ /* Initialise the pd extraconf registers */
+ pmu_raw_writel(0, off_base + EXYNOS7_CLKRUN_CMU_PD_SYS_PWR_REG);
+ pmu_raw_writel(0, off_base + EXYNOS7_CLKSTOP_CMU_PD_SYS_PWR_REG);
+ pmu_raw_writel(0, off_base + EXYNOS7_DISABLE_PLL_CMU_PD_SYS_PWR_REG);
+ pmu_raw_writel(0, off_base + EXYNOS7_RESET_LOGIC_PD_SYS_PWR_REG);
+ pmu_raw_writel(0, off_base + EXYNOS7_MEMORY_PD_SYS_PWR_REG);
+ pmu_raw_writel(0, off_base + EXYNOS7_RESET_CMU_PD_SYS_PWR_REG);
+
+ if (!strcmp(samsung,exynos7-pd-fsys0, pd_name) ||
+ !strcmp(samsung,exynos7-pd-fsys1, pd_name))
+ pmu_raw_writel(1,
+ off_base +
Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
On pon, 2014-11-24 at 19:20 -0800, Kevin Hilman wrote:
On Mon, Nov 24, 2014 at 5:50 PM, Kukjin Kim kg...@kernel.org wrote:
Olof Johansson wrote:
On Mon, Nov 24, 2014 at 5:37 PM, Olof Johansson o...@lixom.net wrote:
On Mon, Nov 24, 2014 at 5:35 PM, Kevin Hilman khil...@kernel.org wrote:
On Mon, Nov 24, 2014 at 4:25 PM, Olof Johansson o...@lixom.net wrote:
On Mon, Nov 24, 2014 at 11:51 AM, Kevin Hilman khil...@kernel.org
wrote:
Is anyone at Samsung actually looking into these MCPM issues?
Hi Kevin,
What hardware are you having problems with? 5420 or 5422/5800?
Yes. :)
exynos5420-arndale-octa:
http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5420-
arndale-octa.html
exynos5422-odroid-xu3:
http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5422-
odroid-xu3.html
My boot tests seem to pass fine because I have such a minimal
userspace, but Tyler Baker reported that with a real userspace, he
can't boot to a shell:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/286203.html
Hmm...his report was in Sep...I think it should be fine with current -next?
No, it is still broken in linux-next (as I stated above.)
Moreover, earlier in this thread you mentioned you were merging some
MCPM patches that should address this, but did not respond when I
asked which patches you thing should address this issue
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
Interesting thing can be found in exynos5420.dtsi:
mdma1: mdma@11C1 {
...
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = disabled;
};
I am booting Arndale Octa on some other config and exynos. However with
or without MCPM the imprecise aborts are still present (but not fatal,
shell comes up).
My board boots also under secure firmware (I am using Linaro's ubuntu
image). Maybe that is the cause?
Best regards,
Krzysztof
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Re: [PATCH RFC v2 07/12] PM / Domains: export pm_genpd_lookup_name
On Tue, Nov 25, 2014 at 1:05 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 24 November 2014 at 14:04, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This API may be needed to set the power domain parent/child relationship
in the power domain platform driver. The parent relationship is
generally set after the child power domain is registered with the power
domain subsystem. In this case, pm_genpd_lookup_name API might be
useful.
I think this is a step in the wrong direction. Instead we should be
working on removing the name based APIs from genpd.
The proper way should be to pass the PM domain as a parameter to the
APIs instead.
Yes i understand but i had a special requirement for using this API
during pd probe.
I cannot use hierarchy to represent parent/child pd nodes as it will
break the existing SoC's. In my case all the PD nodes are linear. The
parent/child relationship are established in the second pass after all
the PD entries are registered with the help of this API.
Although there a way that i can always keep parent PD's before the
child PD's in DT in linear order. Will check this approach.
Regards,
Amit
Kind regards
Uffe
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
drivers/base/power/domain.c |3 ++-
include/linux/pm_domain.h |7 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index fb83d4a..b0e1c2f 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -49,7 +49,7 @@
static LIST_HEAD(gpd_list);
static DEFINE_MUTEX(gpd_list_lock);
-static struct generic_pm_domain *pm_genpd_lookup_name(const char
*domain_name)
+struct generic_pm_domain *pm_genpd_lookup_name(const char *domain_name)
{
struct generic_pm_domain *genpd = NULL, *gpd;
@@ -66,6 +66,7 @@ static struct generic_pm_domain
*pm_genpd_lookup_name(const char *domain_name)
mutex_unlock(gpd_list_lock);
return genpd;
}
+EXPORT_SYMBOL_GPL(pm_genpd_lookup_name);
struct generic_pm_domain *dev_to_genpd(struct device *dev)
{
diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
index 2e0e06d..aedcec3 100644
--- a/include/linux/pm_domain.h
+++ b/include/linux/pm_domain.h
@@ -150,6 +150,8 @@ extern int pm_genpd_name_poweron(const char
*domain_name);
extern struct dev_power_governor simple_qos_governor;
extern struct dev_power_governor pm_domain_always_on_gov;
+
+extern struct generic_pm_domain *pm_genpd_lookup_name(const char
*domain_name);
#else
static inline struct generic_pm_domain_data *dev_gpd_data(struct device
*dev)
@@ -221,6 +223,11 @@ static inline int pm_genpd_name_poweron(const char
*domain_name)
{
return -ENOSYS;
}
+static inline
+struct generic_pm_domain *pm_genpd_lookup_name(const char *domain_name)
+{
+ return NULL;
+}
#define simple_qos_governor NULL
#define pm_domain_always_on_gov NULL
#endif
--
1.7.9.5
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Re: [PATCH RFC v2 08/12] soc: samsung: pm_domain: Add support for parent power domain
On Tue, Nov 25, 2014 at 1:29 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 24 November 2014 at 14:04, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
This patch adds supports for parent power domain. This will ensure
invoking of parent/child power domain on/off in a correct sequence.
In exynos7 SOC's, power domain controllers have parent and child
hierarchy.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
.../bindings/arm/exynos/power_domain.txt |2 +
drivers/soc/samsung/pm_domains.c | 43
+++-
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 00ebda1..0160bdc 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -24,6 +24,7 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently.
+- parents: phandle of parent power domains.
Node of a device using power domains must have a samsung,power-domain
property
defined with a phandle to respective power domain.
@@ -48,6 +49,7 @@ Example:
mfc_pd: power-domain@10044060 {
compatible = samsung,exynos4210-pd,
samsung,exynos7-pd-mfc;
reg = 0x10044060 0x20;
+ parents = pd_top;
#power-domain-cells = 0;
};
This seems like a good and generic approach to describe that a PM
domain could have a parent. I would suggest to rename it, such it
reflects its a PM domain binding though.
I am not sure if this is generic. I guess PD's represented like below
are more generic.
PD1 {
PD2 {
PD3 {
};
};
};
So, maybe we can add this as a common DT binding for the generic PM
domain instead of having it as Exynos specific?
Yes sure.
Regards,
Amit D
Kind regards
Uffe
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Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
On wto, 2014-11-25 at 09:47 +0100, Krzysztof Kozlowski wrote:
On pon, 2014-11-24 at 19:20 -0800, Kevin Hilman wrote:
On Mon, Nov 24, 2014 at 5:50 PM, Kukjin Kim kg...@kernel.org wrote:
Olof Johansson wrote:
On Mon, Nov 24, 2014 at 5:37 PM, Olof Johansson o...@lixom.net wrote:
On Mon, Nov 24, 2014 at 5:35 PM, Kevin Hilman khil...@kernel.org
wrote:
On Mon, Nov 24, 2014 at 4:25 PM, Olof Johansson o...@lixom.net
wrote:
On Mon, Nov 24, 2014 at 11:51 AM, Kevin Hilman khil...@kernel.org
wrote:
Is anyone at Samsung actually looking into these MCPM issues?
Hi Kevin,
What hardware are you having problems with? 5420 or 5422/5800?
Yes. :)
exynos5420-arndale-octa:
http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5420-
arndale-octa.html
exynos5422-odroid-xu3:
http://storage.armcloud.us/kernel-ci/mainline/v3.18-rc6/arm-exynos_defconfig/boot-exynos5422-
odroid-xu3.html
My boot tests seem to pass fine because I have such a minimal
userspace, but Tyler Baker reported that with a real userspace, he
can't boot to a shell:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/286203.html
Hmm...his report was in Sep...I think it should be fine with current
-next?
No, it is still broken in linux-next (as I stated above.)
Moreover, earlier in this thread you mentioned you were merging some
MCPM patches that should address this, but did not respond when I
asked which patches you thing should address this issue
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a
test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
Interesting thing can be found in exynos5420.dtsi:
mdma1: mdma@11C1 {
...
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = disabled;
};
I am booting Arndale Octa on some other config and exynos. However with
or without MCPM the imprecise aborts are still present (but not fatal,
shell comes up).
My board boots also under secure firmware (I am using Linaro's ubuntu
image). Maybe that is the cause?
One update: some fatal imprecise aborts (hanging boot) happen also on
exynos_defconfig without MCPM. It looks random... one boot fails, next
succeeds (however also with imprecise external abort message but shell
comes up).
Best regards,
Krzysztof
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Re: [PATCH RFC v2 08/12] soc: samsung: pm_domain: Add support for parent power domain
On Tue, Nov 25, 2014 at 9:57 AM, amit daniel kachhap
amit.dan...@samsung.com wrote:
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 00ebda1..0160bdc 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -24,6 +24,7 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to
3)
are supported currently.
+- parents: phandle of parent power domains.
Why not using just power-domains = pd_top?
This is consistent with how clocks refer to their parent clocks.
Node of a device using power domains must have a samsung,power-domain
property
defined with a phandle to respective power domain.
@@ -48,6 +49,7 @@ Example:
mfc_pd: power-domain@10044060 {
compatible = samsung,exynos4210-pd,
samsung,exynos7-pd-mfc;
reg = 0x10044060 0x20;
+ parents = pd_top;
#power-domain-cells = 0;
};
This seems like a good and generic approach to describe that a PM
domain could have a parent. I would suggest to rename it, such it
reflects its a PM domain binding though.
I am not sure if this is generic. I guess PD's represented like below
are more generic.
PD1 {
PD2 {
PD3 {
};
};
};
Such a representation is not always possible.
If you have one power-controller for a hierarchy of PM domains, you can
use it.
If you have multiple power-controllers, the power controller nodes are at the
same level in DT, so you'll have to use power-domains properties to link
them together.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
-- Linus Torvalds
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Re: [RFC 0/2] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
On pon, 2014-11-24 at 18:28 +0100, Javier Martinez Canillas wrote:
Hello Krzysztof,
On 11/24/2014 04:18 PM, Krzysztof Kozlowski wrote:
Hi,
This is initial idea to solve dependency between AudioSS clocks
and main clock controller on Exynos platform.
This solves boot failure of Peach Pi/Pit and Arndale Octa [1].
I tested this series on an Exynos5420 Peach Pit but I still
have the boot hang so it doesn't solve the issue on this board.
I'm using linux-next + your patches with exynos_defconfig and
without the clk_ignore_unused command line parameter.
Hmmm, that's strange. I've looked again at your dmesg and it is little
different than mine (when system fails).
1. Does your PMIC come up? In your dmesg:
[2.687297] max77802-pmic max77802-pmic: regulator init failed for 0
[2.693539] platform max77802-pmic: Driver max77802-pmic requests probe
deferral
2. In my case booting fails just after disabling unused clocks which is
quite early, my dmesg:
[ 11.700074] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[ 11.704282] s3c-rtc 101e.rtc: setting system clock to 2029-01-11
19:19:17 UTC (1862853557)
[ 11.770602] mmcblk0: mmc0:0001 M8G1WA 7.28 GiB
[ 11.776201] mmcblk0boot0: mmc0:0001 M8G1WA partition 1 2.00 MiB
[ 11.780968] mmcblk0boot1: mmc0:0001 M8G1WA partition 2 2.00 MiB
[ 11.786823] mmcblk0rpmb: mmc0:0001 M8G1WA partition 3 128 KiB
[ 11.793815] mmcblk0: p1 p2 p3 p4
[ 11.824165] PVDD_G3D_1V0: disabling
[ 11.830833] PVDD_G3DS_1V0: disabling
[ 11.837771] PVDD_HSIC_1V8: disabling
[ 11.841172] PVDD_ABB_1V8: disabling
[ 11.844866] PVDD_ANAIP_1V8: disabling
[ 11.847157] usb 5-1.4: new high-speed USB device number 3 using exynos-ehci
[ 11.848778] PVDD
In your case you have a gap here:
[3.624142] platform 12d1.adc: Driver exynos-adc requests probe deferral
[ 24.188722] random: nonblocking pool is initialized
Could you try my patches once again but this time with enabled:
DEBUG_EXYNOS_UART
EARLY_PRINTK
DEBUG_S3C_UART3
DEBUG_LL
and with following change:
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 4896ae9e23da..316856e55784 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -478,7 +478,9 @@ static void clk_disable_unused_subtree(struct clk *clk)
* sequence. call .disable_unused if available, otherwise fall
* back to .disable
*/
+ pr_err(clk: checking %s\n, clk-name);
if (__clk_is_enabled(clk)) {
+ pr_err(clk: enabled %s, disabling\n, clk-name);
if (clk-ops-disable_unused)
clk-ops-disable_unused(clk-hw);
else if (clk-ops-disable)
Without my patch the boot hangs:
[ 12.230666] clk: checking dout_unipro
[ 12.234304] clk: checking mout_unipro
[ 12.237913] clk: checking sclk_usbd300
[ 12.241638] clk: enabled sclk_usbd300, disabling
[ 12.246264] clk: checking dout_usbd300
[ 12.249992] clk: checking sclk_usbd301
[ 12.253683] clk: enabled sclk_usbd301, disabling
[ 12.258309] clk: checking dout_usbd301
[ 12.262007] clk: checking sclk_maudio0
[ 12.265728] clk: enabled sclk_maudio0, disabling
[ 12.270355] clk: checking pcm_bus
because audss seems to be gated so kernel cannot access status of
pcm_bus clock.
Best regards,
Krzysztof
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Re: [PATCH v11 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
On 24 November 2014 at 19:14, Sudeep Holla sudeep.ho...@arm.com wrote: On 20/11/14 03:48, Viresh Kumar wrote: - I believe CPUs boot in the order they are present in DT except for the boot CPU. So, the first node for every cluster should have it. Correct ? Then we can update the fixme. No, I disagree as you trying to implicitly depend on the logic Linux uses to assign logical index. It can be changed any time, and depending on it might break things in future which can't be fixed easily later especially if it's DT related. Yeah, correct. Hmm, I never thought about it. But yes the CPU with the OPPs should be the first one to come back. How can you assume that ? I can write a simple test which hot-plugs out all the CPUs in the (esp. multi-cluster) system in ascending order of logical index and hot-plug back in descending order. Then the above logic fails. What I said is: Yes the CPU with the OPPs should be the first one to come back, if this has to work correctly. Otherwise it will break.. And you repeated the same :) The platforms needing it have to get involved in such discussions to make any progress. Yes there were people involved. I hope I cc'd you as well... -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 2/2] clk: samsung: Fix clock disable failure because domain being gated
Hi Krzysztof,
Please see my comments inline.
2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
+static int audss_clk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ if (!IS_ERR(pll_in))
+ clk_prepare_enable(pll_in);
Calling clk_prepare_enable() from enable() callback doesn't look like
a good idea, because enabling is not supposed to sleep, while
preparing might do so.
I guess you have to pre-prepare this clock in probe and then only call
enable here.
+ ret = clk_gate_ops.enable(hw);
+ if (!IS_ERR(pll_in))
+ clk_disable_unprepare(pll_in);
+
+ return ret;
+}
[snip]
+/* TODO: Also mux and div */
+const struct clk_ops audss_clk_gate_ops = {
nit: static const probably?
+ .enable = audss_clk_gate_enable,
+ .disable = audss_clk_gate_disable,
+ .is_enabled = audss_clk_gate_is_enabled,
+};
As for the approach itself, maybe you should simply register fully
custom clocks with clk_register(), without altering
clk_register_gate() at all and simply calling gate ops whenever
necessary? I don't know, just a loose idea.
By the way, this issue could be probably solved by integrating generic
clocks with regmap API, since regmap-mmio can automatically control a
clock.
Best regards,
Tomasz
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Re: [PATCH 00/11] Exynos7: Adding USB 3.0 support
Hi Sylwester, On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim kg...@kernel.org wrote: On 11/22/14 17:40, Kishon Vijay Abraham I wrote: On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote: On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote: The series has dependency on a) [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/linux-samsung-soc/msg38734.html b) [GIT PULL] Samsung clock changes for 3.19 - specifically the clock dt bindings header. http://comments.gmane.org/gmane.linux.kernel.samsung-soc/39142 c) tty: serial: samsung: Clean-up selection of number of available UARTs http://www.spinics.net/lists/linux-samsung-soc/msg37418.html d) dts, kbuild: Implement support for dtb vendor subdirs(merged in linux-next) https://lkml.org/lkml/2014/10/21/654 e) Samsung pinctrl patches for v3.19 http://www.spinics.net/lists/linux-samsung-soc/msg38744.html Tested on Exynos7-espresso board with 3.18-rc5 and above dependencies. Clubbing the pinctrl, clk, and usb driver changes alongwith the dt changes together in this series only so as to avoid having 'n' number of dependencies. The USB driver patches in this series were part of [1] sent earlier. [1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7 https://lkml.org/lkml/2014/10/7/191 I took dwc3 driver patches. I took the phy patches. I'll take DT changes once exynos7 is landing into samsung tree :) You too may want to pick the sole clock driver patch in this series for 3.19 ? :-) clk: exynos7: Add required clock tree for USB Please let me know if the merge window is still open on your side so that you can pick this patch. -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] drm/exynos: Add DECON driver
ping. On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be samsung,exynos7-decon; If exynos5433 was just renamed to exynos7 then, it should be one of the following: (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Or, (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos5433-decon for Display and enhancement controller IP for Exynos5433 (c) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Eventually, we will end up here. + +- reg: physical base address and length of the DECON registers set. + +- interrupt-parent: should be the phandle of the decon controller's + parent interrupt controller. + +- interrupts: should contain a list of all DECON IP block interrupts in the + order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier + format depends on the interrupt controller used. + +- interrupt-names: should contain the interrupt names: fifo, vsync, + lcd_sys, in the same order as they were listed in the interrupts +property. + +- pinctrl-0: pin control group to be used for this controller. + +- pinctrl-names: must contain a default entry. + +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. + +- clock-names: list of clock names sorted in the
Re: [RFC 2/2] clk: samsung: Fix clock disable failure because domain being gated
On wto, 2014-11-25 at 20:35 +0900, Tomasz Figa wrote:
Hi Krzysztof,
Please see my comments inline.
2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski k.kozlow...@samsung.com:
+static int audss_clk_gate_enable(struct clk_hw *hw)
+{
+ int ret;
+
+ if (!IS_ERR(pll_in))
+ clk_prepare_enable(pll_in);
Calling clk_prepare_enable() from enable() callback doesn't look like
a good idea, because enabling is not supposed to sleep, while
preparing might do so.
Right.
I guess you have to pre-prepare this clock in probe and then only call
enable here.
Yes, the prepare won't have any negative effect on energy usage anyway.
+ ret = clk_gate_ops.enable(hw);
+ if (!IS_ERR(pll_in))
+ clk_disable_unprepare(pll_in);
+
+ return ret;
+}
[snip]
+/* TODO: Also mux and div */
+const struct clk_ops audss_clk_gate_ops = {
nit: static const probably?
Yes.
+ .enable = audss_clk_gate_enable,
+ .disable = audss_clk_gate_disable,
+ .is_enabled = audss_clk_gate_is_enabled,
+};
As for the approach itself, maybe you should simply register fully
custom clocks with clk_register(), without altering
clk_register_gate() at all and simply calling gate ops whenever
necessary? I don't know, just a loose idea.
Initially that seemed to me the simplest way to encapsulate gate_ops
calls. However in that approach I should also change clk_register_mux
and clk_register_divider... which complicates this patch and maybe your
idea will be simpler overall.
By the way, this issue could be probably solved by integrating generic
clocks with regmap API, since regmap-mmio can automatically control a
clock.
Indeed but this looks like much bigger task.
Anyway thanks for feedback. I'll prepare another version.
Best regards,
Krzysztof
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[GIT PULL] exynos-drm-next
Hi Dave, Add Exynos4415 SoC support, some fixups and cleanups. Summary: - Resolve kernel lockup issue incurred by probe request in probe context. . For this, it moves all register codes of sub drivers into init function and adds component binding support for vidi driver. - Add Exynos4415 SoC support. - Make each manager and display object to be embedded in each driver context. - Fix and clean up FIMD and MIPI-DSI drivers. - Clean up unnecesary or wrong descriptions. - And trivial cleanups. Please kindly let me know if there is my missing point. Thanks, Inki Dae The following changes since commit ed1e8777a56f3523712506d608a29f57ed37b613: Merge branch 'drm-next-3.19' of git://people.freedesktop.org/~agd5f/linux into drm-next (2014-11-21 12:17:43 +1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos exynos-drm-next for you to fetch changes up to 5baf5d44fbcde002d7f3f8148e69305f520770dd: drm/exynos: avoid leak if exynos_dpi_probe() fails (2014-11-25 11:58:43 +0900) Andrzej Hajda (19): drm/exynos: remove ifdeferry from initialization code drm/exynos: dsi: remove global variable exynos_dsi_display drm/exynos: dsi: simplify device pointer evaluation drm/exynos: dsi: remove redundant encoder field drm/exynos: dsi: stop using display-ctx pointer drm/exynos/mixer: embed manager into private context drm/exynos/mixer: stop using manager-ctx pointer drm/exynos/vidi: embed manager into private context drm/exynos/vidi: stop using manager-ctx pointer drm/exynos/fimd: embed manager into private context drm/exynos/fimd: stop using manager-ctx pointer drm/exynos/hdmi: embed display into private context drm/exynos/hdmi: stop using display-ctx pointer drm/exynos/vidi: embed display into private context drm/exynos/vidi: stop using display-ctx pointer drm/exynos/dp: embed display into private context drm/exynos/dp: stop using display-ctx pointer drm/exynos/dpi: embed display into private context drm/exynos/dpi: stop using display-ctx pointer Gustavo Padovan (13): drm/exynos: remove uneeded declaration of struct dma_iommu_mapping drm/exynos: remove extra declaration of struct exynos_drm_manager drm/exynos: remove extra declaration of struct exynos_overlay drm/exynos: Replace repeated declaration by include drm/drmP.h drm/exynos: Replace repeated declarations by #include exynos_drm_drv.h drm/exynos: remove unused wait_for macro drm/exynos: Save up space using bool var as bitfields drm/exynos: update documentation to reflect code changes drm/exynos: remove leftover hdmi function declarations Revert drm/exynos: fix null pointer dereference issue drm/exynos: move Exynos platform drivers registration to init drm/exynos: Fix exynos_dpi_remove() parameter drm/exynos: avoid leak if exynos_dpi_probe() fails Inki Dae (8): drm/exynos: resolve infinite loop issue on multi-platform drm/exynos: resolve infinite loop issue on non multi-platform drm/exynos: g2d: fix null pointer dereference drm/exynos: fix possible infinite loop issue drm/exynos: fix null pointer dereference issue drm/exynos: clean up machine compatible string check drm/exynos: fix exynos_drm_component_del drm/exynos: vidi: add component support Joonyoung Shim (3): drm/exynos: add has_vtsel flag drm/exynos: move triggering checking drm/exynos: use irq_flags instead of triggering Julia Lawall (1): drm/exynos/ipp: fix error return code Krzysztof Kozlowski (1): drm/exynos: Fix DSI resuming fail because power domain being off Vivek Gautam (1): drm/exynos: dp: Remove support for unused dptx-phy YoungJun Cho (12): drm/exynos: dsi: support Exynos4415 SoC drm/exynos: fimd: support Exynos4415 SoC drm/exynos: fimd: remove unnecessary waiting vblank routine drm/exynos: fimd: move handle vblank position in TE handler drm/exynos: dsi: move DSIM_STATE_ENABLED set position drm/exynos: fimd: move shadow unprotection position drm/exynos: fimd: add fimd_enable_video_output() to cleanup drm/exynos: fimd: add fimd_enable_shadow_channel_path() to cleanup drm/exynos: fimd: modify I80 i/f irq relevant routine drm/exynos: fimd: add triggering unset routine in fimd_trigger() drm/exynos: dsi: move TE irq handler registration position drm/exynos: dsi: set TE GPIO IRQ status as IRQ_NOAUTOEN .../devicetree/bindings/video/exynos_dsim.txt |1 + .../devicetree/bindings/video/samsung-fimd.txt |1 + drivers/gpu/drm/exynos/exynos_dp_core.c| 132 -- drivers/gpu/drm/exynos/exynos_dp_core.h|5 +-
Re: [RFC PATCH] drm/exynos: Add DECON driver
On 2014년 11월 25일 21:17, Ajay kumar wrote: ping. You'd need to clean up clocks and fix up binding file. And then let's have review in more details. I wish that other people also give you their reviews. Anyway, below is my answer. Thanks, Inki Dae On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Just for the time being. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be samsung,exynos7-decon; If exynos5433 was just renamed to exynos7 then, it should be one of the following: (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Or, (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos5433-decon for Display and enhancement controller IP for Exynos5433 (c) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Eventually, we will end up here. + +- reg: physical base address and length of the DECON registers set. + +- interrupt-parent: should be the phandle of the decon controller's + parent interrupt controller. + +- interrupts: should contain a list of all DECON IP block interrupts in the + order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier + format depends on the interrupt controller used. + +- interrupt-names: should contain the interrupt names: fifo, vsync, + lcd_sys, in the same order as they were listed in the interrupts +property. + +-
Re: [RFC PATCH] drm/exynos: Add DECON driver
Hi Inki, On Tue, Nov 25, 2014 at 6:30 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 21:17, Ajay kumar wrote: ping. You'd need to clean up clocks and fix up binding file. And then let's have review in more details. I wish that other people also give you their reviews. Nice to hear. Earlier, you mentioned that its good if FIMD driver itself is modified to support Exynos7 DECON. So, what is your take now? 1) Should I add it in FIMD driver itself? We may need to add lot of driver_data for that, since offsets are much different. 2) Or, create two seperate register level files for Exynos5 and Exynos7? 3) Or the current way - Entirely different driver Anyway, below is my answer. Thanks, Inki Dae On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Just for the time being. Ok. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be samsung,exynos7-decon; If exynos5433 was just renamed to exynos7 then, it should be one of the following: (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Or, (a) samsung,exynos5430-decon for Display and enhancement controller IP for Exynos5430 (b) samsung,exynos5433-decon for Display and enhancement controller IP for Exynos5433 (c) samsung,exynos7 for Display and enhancement controller IP for Exynos7 Eventually, we will end up here. + +- reg: physical base address and length of the DECON registers set. + +- interrupt-parent: should
[PATCH 00/19] Add Support for USB DRD in AM437x
The series add DRD suport for AM437x. The serires adds - USB DRD Library This Library facilitates in switching roles between HOST and Device. - DWC3 OTG driver. This driver currently suports only the ID based switching Felipe Balbi (2): usb: dwc3: core: Adapt to named interrupts arm: dts: am4372: Add named interrupt property for dwc3 George Cherian (17): usb: common: drd-lib: Add DRD lib for USB. usb: host xhci: fix up deallocation code usb: host: xhci-plat: Add support to pass XHCI_DRD_SUPPORT quirk usb: host xhci: Add XHCI_NEEDS_LHC_RESET quirk usb: host: xhci-plat: Add support to pass XHCI_NEEDS_LHC_RESET quirk usb: dwc3: host: Pass the XHCI_DRD_SUPPORT and XHCI_NEEDS_LHC_RESET quirk usb: host: xhci: Adapt xhci to use usb drd library usb: dwc3: core: Add dwc3_drd_helper function usb: dwc3: dwc3-omap: Make the wrapper interrupt shared usb: dwc3: Add seperate dwc3_gadget object to support gadget release usb: dwc3: gadget: Adapt gadget to drd library usb: dwc3: core: Add DWC3 OTG specific register defines usb: dwc3: otg: Add the initial otg driver for dwc3. arm: dts: omap5: Add named interrupt property for dwc3 arm: dts: dra7: Add named interrupt property for dwc3 arm: dts: exynos5250: Add named interrupt property for dwc3 arm: dts: am43x evms: Make usb1 as OTG arch/arm/boot/dts/am4372.dtsi| 18 +- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/am437x-sk-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- arch/arm/boot/dts/dra7.dtsi | 28 ++- arch/arm/boot/dts/exynos5250.dtsi| 7 +- arch/arm/boot/dts/omap5.dtsi | 7 +- drivers/usb/Kconfig | 15 ++ drivers/usb/common/Makefile | 1 + drivers/usb/common/drd-lib.c | 346 +++ drivers/usb/dwc3/Makefile| 4 + drivers/usb/dwc3/core.c | 27 ++- drivers/usb/dwc3/core.h | 93 +- drivers/usb/dwc3/dwc3-omap.c | 4 +- drivers/usb/dwc3/ep0.c | 35 ++-- drivers/usb/dwc3/gadget.c| 211 +++-- drivers/usb/dwc3/gadget.h| 1 + drivers/usb/dwc3/host.c | 2 + drivers/usb/dwc3/otg.c | 126 + drivers/usb/host/xhci-plat.c | 22 +++ drivers/usb/host/xhci.c | 27 ++- drivers/usb/host/xhci.h | 2 + include/linux/usb/drd.h | 77 include/linux/usb/xhci_pdriver.h | 2 + 24 files changed, 962 insertions(+), 99 deletions(-) create mode 100644 drivers/usb/common/drd-lib.c create mode 100644 drivers/usb/dwc3/otg.c create mode 100644 include/linux/usb/drd.h -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 17/19] arm: dts: dra7: Add named interrupt property for dwc3
Add interrupt names so that the same can be used for OTG easily.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc9843..78f1761 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1153,7 +1153,12 @@
usb1: usb@4889 {
compatible = snps,dwc3;
reg = 0x4889 0x17000;
- interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usb2_phy1, usb3_phy1;
phy-names = usb2-phy, usb3-phy;
tx-fifo-resize;
@@ -1174,7 +1179,12 @@
usb2: usb@488d {
compatible = snps,dwc3;
reg = 0x488d 0x17000;
- interrupts = GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usb2_phy2;
phy-names = usb2-phy;
tx-fifo-resize;
@@ -1197,7 +1207,12 @@
usb3: usb@4891 {
compatible = snps,dwc3;
reg = 0x4891 0x17000;
- interrupts = GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
tx-fifo-resize;
maximum-speed = high-speed;
dr_mode = otg;
@@ -1217,7 +1232,12 @@
usb4: usb@4895 {
compatible = snps,dwc3;
reg = 0x4895 0x17000;
- interrupts = GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
tx-fifo-resize;
maximum-speed = high-speed;
dr_mode = otg;
--
1.8.3.1
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[PATCH 19/19] arm: dts: am43x evms: Make usb1 as OTG
USB1 of am43x EPOS EVM, am437x GP EVM and am437x SK EVM can be used as OTG.
Enable the same.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 2 +-
arch/arm/boot/dts/am437x-sk-evm.dts | 2 +-
arch/arm/boot/dts/am43x-epos-evm.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index e7ac47f..a8b5752 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -380,7 +380,7 @@
};
usb1 {
- dr_mode = peripheral;
+ dr_mode = otg;
status = okay;
};
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts
b/arch/arm/boot/dts/am437x-sk-evm.dts
index 859ff3d..b258826 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -478,7 +478,7 @@
};
usb1 {
- dr_mode = peripheral;
+ dr_mode = otg;
status = okay;
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index ac3e485..3d106e9 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -542,7 +542,7 @@
};
usb1 {
- dr_mode = peripheral;
+ dr_mode = otg;
status = okay;
};
--
1.8.3.1
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[PATCH 16/19] arm: dts: omap5: Add named interrupt property for dwc3
Add interrupt names so that the same can be used for OTG easily.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f6..a712ad9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -817,7 +817,12 @@
dwc3@4a03 {
compatible = snps,dwc3;
reg = 0x4a03 0x1;
- interrupts = GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH;
+ interrupts = GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usb2_phy, usb3_phy;
phy-names = usb2-phy, usb3-phy;
dr_mode = peripheral;
--
1.8.3.1
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[PATCH 13/19] usb: dwc3: core: Add DWC3 OTG specific register defines
Add OTG reggister defines to DWC3 core.h Signed-off-by: George Cherian george.cher...@ti.com --- drivers/usb/dwc3/core.h | 68 + 1 file changed, 68 insertions(+) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 7fbe736..eb2e970 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -381,6 +381,74 @@ #define DWC3_DEPCMD_TYPE_BULK 2 #define DWC3_DEPCMD_TYPE_INTR 3 +/* OTG Configuration Register */ +#define DWC3_OCFG_DISPWRCUTTOFF(1 5) +#define DWC3_OCFG_HIBDISMASK (1 4) +#define DWC3_OCFG_SFTRSTMASK (1 3) +#define DWC3_OCFG_OTGVERSION (1 2) +#define DWC3_OCFG_HNPCAP (1 1) +#define DWC3_OCFG_SRPCAP (1 0) + +/* OTG CTL Register */ +#define DWC3_OCTL_OTG3GOERR(1 7) +#define DWC3_OCTL_PERIMODE (1 6) +#define DWC3_OCTL_PRTPWRCTL(1 5) +#define DWC3_OCTL_HNPREQ (1 4) +#define DWC3_OCTL_SESREQ (1 3) +#define DWC3_OCTL_TERMSELIDPULSE (1 2) +#define DWC3_OCTL_DEVSETHNPEN (1 1) +#define DWC3_OCTL_HOSTSETHNPEN (1 0) + +/* OTG Event Register */ +#define DWC3_OEVT_DEVICEMODE (1 31) +#define DWC3_OEVT_XHCIRUNSTPSET(1 27) +#define DWC3_OEVT_DEVRUNSTPSET (1 26) +#define DWC3_OEVT_HIBENTRY (1 25) +#define DWC3_OEVT_IDSTSCHNG(1 24) +#define DWC3_OEVT_HRRCONFNOTIF (1 23) +#define DWC3_OEVT_HRRINITNOTIF (1 22) +#define DWC3_OEVT_ADEVIDLE (1 21) +#define DWC3_OEVT_ADEVBHOSTEND (1 20) +#define DWC3_OEVT_ADEVHOST (1 19) +#define DWC3_OEVT_ADEVHNPCHNG (1 18) +#define DWC3_OEVT_ADEVSRPDET (1 17) +#define DWC3_OEVT_ADEVSESSENDDET (1 16) +#define DWC3_OEVT_BDEVBHOSTEND (1 11) +#define DWC3_OEVT_BDEVHNPCHNG (1 10) +#define DWC3_OEVT_BDEVSESSVLDDET (1 9) +#define DWC3_OEVT_BDEVVBUSCHNG (1 8) +#define DWC3_OEVT_BSESSVLD (1 3) +#define DWC3_OEVT_HOSTNEGSTS (1 2) +#define DWC3_OEVT_SESSREQSTS (1 1) +#define DWC3_OEVT_ERR (1 0) + +/* OTG Event Enable Register */ +#define DWC3_OEVTEN_XHCIRUNSTPSETEN(1 27) +#define DWC3_OEVTEN_DEVRUNSTPSETEN (1 26) +#define DWC3_OEVTEN_HIBENTRYEN (1 25) +#define DWC3_OEVTEN_CONIDSTSCHNGEN (1 24) +#define DWC3_OEVTEN_HRRCONFNOTIFEN (1 23) +#define DWC3_OEVTEN_HRRINITNOTIFEN (1 22) +#define DWC3_OEVTEN_ADEVIDLEEN (1 21) +#define DWC3_OEVTEN_ADEVBHOSTENDEN (1 20) +#define DWC3_OEVTEN_ADEVHOSTEN (1 19) +#define DWC3_OEVTEN_ADEVHNPCHNGEN (1 18) +#define DWC3_OEVTEN_ADEVSRPDETEN (1 17) +#define DWC3_OEVTEN_ADEVSESSENDDETEN (1 16) +#define DWC3_OEVTEN_BDEVHOSTENDEN (1 11) +#define DWC3_OEVTEN_BDEVHNPCHNGEN (1 10) +#define DWC3_OEVTEN_BDEVSESSVLDDETEN (1 9) +#define DWC3_OEVTEN_BDEVVBUSCHNGEVNTEN (1 8) + +/* OTG Status Register */ +#define DWC3_OSTS_DEVRUNSTP(1 13) +#define DWC3_OSTS_XHCIRUNSTP (1 12) +#define DWC3_OSTS_PERIPHERALSTATE (1 4) +#define DWC3_OSTS_XHCIPORTPOWER(1 3) +#define DWC3_OSTS_BSESVLD (1 2) +#define DWC3_OSTS_VBUSVLD (1 1) +#define DWC3_OSTS_CONIDSTS (1 0) + /* Structures */ struct dwc3_trb; -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/19] usb: dwc3: Add seperate dwc3_gadget object to support gadget release
With the current implementation it's impossible to release the gadget.
Add a separate dwc3_gadget object to dwc3 structure so that the same
can be freed during the gadget release.
This is in prepration to adapt dwc3 gadget driver to drd library.
DRD library uses usb_del/add_gadget_udc while switching roles between
HOST and DEVICE modes. If the usb_gadget is not released during
usb_del_gadget_udc,
the subsequent usb_add_gadget_udc would try to initialize an already initialized
kobject. To avoid this make sure we have an easily freeable object.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/core.h | 7 ++-
drivers/usb/dwc3/ep0.c| 35 --
drivers/usb/dwc3/gadget.c | 113 ++
drivers/usb/dwc3/gadget.h | 1 +
4 files changed, 101 insertions(+), 55 deletions(-)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7c5ae37..7fbe736 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -626,6 +626,11 @@ struct dwc3_scratchpad_array {
__le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
};
+struct dwc3_gadget {
+ struct usb_gadget gadget;
+ struct dwc3 *dwc;
+};
+
/**
* struct dwc3 - representation of our controller
* @ctrl_req: usb control request which is used for ep0
@@ -736,7 +741,7 @@ struct dwc3 {
struct dwc3_event_buffer **ev_buffs;
struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
- struct usb_gadget gadget;
+ struct dwc3_gadget *dwc_gadget;
struct usb_gadget_driver *gadget_driver;
struct usb_phy *usb2_phy;
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index baeedbd..e7409f1 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -109,6 +109,7 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
struct dwc3_request *req)
{
struct dwc3 *dwc = dep-dwc;
+ struct dwc3_gadget *dwc_gadget = dwc-dwc_gadget;
req-request.actual = 0;
req-request.status = -EINPROGRESS;
@@ -152,7 +153,7 @@ static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
direction = !dwc-ep0_expect_in;
dwc-delayed_status = false;
- usb_gadget_set_state(dwc-gadget, USB_STATE_CONFIGURED);
+ usb_gadget_set_state(dwc_gadget-gadget, USB_STATE_CONFIGURED);
if (dwc-ep0state == EP0_STATUS_PHASE)
__dwc3_ep0_do_control_status(dwc, dwc-eps[direction]);
@@ -391,6 +392,7 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
struct usb_ctrlrequest *ctrl, int set)
{
struct dwc3_ep *dep;
+ struct dwc3_gadget *dwc_gadget = dwc-dwc_gadget;
u32 recip;
u32 wValue;
u32 wIndex;
@@ -401,7 +403,7 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
wValue = le16_to_cpu(ctrl-wValue);
wIndex = le16_to_cpu(ctrl-wIndex);
recip = ctrl-bRequestType USB_RECIP_MASK;
- state = dwc-gadget.state;
+ state = dwc_gadget-gadget.state;
switch (recip) {
case USB_RECIP_DEVICE:
@@ -499,7 +501,8 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
- enum usb_device_state state = dwc-gadget.state;
+ struct dwc3_gadget *dwc_gadget = dwc-dwc_gadget;
+ enum usb_device_state state = dwc_gadget-gadget.state;
u32 addr;
u32 reg;
@@ -521,26 +524,28 @@ static int dwc3_ep0_set_address(struct dwc3 *dwc, struct
usb_ctrlrequest *ctrl)
dwc3_writel(dwc-regs, DWC3_DCFG, reg);
if (addr)
- usb_gadget_set_state(dwc-gadget, USB_STATE_ADDRESS);
+ usb_gadget_set_state(dwc_gadget-gadget, USB_STATE_ADDRESS);
else
- usb_gadget_set_state(dwc-gadget, USB_STATE_DEFAULT);
+ usb_gadget_set_state(dwc_gadget-gadget, USB_STATE_DEFAULT);
return 0;
}
static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest
*ctrl)
{
+ struct dwc3_gadget *dwc_gadget = dwc-dwc_gadget;
int ret;
spin_unlock(dwc-lock);
- ret = dwc-gadget_driver-setup(dwc-gadget, ctrl);
+ ret = dwc-gadget_driver-setup(dwc_gadget-gadget, ctrl);
spin_lock(dwc-lock);
return ret;
}
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
- enum usb_device_state state = dwc-gadget.state;
+ struct dwc3_gadget *dwc_gadget = dwc-dwc_gadget;
+ enum usb_device_state state = dwc_gadget-gadget.state;
u32 cfg;
int ret;
u32 reg;
@@ -564,8 +569,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct
usb_ctrlrequest *ctrl)
* to change the state on the next usb_ep_queue()
[PATCH 12/19] usb: dwc3: gadget: Adapt gadget to drd library
Adapt the dwc3 gadget to use drd library functions.
In prepration to support DRD on dwc3.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/gadget.c | 128 --
1 file changed, 100 insertions(+), 28 deletions(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 2c54d45..a75fae5 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -29,6 +29,7 @@
#include linux/usb/ch9.h
#include linux/usb/gadget.h
+#include linux/usb/drd.h
#include debug.h
#include core.h
@@ -2681,6 +2682,89 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
return ret;
}
+void dwc3_gadget_release(struct device *dev)
+{
+ struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
+ struct dwc3_gadget *dwc_gadget = gadget_to_dwc_gadget(gadget);
+ struct dwc3 *dwc = dwc_gadget-dwc;
+
+ dev_dbg(dev, releasing '%s'\n, dev_name(dev));
+ dwc3_gadget_free_endpoints(dwc);
+ dma_free_coherent(dwc-dev, DWC3_EP0_BOUNCE_SIZE,
+ dwc-ep0_bounce, dwc-ep0_bounce_addr);
+ kfree(dwc-setup_buf);
+ dma_free_coherent(dwc-dev, sizeof(*dwc-ep0_trb),
+ dwc-ep0_trb, dwc-ep0_trb_addr);
+ dma_free_coherent(dwc-dev, sizeof(*dwc-ctrl_req),
+ dwc-ctrl_req, dwc-ctrl_req_addr);
+ usb_drd_unregister_udc(dwc-dev);
+ kfree(dwc_gadget);
+}
+
+int dwc3_gadget_setup(void *data)
+{
+ struct dwc3 *dwc = data;
+ struct dwc3_gadget *dwc_gadget;
+ struct usb_drd_gadget *drd_gadget;
+ struct usb_drd_setup *gadget_setup;
+ int ret;
+
+ drd_gadget = kzalloc(sizeof(*drd_gadget), GFP_KERNEL);
+ if (!drd_gadget) {
+ ret = -ENOMEM;
+ goto err1;
+ }
+
+ gadget_setup = kzalloc(sizeof(*gadget_setup), GFP_KERNEL);
+ if (!gadget_setup) {
+ ret = -ENOMEM;
+ goto err2;
+ }
+
+ dwc_gadget = kzalloc(sizeof(*dwc_gadget), GFP_KERNEL);
+ if (!dwc_gadget) {
+ ret = -ENOMEM;
+ goto err3;
+ }
+
+ drd_gadget-g_driver = dwc-gadget_driver;
+
+ /*
+* Pass the DWC3 specific routines for
+* switching roles to the drd library
+*/
+ gadget_setup-ll_start = NULL;
+ gadget_setup-ll_stop = NULL;
+ gadget_setup-ll_release = dwc3_gadget_release;
+ gadget_setup-data = (void *)dwc;
+ drd_gadget-gadget_setup = gadget_setup;
+
+ dwc_gadget-gadget.ops = dwc3_gadget_ops;
+ dwc_gadget-gadget.max_speed= USB_SPEED_SUPER;
+ dwc_gadget-gadget.speed= USB_SPEED_UNKNOWN;
+ dwc_gadget-gadget.sg_supported = true;
+ dwc_gadget-gadget.name = dwc3-gadget;
+ dwc_gadget-dwc = dwc;
+ drd_gadget-gadget = dwc_gadget-gadget;
+
+ /*
+* Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
+* on ep out.
+*/
+ dwc_gadget-gadget.quirk_ep_out_aligned_size = true;
+ dwc-dwc_gadget = dwc_gadget;
+ usb_drd_register_udc(dwc-dev, drd_gadget);
+
+ return 0;
+
+err3:
+ kfree(gadget_setup);
+err2:
+ kfree(drd_gadget);
+err1:
+ return ret;
+}
+
/**
* dwc3_gadget_init - Initializes gadget related registers
* @dwc: pointer to our controller context structure
@@ -2690,7 +2774,6 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
int dwc3_gadget_init(struct dwc3 *dwc)
{
int ret;
- struct dwc3_gadget *dwc_gadget;
dwc-ctrl_req = dma_alloc_coherent(dwc-dev, sizeof(*dwc-ctrl_req),
dwc-ctrl_req_addr, GFP_KERNEL);
@@ -2723,24 +2806,9 @@ int dwc3_gadget_init(struct dwc3 *dwc)
goto err3;
}
- dwc_gadget = kzalloc(sizeof(*dwc_gadget), GFP_KERNEL);
- if (!dwc_gadget) {
- ret = -ENOMEM;
+ ret = dwc3_gadget_setup(dwc);
+ if (ret)
goto err3;
- }
-
- dwc_gadget-gadget.ops = dwc3_gadget_ops;
- dwc_gadget-gadget.max_speed= USB_SPEED_SUPER;
- dwc_gadget-gadget.speed= USB_SPEED_UNKNOWN;
- dwc_gadget-gadget.sg_supported = true;
- dwc_gadget-gadget.name = dwc3-gadget;
- dwc_gadget-dwc = dwc;
-
- /*
-* Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
-* on ep out.
-*/
- dwc_gadget-gadget.quirk_ep_out_aligned_size = true;
/*
* REVISIT: Here we should clear all pending IRQs to be
@@ -2751,7 +2819,8 @@ int dwc3_gadget_init(struct dwc3 *dwc)
if (ret)
goto err4;
- ret = usb_add_gadget_udc(dwc-dev, dwc_gadget-gadget);
+ ret =
[PATCH 10/19] usb: dwc3: core: Adapt to named interrupts
From: Felipe Balbi ba...@ti.com
Add support to use interrupt names,
Following are the interrupt names
Peripheral Interrupt - peripheral
HOST Interrupt - host
OTG Interrupt - otg
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/core.c | 12
drivers/usb/dwc3/core.h | 7 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fadd767..dbd5589 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -760,6 +760,18 @@ static int dwc3_probe(struct platform_device *pdev)
dwc-xhci_resources[1].flags = res-flags;
dwc-xhci_resources[1].name = res-name;
+ dwc-otg_irq = platform_get_irq_byname(pdev, otg);
+ if (!dwc-otg_irq)
+ dev_err(dev, missing OTG IRQ\n);
+
+ dwc-gadget_irq = platform_get_irq_byname(pdev, peripheral);
+ if (!dwc-gadget_irq)
+ dev_err(dev, missing peripheral IRQ\n);
+
+ dwc-xhci_irq = platform_get_irq_byname(pdev, host);
+ if (!dwc-xhci_irq)
+ dev_err(dev, missing HOST IRQ\n);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, missing memory resource\n);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 6b38223..7c5ae37 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -651,6 +651,9 @@ struct dwc3_scratchpad_array {
* @maximum_speed: maximum speed requested (mainly for testing purposes)
* @revision: revision register contents
* @dr_mode: requested mode of operation
+ * @xhci_irq: IRQ number for XHCI IRQs
+ * @gadget_irq: IRQ number for Peripheral IRQs
+ * @otg_irq: IRQ number for OTG IRQs
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY
@@ -747,6 +750,10 @@ struct dwc3 {
enum usb_dr_modedr_mode;
+ int gadget_irq;
+ int xhci_irq;
+ int otg_irq;
+
/* used for suspend/resume */
u32 dcfg;
u32 gctl;
--
1.8.3.1
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[PATCH 15/19] arm: dts: am4372: Add named interrupt property for dwc3
From: Felipe Balbi ba...@ti.com
Add interrupt names so that the same can be used for OTG easily.
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index e19068d..3dda4c8 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -810,8 +810,13 @@
usb1: usb@4839 {
compatible = synopsys,dwc3;
- reg = 0x4839 0x1;
- interrupts = GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH;
+ reg = 0x4839 0x17000;
+ interrupts = GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usb2_phy1;
phy-names = usb2-phy;
maximum-speed = high-speed;
@@ -834,8 +839,13 @@
usb2: usb@483d {
compatible = synopsys,dwc3;
- reg = 0x483d 0x1;
- interrupts = GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH;
+ reg = 0x483d 0x17000;
+ interrupts = GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usb2_phy2;
phy-names = usb2-phy;
maximum-speed = high-speed;
--
1.8.3.1
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[PATCH 18/19] arm: dts: exynos5250: Add named interrupt property for dwc3
Add interrupt names so that the same can be used for OTG easily.
Signed-off-by: George Cherian george.cher...@ti.com
---
arch/arm/boot/dts/exynos5250.dtsi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index f21b9aa..c74cd8b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -558,7 +558,12 @@
dwc3 {
compatible = synopsys,dwc3;
reg = 0x1200 0x1;
- interrupts = 0 72 0;
+ interrupts = 0 72 0,
+0 72 0,
+0 72 0;
+ interrupt-names = peripheral,
+ host,
+ otg;
phys = usbdrd_phy 0, usbdrd_phy 1;
phy-names = usb2-phy, usb3-phy;
};
--
1.8.3.1
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[PATCH 14/19] usb: dwc3: otg: Add the initial otg driver for dwc3.
Add the Initial OTG driver for dwc3.
Currently support only
* ID based Role switching.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/Makefile | 4 ++
drivers/usb/dwc3/core.c | 10 +---
drivers/usb/dwc3/core.h | 10
drivers/usb/dwc3/otg.c| 126 ++
4 files changed, 142 insertions(+), 8 deletions(-)
create mode 100644 drivers/usb/dwc3/otg.c
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index bb34fbc..fe7af97 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -12,6 +12,10 @@ ifneq ($(filter y,$(CONFIG_USB_DWC3_HOST)
$(CONFIG_USB_DWC3_DUAL_ROLE)),)
dwc3-y += host.o
endif
+ifneq ($(CONFIG_USB_DWC3_DUAL_ROLE),)
+ dwc3-y += otg.o
+endif
+
ifneq ($(filter y,$(CONFIG_USB_DWC3_GADGET) $(CONFIG_USB_DWC3_DUAL_ROLE)),)
dwc3-y += gadget.o ep0.o
endif
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index dbd5589..dd4af3f 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -685,15 +685,9 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
break;
case USB_DR_MODE_OTG:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
- ret = dwc3_host_init(dwc);
- if (ret) {
- dev_err(dev, failed to initialize host\n);
- return ret;
- }
-
- ret = dwc3_gadget_init(dwc);
+ ret = dwc3_otg_init(dwc);
if (ret) {
- dev_err(dev, failed to initialize gadget\n);
+ dev_err(dev, failed to initialize otg\n);
return ret;
}
break;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index eb2e970..001d77d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1103,6 +1103,16 @@ static inline int
dwc3_send_gadget_generic_command(struct dwc3 *dwc,
{ return 0; }
#endif
+#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
+int dwc3_otg_init(struct dwc3 *dwc);
+void dwc3_otg_exit(struct dwc3 *dwc);
+#else
+static inline int dwc3_otg_init(struct dwc3 *dwc)
+{ return 0; }
+static inline void dwc3_otg_exit(struct dwc3 *dwc)
+{ }
+#endif
+
/* power management interface */
#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
int dwc3_gadget_suspend(struct dwc3 *dwc);
diff --git a/drivers/usb/dwc3/otg.c b/drivers/usb/dwc3/otg.c
new file mode 100644
index 000..b5c31c0
--- /dev/null
+++ b/drivers/usb/dwc3/otg.c
@@ -0,0 +1,126 @@
+/**
+ * otg.c - DesignWare USB3 DRD Controller OTG
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Authors: George Cherian george.cher...@ti.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/kernel.h
+#include linux/platform_device.h
+#include linux/interrupt.h
+#include linux/usb.h
+#include linux/usb/hcd.h
+
+#include linux/usb/drd.h
+#include core.h
+#include io.h
+
+#define DWC3_GSTS_OTG_IP (1 10)
+
+static irqreturn_t dwc3_otg_interrupt(int irq , void *_dwc)
+{
+ struct dwc3 *dwc = _dwc;
+ u32 reg;
+
+ spin_lock(dwc-lock);
+ reg = dwc3_readl(dwc-regs, DWC3_GSTS);
+ if (reg DWC3_GSTS_OTG_IP) {
+ reg = dwc3_readl(dwc-regs, DWC3_OEVT);
+ dev_vdbg(dwc-dev, OTG Interrupt %x\n, reg);
+ dwc3_writel(dwc-regs, DWC3_OEVT, reg);
+ spin_unlock(dwc-lock);
+ return IRQ_WAKE_THREAD;
+ }
+
+ spin_unlock(dwc-lock);
+ return IRQ_NONE;
+}
+
+static irqreturn_t dwc3_otg_thread_interrupt(int irq, void *_dwc)
+{
+ struct dwc3 *dwc = _dwc;
+ u32 reg = dwc3_readl(dwc-regs, DWC3_OSTS);
+
+ dev_vdbg(dwc-dev, OTG thread interrupt\n);
+ if ((reg DWC3_OSTS_CONIDSTS)) {
+ usb_drd_stop_hcd(dwc-dev);
+ dwc3_writel(dwc-regs, DWC3_OCFG, DWC3_OCFG_SFTRSTMASK);
+ dwc3_writel(dwc-regs, DWC3_OCTL,
+ DWC3_OCTL_SESREQ | DWC3_OCTL_PERIMODE);
+ if (usb_drd_get_state(dwc-dev) DRD_DEVICE_REGISTERED) {
+ usb_drd_start_udc(dwc-dev);
+ } else {
+ dwc3_core_gadget_helper(dwc);
+ dwc3_gadget_init(dwc);
+ }
+ dwc3_writel(dwc-regs, DWC3_OEVTEN,
+ DWC3_OEVTEN_CONIDSTSCHNGEN);
+ } else if
RE: [1/2] ARM: dts: Fix bootup issue on smdk5250
Hi Kukjin,
Subject: RE: [1/2] ARM: dts: Fix bootup issue on smdk5250
Pankaj Dubey wrote:
Hi,
Hi,
Yadwinder, please don't miss [PATCH 1/2] in subject, so that my e-mail
client can't filter wrong ;)
Sure, but I think your mail client had played some trick, as patches
were posted with [PATCH */2] prefix.
On Tuesday 18 November 2014 05:38 PM, Yadwinder Singh Brar wrote:
With default config on smdk5250 latest tree throws below message :
[2.226049] thermal thermal_zone0: critical temperature
reached(224 C),shutting down
[2.227840] reboot: Failed to start orderly shutdown: forcing
the issue
and hangs randomly because it reads wrong temperature value.
I can't figure out any direct relation between LDO10 and TMU from
board schematics which I have. So making LDO10 always-on to fix
issue for now.
Hmm...strange, I also can't see any relations now...but I need to
contact to hardware guy before applying this, this fixes the problem
though.
Ok, sure it will be good know actual relation from hardware guy.
Meanwhile can we get another patch[1] merged which was posted along
with patch just because both patches were on same file. Otherwise
there is no dependency between them and can be applied independently.
Best Regards,
Yadwinder
[1] : http://www.spinics.net/lists/linux-samsung-soc/msg39107.html
Thanks,
Kukjin
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
Tested this on SMDK5250 board, system boot is fine now, hence
Tested-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index bc27cc2..95b5b51 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -190,6 +190,7 @@
regulator-name = P1.8V_LDO_OUT10;
regulator-min-microvolt = 180;
regulator-max-microvolt = 180;
+ regulator-always-on;
};
ldo11_reg: LDO11 {
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[PATCH 06/19] usb: dwc3: host: Pass the XHCI_DRD_SUPPORT and XHCI_NEEDS_LHC_RESET quirk
Pass the quir flag XHCI_DRD_SUPPORT from DWC3 host to xhci platform driver.
This enables xhci driver to handle deallocation's differently while in DRD mode.
Pass the quirk flag XHCI_NEEDS_LHC_RESET from DWC3 host to xhci platform
driver. This enables to do LHRESET during xhci_reset().
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index dcb8ca0..257b5b5 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -53,6 +53,8 @@ int dwc3_host_init(struct dwc3 *dwc)
#ifdef CONFIG_DWC3_HOST_USB3_LPM_ENABLE
pdata.usb3_lpm_capable = 1;
#endif
+ pdata.usb_drd_support = 1;
+ pdata.usb_needs_lhc_reset = 1;
ret = platform_device_add_data(xhci, pdata, sizeof(pdata));
if (ret) {
--
1.8.3.1
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[PATCH 07/19] usb: host: xhci: Adapt xhci to use usb drd library
Adapt the xhci-plat driver to use drd library functions. In prepration to support DRD on dwc3. Signed-off-by: George Cherian george.cher...@ti.com --- drivers/usb/host/xhci-plat.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index d8d024d..fbbbd59 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -17,6 +17,8 @@ #include linux/of.h #include linux/platform_device.h #include linux/slab.h +#include linux/usb/otg.h +#include linux/usb/drd.h #include linux/usb/xhci_pdriver.h #include xhci.h @@ -78,6 +80,7 @@ static int xhci_plat_probe(struct platform_device *pdev) struct resource *res; struct usb_hcd *hcd; struct clk *clk; + struct usb_drd_host *drd_host; int ret; int irq; @@ -169,6 +172,17 @@ static int xhci_plat_probe(struct platform_device *pdev) if (ret) goto put_usb3_hcd; + drd_host = kzalloc(sizeof(*drd_host), GFP_KERNEL); + if (!drd_host) + return -ENOMEM; + + drd_host-main_hcd = xhci-main_hcd; + drd_host-shared_hcd = xhci-shared_hcd; + drd_host-hcd_irq = irq; + drd_host-host_setup = NULL; + + usb_drd_register_hcd(pdev-dev.parent, drd_host); + return 0; put_usb3_hcd: @@ -200,6 +214,7 @@ static int xhci_plat_remove(struct platform_device *dev) if (!IS_ERR(clk)) clk_disable_unprepare(clk); usb_put_hcd(hcd); + usb_drd_unregister_hcd(dev-dev.parent); kfree(xhci); return 0; -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 09/19] usb: dwc3: dwc3-omap: Make the wrapper interrupt shared
OTG interrupt and wrapper is shared
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/dwc3-omap.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 172d64e..f99e2ca 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -525,8 +525,8 @@ static int dwc3_omap_probe(struct platform_device *pdev)
reg = dwc3_omap_readl(omap-base, USBOTGSS_SYSCONFIG);
omap-dma_status = !!(reg USBOTGSS_SYSCONFIG_DMADISABLE);
- ret = devm_request_irq(dev, omap-irq, dwc3_omap_interrupt, 0,
- dwc3-omap, omap);
+ ret = devm_request_irq(dev, omap-irq, dwc3_omap_interrupt, IRQF_SHARED,
+ dwc3-omap, omap);
if (ret) {
dev_err(dev, failed to request IRQ #%d -- %d\n,
omap-irq, ret);
--
1.8.3.1
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[PATCH 08/19] usb: dwc3: core: Add dwc3_drd_helper function
This helper function, facilitates to re-initialize the event buffers.
It re-initilizes the event buffers while switching role from
HOST to DEVICE mode.
The DWC3 IP shares internal RAM for both HOST and Device specific registers.
So while switching roles from HOST to Device modes, it's required to
re-initialize the EVENT buffer registers for the Device mode to continue
work properly. dwc3_event_buffers_setup() is exported out from core.c via
wrapper dwc3_core_gadget_helper() which will be invoked from dwc3 otg driver.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/core.c | 5 +
drivers/usb/dwc3/core.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 25ddc39..fadd767 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -254,6 +254,11 @@ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
}
}
+int dwc3_core_gadget_helper(struct dwc3 *dwc)
+{
+ return dwc3_event_buffers_setup(dwc);
+}
+
static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
{
if (!dwc-has_hibernation)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4bb9aa6..6b38223 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -981,6 +981,7 @@ struct dwc3_gadget_ep_cmd_params {
/* prototypes */
void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
+int dwc3_core_gadget_helper(struct dwc3 *dwc);
#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
int dwc3_host_init(struct dwc3 *dwc);
--
1.8.3.1
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[PATCH 04/19] usb: host xhci: Add XHCI_NEEDS_LHC_RESET quirk
This adds XHCI_NEEDS_LHC_RESET quirk, to make sure only Light Host Reset
is done during xhci_reset(). This is mainly useful when we switch roles
HOST to Device mode and viceversa.
The DWC3 IP shares internal RAM for both HOST and Device specific registers.
So while switching roles between HOST and Device modes, it's advbised to do
a LIGHT HC reset else the already configured global registers of the DWC3 IP
gets re-initialized.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/host/xhci.c | 5 +++--
drivers/usb/host/xhci.h | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index d4196f8..5dabf9a 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -170,11 +170,12 @@ int xhci_reset(struct xhci_hcd *xhci)
xhci_dbg_trace(xhci, trace_xhci_dbg_init, // Reset the HC);
command = readl(xhci-op_regs-command);
- command |= CMD_RESET;
+ command |= (xhci-quirks XHCI_NEEDS_LHC_RESET) ? CMD_LRESET :
CMD_RESET;
writel(command, xhci-op_regs-command);
ret = xhci_handshake(xhci, xhci-op_regs-command,
- CMD_RESET, 0, 10 * 1000 * 1000);
+ (xhci-quirks XHCI_NEEDS_LHC_RESET) ? CMD_LRESET :
CMD_RESET,
+ 0, 10 * 1000 * 1000);
if (ret)
return ret;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 2248058..1b14b09 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1561,6 +1561,7 @@ struct xhci_hcd {
/* For controllers with a broken beyond repair streams implementation */
#define XHCI_BROKEN_STREAMS(1 19)
#define XHCI_DRD_SUPPORT (1 20)
+#define XHCI_NEEDS_LHC_RESET (1 21)
unsigned intnum_active_eps;
unsigned intlimit_active_eps;
/* There are two roothubs to keep track of bus suspend info for */
--
1.8.3.1
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[PATCH 01/19] usb: common: drd-lib: Add DRD lib for USB.
Add USB DRD library. This Library facilitates to
switch roles between HOST and Device modes.
A DRD should be added to the library using usb_drd_add().
Register the HOST and UDC using usb_drd_register_hcd/udc().
Un-Register the HOST and UDC using usb_drd_unregister_hcd/udc().
Depending on the state of IP -
Call the following to start/stop HOST controller
usb_drd_start/stop_hcd().
This internally calls usb_add/remove_hcd() or IP specific low level start/stop
defined in ll_start/stop
Call the following to start/stop UDC
usb_drd_start/stop_udc().
This internally calls udc_start/udc_stop() or IP specific low level start/stop
defined in ll_start/stop
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/Kconfig | 15 ++
drivers/usb/common/Makefile | 1 +
drivers/usb/common/drd-lib.c | 346 +++
include/linux/usb/drd.h | 77 ++
4 files changed, 439 insertions(+)
create mode 100644 drivers/usb/common/drd-lib.c
create mode 100644 include/linux/usb/drd.h
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index ae481c3..ea0d944 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -34,6 +34,21 @@ config USB_COMMON
default y
depends on USB || USB_GADGET
+config DRD_LIB
+ tristate DRD Library support
+ default y
+ depends on USB USB_GADGET
+ ---help---
+ This option adds DRD Library support for Universal Serial Bus (USB).
+ DRD Library faciliatets the Role switching by HOST and DEVICE roles,
+ If your hardware has a Dual Role Device.
+
+ The DRD Library uses USB core API's to start/stop HOST controllers,
+ UDC API's to start/stop DEVICE controllers, ther by enabling to
+ switch roles between HOST and Device modes.
+
+ Say N if unsure.
+
config USB_ARCH_HAS_HCD
def_bool y
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index ca2f8bd..e2c1593 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -7,3 +7,4 @@ usb-common-y += common.o
usb-common-$(CONFIG_USB_LED_TRIG) += led.o
obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+obj-$(CONFIG_DRD_LIB) += drd-lib.o
diff --git a/drivers/usb/common/drd-lib.c b/drivers/usb/common/drd-lib.c
new file mode 100644
index 000..6159436
--- /dev/null
+++ b/drivers/usb/common/drd-lib.c
@@ -0,0 +1,346 @@
+/**
+ * drd-lib.c - USB DRD library functions
+ *
+ * Copyright (C) 2014 Texas Instruments
+ * Author: George Cherian george.cher...@ti.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/device.h
+#include linux/err.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/usb.h
+
+#include linux/usb/hcd.h
+#include linux/usb/gadget.h
+#include linux/usb/drd.h
+
+/**
+ * struct usb_drd - describes one dual role device
+ * @host - the HOST controller device of this drd
+ * @gadget - the gadget of drd
+ * @parent - the device to the actual controller
+ * @list - for use by the drd lib
+ * @state - specifies the current state
+ *
+ * This represents the internal data structure which is used by the UDC-class
+ * to hold information about udc driver and gadget together.
+ */
+struct usb_drd {
+ struct usb_drd_host *host;
+ struct usb_drd_gadget *gadget;
+ struct device *parent;
+ struct list_headlist;
+ unsigned intstate;
+};
+
+static LIST_HEAD(drd_list);
+static DEFINE_SPINLOCK(drd_lock);
+
+static struct usb_drd *usb_drd_get_dev(struct device *parent)
+{
+ struct usb_drd *drd;
+
+ spin_lock(drd_lock);
+ list_for_each_entry(drd, drd_list, list)
+ if (drd-parent == parent)
+ goto out;
+ drd = NULL;
+out:
+ spin_unlock(drd_lock);
+
+ return drd;
+}
+
+int usb_drd_get_state(struct device *parent)
+{
+ struct usb_drd *drd;
+
+ drd = usb_drd_get_dev(parent);
+ if (!drd)
+ return -ENODEV;
+
+ return drd-state;
+}
+EXPORT_SYMBOL_GPL(usb_drd_get_state);
+
+int usb_drd_release(struct device *parent)
+{
+ struct usb_drd *drd;
+ int ret;
+
+ spin_lock(drd_lock);
+ list_for_each_entry(drd, drd_list, list) {
+ if (drd-parent == parent) {
+ kfree(drd);
+ ret =
[PATCH 05/19] usb: host: xhci-plat: Add support to pass XHCI_NEEDS_LHC_RESET quirk
Extend the platform data to pass XHCI_NEEDS_LHC_RESET quirk to
the xhci driver.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/host/xhci-plat.c | 3 +++
include/linux/usb/xhci_pdriver.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 2c42273..d8d024d 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -31,6 +31,9 @@ static void xhci_plat_quirks(struct device *dev, struct
xhci_hcd *xhci)
if (pdata-usb_drd_support)
xhci-quirks |= XHCI_DRD_SUPPORT;
+
+ if (pdata-usb_needs_lhc_reset)
+ xhci-quirks |= XHCI_NEEDS_LHC_RESET;
/*
* As of now platform drivers don't provide MSI support so we ensure
* here that the generic code does not try to make a pci_dev from our
diff --git a/include/linux/usb/xhci_pdriver.h b/include/linux/usb/xhci_pdriver.h
index 539c2d8..8ef7321 100644
--- a/include/linux/usb/xhci_pdriver.h
+++ b/include/linux/usb/xhci_pdriver.h
@@ -23,6 +23,7 @@
struct usb_xhci_pdata {
unsignedusb3_lpm_capable:1;
unsignedusb_drd_support:1;
+ unsignedusb_needs_lhc_reset:1;
};
#endif /* __USB_CORE_XHCI_PDRIVER_H */
--
1.8.3.1
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[PATCH 03/19] usb: host: xhci-plat: Add support to pass XHCI_DRD_SUPPORT quirk
Extend the platform data to pass XHCI_DRD_SUPPORT quirk to the xhci driver.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/host/xhci-plat.c | 4
include/linux/usb/xhci_pdriver.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 3d78b0c..2c42273 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -27,6 +27,10 @@ static struct hc_driver __read_mostly xhci_plat_hc_driver;
static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
{
+ struct usb_xhci_pdata *pdata = dev_get_platdata(dev);
+
+ if (pdata-usb_drd_support)
+ xhci-quirks |= XHCI_DRD_SUPPORT;
/*
* As of now platform drivers don't provide MSI support so we ensure
* here that the generic code does not try to make a pci_dev from our
diff --git a/include/linux/usb/xhci_pdriver.h b/include/linux/usb/xhci_pdriver.h
index 376654b..539c2d8 100644
--- a/include/linux/usb/xhci_pdriver.h
+++ b/include/linux/usb/xhci_pdriver.h
@@ -22,6 +22,7 @@
*/
struct usb_xhci_pdata {
unsignedusb3_lpm_capable:1;
+ unsignedusb_drd_support:1;
};
#endif /* __USB_CORE_XHCI_PDRIVER_H */
--
1.8.3.1
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[PATCH 02/19] usb: host xhci: fix up deallocation code
This fixes up the deallocation code in the xhci driver, so that
usb_add_hcd()/usb_remove_hcd() can be called repeatedly without
crashing.
In case of DRD mode, the DRD library calls /usb_remove_hcd() while
switching from HOST mode to Device mode, but it doesnot call usb_put_hcd().
We need to preserve the already allocated xhci struct for the subsequent
call of usb_add_hcd() from the DRD library.
A new quirk flag XHCI_DRD_SUPPORT is added to differentiate between
normal usb_remove_hcd and drd specific call.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/host/xhci.c | 22 --
drivers/usb/host/xhci.h | 1 +
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 2a5d45b..d4196f8 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -666,7 +666,8 @@ static void xhci_only_stop_hcd(struct usb_hcd *hcd)
* calls this function when allocation fails in usb_add_hcd(), or
* usb_remove_hcd() is called). So we need to unset xHCI's pointer.
*/
- xhci-shared_hcd = NULL;
+ if (!(xhci-quirks XHCI_DRD_SUPPORT))
+ xhci-shared_hcd = NULL;
spin_unlock_irq(xhci-lock);
}
@@ -4815,6 +4816,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t
get_quirks)
struct xhci_hcd *xhci;
struct device *dev = hcd-self.controller;
int retval;
+ boolallocated = false;
/* Accept arbitrarily long scatter-gather lists */
hcd-self.sg_tablesize = ~0;
@@ -4826,10 +4828,15 @@ int xhci_gen_setup(struct usb_hcd *hcd,
xhci_get_quirks_t get_quirks)
hcd-self.no_stop_on_short = 1;
if (usb_hcd_is_primary_hcd(hcd)) {
- xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
- if (!xhci)
- return -ENOMEM;
- *((struct xhci_hcd **) hcd-hcd_priv) = xhci;
+ if (*((struct xhci_hcd **)hcd-hcd_priv) == NULL) {
+ xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
+ if (!xhci)
+ return -ENOMEM;
+ *((struct xhci_hcd **)hcd-hcd_priv) = xhci;
+ allocated = true;
+ } else {
+ xhci = *((struct xhci_hcd **)hcd-hcd_priv);
+ }
xhci-main_hcd = hcd;
/* Mark the first roothub as being USB 2.0.
* The xHCI driver will register the USB 3.0 roothub.
@@ -4902,7 +4909,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
xhci_get_quirks_t get_quirks)
xhci_dbg(xhci, Called HCD init\n);
return 0;
error:
- kfree(xhci);
+ if (allocated) {
+ *((struct xhci_hcd **)hcd-hcd_priv) = NULL;
+ kfree(xhci);
+ }
return retval;
}
EXPORT_SYMBOL_GPL(xhci_gen_setup);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index df76d64..2248058 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1560,6 +1560,7 @@ struct xhci_hcd {
#define XHCI_SPURIOUS_WAKEUP (1 18)
/* For controllers with a broken beyond repair streams implementation */
#define XHCI_BROKEN_STREAMS(1 19)
+#define XHCI_DRD_SUPPORT (1 20)
unsigned intnum_active_eps;
unsigned intlimit_active_eps;
/* There are two roothubs to keep track of bus suspend info for */
--
1.8.3.1
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Re: [RFC PATCH] drm/exynos: Add DECON driver
On 2014년 11월 25일 22:08, Ajay kumar wrote: Hi Inki, On Tue, Nov 25, 2014 at 6:30 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 21:17, Ajay kumar wrote: ping. You'd need to clean up clocks and fix up binding file. And then let's have review in more details. I wish that other people also give you their reviews. Nice to hear. Earlier, you mentioned that its good if FIMD driver itself is modified to support Exynos7 DECON. So, what is your take now? 1) Should I add it in FIMD driver itself? We may need to add lot of driver_data for that, since offsets are much different. 2) Or, create two seperate register level files for Exynos5 and Exynos7? 3) Or the current way - Entirely different driver This one, 3), for now because they, Exynos4, Exynos543x and Exynos7, are much different each other. So for next version of your patch, you'd need to change the driver name to exynos7-decon or what you want so that each driver can be entirely separated in SoC name somehow. i.e., - exynos_drm_fimd covers Exynos64xx, Exynos3250, all Exynos4 series and Exynos5250 ~ 5422 SoC. - exynos5-decon covers Exynos5430 and Exynos5433 SoC. - exynos7-decon covers Exynos7 and maybe later SoC. After that, let's consider how we can integrate these drivers later. Thanks, Inki Dae Anyway, below is my answer. Thanks, Inki Dae On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Just for the time being. Ok. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be samsung,exynos7-decon; If exynos5433 was just renamed to exynos7 then, it should be one of
Re: [RFC 0/2] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
Hello Krzysztof,
On 11/25/2014 10:22 AM, Krzysztof Kozlowski wrote:
Hmmm, that's strange. I've looked again at your dmesg and it is little
different than mine (when system fails).
1. Does your PMIC come up? In your dmesg:
[2.687297] max77802-pmic max77802-pmic: regulator init failed for 0
[2.693539] platform max77802-pmic: Driver max77802-pmic requests probe
deferral
The Peach Pit/Pi DTS define the parent input supplies for the max77802 PMIC
regulators and these are regulators from the tps65090 PMU but the max77802
is probed before. When the system does not fail, the probe is deferred and
succeed later but I don't know when the system fails (more on that below).
2. In my case booting fails just after disabling unused clocks which is
quite early, my dmesg:
[ 11.700074] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[ 11.704282] s3c-rtc 101e.rtc: setting system clock to 2029-01-11
19:19:17 UTC (1862853557)
[ 11.770602] mmcblk0: mmc0:0001 M8G1WA 7.28 GiB
[ 11.776201] mmcblk0boot0: mmc0:0001 M8G1WA partition 1 2.00 MiB
[ 11.780968] mmcblk0boot1: mmc0:0001 M8G1WA partition 2 2.00 MiB
[ 11.786823] mmcblk0rpmb: mmc0:0001 M8G1WA partition 3 128 KiB
[ 11.793815] mmcblk0: p1 p2 p3 p4
[ 11.824165] PVDD_G3D_1V0: disabling
[ 11.830833] PVDD_G3DS_1V0: disabling
[ 11.837771] PVDD_HSIC_1V8: disabling
[ 11.841172] PVDD_ABB_1V8: disabling
[ 11.844866] PVDD_ANAIP_1V8: disabling
[ 11.847157] usb 5-1.4: new high-speed USB device number 3 using exynos-ehci
[ 11.848778] PVDD
In your case you have a gap here:
[3.624142] platform 12d1.adc: Driver exynos-adc requests probe
deferral
[ 24.188722] random: nonblocking pool is initialized
Could you try my patches once again but this time with enabled:
DEBUG_EXYNOS_UART
EARLY_PRINTK
DEBUG_S3C_UART3
DEBUG_LL
Yes, there is a gap and I don't know why. Even after enabling all those
config options, nothing is printed on the serial console after the exynos-adc
probe deferral. Only that message in drivers/char/random.c is printed but
nothing else is printed after all...
and with following change:
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 4896ae9e23da..316856e55784 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -478,7 +478,9 @@ static void clk_disable_unused_subtree(struct clk *clk)
* sequence. call .disable_unused if available, otherwise fall
* back to .disable
*/
+ pr_err(clk: checking %s\n, clk-name);
if (__clk_is_enabled(clk)) {
+ pr_err(clk: enabled %s, disabling\n, clk-name);
if (clk-ops-disable_unused)
clk-ops-disable_unused(clk-hw);
else if (clk-ops-disable)
Without my patch the boot hangs:
[ 12.230666] clk: checking dout_unipro
[ 12.234304] clk: checking mout_unipro
[ 12.237913] clk: checking sclk_usbd300
[ 12.241638] clk: enabled sclk_usbd300, disabling
[ 12.246264] clk: checking dout_usbd300
[ 12.249992] clk: checking sclk_usbd301
[ 12.253683] clk: enabled sclk_usbd301, disabling
[ 12.258309] clk: checking dout_usbd301
[ 12.262007] clk: checking sclk_maudio0
[ 12.265728] clk: enabled sclk_maudio0, disabling
[ 12.270355] clk: checking pcm_bus
because audss seems to be gated so kernel cannot access status of
pcm_bus clock.
I added those printk's but clk_disable_unused() is executed after the
exynos-adc probe function so the logs are not shown on the serial console.
As mentioned previously in the thread, Tushar's fix [0] works for me and with
that patch I see the clocks disabled by clk_disable_unused_subtree() and the
kernel is able to access pcm_bus and other audio clocks:
[5.007368] clk: checking mout_spdif
[5.010908] clk: checking dout_audio0
[5.014566] clk: checking mout_audio0
[5.018208] clk: checking sclk_maudio0
[5.021926] clk: enabled sclk_maudio0, disabling
[5.026541] clk: checking pcm_bus
[5.029820] clk: enabled pcm_bus, disabling
[5.034001] clk: checking sclk_pcm
[5.037367] clk: enabled sclk_pcm, disabling
Any ideas?
Best regards,
Javier
[0]: http://www.spinics.net/lists/arm-kernel/msg337970.html
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Re: [RFC PATCH] drm/exynos: Add DECON driver
On Tue, Nov 25, 2014 at 6:59 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 22:08, Ajay kumar wrote: Hi Inki, On Tue, Nov 25, 2014 at 6:30 PM, Inki Dae inki@samsung.com wrote: On 2014년 11월 25일 21:17, Ajay kumar wrote: ping. You'd need to clean up clocks and fix up binding file. And then let's have review in more details. I wish that other people also give you their reviews. Nice to hear. Earlier, you mentioned that its good if FIMD driver itself is modified to support Exynos7 DECON. So, what is your take now? 1) Should I add it in FIMD driver itself? We may need to add lot of driver_data for that, since offsets are much different. 2) Or, create two seperate register level files for Exynos5 and Exynos7? 3) Or the current way - Entirely different driver This one, 3), for now because they, Exynos4, Exynos543x and Exynos7, are much different each other. So for next version of your patch, you'd need to change the driver name to exynos7-decon or what you want so that each driver can be entirely separated in SoC name somehow. i.e., - exynos_drm_fimd covers Exynos64xx, Exynos3250, all Exynos4 series and Exynos5250 ~ 5422 SoC. - exynos5-decon covers Exynos5430 and Exynos5433 SoC. Use exynos543x-decon here. - exynos7-decon covers Exynos7 and maybe later SoC. Ok. I will use exynos7-decon. By the way, On which branch of exynos-drm tree should I create this patch? Ajay After that, let's consider how we can integrate these drivers later. Thanks, Inki Dae Anyway, below is my answer. Thanks, Inki Dae On Tue, Nov 11, 2014 at 10:08 PM, Ajay kumar ajayn...@gmail.com wrote: Hi Inki, On Mon, Nov 3, 2014 at 3:31 PM, Inki Dae inki@samsung.com wrote: Hi, Fortunately, I could get the user manual for Exynos7420. Below are my comments. Thanks, Inki Dae On 2014년 10월 23일 01:34, Ajay kumar wrote: On Wed, Oct 22, 2014 at 8:26 PM, Inki Dae inki@samsung.com wrote: Thanks for contribution. It seems reasonable that you separate device drivers into FIMD and DECON because many registers of them have many different offsets and fields. However, there may be a good solution that we can combine common sets of these drivers later. Yes, this is the main reason behind sending this as RFC patch. I want to know what's the best way to do this. FIMD, 5433 DECON and Exynos7 DECON - all are different. Also, in Exynos7 DECON-INT is same as DECON-EXT(Mixer). So, even I am not sure how the driver layouts should be! Please, make sure Exynos SoC name, Exynos7410 or Exynos7420. In my understanding, Exynos7 doesn't mean one real SoC. We shall use Exynos7 as per the discussion. Just for the time being. Ok. Below are my comments. Thanks, Inki Dae On 2014년 10월 10일 21:48, Ajay Kumar wrote: This series is based on exynos-drm-next branch of Inki Dae's tree at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git DECON(Display and Enhancement Controller) is the new IP in exynos7 SOC for generating video signals using pixel data. DECON was used since Exynos5430. And is Exynos5433 different from Exynos7? If so, could I get the Exynos7 user manual (TRM) for review? Yes, Exynos5433 DECON is very much different than Exynos7 DECON. Do not use Exynos7 word and use Exynos7410 or Exynos7420 instead. Again, we shall use Exynos7. I will see how manual can be arranged. DECON driver can be used to drive 2 different interfaces on Exynos7: DECON-INT(video controller) and DECON-EXT(Mixer for HDMI) The existing FIMD driver code was used as a template to create DECON driver. Only DECON-INT is supported as of now, and DECON-EXT support will be added later. Signed-off-by: Akshu Agrawal aksh...@samsung.com Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- .../devicetree/bindings/video/exynos-decon.txt | 68 ++ drivers/gpu/drm/exynos/Kconfig | 11 +- drivers/gpu/drm/exynos/Makefile|1 + drivers/gpu/drm/exynos/exynos_drm_decon.c | 1086 drivers/gpu/drm/exynos/exynos_drm_drv.c| 17 +- drivers/gpu/drm/exynos/exynos_drm_drv.h| 11 + include/video/samsung_decon.h | 346 +++ 7 files changed, 1537 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/video/exynos-decon.txt create mode 100644 drivers/gpu/drm/exynos/exynos_drm_decon.c create mode 100644 include/video/samsung_decon.h diff --git a/Documentation/devicetree/bindings/video/exynos-decon.txt b/Documentation/devicetree/bindings/video/exynos-decon.txt new file mode 100644 index 000..e865650 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the
Re: [RFC 0/2] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
On wto, 2014-11-25 at 14:36 +0100, Javier Martinez Canillas wrote:
Hello Krzysztof,
On 11/25/2014 10:22 AM, Krzysztof Kozlowski wrote:
Hmmm, that's strange. I've looked again at your dmesg and it is little
different than mine (when system fails).
1. Does your PMIC come up? In your dmesg:
[2.687297] max77802-pmic max77802-pmic: regulator init failed for 0
[2.693539] platform max77802-pmic: Driver max77802-pmic requests probe
deferral
The Peach Pit/Pi DTS define the parent input supplies for the max77802 PMIC
regulators and these are regulators from the tps65090 PMU but the max77802
is probed before. When the system does not fail, the probe is deferred and
succeed later but I don't know when the system fails (more on that below).
OK.
2. In my case booting fails just after disabling unused clocks which is
quite early, my dmesg:
[ 11.700074] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[ 11.704282] s3c-rtc 101e.rtc: setting system clock to 2029-01-11
19:19:17 UTC (1862853557)
[ 11.770602] mmcblk0: mmc0:0001 M8G1WA 7.28 GiB
[ 11.776201] mmcblk0boot0: mmc0:0001 M8G1WA partition 1 2.00 MiB
[ 11.780968] mmcblk0boot1: mmc0:0001 M8G1WA partition 2 2.00 MiB
[ 11.786823] mmcblk0rpmb: mmc0:0001 M8G1WA partition 3 128 KiB
[ 11.793815] mmcblk0: p1 p2 p3 p4
[ 11.824165] PVDD_G3D_1V0: disabling
[ 11.830833] PVDD_G3DS_1V0: disabling
[ 11.837771] PVDD_HSIC_1V8: disabling
[ 11.841172] PVDD_ABB_1V8: disabling
[ 11.844866] PVDD_ANAIP_1V8: disabling
[ 11.847157] usb 5-1.4: new high-speed USB device number 3 using
exynos-ehci
[ 11.848778] PVDD
In your case you have a gap here:
[3.624142] platform 12d1.adc: Driver exynos-adc requests probe
deferral
[ 24.188722] random: nonblocking pool is initialized
Could you try my patches once again but this time with enabled:
DEBUG_EXYNOS_UART
EARLY_PRINTK
DEBUG_S3C_UART3
DEBUG_LL
Yes, there is a gap and I don't know why. Even after enabling all those
config options, nothing is printed on the serial console after the exynos-adc
probe deferral. Only that message in drivers/char/random.c is printed but
nothing else is printed after all...
You may try attached patch (very early printk) if you suspect that some
logs are missing.
and with following change:
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 4896ae9e23da..316856e55784 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -478,7 +478,9 @@ static void clk_disable_unused_subtree(struct clk *clk)
* sequence. call .disable_unused if available, otherwise fall
* back to .disable
*/
+ pr_err(clk: checking %s\n, clk-name);
if (__clk_is_enabled(clk)) {
+ pr_err(clk: enabled %s, disabling\n, clk-name);
if (clk-ops-disable_unused)
clk-ops-disable_unused(clk-hw);
else if (clk-ops-disable)
Without my patch the boot hangs:
[ 12.230666] clk: checking dout_unipro
[ 12.234304] clk: checking mout_unipro
[ 12.237913] clk: checking sclk_usbd300
[ 12.241638] clk: enabled sclk_usbd300, disabling
[ 12.246264] clk: checking dout_usbd300
[ 12.249992] clk: checking sclk_usbd301
[ 12.253683] clk: enabled sclk_usbd301, disabling
[ 12.258309] clk: checking dout_usbd301
[ 12.262007] clk: checking sclk_maudio0
[ 12.265728] clk: enabled sclk_maudio0, disabling
[ 12.270355] clk: checking pcm_bus
because audss seems to be gated so kernel cannot access status of
pcm_bus clock.
I added those printk's but clk_disable_unused() is executed after the
exynos-adc probe function so the logs are not shown on the serial console.
So this would mean that something fails before clk_disable_unused().
As mentioned previously in the thread, Tushar's fix [0] works for me and with
that patch I see the clocks disabled by clk_disable_unused_subtree() and the
kernel is able to access pcm_bus and other audio clocks:
[5.007368] clk: checking mout_spdif
[5.010908] clk: checking dout_audio0
[5.014566] clk: checking mout_audio0
[5.018208] clk: checking sclk_maudio0
[5.021926] clk: enabled sclk_maudio0, disabling
[5.026541] clk: checking pcm_bus
[5.029820] clk: enabled pcm_bus, disabling
[5.034001] clk: checking sclk_pcm
[5.037367] clk: enabled sclk_pcm, disabling
Any ideas?
Yes, I got. On Peach board the i2s0 is enabled in DTS. Probing it could
fail because it relies on enabling audss clocks (which cannot be
accessed).
I reproduced another hang on Arndale Octa after enabling i2s0 in DTS.
Maybe that is the cause also on Peach.
Best regards,
Krzysztof
From def8df7c5d8098ec1656c075701e9ba17f0617c9 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski k.kozlow...@samsung.com
Date: Thu, 6 Nov 2014 12:58:07 +0100
Subject: [PATCH] Very early printk, for
Re: [RFC 0/2] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
Hello Krzysztof, On 11/25/2014 03:22 PM, Krzysztof Kozlowski wrote: Any ideas? Yes, I got. On Peach board the i2s0 is enabled in DTS. Probing it could fail because it relies on enabling audss clocks (which cannot be accessed). I reproduced another hang on Arndale Octa after enabling i2s0 in DTS. Maybe that is the cause also on Peach. You are correct, if I disable i2s0 then I see the logs from clk_disable_unused_subtree() and boot hangs when accessing the adma clock: clk: checking dout_fimd1 clk: checking mout_fimd1_final clk: checking mout_fimd1 clk: checking mout_sclk_rpll clk: checking fout_rpll clk: checking adma With i2s0 disabled, your series are indeed enough to make it boot again but as you said enabling i2s0 in the DTS makes it hang even with your patches. Thanks a lot for digging into this! Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] media: exynos-gsc: fix build warning
Em Tue, 18 Nov 2014 10:57:48 +
Lad, Prabhakar prabhakar.cse...@gmail.com escreveu:
this patch fixes following build warning:
gsc-core.c:350:17: warning: 'low_plane' may be used uninitialized
gsc-core.c:371:31: warning: 'high_plane' may be used uninitialized
Signed-off-by: Lad, Prabhakar prabhakar.cse...@gmail.com
---
drivers/media/platform/exynos-gsc/gsc-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/exynos-gsc/gsc-core.c
b/drivers/media/platform/exynos-gsc/gsc-core.c
index 91d226b..6c71b17 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.c
+++ b/drivers/media/platform/exynos-gsc/gsc-core.c
@@ -347,8 +347,8 @@ void gsc_set_prefbuf(struct gsc_dev *gsc, struct
gsc_frame *frm)
s_chk_addr = frm-addr.cb;
s_chk_len = frm-payload[1];
} else if (frm-fmt-num_planes == 3) {
- u32 low_addr, low_plane, mid_addr, mid_plane;
- u32 high_addr, high_plane;
+ u32 low_addr, low_plane = 0, mid_addr, mid_plane;
+ u32 high_addr, high_plane = 0;
u32 t_min, t_max;
t_min = min3(frm-addr.y, frm-addr.cb, frm-addr.cr);
Actually, this just hides the error, without fixing.
If the address is not found, a real error occurs, and the address
is also invalid.
So, I think that the enclosed patch will be doing a better job fixing it.
Still, the entire code seems mostly useless on my eyes, as this function
seems to be used only for debugging purposes, and errors there aren't
actually handled properly.
[PATCH] [media] exynos-gsc: fix build warning
Fixes following build warnings:
gsc-core.c:350:17: warning: 'low_plane' may be used uninitialized
gsc-core.c:371:31: warning: 'high_plane' may be used uninitialized
Reported-by: Prabhakar Lad prabhakar.cse...@gmail.com
Signed-off-by: Mauro Carvalho Chehab mche...@osg.samsung.com
diff --git a/drivers/media/platform/exynos-gsc/gsc-core.c
b/drivers/media/platform/exynos-gsc/gsc-core.c
index 91d226b8fe5c..3062e9fac6da 100644
--- a/drivers/media/platform/exynos-gsc/gsc-core.c
+++ b/drivers/media/platform/exynos-gsc/gsc-core.c
@@ -319,21 +319,22 @@ int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f)
return 0;
}
-static u32 get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index)
+static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32
*ret_addr)
{
if (frm-addr.y == addr) {
*index = 0;
- return frm-addr.y;
+ *ret_addr = frm-addr.y;
} else if (frm-addr.cb == addr) {
*index = 1;
- return frm-addr.cb;
+ *ret_addr = frm-addr.cb;
} else if (frm-addr.cr == addr) {
*index = 2;
- return frm-addr.cr;
+ *ret_addr = frm-addr.cr;
} else {
pr_err(Plane address is wrong);
return -EINVAL;
}
+ return 0;
}
void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
@@ -352,9 +353,11 @@ void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame
*frm)
u32 t_min, t_max;
t_min = min3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- low_addr = get_plane_info(frm, t_min, low_plane);
+ if (get_plane_info(frm, t_min, low_plane, low_addr))
+ return;
t_max = max3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- high_addr = get_plane_info(frm, t_max, high_plane);
+ if (get_plane_info(frm, t_max, high_plane, high_addr))
+ return;
mid_plane = 3 - (low_plane + high_plane);
if (mid_plane == 0)
--
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Re: [RFC 0/2] Fix Arndale Octa/Peach Pi boot on Audio subsystem clocks
Hello Krzysztof, On 11/25/2014 03:54 PM, Krzysztof Kozlowski wrote: My patch only fixed the gate clocks but it didn't touched div and mux. I'll prepare a v2 of it (I got some feedback) which I hope will fix both cases: i2s and disabling unused clocks. Perfect, I will gladly test on Peach boards once you post it. Thanks a lot for your help. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] media: exynos-gsc: fix build warning
Hi,
On Tue, Nov 25, 2014 at 3:18 PM, Prabhakar Lad
prabhakar.cse...@gmail.com wrote:
Hi Mauro,
On Tue, Nov 25, 2014 at 3:04 PM, Mauro Carvalho Chehab
mche...@osg.samsung.com wrote:
Em Tue, 18 Nov 2014 10:57:48 +
[Snip]
-static u32 get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index)
+static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32
*ret_addr)
{
if (frm-addr.y == addr) {
*index = 0;
- return frm-addr.y;
+ *ret_addr = frm-addr.y;
} else if (frm-addr.cb == addr) {
*index = 1;
- return frm-addr.cb;
+ *ret_addr = frm-addr.cb;
} else if (frm-addr.cr == addr) {
*index = 2;
- return frm-addr.cr;
+ *ret_addr = frm-addr.cr;
} else {
pr_err(Plane address is wrong);
return -EINVAL;
}
+ return 0;
the control wont reach here! may be you can remove the complete else
part outside ?
Ah my bad :(, I missread 'ret_addr' to return.
Thanks,
--Prabhakar Lad
with that change,
Reported-by: Lad, Prabhakar prabhakar.cse...@gmail.com
Acked-by: Lad, Prabhakar prabhakar.cse...@gmail.com
Thanks,
--Prabhakar Lad
}
void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
@@ -352,9 +353,11 @@ void gsc_set_prefbuf(struct gsc_dev *gsc, struct
gsc_frame *frm)
u32 t_min, t_max;
t_min = min3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- low_addr = get_plane_info(frm, t_min, low_plane);
+ if (get_plane_info(frm, t_min, low_plane, low_addr))
+ return;
t_max = max3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- high_addr = get_plane_info(frm, t_max, high_plane);
+ if (get_plane_info(frm, t_max, high_plane, high_addr))
+ return;
mid_plane = 3 - (low_plane + high_plane);
if (mid_plane == 0)
--
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Re: [PATCH] media: exynos-gsc: fix build warning
Hi Mauro,
On Tue, Nov 25, 2014 at 3:04 PM, Mauro Carvalho Chehab
mche...@osg.samsung.com wrote:
Em Tue, 18 Nov 2014 10:57:48 +
[Snip]
-static u32 get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index)
+static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32
*ret_addr)
{
if (frm-addr.y == addr) {
*index = 0;
- return frm-addr.y;
+ *ret_addr = frm-addr.y;
} else if (frm-addr.cb == addr) {
*index = 1;
- return frm-addr.cb;
+ *ret_addr = frm-addr.cb;
} else if (frm-addr.cr == addr) {
*index = 2;
- return frm-addr.cr;
+ *ret_addr = frm-addr.cr;
} else {
pr_err(Plane address is wrong);
return -EINVAL;
}
+ return 0;
the control wont reach here! may be you can remove the complete else
part outside ?
with that change,
Reported-by: Lad, Prabhakar prabhakar.cse...@gmail.com
Acked-by: Lad, Prabhakar prabhakar.cse...@gmail.com
Thanks,
--Prabhakar Lad
}
void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
@@ -352,9 +353,11 @@ void gsc_set_prefbuf(struct gsc_dev *gsc, struct
gsc_frame *frm)
u32 t_min, t_max;
t_min = min3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- low_addr = get_plane_info(frm, t_min, low_plane);
+ if (get_plane_info(frm, t_min, low_plane, low_addr))
+ return;
t_max = max3(frm-addr.y, frm-addr.cb, frm-addr.cr);
- high_addr = get_plane_info(frm, t_max, high_plane);
+ if (get_plane_info(frm, t_max, high_plane, high_addr))
+ return;
mid_plane = 3 - (low_plane + high_plane);
if (mid_plane == 0)
--
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[PATCH] drm/exynos/fimd: only finish pageflip if START == START_S
From: Daniel Kurtz djku...@chromium.org
A framebuffer gets committed to FIMD's default window like this:
exynos_drm_crtc_update()
exynos_plane_commit()
fimd_win_commit()
fimd_win_commit() programs BUF_START[0]. At each vblank, FIMD hardware
copies the value from BUF_START to BUF_START_S (BUF_START's shadow
register), starts scanning out from BUF_START_S, and asserts its irq.
This irq is handled by fimd_irq_handler(), which calls
exynos_drm_crtc_finish_pageflip() to free the old buffer that FIMD just
finished scanning out, and potentially commit the next pending flip.
There is a race, however, if fimd_win_commit() programs BUF_START(0)
between the actual vblank irq, and its corresponding fimd_irq_handler().
= FIMD vblank: BUF_START_S[0] := BUF_START[0], and irq asserted
| = fimd_win_commit(0) writes new BUF_START[0]
|exynos_drm_crtc_try_do_flip() marks exynos_fb as prepared
= fimd_irq_handler()
exynos_drm_crtc_finish_pageflip() sees prepared exynos_fb,
and unmaps old fb
== but, since BUF_START_S[0] still points to that old fb...
== FIMD iommu fault
This patch ensures that fimd_irq_handler() only calls
exynos_drm_crtc_finish_pageflip() if any previously scheduled flip
has really completed.
This works because exynos_drm_crtc's flip fifo ensures that
fimd_win_commit() is never called more than once per
exynos_drm_crtc_finish_pageflip().
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Sean Paul seanp...@chromium.org
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 ++
include/video/samsung_fimd.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index e5810d1..afb0586 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -55,6 +55,7 @@
#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
+#define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
#define VIDWx_BUF_END(win, buf)(VIDW_BUF_END(buf) + (win) * 8)
#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
@@ -1039,6 +1040,7 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
{
struct fimd_context *ctx = (struct fimd_context *)dev_id;
u32 val, clear_bit;
+ u32 start, start_s;
val = readl(ctx-regs + VIDINTCON1);
@@ -1066,6 +1068,30 @@ static irqreturn_t fimd_irq_handler(int irq, void
*dev_id)
}
}
+ /*
+* Ensure finish_pageflip is called iff a pending flip has completed.
+* This works around a race between a page_flip request and the latency
+* between vblank interrupt and this irq_handler:
+* = FIMD vblank: BUF_START_S[0] := BUF_START[0], and asserts irq
+* | = fimd_win_commit(0) writes new BUF_START[0]
+* |exynos_drm_crtc_try_do_flip() marks exynos_fb as prepared
+* = fimd_irq_handler()
+* exynos_drm_crtc_finish_pageflip() sees prepared exynos_fb,
+* and unmaps old fb
+* == but, since BUF_START_S[0] still points to that old fb...
+* == FIMD iommu fault
+*/
+ start = readl(ctx-regs + VIDWx_BUF_START(0, 0));
+ start_s = readl(ctx-regs + VIDWx_BUF_START_S(0, 0));
+ if (start == start_s)
+ exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
+
+ /* set wait vsync event to zero and wake up queue. */
+ if (atomic_read(ctx-wait_vsync_event)) {
+ atomic_set(ctx-wait_vsync_event, 0);
+ wake_up(ctx-wait_vsync_queue);
+ }
+
out:
return IRQ_HANDLED;
}
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index a20e4a3..f81d081 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -291,6 +291,7 @@
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START_S(_buff) (0x40A0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff)(0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
--
1.9.3
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Re: [PATCH v12 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Thomas,
On Mon, Nov 24, 2014 at 10:58 AM, Kevin Hilman khil...@kernel.org wrote:
[...]
Second, as with earlier versions of this series, I'm still seeing lots
of wait_until_divider_stable: timeout in divider stablization messages
coming out when running powertop.
I found a simpler way to reproduce these messages. If I simply use
the userspace governor and cycle through all the A7 OPPs, I'll hit
this message (script below[1]). Note that I'm also using my DTS
change that fixes the vdd_arm and vdd_kfc voltages to a voltage that
is high enough for all the OPPs.
Kevin
[1]
#!/bin/sh
cpu=cpu4
reg_name=vdd_kfc
cpu_reg=$(dirname `find /sys/class/regulator/regulator.*/ -name name
-exec grep -l $reg_name {} \;`)
echo $cpu_reg
# Cycle through frequencies (and check voltage)
cd /sys/devices/system/cpu/$cpu/cpufreq
echo userspace scaling_governor
for freq in `cat scaling_available_frequencies`; do
echo ${freq} scaling_setspeed
echo -n current freq:
cat scaling_cur_freq
echo -n current voltage:
cat ${cpu_reg}/microvolts
sleep 1
done
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Re: [PATCH] ARM: exynos_defconfig: disable CONFIG_EXYNOS5420_MCPM; not stable
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test it...I'll try to make a test
farm like you guys...
Do you have some colleagues with any other 542x hardware? I had
assumed that linux-next was being better tested on the publicaly
available, and widely available boards like odroid-xu3 and
Chromebook2, but I've come to realize the hard way that that is not
Are you seeing this on Chromebook2 (Peach-Pi 5800) too ?
No, it seems that my exynos5800-peach-pi is not having this problem,
which suggests it's a bootloader setup issue.
the case. You mention your board has a different bootloader. Do you
suspect there's a bootloader issue on these other platforms? If so,
could you elaborate on possible fixes? I'm more than willing to test
any proposed fixes, but I'm not familiar enough yet with these SoCs to
figure out the underlying issues alone.
Until you have a working board farm, you could start having a closer
look at the boot logs we're already producing. Admittedly linux-next
broken in many ways besides this one for exynos currently, but it has
been having these imprecise aborts well before the other recent
issues.
Also, It's very possible that this issue is not even MCPM related at
all, and MCPM is just uncovering a previously hidden bug. It would be
very helpful if people more familiar with this hardware and SoC would
investigate bug reports like these.
The 3 boards I have access to (SMDK5420, Chromebook Peach-Pi and
Chromebook Peach-Pit) work fine with MCPM enabled.
Thanks for helping look into this.
I am not sure why
it is failing only on the above mentioned boards as there is nothing
specific to them in the MCPM back-end.
I assume that when you default to platsmp (on disabling MCPM), the
non-working boards boot all cores upto userspace without any issues ?
Nope. With MCPM disabled:
- 5420/arndale-octa: CPU0-3 come up (A15s)
- 5422/odroid-xu3: only CPU0 (A7)
- 5800/peach-pi: only CPU0 (A15)
Note that with MCPM enabled, the arndale-octa gets the same result.
Peach-pi on the other hand gets all 8 CPUs, and the odroid-xu3 only gets
6/8 CPUs (see other thread on that topic.)
Based on the timeline (problems started about 2.5 months back), there
have only been a couple of changes in the 5420 MCPM back-end. Could
you revert the following commits and check if things improve.
20fe6f9 ARM: EXYNOS: Support cluster power off on exynos5420/5800
fbb0499 ARM: 8083/1: exynos: activate the CCI on boot CPU/cluster
using the MCPM loopback
These might not revert cleanly, so instead of the above you could also
comment the following 2 lines:
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c
b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764..9a07188 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -152,7 +152,7 @@ static void exynos_power_down(void)
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster)) {
- exynos_cluster_power_down(cluster);
+ //exynos_cluster_power_down(cluster);
last_man = true;
}
2 } else if (cpu_use_count[cpu][cluster] == 1) {
@@ -356,8 +356,8 @@ static int __init exynos_mcpm_init(void)
ret = mcpm_platform_register(exynos_power_ops);
if (!ret)
ret = mcpm_sync_init(exynos_pm_power_up_setup);
- if (!ret)
- ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
+ //if (!ret)
+ //ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
if (ret) {
iounmap(ns_sram_base_addr);
return ret;
If you still get aborts then I suspect that the problem is with the
bootloader configuration but am not sure.
Nice. With those lines commented out, the arndale-octa is not geting
imprecise aborts anymore, and this is the platform where those aborts
seem to prevent booting into a full userspace (as originally reported by
Tyler.)
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts go away.
The odroid-xu3 is still getting them, but these seem to happen whether
or not MCPM is enabled, so must a different issue related to the
bootloader setup.
I am OK with disabling
5420_MCPM in the default configuration in such a case. This would
however mean that S2R also stops working by default on 5420.
Disabling the option isn't my first choice either, I would rather see
this issue debugged and fixed by folks that are more familiar with MCPM
on Exynos.
Kevin
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Re: [PATCH v2 1/2] Input: add regulator haptic driver
Hi Jaewon,
On Monday 24 November 2014 08:20 PM, Jaewon Kim wrote:
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/input/regulator-haptic.txt | 24 ++
drivers/input/misc/Kconfig | 11 +
drivers/input/misc/Makefile|1 +
drivers/input/misc/regulator-haptic.c | 247
include/linux/input/regulator-haptic.h | 30 +++
5 files changed, 313 insertions(+)
create mode 100644
Documentation/devicetree/bindings/input/regulator-haptic.txt
create mode 100644 drivers/input/misc/regulator-haptic.c
create mode 100644 include/linux/input/regulator-haptic.h
diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt
b/Documentation/devicetree/bindings/input/regulator-haptic.txt
new file mode 100644
index 000..5a44e8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/regulator-haptic.txt
@@ -0,0 +1,24 @@
+* Requlator Haptic Device Tree Bindings
Nit: %s/Requlator/Regulator
+
+The regulator haptic driver controlled by voltage of regulator.
+This driver implemented via Force Feedback interface.
+
[Snip]
diff --git a/include/linux/input/regulator-haptic.h
b/include/linux/input/regulator-haptic.h
new file mode 100644
index 000..15a629c
--- /dev/null
+++ b/include/linux/input/regulator-haptic.h
@@ -0,0 +1,30 @@
+/*
+ * Regulator Haptic Platform Data
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Jaewon Kim jaewon02@samsung.com
+ * Author: Hyunhee Kim hyunhee@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _REGULATOR_HAPTIC_H
+
Please define _REGULATOR_HAPTIC_H here as:
#define _REGULATOR_HAPTIC_H
+/*
+ * struct regulator_haptic_data - Platform device data
+ *
+ * @regulator: Power supply to the haptic motor
+ * @max_volt: maximum voltage value supplied to the haptic motor.
+ * The unit of the voltage is a micro
+ * @min_volt: minimum voltage value supplied to the haptic motor.
+ * The unit of the voltage is a micro
+ */
+struct regulator_haptic_data {
+ struct regulator *regulator;
+ unsigned int max_volt;
+ unsigned int min_volt;
+};
+
+#endif /* _REGULATOR_HAPTIC_H */
With these two minor fixes please feel free to add:
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
Thanks,
Pankaj Dubey
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RE: [PATCH v2 0/3] Some cleanup for samsung clock
Hi Sylwester, On Thursday, October 23, 2014 10:58 PM, Sylwester Nawrocki Wrote: To: Pankaj Dubey; linux-arm-ker...@lists.infradead.org; linux-samsung- s...@vger.kernel.org; tomasz.f...@gmail.com Cc: kgene@samsung.com; mturque...@linaro.org; naus...@samsung.com Subject: Re: [PATCH v2 0/3] Some cleanup for samsung clock Hi Pankaj, On 22/10/14 12:34, Pankaj Dubey wrote: It there are no comments will you please pick up this patch series. I've picked up these patches and I'm planning to send a pull request to Mike this week, including any other pending samsung clk patches. Tomasz is going to be busy for few days. Any update on this series? Thanks, Pankaj Dubey -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/19] usb: common: drd-lib: Add DRD lib for USB.
On Tue, Nov 25, 2014 at 06:41:37PM +0530, George Cherian wrote:
Add USB DRD library. This Library facilitates to
switch roles between HOST and Device modes.
A DRD should be added to the library using usb_drd_add().
Register the HOST and UDC using usb_drd_register_hcd/udc().
Un-Register the HOST and UDC using usb_drd_unregister_hcd/udc().
Depending on the state of IP -
Call the following to start/stop HOST controller
usb_drd_start/stop_hcd().
This internally calls usb_add/remove_hcd() or IP specific low level start/stop
defined in ll_start/stop
Call the following to start/stop UDC
usb_drd_start/stop_udc().
This internally calls udc_start/udc_stop() or IP specific low level start/stop
defined in ll_start/stop
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/Kconfig | 15 ++
drivers/usb/common/Makefile | 1 +
drivers/usb/common/drd-lib.c | 346
+++
include/linux/usb/drd.h | 77 ++
4 files changed, 439 insertions(+)
create mode 100644 drivers/usb/common/drd-lib.c
create mode 100644 include/linux/usb/drd.h
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index ae481c3..ea0d944 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -34,6 +34,21 @@ config USB_COMMON
default y
depends on USB || USB_GADGET
+config DRD_LIB
+ tristate DRD Library support
+ default y
+ depends on USB USB_GADGET
+ ---help---
+ This option adds DRD Library support for Universal Serial Bus (USB).
+ DRD Library faciliatets the Role switching by HOST and DEVICE roles,
+ If your hardware has a Dual Role Device.
+
+ The DRD Library uses USB core API's to start/stop HOST controllers,
+ UDC API's to start/stop DEVICE controllers, ther by enabling to
+ switch roles between HOST and Device modes.
%s/ther by/thereby
+
+ Say N if unsure.
+
config USB_ARCH_HAS_HCD
def_bool y
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index ca2f8bd..e2c1593 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -7,3 +7,4 @@ usb-common-y+= common.o
usb-common-$(CONFIG_USB_LED_TRIG) += led.o
obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+obj-$(CONFIG_DRD_LIB) += drd-lib.o
diff --git a/drivers/usb/common/drd-lib.c b/drivers/usb/common/drd-lib.c
new file mode 100644
index 000..6159436
--- /dev/null
+++ b/drivers/usb/common/drd-lib.c
@@ -0,0 +1,346 @@
+/**
+ * drd-lib.c - USB DRD library functions
+ *
+ * Copyright (C) 2014 Texas Instruments
+ * Author: George Cherian george.cher...@ti.com
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/device.h
+#include linux/err.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/usb.h
+
+#include linux/usb/hcd.h
+#include linux/usb/gadget.h
+#include linux/usb/drd.h
+
+/**
+ * struct usb_drd - describes one dual role device
+ * @host - the HOST controller device of this drd
+ * @gadget - the gadget of drd
+ * @parent - the device to the actual controller
+ * @list - for use by the drd lib
+ * @state - specifies the current state
+ *
+ * This represents the internal data structure which is used by the UDC-class
+ * to hold information about udc driver and gadget together.
+ */
It is dual role struct, why you only talk about device?
+struct usb_drd {
+ struct usb_drd_host *host;
+ struct usb_drd_gadget *gadget;
+ struct device *parent;
+ struct list_headlist;
+ unsigned intstate;
+};
+
+static LIST_HEAD(drd_list);
+static DEFINE_SPINLOCK(drd_lock);
+
+static struct usb_drd *usb_drd_get_dev(struct device *parent)
+{
+ struct usb_drd *drd;
+
+ spin_lock(drd_lock);
+ list_for_each_entry(drd, drd_list, list)
+ if (drd-parent == parent)
+ goto out;
+ drd = NULL;
+out:
+ spin_unlock(drd_lock);
+
+ return drd;
+}
+
+int usb_drd_get_state(struct device *parent)
+{
+ struct usb_drd *drd;
+
+ drd = usb_drd_get_dev(parent);
+ if (!drd)
+ return -ENODEV;
+
+ return drd-state;
+}
+EXPORT_SYMBOL_GPL(usb_drd_get_state);
+
+int usb_drd_release(struct device *parent)
+{
+
Re: [PATCH] ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
Hi Bartilomiej,
On Tuesday 08 July 2014 05:33 PM, Bartlomiej Zolnierkiewicz wrote:
Values stored in val[] are never bigger than a byte.
textdata bss dec hex filename
5264 4 452721498 arch/arm/mach-exynos/pmu.o.before
2992 4 43000 bb8 arch/arm/mach-exynos/pmu.o.after
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
I tested this patch and it's really helpful to reduce size.
How about resubmitting this change? As this will not get applied on
current tree.
Thanks,
Pankaj Dubey
---
arch/arm/mach-exynos/common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index b850db4..55ff019 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -101,7 +101,7 @@ enum sys_powerdown {
struct exynos_pmu_conf {
void __iomem *reg;
- unsigned int val[NUM_SYS_POWERDOWN];
+ u8 val[NUM_SYS_POWERDOWN];
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
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