Re: [RFC 1/3] devfreq: dt-bindings: Document Exynos3250 devfreq driver
On pią, 2014-12-05 at 16:53 +, Mark Rutland wrote:
On Fri, Dec 05, 2014 at 04:46:26PM +, Krzysztof Kozlowski wrote:
Add documentation for bindings used by Exynos3250 devfreq driver.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
.../bindings/arm/samsung/exynos3250-devfreq.txt| 66
++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
diff --git
a/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
new file mode 100644
index ..047955e9e371
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
@@ -0,0 +1,66 @@
+Samsung Exynos3250 devfreq driver
The binding should describe the hardware, not a particular driver of
that hardware. Please write the binding (and its documentation) with
that in mind, and drop references to the driver and busfreq.
With an adequate binding we can probe the device and forward the
information to relevant driver(s) as necessary.
OK
+=
+
+The driver support changing frequencies and voltage for:
+ - memory controller and bus,
+ - peripheral buses (left and right).
What do left and right mean in this context?
These are names for clock domains associated with buses between memory
controller and peripherals. They're called leftbus and rightbus in
documentation.
+
+Memory controller and bus
+=
+Required properties:
+ - compatible : should be samsung,exynos3250-busfreq-mif
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : one clock of name dmc to manage frequency
+ - clocks : phandle and specifier for clock listed in clock-names property
+ - vdd_mif-supply : phandle to MIF voltage regulator
s/_/-/ in property names please.
Sure.
+
+Peripheral buses
+
+Required properties:
+ - compatible : should be samsung,exynos3250-busfreq-int
What does int mean here?
It is the name of power source (VDD_INT) and regulator supplying certain
power domains in SoC. However I have no clue what engineers meant by
this abbreviation.
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : names for PPMU clocks and bus clocks to manage
frequencies;
+ All following clock names (and corresponding phandles) must be
+ provided:
+ - ppmu_left, ppmu_right,
+ - aclk_400, aclk_266, aclk_200, aclk_160, aclk_gdl,
aclk_gdr, mfc;
+ - clocks : phandles and specifiers for clocks listed in clock-names
property
+ - vdd_mif-supply : phandle to INT voltage regulator
s/_/-/ here too.
OK
Thanks for feedback.
Best regards,
Krzysztof
Thanks,
Mark.
+
+Example
+===
+ busfreq_mif: busfreq@106A {
+ compatible = samsung,exynos3250-busfreq-mif;
+ reg = 0x106A 0x2000, 0x106B 0x2000;
+ clocks = cmu_dmc CLK_DIV_DMC;
+ clock-names = dmc;
+ vdd_mif-supply = buck1_reg;
+ status = okay;
+ };
+
+ busfreq_int: busfreq@116A {
+ compatible = samsung,exynos3250-busfreq-int;
+ reg = 0x116A 0x2000, 0x112A 0x2000;
+ clocks = cmu CLK_PPMULEFT,
+ cmu CLK_PPMURIGHT,
+ cmu CLK_DIV_ACLK_400_MCUISP,
+ cmu CLK_DIV_ACLK_266,
+ cmu CLK_DIV_ACLK_200,
+ cmu CLK_DIV_ACLK_160,
+ cmu CLK_DIV_GDL,
+ cmu CLK_DIV_GDR,
+ cmu CLK_DIV_MFC;
+ clock-names = ppmuleft,
+ ppmuright,
+ aclk_400,
+ aclk_266,
+ aclk_200,
+ aclk_160,
+ aclk_gdl,
+ aclk_gdr,
+ mfc;
+ vdd_int-supply = buck3_reg;
+ status = okay;
+ };
--
1.9.1
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Re: [PATCH 1/20] mtd: s3c2410: fix misspelling of current function in string
Am 08.12.2014 um 08:11 schrieb Julia Lawall: diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 35aef5e..0a9c41f 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -948,7 +948,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev) cpu_type = platform_get_device_id(pdev)-driver_data; - pr_debug(s3c2410_nand_probe(%p)\n, pdev); + pr_debug(%s(%p)\n, __func__, pdev); I think we can drop the line completely. We have ftrace to trace function calls... Should the initialised ok at the end of the function be remove as well? Will it be confusing if this cleanup is done in this function, but not in others where it may be useful? Perhaps s3c2410_nand_update_chip, for example? Hmm, this driver seems to have a lot of debugging printks(). IMHO we can remove them. Let's see what Brain says. Thanks, //richard -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 1/3] devfreq: dt-bindings: Document Exynos3250 devfreq driver
On pon, 2014-12-08 at 05:06 +, MyungJoo Ham wrote:
Add documentation for bindings used by Exynos3250 devfreq driver.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
.../bindings/arm/samsung/exynos3250-devfreq.txt| 66
++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
diff --git
a/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
new file mode 100644
index ..047955e9e371
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos3250-devfreq.txt
@@ -0,0 +1,66 @@
+Samsung Exynos3250 devfreq driver
+=
+
+The driver support changing frequencies and voltage for:
+ - memory controller and bus,
+ - peripheral buses (left and right).
+
+Memory controller and bus
+=
+Required properties:
+ - compatible : should be samsung,exynos3250-busfreq-mif
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : one clock of name dmc to manage frequency
+ - clocks : phandle and specifier for clock listed in clock-names property
+ - vdd_mif-supply : phandle to MIF voltage regulator
+
+Peripheral buses
+
+Required properties:
+ - compatible : should be samsung,exynos3250-busfreq-int
+ - reg : two sets (offset and length of the register) for PPMU registers
+ used by this devfreq driver
+ - clock-names : names for PPMU clocks and bus clocks to manage
frequencies;
+ All following clock names (and corresponding phandles) must be
+ provided:
+ - ppmu_left, ppmu_right,
+ - aclk_400, aclk_266, aclk_200, aclk_160, aclk_gdl,
aclk_gdr, mfc;
+ - clocks : phandles and specifiers for clocks listed in clock-names
property
+ - vdd_mif-supply : phandle to INT voltage regulator
+
+Example
+===
+ busfreq_mif: busfreq@106A {
+ compatible = samsung,exynos3250-busfreq-mif;
+ reg = 0x106A 0x2000, 0x106B 0x2000;
+ clocks = cmu_dmc CLK_DIV_DMC;
+ clock-names = dmc;
+ vdd_mif-supply = buck1_reg;
+ status = okay;
+ };
The hardware you are binding hereby is Exynos PPMU.
You may consider to bind PPMU (DMC PPMU or BUS PPMU whichever hardware
you want to use) with DT and then let exynos bus devfreq driver use
the already-bound devices if found, ... in principle.
In other words or point of view, you may implement PPMU driver in
devfreq class device driver so that you let it bind PPMU device with DT.
It may be done similarly with the device below.
Yes, you're right. I saw also similar case for Tegra Activity Monitor.
Thanks for pointing this,
Krzysztof
Cheers,
MyungJoo.
+
+ busfreq_int: busfreq@116A {
+ compatible = samsung,exynos3250-busfreq-int;
+ reg = 0x116A 0x2000, 0x112A 0x2000;
+ clocks = cmu CLK_PPMULEFT,
+ cmu CLK_PPMURIGHT,
+ cmu CLK_DIV_ACLK_400_MCUISP,
+ cmu CLK_DIV_ACLK_266,
+ cmu CLK_DIV_ACLK_200,
+ cmu CLK_DIV_ACLK_160,
+ cmu CLK_DIV_GDL,
+ cmu CLK_DIV_GDR,
+ cmu CLK_DIV_MFC;
+ clock-names = ppmuleft,
+ ppmuright,
+ aclk_400,
+ aclk_266,
+ aclk_200,
+ aclk_160,
+ aclk_gdl,
+ aclk_gdr,
+ mfc;
+ vdd_int-supply = buck3_reg;
+ status = okay;
+ };
--
1.9.1
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Re: [PATCH V8 03/14] drm/bridge: make bridge registration independent of drm flow
On Tue, Dec 2, 2014 at 11:31 AM, Ajay kumar ajayn...@gmail.com wrote:
On Sat, Nov 15, 2014 at 3:24 PM, Ajay Kumar ajaykumar...@samsung.com wrote:
Currently, third party bridge drivers(ptn3460) are dependent
on the corresponding encoder driver init, since bridge driver
needs a drm_device pointer to finish drm initializations.
The encoder driver passes the drm_device pointer to the
bridge driver. Because of this dependency, third party drivers
like ptn3460 doesn't adhere to the driver model.
In this patch, we reframe the bridge registration framework
so that bridge initialization is split into 2 steps, and
bridge registration happens independent of drm flow:
--Step 1: gather all the bridge settings independent of drm and
add the bridge onto a global list of bridges.
--Step 2: when the encoder driver is probed, call drm_bridge_attach
for the corresponding bridge so that the bridge receives
drm_device pointer and continues with connector and other
drm initializations.
The old set of bridge helpers are removed, and a set of new helpers
are added to accomplish the 2 step initialization.
The bridge devices register themselves onto global list of bridges
when they get probed by calling drm_bridge_add.
The parent encoder driver waits till the bridge is available
in the lookup table(by calling of_drm_find_bridge) and then
continues with its initialization.
The encoder driver should also call drm_bridge_attach to pass
on the drm_device to the bridge object.
drm_bridge_attach inturn calls bridge-funcs-attach so that
bridge can continue with drm related initializations.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/Makefile |2 +-
drivers/gpu/drm/bridge/ptn3460.c | 27 +-
drivers/gpu/drm/drm_bridge.c | 91
drivers/gpu/drm/drm_crtc.c | 65 ---
drivers/gpu/drm/msm/hdmi/hdmi.c|7 +--
drivers/gpu/drm/msm/hdmi/hdmi.h|1 +
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c |7 ++-
drivers/gpu/drm/sti/sti_hda.c | 10 +---
drivers/gpu/drm/sti/sti_hdmi.c | 10 +---
include/drm/bridge/ptn3460.h |8 +++
include/drm/drm_crtc.h | 26 -
11 files changed, 136 insertions(+), 118 deletions(-)
create mode 100644 drivers/gpu/drm/drm_bridge.c
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 9292a76..00f97a5 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -14,7 +14,7 @@ drm-y :=drm_auth.o drm_bufs.o drm_cache.o \
drm_info.o drm_debugfs.o drm_encoder_slave.o \
drm_trace_points.o drm_global.o drm_prime.o \
drm_rect.o drm_vma_manager.o drm_flip_work.o \
- drm_modeset_lock.o
+ drm_modeset_lock.o drm_bridge.o
drm-$(CONFIG_COMPAT) += drm_ioc32.o
drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
diff --git a/drivers/gpu/drm/bridge/ptn3460.c
b/drivers/gpu/drm/bridge/ptn3460.c
index a2ddc8d..4a818c1 100644
--- a/drivers/gpu/drm/bridge/ptn3460.c
+++ b/drivers/gpu/drm/bridge/ptn3460.c
@@ -176,24 +176,11 @@ static void ptn3460_post_disable(struct drm_bridge
*bridge)
{
}
-static void ptn3460_bridge_destroy(struct drm_bridge *bridge)
-{
- struct ptn3460_bridge *ptn_bridge = bridge_to_ptn3460(bridge);
-
- drm_bridge_cleanup(bridge);
- if (gpio_is_valid(ptn_bridge-gpio_pd_n))
- gpio_free(ptn_bridge-gpio_pd_n);
- if (gpio_is_valid(ptn_bridge-gpio_rst_n))
- gpio_free(ptn_bridge-gpio_rst_n);
- /* Nothing else to free, we've got devm allocated memory */
-}
-
static struct drm_bridge_funcs ptn3460_bridge_funcs = {
.pre_enable = ptn3460_pre_enable,
.enable = ptn3460_enable,
.disable = ptn3460_disable,
.post_disable = ptn3460_post_disable,
- .destroy = ptn3460_bridge_destroy,
};
static int ptn3460_get_modes(struct drm_connector *connector)
@@ -314,7 +301,7 @@ int ptn3460_init(struct drm_device *dev, struct
drm_encoder *encoder,
}
ptn_bridge-bridge.funcs = ptn3460_bridge_funcs;
- ret = drm_bridge_init(dev, ptn_bridge-bridge);
+ ret = drm_bridge_attach(dev, ptn_bridge-bridge);
if (ret) {
DRM_ERROR(Failed to initialize bridge with drm\n);
goto err;
@@ -343,3 +330,15 @@ err:
return ret;
}
EXPORT_SYMBOL(ptn3460_init);
+
+void ptn3460_destroy(struct drm_bridge *bridge)
+{
+ struct ptn3460_bridge *ptn_bridge = bridge-driver_private;
+
+ if (gpio_is_valid(ptn_bridge-gpio_pd_n))
+ gpio_free(ptn_bridge-gpio_pd_n);
+ if (gpio_is_valid(ptn_bridge-gpio_rst_n))
+ gpio_free(ptn_bridge-gpio_rst_n);
+ /* Nothing else to free, we've got
Re: [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433. CMU_TOP domain provides source clocks to other CMU domains. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- Reviewed all registers and clock relationships w.r.t UM I have and all changes are OK. So Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks, Pankaj Dubey -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 80 +-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 88e8cac..a48b36c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[]
__initdata = {
FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+ /* XspiCLK[4:0] input clock for SPI */
+ FRATE(0, ioclk_spi4_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi3_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi2_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi1_clk_in, NULL, CLK_IS_ROOT, 5000),
+ FRATE(0, ioclk_spi0_clk_in, NULL, CLK_IS_ROOT, 5000),
+ /* Xi2s1SCLK input clock for I2S1_BCLK */
+ FRATE(0, ioclk_i2s1_bclk_in, NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC 0x0600
+#define DIV_STAT_PERIC 0x0700
#define ENABLE_ACLK_PERIC 0x0800
#define ENABLE_PCLK_PERIC00x0900
#define ENABLE_PCLK_PERIC10x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+ DIV_STAT_PERIC,
IMO, this line should have been added in first place itself when you
added peric_clk_regs.
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+ /* DIV_PERIC */
+ DIV(CLK_DIV_SCLK_SCI, div_sclk_sci, fin_pll, DIV_PERIC, 4, 8),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
+ DIV(CLK_DIV_SCLK_SC_IN, div_sclk_sc_in, fin_pll, DIV_PERIC, 0, 4),
+};
+
static struct samsung_gate_clock peric_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_PERIC */
+ GATE(CLK_ACLK_AHB2APB_PERIC2P, aclk_ahb2apb_peric2p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC1P, aclk_ahb2apb_peric1p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_AHB2APB_PERIC0P, aclk_ahb2apb_peric0p, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PERICNP_66, aclk_pericnp_66, aclk_peric_66,
+ ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
+
/* ENABLE_PCLK_PERIC0 */
+ GATE(CLK_PCLK_SCI, pclk_sci, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 31, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_GPIO_FINGER, pclk_gpio_finger, aclk_peric_66,
+ ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_GPIO_ESE, pclk_gpio_ese, aclk_peric_66,
+ ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PWM, pclk_pwm, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 28, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_SPDIF, pclk_spdif, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 26, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_PCM1, pclk_pcm1, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 25, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_PCLK_I2S1, pclk_i2s, aclk_peric_66, ENABLE_PCLK_PERIC0,
+ 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI2, pclk_spi2, aclk_peric_66, ENABLE_PCLK_PERIC0,
23, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI1, pclk_spi1, aclk_peric_66, ENABLE_PCLK_PERIC0,
22, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI0, pclk_spi0, aclk_peric_66, ENABLE_PCLK_PERIC0,
21,
Re: [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds missing gate clocks of CMU_PERIS domain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks of CMU_PERIS use fin_pll source clock directly. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- drivers/clk/samsung/clk-exynos5433.c | 146 - include/dt-bindings/clock/exynos5433.h | 33 +++- 2 files changed, 176 insertions(+), 3 deletions(-) Verified all registers and clock relationship against UM I have, and changes are OK. Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks, Pankaj Dubey -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes nit: %s/clocksof/clocks of G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 + include/dt-bindings/clock/exynos5433.h | 42 +- 3 files changed, 193 insertions(+), 1 deletion(-) Verified all changes in clock file against UM I have with me, all changes are OK. With small nit in commit message feel free to add: Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks, Pankaj Dubey -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590 +
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
[snip]
static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata
= {
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
};
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p) = { mout_mfc_pll, dout_mfc_pll, };
+PNAME(mout_bus_pll_div2_p) = { mout_bus_pll, dout_bus_pll, };
+PNAME(mout_mem1_pll_div2_p)= { mout_mem1_pll, dout_mem1_pll, };
+PNAME(mout_mem0_pll_div2_p)= { mout_mem0_pll, dout_mem0_pll, };
+PNAME(mout_mfc_pll_p) = { fin_pll, fout_mfc_pll, };
+PNAME(mout_bus_pll_p) = { fin_pll, fout_bus_pll, };
+PNAME(mout_mem1_pll_p) = { fin_pll, fout_mem1_pll, };
+PNAME(mout_mem0_pll_p) = { fin_pll, fout_mem0_pll, };
+
+PNAME(mout_clk2x_phy_c_p) = { mout_mem0_pll_div2, mout_clkm_phy_b, };
+PNAME(mout_clk2x_phy_b_p) = { mout_bus_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clk2x_phy_a_p) = { mout_bus_pll_div2, mout_mfc_pll_div2, };
+PNAME(mout_clkm_phy_c_p) = { mout_mem0_pll_div2, mout_clkm_phy_b, };
As mout_clk2x_phy_c_p and mout_clkm_phy_c_p both has same parent list
one of them can be dropped.
+PNAME(mout_clkm_phy_b_p) = { mout_mem1_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clkm_phy_a_p) = { mout_bus_pll_div2, mout_mfc_pll_div2, };
As mout_clk2x_phy_a_p and mout_clkm_phy_a_p both has same parent list
one of them can be dropped.
+
+PNAME(mout_aclk_mifnm_200_p) = { mout_mem0_pll_div2, div_mif_pre, };
+PNAME(mout_aclk_mifnm_400_p) = { mout_mem1_pll_div2, mout_bus_pll_div2,};
+
+PNAME(mout_aclk_disp_333_b_p) = { mout_aclk_disp_333_a,
+ mout_bus_pll_div2, };
+PNAME(mout_aclk_disp_333_a_p) = { mout_mfc_pll_div2, sclk_mphy_pll, };
+
+PNAME(mout_sclk_decon_vclk_c_p)= { mout_sclk_decon_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_vclk_b_p)= { mout_sclk_decon_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_vclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_decon_eclk_c_p)= { mout_sclk_decon_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_eclk_b_p)= { mout_sclk_decon_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_eclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { mout_sclk_decon_tv_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { mout_sclk_decon_tv_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_eclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_c_p) = { mout_sclk_dsd_b, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_b_p) = { mout_sclk_dsd_a, sclk_mphy_pll, };
+PNAME(mout_sclk_dsd_a_p) = { fin_pll, mout_mfc_pll_div2, };
+
+PNAME(mout_sclk_dsim0_c_p) = { mout_sclk_dsim0_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim0_b_p) = { mout_sclk_dsim0_a, mout_mfc_pll_div2 };
+PNAME(mout_sclk_dsim0_a_p) = { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { mout_sclk_decon_tv_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { mout_sclk_decon_tv_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_vclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsim1_c_p) = { mout_sclk_dsim1_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim1_b_p) = { mout_sclk_dsim1_a, mout_mfc_pll_div2,};
+PNAME(mout_sclk_dsim1_a_p) = { fin_pll, mout_bus_pll_div2, };
+
Same way I can see {fin_pll, mout_bus_pll_div2, } this combination
of parents is repeated six times above in different PNAME, which can be
replaced by one PNAME list with some common name, thus saving of 5 lines.
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
+ /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+ FFACTOR(CLK_DOUT_MFC_PLL, dout_mfc_pll, mout_mfc_pll, 1, 1, 0),
+ FFACTOR(CLK_DOUT_BUS_PLL, dout_bus_pll, mout_bus_pll,
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk: On Fri, Dec 05, 2014 at 10:13:51AM -0600, Nishanth Menon wrote: On 12/05/2014 10:10 AM, Nishanth Menon wrote: Case #2: Reverting the following allows boot. From next-20141204 10df7d5 ARM: 8211/1: l2c: Add support for overriding prefetch settings revert this - boot still fails d42ced0 ARM: 8210/1: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL revert this - boot still fails 46b9af8 ARM: 8209/1: l2c: Add interface to ask hypervisor to configure L2C revert this - boot still fails c94e325 ARM: 8208/1: l2c: Refactor the driver to use commit-like revert this - boot passed (first bad commit). + linux-samsung soc and updated Thomaz's mail ID (gmail now). Given where we are in the cycle (-final likely this weekend) the only thing we can do right now is to drop the patch set; exynos (and mvebu) will have to wait another cycle until this patch set (hopefully in a revised form) can be merged. Or a fix could be queued on top of this. Since (I believe) this series has been queued for 3.19, we have 6 or 7 RC releases ahead, which could be used for the purpose of fixing things (as they are supposed to?). I think we need 8208/1 split up into smaller changes so that the cause of this regression can be found. I'm afraid we need more than that. First of all, this series has been in the wild for more than 3 months already, without any serious changes. Need not to mention that mailing lists and maintainers of all potentially affected platforms had been added. It had been noted in cover letter that the only platform I (and Marek later) could test on was Exynos and that it would be good if somebody working with other platforms could test the patches. Looks like nobody cared back then, so why should we care that much now, especially that we have several RC releases ahead and we can still fix this? Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
On Mon, Dec 08, 2014 at 08:54:18PM +0900, Tomasz Figa wrote: 2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk: Given where we are in the cycle (-final likely this weekend) the only thing we can do right now is to drop the patch set; exynos (and mvebu) will have to wait another cycle until this patch set (hopefully in a revised form) can be merged. Or a fix could be queued on top of this. Since (I believe) this series has been queued for 3.19, we have 6 or 7 RC releases ahead, which could be used for the purpose of fixing things (as they are supposed to?). They were merged on 27th November, so they would've been in linux-next from about last Monday. Nishanth reported a failure on Friday, the last week day before the merge window opens. There's no time to try and fix this before the merge window, which is why I decided to drop it. They have already been dropped. They were dropped immediately after my message on Friday was sent. So they've not been in linux-next over this past weekend. We don't push known broken code in during the merge window. The merge window is the exact time when subtle bugs are likely to be introduced, and is the exact time that you want bisect to work. If we push known broken patches into the kernel during that period, we break the ability to use bisect to find problems, especially where it causes a platform to become unbootable. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
On Sat, Dec 06, 2014 at 12:31:01PM +0530, Jassi Brar wrote: It does, though, create an awkward situation when a channel is active while new requests are submitted - why would the channel want to stop after current transfer and await fresh issue_pending()? It's not that the request can be modified after submission. And it isn't that tx_submit() is meant for 'sleepable' preparation for the transfer and we need another call to be issued from atomic context. From what I see most drivers don't need to sleep in tx_submit(). In fact, from a quick look most clients seem to suffer from the ritual i.e, there's nothing between tx_submit() and issue_pending() calls. And when there is indeed some code, it seems that can be moved just before tx_submit(). Last and apparently the least of all, we can never enforce the same behavior of the api on Async dma and have uniform behavior over the api. So, if all tx_submit() does is put the request in controller driver's internal queue and the client can't touch the request after tx_submit(), why not merge the tx_submit() and issue_pending()? You are thinking from an API point and not what can be done with this API. Today this API allows you to collate all pending txn and start while dmaengine driver can collate and submit as a batch to hardware and not waste time in getting irq and then setting next one. Sadly none of the drivers use this feature... I actually like the split model, you can also prepare txn ahead of time and submit them when needed. If you don't like this, then please do as most implementation do today, call prepare and submit in series. Flexiblity in API is a better option IMO Thanks -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] drm/exynos: fimd: Remove drm_dev and pipe members from fimd_context
On 2014년 12월 07일 21:04, Ajay Kumar wrote:
ctx-drm_dev is unnecessary since it can be easily accessed
via ctx-manager-drm_dev. Even the pipe variable inside
fimd_context is redundant. Cleaning up the same.
Already applied.
Thanks,
Inki Dae
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index e5810d1..157f4dd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -159,7 +159,6 @@ struct fimd_win_data {
struct fimd_context {
struct exynos_drm_manager manager;
struct device *dev;
- struct drm_device *drm_dev;
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
@@ -174,7 +173,6 @@ struct fimd_context {
u32 i80ifcon;
booli80_if;
boolsuspended;
- int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
atomic_twin_updated;
@@ -298,17 +296,17 @@ static int fimd_mgr_initialize(struct
exynos_drm_manager *mgr,
struct exynos_drm_private *priv;
priv = drm_dev-dev_private;
- mgr-drm_dev = ctx-drm_dev = drm_dev;
- mgr-pipe = ctx-pipe = priv-pipe++;
+ mgr-drm_dev = drm_dev;
+ mgr-pipe = priv-pipe++;
/* attach this sub driver to iommu mapping if supported. */
- if (is_drm_iommu_supported(ctx-drm_dev)) {
+ if (is_drm_iommu_supported(mgr-drm_dev)) {
/*
* If any channel is already active, iommu will throw
* a PAGE FAULT when enabled. So clear any channel if enabled.
*/
fimd_clear_channel(mgr);
- drm_iommu_attach_device(ctx-drm_dev, ctx-dev);
+ drm_iommu_attach_device(mgr-drm_dev, ctx-dev);
}
return 0;
@@ -319,8 +317,8 @@ static void fimd_mgr_remove(struct exynos_drm_manager
*mgr)
struct fimd_context *ctx = mgr_to_fimd(mgr);
/* detach this sub driver from iommu mapping if supported. */
- if (is_drm_iommu_supported(ctx-drm_dev))
- drm_iommu_detach_device(ctx-drm_dev, ctx-dev);
+ if (is_drm_iommu_supported(mgr-drm_dev))
+ drm_iommu_detach_device(mgr-drm_dev, ctx-dev);
}
static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
@@ -1001,7 +999,7 @@ static void fimd_te_handler(struct exynos_drm_manager
*mgr)
struct fimd_context *ctx = mgr_to_fimd(mgr);
/* Checks the crtc is detached already from encoder */
- if (ctx-pipe 0 || !ctx-drm_dev)
+ if (mgr-pipe 0 || !mgr-drm_dev)
return;
/*
@@ -1018,7 +1016,7 @@ static void fimd_te_handler(struct exynos_drm_manager
*mgr)
}
if (test_bit(0, ctx-irq_flags))
- drm_handle_vblank(ctx-drm_dev, ctx-pipe);
+ drm_handle_vblank(mgr-drm_dev, mgr-pipe);
}
static struct exynos_drm_manager_ops fimd_manager_ops = {
@@ -1047,17 +1045,19 @@ static irqreturn_t fimd_irq_handler(int irq, void
*dev_id)
writel(clear_bit, ctx-regs + VIDINTCON1);
/* check the crtc is detached already from encoder */
- if (ctx-pipe 0 || !ctx-drm_dev)
+ if (ctx-manager.pipe 0 || !ctx-manager.drm_dev)
goto out;
if (ctx-i80_if) {
- exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
+ exynos_drm_crtc_finish_pageflip(ctx-manager.drm_dev,
+ ctx-manager.pipe);
/* Exits triggering mode */
atomic_set(ctx-triggering, 0);
} else {
- drm_handle_vblank(ctx-drm_dev, ctx-pipe);
- exynos_drm_crtc_finish_pageflip(ctx-drm_dev, ctx-pipe);
+ drm_handle_vblank(ctx-manager.drm_dev, ctx-manager.pipe);
+ exynos_drm_crtc_finish_pageflip(ctx-manager.drm_dev,
+ ctx-manager.pipe);
/* set wait vsync event to zero and wake up queue. */
if (atomic_read(ctx-wait_vsync_event)) {
--
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Re: [PATCH V3] drm/exynos: Add DECON driver
On 2014년 12월 07일 21:04, Ajay Kumar wrote:
This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
DECON(Display and Enhancement Controller) is the new IP
in exynos7 SOC for generating video signals using pixel data.
DECON driver can be used to drive 2 different interfaces on Exynos7:
DECON-INT(video controller) and DECON-EXT(Mixer for HDMI)
The existing FIMD driver code was used as a template to create
DECON driver. Only DECON-INT is supported as of now, and
DECON-EXT support will be added later.
Signed-off-by: Akshu Agrawal aks...@gmail.com
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
-- Address comments from Pankaj and do few cleanups.
Changes since V2:
-- Address more comments from Pankaj and cleanup.
.../devicetree/bindings/video/exynos7-decon.txt| 67 ++
drivers/gpu/drm/exynos/Kconfig | 13 +-
drivers/gpu/drm/exynos/Makefile|1 +
drivers/gpu/drm/exynos/exynos7_drm_decon.c | 1042
drivers/gpu/drm/exynos/exynos_drm_drv.c|4 +
drivers/gpu/drm/exynos/exynos_drm_drv.h|1 +
include/video/exynos7_decon.h | 346 +++
7 files changed, 1471 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/video/exynos7-decon.txt
create mode 100644 drivers/gpu/drm/exynos/exynos7_drm_decon.c
create mode 100644 include/video/exynos7_decon.h
diff --git a/Documentation/devicetree/bindings/video/exynos7-decon.txt
b/Documentation/devicetree/bindings/video/exynos7-decon.txt
new file mode 100644
index 000..14db519
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/exynos7-decon.txt
@@ -0,0 +1,67 @@
+Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
+
+DECON (Display and Enhancement Controller) is the Display Controller
for the
+Exynos7 series of SoCs which transfers the image data from a video memory
+buffer to an external LCD interface.
+
+Required properties:
+- compatible: value should be samsung,exynos7-decon;
+
+- reg: physical base address and length of the DECON registers set.
+
+- interrupt-parent: should be the phandle of the decon controller's
+ parent interrupt controller.
+
+- interrupts: should contain a list of all DECON IP block interrupts
in the
+ order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
+ format depends on the interrupt controller used.
+
+- interrupt-names: should contain the interrupt names: fifo, vsync,
+ lcd_sys, in the same order as they were listed in the interrupts
+property.
+
+- pinctrl-0: pin control group to be used for this controller.
+
+- pinctrl-names: must contain a default entry.
+
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+
+- clock-names: list of clock names sorted in the same order as the clocks
+ property. Must contain pclk_decon0, aclk_decon0,
+decon0_eclk, decon0_vclk.
Should the DECON driver really care about decon0_eclk and decon0_vclk?
If so then What is the purpose of these special clocks? I'm not sure
that these clocks should be cared by driver. Until now, Exynos driver
has cared about only video source and core source clocks.
Can you give me more details about the use of the special clocks?
+
+Optional Properties:
+- samsung,power-domain: a phandle to DECON power domain node.
+- display-timings: timing settings for FIMD, as described in document
[1].
+ Can be used in case timings cannot be provided otherwise
+ or to override timings provided by the panel.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+
+Example:
+
+SoC specific DT entry:
+
+ decon@1393 {
+ compatible = samsung,exynos7-decon;
+ interrupt-parent = combiner;
+ reg = 0x1393 0x1000;
+ interrupt-names = lcd_sys, vsync, fifo;
+ interrupts = 0 188 0, 0 189 0, 0 190 0;
+ clocks = clock_disp PCLK_DECON_INT,
+ clock_disp ACLK_DECON_INT,
+ clock_disp SCLK_DECON_INT_ECLK,
+ clock_disp SCLK_DECON_INT_EXTCLKPLL;
+ clock-names = pclk_decon0, aclk_decon0, decon0_eclk,
+ decon0_vclk;
+ status = disabled;
+ };
+
+Board specific DT entry:
+
+ decon@1393 {
+ pinctrl-0 = lcd_clk pwm1_out;
+ pinctrl-names = default;
+ status = okay;
+ };
diff --git a/drivers/gpu/drm/exynos/Kconfig
b/drivers/gpu/drm/exynos/Kconfig
index 7f9f6f9..d3434cb 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -32,9 +32,16 @@ config DRM_EXYNOS_FIMD
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
On 12/08/2014 06:22 AM, Russell King - ARM Linux wrote: On Mon, Dec 08, 2014 at 08:54:18PM +0900, Tomasz Figa wrote: 2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk: Given where we are in the cycle (-final likely this weekend) the only thing we can do right now is to drop the patch set; exynos (and mvebu) will have to wait another cycle until this patch set (hopefully in a revised form) can be merged. Or a fix could be queued on top of this. Since (I believe) this series has been queued for 3.19, we have 6 or 7 RC releases ahead, which could be used for the purpose of fixing things (as they are supposed to?). They were merged on 27th November, so they would've been in linux-next from about last Monday. Nishanth reported a failure on Friday, the For what ever it is worth, the l2c changes actually appeared on Thursday CST (next-20141204). Found the regression against next-20141203 tag and it took me a day to track it down (after looking at a few other regressions as well).. Anyways... -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
On Mon, Dec 08, 2014 at 06:37:27PM +0530, Vinod Koul wrote: I actually like the split model, you can also prepare txn ahead of time and submit them when needed. Actually, you can't - that's not permitted. I have email(s) from Dan explicitly stating that it is permitted for a driver to take a spinlock in their prepare callback, and release it when the descriptor is submitted. Several DMA engine drivers (particularly those in for async_tx) do exactly that. The reason that submit is separate from prepare is to allow DMA engine users to set a callback - if it weren't for that, there wouldn't be a submit step, prepare would have done everything. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: request memory region in driver probe()
The memory mapped registers region is common for both DAIs so request
it in the I2S platform device driver probe for the platform device
corresponding to the primary DAI, rather than in the ASoC DAI probe
callback. While at it switch to devm_ioremap_resource(). This also
drops the hard coded (0x100) register region size in the driver.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
Tested on Odroid X2.
sound/soc/samsung/i2s.c | 44 +++-
1 file changed, 7 insertions(+), 37 deletions(-)
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 26d1a1a..fff429da 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -59,10 +59,8 @@ struct samsung_i2s_dai_data {
struct i2s_dai {
/* Platform device for this DAI */
struct platform_device *pdev;
- /* IOREMAP'd SFRs */
+ /* Memory mapped SFR region */
void __iomem*addr;
- /* Physical base address of SFRs */
- u32 base;
/* Rate of RCLK source clock */
unsigned long rclk_srcrate;
/* Frame Clock */
@@ -980,12 +978,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
goto probe_exit;
}
- i2s-addr = ioremap(i2s-base, 0x100);
- if (i2s-addr == NULL) {
- dev_err(i2s-pdev-dev, cannot ioremap registers\n);
- return -ENXIO;
- }
-
i2s-clk = clk_get(i2s-pdev-dev, iis);
if (IS_ERR(i2s-clk)) {
dev_err(i2s-pdev-dev, failed to get i2s_clock\n);
@@ -1002,7 +994,6 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
samsung_asoc_init_dma_data(dai, i2s-dma_playback, i2s-dma_capture);
if (other) {
- other-addr = i2s-addr;
other-clk = i2s-clk;
}
@@ -1044,8 +1035,6 @@ static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
clk_disable_unprepare(i2s-clk);
clk_put(i2s-clk);
-
- iounmap(i2s-addr);
}
i2s-clk = NULL;
@@ -1164,7 +1153,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
u32 regs_base, quirks = 0, idma_addr = 0;
struct device_node *np = pdev-dev.of_node;
const struct samsung_i2s_dai_data *i2s_dai_data;
- int ret = 0;
/* Call during Seconday interface registration */
i2s_dai_data = samsung_i2s_get_driver_data(pdev);
@@ -1229,16 +1217,10 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(pdev-dev, Unable to get I2S SFR address\n);
- return -ENXIO;
- }
+ pri_dai-addr = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(pri_dai-addr))
+ return PTR_ERR(pri_dai-addr);
- if (!request_mem_region(res-start, resource_size(res),
- samsung-i2s)) {
- dev_err(pdev-dev, Unable to request SFR region\n);
- return -EBUSY;
- }
regs_base = res-start;
pri_dai-dma_playback.dma_addr = regs_base + I2STXD;
@@ -1247,7 +1229,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
pri_dai-dma_capture.ch_name = rx;
pri_dai-dma_playback.dma_size = 4;
pri_dai-dma_capture.dma_size = 4;
- pri_dai-base = regs_base;
pri_dai-quirks = quirks;
pri_dai-variant_regs = i2s_dai_data-i2s_variant_regs;
@@ -1258,8 +1239,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
sec_dai = i2s_alloc_dai(pdev, true);
if (!sec_dai) {
dev_err(pdev-dev, Unable to alloc I2S_sec\n);
- ret = -ENOMEM;
- goto err;
+ return -ENOMEM;
}
sec_dai-dma_playback.dma_addr = regs_base + I2STXDS;
sec_dai-dma_playback.ch_name = tx-sec;
@@ -1271,7 +1251,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
}
sec_dai-dma_playback.dma_size = 4;
- sec_dai-base = regs_base;
+ sec_dai-addr = pri_dai-addr;
sec_dai-quirks = quirks;
sec_dai-idma_playback.dma_addr = idma_addr;
sec_dai-pri_dai = pri_dai;
@@ -1280,8 +1260,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
if (i2s_pdata i2s_pdata-cfg_gpio i2s_pdata-cfg_gpio(pdev)) {
dev_err(pdev-dev, Unable to configure gpio\n);
- ret = -EINVAL;
- goto err;
+ return -EINVAL;
}
devm_snd_soc_register_component(pri_dai-pdev-dev,
@@ -1293,17 +1272,11 @@ static int samsung_i2s_probe(struct platform_device
*pdev)
samsung_asoc_dma_platform_register(pdev-dev);
return 0;
-err:
- if (res)
-
Re: regression: OMAP4 (next-20141204) (bisect to: ARM: 8208/1: l2c: Refactor the driver to use commit-like)
On Mon, Dec 08, 2014 at 07:54:08AM -0600, Nishanth Menon wrote: On 12/08/2014 06:22 AM, Russell King - ARM Linux wrote: On Mon, Dec 08, 2014 at 08:54:18PM +0900, Tomasz Figa wrote: 2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk: Given where we are in the cycle (-final likely this weekend) the only thing we can do right now is to drop the patch set; exynos (and mvebu) will have to wait another cycle until this patch set (hopefully in a revised form) can be merged. Or a fix could be queued on top of this. Since (I believe) this series has been queued for 3.19, we have 6 or 7 RC releases ahead, which could be used for the purpose of fixing things (as they are supposed to?). They were merged on 27th November, so they would've been in linux-next from about last Monday. Nishanth reported a failure on Friday, the For what ever it is worth, the l2c changes actually appeared on Thursday CST (next-20141204). Found the regression against next-20141203 tag and it took me a day to track it down (after looking at a few other regressions as well).. I wonder if that's because I didn't push my tree out until Tuesday-ish. It takes around 48 hours between when I push stuff out to it appearing in linux-next, which is not particularly desirable, but unavoidable due to timezone differences. I did decide that I wouldn't push it out the same day I merged it because I wanted it to run through my build/boot system, which it did successfully, but then my OMAP4 build doesn't have CPU idle enabled (and as you've identified, when CPU idle is disabled, it works.) The problem there is that if I decide not to push some merged changes out, it takes several days before I get around to touching the kernel tree again. Hence why it took from Thursday until Tuesday for it to eventually get pushed out. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/4] removal of extra abstraction layers
Hi Inki, 2014-12-06 Dave Airlie airl...@gmail.com: On 2 December 2014 at 22:38, Gustavo Padovan gust...@padovan.org wrote: Hi Inki, Can you please review this? I also have sent other two patch sets that sits on top of this one. Thanks. Inki, any plans on when you can get to looking at this? I think cleaning up exynos so we can get atomic using it is something that will benefit it heavily. Besides these patches I have other two clean up patchsets[0][1] that are very important for atomic support, can you review these two too? [0] http://www.spinics.net/lists/linux-samsung-soc/msg39614.html [1] http://www.spinics.net/lists/linux-samsung-soc/msg39632.html Gustavo -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ASoC: samsung: i2s: Add missing assignment of variant_regs
Add assignment of the variant_regs field which is missing in commit a5a56871f804edac93a53b5e871c0e9818fb9033 (ASoC: samsung: add support for exynos7 I2S controller). Without this attempting to probe the secondary DAI fails with an error like: [1.763026] Unable to handle kernel NULL pointer dereference at virtual address 000c [1.780895] pgd = c0004000 [1.783606] [000c] *pgd= [1.838255] Internal error: Oops: 5 [#1] PREEMPT SMP ARM [1.843514] Modules linked in: [1.846558] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc1-9-g5dcb01e-dirty #1521 [1.854887] task: ee00a800 ti: ee088000 task.ti: ee088000 [1.860284] PC is at i2s_txctrl+0x40/0x2d4 [1.864350] LR is at i2s_txctrl+0x28/0x2d4 [1.868428] pc : [c036ffd4]lr : [c036ffbc]psr: 6153 [1.868428] sp : ee089dc0 ip : fp : ee21f000 [1.879883] r10: r9 : ee21fb00 r8 : c06406c4 [1.885091] r7 : ee21fb00 r6 : r5 : f00f6000 r4 : ed943410 [1.891601] r3 : 016c r2 : c0464550 r1 : c055cef8 r0 : ed943610 [1.898113] Flags: nZCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel [1.905490] Control: 10c5387d Table: 4000404a DAC: 0015 [1.911218] Process swapper/0 (pid: 1, stack limit = 0xee088240) [1.917208] Stack: (0xee089dc0 to 0xee08a000) ... [2.068431] [c036ffd4] (i2s_txctrl) from [c03719fc] (samsung_i2s_dai_probe+0xb8/0x450) [2.076676] [c03719fc] (samsung_i2s_dai_probe) from [c03607e0] (snd_soc_register_card+0xd98/0x1348) [2.086044] [c03607e0] (snd_soc_register_card) from [c03726e4] (odroidx2_audio_probe+0xa8/0x11c) [2.095160] [c03726e4] (odroidx2_audio_probe) from [c0249dd0] (platform_drv_probe+0x48/0xa4) [2.103922] [c0249dd0] (platform_drv_probe) from [c0248988] (driver_probe_device+0x10c/0x22c) [2.112773] [c0248988] (driver_probe_device) from [c0248b34] (__driver_attach+0x8c/0x90) [2.121192] [c0248b34] (__driver_attach) from [c02471c8] (bus_for_each_dev+0x54/0x88) [2.129352] [c02471c8] (bus_for_each_dev) from [c0248188] (bus_add_driver+0xd4/0x1d0) [2.137510] [c0248188] (bus_add_driver) from [c024915c] (driver_register+0x78/0xf4) [2.145499] [c024915c] (driver_register) from [c0008924] (do_one_initcall+0x80/0x1b8) [2.153670] [c0008924] (do_one_initcall) from [c05b7d40] (kernel_init_freeable+0xfc/0x1c8) [2.162260] [c05b7d40] (kernel_init_freeable) from [c04146c0] (kernel_init+0x8/0xec) [2.170330] [c04146c0] (kernel_init) from [c000e7f8] (ret_from_fork+0x14/0x3c) [2.177873] Code: e594 e59f128c e59f228c e2800010 (e59c700c) Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com --- sound/soc/samsung/i2s.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c index c7aafcd..eca17dc 100644 --- a/sound/soc/samsung/i2s.c +++ b/sound/soc/samsung/i2s.c @@ -1261,6 +1261,8 @@ static int samsung_i2s_probe(struct platform_device *pdev) ret = -ENOMEM; goto err; } + + sec_dai-variant_regs = pri_dai-variant_regs; sec_dai-dma_playback.dma_addr = regs_base + I2STXDS; sec_dai-dma_playback.ch_name = tx-sec; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: samsung: request memory region in driver probe()
On 08/12/14 15:36, Sylwester Nawrocki wrote: The memory mapped registers region is common for both DAIs so request it in the I2S platform device driver probe for the platform device corresponding to the primary DAI, rather than in the ASoC DAI probe callback. While at it switch to devm_ioremap_resource(). This also drops the hard coded (0x100) register region size in the driver. Please ignore this patch, there is one iounmap() call removal missing in it. I'll resend it updated together with other patch(es) I'm working on to get the CDCLK gating issue on Odroid X2/U3 fixed. -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ASoC: samsung: i2s: Add missing assignment of variant_regs
On Mon, Dec 08, 2014 at 06:45:54PM +0100, Sylwester Nawrocki wrote: Add assignment of the variant_regs field which is missing in commit a5a56871f804edac93a53b5e871c0e9818fb9033 (ASoC: samsung: add support for exynos7 I2S controller). Without this attempting to probe the secondary DAI fails with an error like: Applied, thanks. Broader testing of changes before sending them upstream would be good... signature.asc Description: Digital signature
Re: [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
Hi Pankaj, On 12/08/2014 08:31 PM, Pankaj Dubey wrote: Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433. CMU_TOP domain provides source clocks to other CMU domains. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- Reviewed all registers and clock relationships w.r.t UM I have and all changes are OK. So Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Hi Pankaj,
On 12/08/2014 08:31 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 80
+-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 88e8cac..a48b36c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[]
__initdata = {
FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+/* XspiCLK[4:0] input clock for SPI */
+FRATE(0, ioclk_spi4_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi3_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi2_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi1_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi0_clk_in, NULL, CLK_IS_ROOT, 5000),
+/* Xi2s1SCLK input clock for I2S1_BCLK */
+FRATE(0, ioclk_i2s1_bclk_in, NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC0x0600
+#define DIV_STAT_PERIC0x0700
#define ENABLE_ACLK_PERIC0x0800
#define ENABLE_PCLK_PERIC00x0900
#define ENABLE_PCLK_PERIC10x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+DIV_STAT_PERIC,
IMO, this line should have been added in first place itself when you added
peric_clk_regs.
Why? I want to locate it according to address base.
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+/* DIV_PERIC */
+DIV(CLK_DIV_SCLK_SCI, div_sclk_sci, fin_pll, DIV_PERIC, 4, 8),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo Choi
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Re: [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
Hi Pankaj, On 12/08/2014 08:32 PM, Pankaj Dubey wrote: Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds missing gate clocks of CMU_PERIS domain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks of CMU_PERIS use fin_pll source clock directly. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- drivers/clk/samsung/clk-exynos5433.c | 146 - include/dt-bindings/clock/exynos5433.h | 33 +++- 2 files changed, 176 insertions(+), 3 deletions(-) Verified all registers and clock relationship against UM I have, and changes are OK. Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
Hi Pankaj, On 12/08/2014 08:36 PM, Pankaj Dubey wrote: Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes nit: %s/clocksof/clocks of I'll fix it. G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain. Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com --- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 + include/dt-bindings/clock/exynos5433.h | 42 +- 3 files changed, 193 insertions(+), 1 deletion(-) Verified all changes in clock file against UM I have with me, all changes are OK. With small nit in commit message feel free to add: Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Pankaj,
On 12/08/2014 08:37 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
nit: %s/fo/of
I'll fix it.
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent
Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 590
+
include/dt-bindings/clock/exynos5433.h | 190 ++-
2 files changed, 779 insertions(+), 1 deletion(-)
[snip]
static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[]
__initdata = {
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
};
+/* list of all parent clock list */
+PNAME(mout_mfc_pll_div2_p)= { mout_mfc_pll, dout_mfc_pll, };
+PNAME(mout_bus_pll_div2_p)= { mout_bus_pll, dout_bus_pll, };
+PNAME(mout_mem1_pll_div2_p)= { mout_mem1_pll, dout_mem1_pll, };
+PNAME(mout_mem0_pll_div2_p)= { mout_mem0_pll, dout_mem0_pll, };
+PNAME(mout_mfc_pll_p)= { fin_pll, fout_mfc_pll, };
+PNAME(mout_bus_pll_p)= { fin_pll, fout_bus_pll, };
+PNAME(mout_mem1_pll_p)= { fin_pll, fout_mem1_pll, };
+PNAME(mout_mem0_pll_p)= { fin_pll, fout_mem0_pll, };
+
+PNAME(mout_clk2x_phy_c_p)= { mout_mem0_pll_div2, mout_clkm_phy_b, };
+PNAME(mout_clk2x_phy_b_p)= { mout_bus_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clk2x_phy_a_p)= { mout_bus_pll_div2, mout_mfc_pll_div2,
};
+PNAME(mout_clkm_phy_c_p)= { mout_mem0_pll_div2, mout_clkm_phy_b, };
As mout_clk2x_phy_c_p and mout_clkm_phy_c_p both has same parent list one of
them can be dropped.
OK, I'll use common parent to remove duplicat code.
+PNAME(mout_clkm_phy_b_p)= { mout_mem1_pll_div2, mout_clkm_phy_a, };
+PNAME(mout_clkm_phy_a_p)= { mout_bus_pll_div2, mout_mfc_pll_div2, };
As mout_clk2x_phy_a_p and mout_clkm_phy_a_p both has same parent list one of
them can be dropped.
OK.
+
+PNAME(mout_aclk_mifnm_200_p)= { mout_mem0_pll_div2, div_mif_pre, };
+PNAME(mout_aclk_mifnm_400_p)= { mout_mem1_pll_div2,
mout_bus_pll_div2,};
+
+PNAME(mout_aclk_disp_333_b_p)= { mout_aclk_disp_333_a,
+mout_bus_pll_div2, };
+PNAME(mout_aclk_disp_333_a_p)= { mout_mfc_pll_div2, sclk_mphy_pll,
};
+
+PNAME(mout_sclk_decon_vclk_c_p)= { mout_sclk_decon_vclk_b,
+sclk_mphy_pll, };
+PNAME(mout_sclk_decon_vclk_b_p)= { mout_sclk_decon_vclk_a,
+mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_vclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_decon_eclk_c_p)= { mout_sclk_decon_eclk_b,
+sclk_mphy_pll, };
+PNAME(mout_sclk_decon_eclk_b_p)= { mout_sclk_decon_eclk_a,
+mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_eclk_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_eclk_c_p) = { mout_sclk_decon_tv_eclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_eclk_b_p) = { mout_sclk_decon_tv_eclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_eclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_c_p)= { mout_sclk_dsd_b, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsd_b_p)= { mout_sclk_dsd_a, sclk_mphy_pll, };
+PNAME(mout_sclk_dsd_a_p)= { fin_pll, mout_mfc_pll_div2, };
+
+PNAME(mout_sclk_dsim0_c_p)= { mout_sclk_dsim0_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim0_b_p)= { mout_sclk_dsim0_a, mout_mfc_pll_div2
};
+PNAME(mout_sclk_dsim0_a_p)= { fin_pll, mout_bus_pll_div2, };
+
+PNAME(mout_sclk_decon_tv_vclk_c_p) = { mout_sclk_decon_tv_vclk_b,
+ sclk_mphy_pll, };
+PNAME(mout_sclk_decon_tv_vclk_b_p) = { mout_sclk_decon_tv_vclk_a,
+ mout_mfc_pll_div2, };
+PNAME(mout_sclk_decon_tv_vclk_a_p) = { fin_pll, mout_bus_pll_div2, };
+PNAME(mout_sclk_dsim1_c_p)= { mout_sclk_dsim1_b, sclk_mphy_pll, };
+PNAME(mout_sclk_dsim1_b_p)= { mout_sclk_dsim1_a,
mout_mfc_pll_div2,};
+PNAME(mout_sclk_dsim1_a_p)= { fin_pll, mout_bus_pll_div2, };
+
Same way I can see {fin_pll, mout_bus_pll_div2, } this combination of
parents is repeated six times above in different PNAME, which can be replaced
by one PNAME list with some common name, thus saving of 5 lines.
OK.
+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata
= {
+/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
+FFACTOR(CLK_DOUT_MFC_PLL, dout_mfc_pll, mout_mfc_pll, 1, 1, 0),
+
Re: [alsa-devel] [PATCH] ASoC: samsung: i2s: Add missing assignment of variant_regs
Hi, On 12/9/14, Mark Brown broo...@kernel.org wrote: On Mon, Dec 08, 2014 at 06:45:54PM +0100, Sylwester Nawrocki wrote: Add assignment of the variant_regs field which is missing in commit a5a56871f804edac93a53b5e871c0e9818fb9033 (ASoC: samsung: add support for exynos7 I2S controller). Without this attempting to probe the secondary DAI fails with an error like: Applied, thanks. Broader testing of changes before sending them upstream would be good... I am really sorry for introducing so many crashes in the driver. Next time will take care of testing all possible cases. Thanks for the support Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 286 +
include/dt-bindings/clock/exynos5433.h | 82 +-
2 files changed, 365 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 5b4ec83..e2b7ea6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_SCLK_MMC2_A, div_sclk_mmc2_a, mout_sclk_mmc2_b,
DIV_TOP_FSYS1, 0, 4),
+ /* DIV_TOP_FSYS2 */
+ DIV(CLK_DIV_SCLK_PCIE_100, div_sclk_pcie_100, mout_sclk_pcie_100,
+ DIV_TOP_FSYS2, 12, 3),
+ DIV(CLK_DIV_SCLK_USBHOST30, div_sclk_usbhost30,
+ mout_sclk_usbhost30, DIV_TOP_FSYS2, 8, 4),
+ DIV(CLK_DIV_SCLK_UFSUNIPRO, div_sclk_ufsunipro,
+ mout_sclk_ufsunipro, DIV_TOP_FSYS2, 4, 4),
+ DIV(CLK_DIV_SCLK_USBDRD30, div_sclk_usbdrd30, mout_sclk_usbdrd30,
+ DIV_TOP_FSYS2, 0, 4),
+
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, div_sclk_spi1_b, div_sclk_spi1_a,
DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[]
__initdata = {
ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
+ GATE(CLK_SCLK_PCIE_100_FSYS, sclk_pcie_100_fsys, div_sclk_pcie_100,
+ ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MMC2_FSYS, sclk_mmc2_fsys, div_sclk_mmc2_b,
ENABLE_SCLK_TOP_FSYS, 6, 0, 0),
GATE(CLK_SCLK_MMC1_FSYS, sclk_mmc1_fsys, div_sclk_mmc1_b,
ENABLE_SCLK_TOP_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC0_FSYS, sclk_mmc0_fsys, div_sclk_mmc0_b,
ENABLE_SCLK_TOP_FSYS, 4, 0, 0),
+ GATE(CLK_SCLK_UFSUNIPRO_FSYS, sclk_ufsunipro_fsys,
+ div_sclk_ufsunipro, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_ufsunipro_fsys is '3'.
+ GATE(CLK_SCLK_USBHOST30_FSYS, sclk_usbhost30_fsys,
+ div_sclk_usbhost30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbhost30_fsys is '1'.
+ GATE(CLK_SCLK_USBDRD30_FSYS, sclk_usbdrd30_fsys,
+ div_sclk_usbdrd30, ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbdrd30_fsys is '0'.
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, sclk_spi4_peric, div_sclk_spi4_b,
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris,
samsung,exynos5433-cmu-peris,
#define ENABLE_IP_FSYS1 0x0b04
/* list of all parent clock list */
+PNAME(mout_sclk_ufs_mphy_user_p) = { fin_pll, sclk_ufs_mphy, };
PNAME(mout_aclk_fsys_200_user_p) = { fin_pll, aclk_fsys_200, };
+PNAME(mout_sclk_pcie_100_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
This parent list looks wrong.
As per UM, it should be: { fin_pll, sclk_pcie_100_fsys,};
+PNAME(mout_sclk_ufsunipro_user_p) = { fin_pll, sclk_ufsunipro_fsys,};
PNAME(mout_sclk_mmc2_user_p) = { fin_pll, sclk_mmc2_fsys, };
PNAME(mout_sclk_mmc1_user_p) = { fin_pll, sclk_mmc1_fsys, };
PNAME(mout_sclk_mmc0_user_p) = { fin_pll, sclk_mmc0_fsys, };
+PNAME(mout_sclk_usbhost30_user_p) = { fin_pll, sclk_usbhost30_fsys,};
+PNAME(mout_sclk_usbdrd30_user_p) = { fin_pll, sclk_usbdrd30_fsys, };
+
+PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
+PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
+ = { fin_pll, phyclk_usbhost20_phy_hsic1_phy, };
+PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_clk48mohci_phy, };
+PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_phyclock_phy, };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
+ = { fin_pll, phyclk_usbhost20_phy_freeclk_phy, };
+PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_pipe_pclk_phy, };
Here second parent should be 'phyclk_usbdrd30_udrd30_pipe_pclk_phy'.
+PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
+ = { fin_pll, phyclk_usbhost30_uhost30_phyclock_phy, };
Here second
Re: [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
typo: %s/regiser/register
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Arnd Bergmann a...@arndb.de
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++
drivers/clk/samsung/clk-exynos5433.c | 185 -
include/dt-bindings/clock/exynos5433.h | 29 +++-
3 files changed, 232 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - samsung,exynos5433-cmu-bus0, samsung,exynos5433-cmu-bus1
+and samsung,exynos5433-cmu-bus2 - clock controller compatible for CMU_BUS
+which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_bus0: clock-controller@0x1360 {
+ compatible = samsung,exynos5433-cmu-bus0;
+ reg = 0x1360 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus1: clock-controller@0x1480 {
+ compatible = samsung,exynos5433-cmu-bus1;
+ reg = 0x1480 0x0b04;
+ #clock-cells = 1;
+ };
+
+ cmu_bus2: clock-controller@0x1340 {
+ compatible = samsung,exynos5433-cmu-bus2;
+ reg = 0x1340 0x0b04;
+ #clock-cells = 1;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 99262e0..5b4ec83 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata =
{
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, div_aclk_imem_sssx,
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, div_aclk_imem_sssx_266,
This change can be moved to patch 1/19 itself.
mout_bus_pll_user, DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, div_aclk_imem_200,
mout_bus_pll_user, DIV_TOP3, 20, 3),
@@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata
= {
DIV(CLK_DIV_ACLK_PERIS_66_A, div_aclk_peris_66_a,
mout_bus_pll_user, DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, div_aclk_g3d_400, mout_bus_pll_user,
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, div_aclk_bus0_400, mout_aclk_bus0_400,
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, div_aclk_bus1_400, mout_bus_pll_user,
+ DIV_TOP4, 0, 3),
+
With these changes you can have:
Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com
Thanks,
Pankaj Dubey
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Re: [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cortex-A6? I think it should be Cortex-A5?
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk-exynos5433.c | 173 +
include/dt-bindings/clock/exynos5433.h | 53 +++
3 files changed, 233 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 8d3dad4..9a6ae75 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -23,6 +23,8 @@ Required Properties:
which generates clocks for G2D/MDMA IPs.
- samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
+ - samsung,exynos5433-cmu-aud - clock controller compatible for CMU_AUD
+which generates clocks for Cortex-A5/BUS/AUDIO clocks.
Commit message says Cortex-A6?
- reg: physical base address of the controller and length of memory mapped
region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_aud: clock-controller@0x114c {
+ compatible = samsung,exynos5433-cmu-aud;
+ reg = 0x114c 0x0b04;
+ #clock-cells = 1;
+ };
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index ec23e97..99262e0 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2454,3 +2454,176 @@ static void __init exynos5433_cmu_disp_init(struct
device_node *np)
CLK_OF_DECLARE(exynos5433_cmu_disp, samsung,exynos5433-cmu-disp,
exynos5433_cmu_disp_init);
+
+/*
+ * Register offset definitions for CMU_AUD
+ */
+#define MUX_SEL_AUD0 0x0200
+#define MUX_SEL_AUD1 0x0204
+#define MUX_ENABLE_AUD00x0300
+#define MUX_ENABLE_AUD10x0304
+#define MUX_STAT_AUD0 0x0400
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define DIV_STAT_AUD0 0x0700
+#define DIV_STAT_AUD1 0x0704
+#define ENABLE_ACLK_AUD0x0800
+#define ENABLE_PCLK_AUD0x0900
+#define ENABLE_SCLK_AUD0 0x0a00
+#define ENABLE_SCLK_AUD1 0x0a04
+#define ENABLE_IP_AUD0 0x0b00
+#define ENABLE_IP_AUD1 0x0b04
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD0,
+ MUX_SEL_AUD1,
+ MUX_ENABLE_AUD0,
+ MUX_ENABLE_AUD1,
+ MUX_STAT_AUD0,
+ DIV_AUD0,
+ DIV_AUD1,
+ DIV_STAT_AUD0,
+ DIV_STAT_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD0,
+ ENABLE_SCLK_AUD1,
+ ENABLE_IP_AUD0,
+ ENABLE_IP_AUD1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aud_pll_user_aud_p) = { fin_pll, fout_aud_pll, };
+PNAME(mout_sclk_aud_pcm_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
+PNAME(mout_sclk_aud_i2s_p) = { mout_aud_pll_user, ioclk_audiocdclk0,};
Above two lines can be clubbed with some common name as both has same
parent clocks.
+
+static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
+ FRATE(0, ioclk_jtag_tclk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_slimbus_clk, NULL, CLK_IS_ROOT, 18800),
+ FRATE(0, ioclk_i2s_bclk, NULL, CLK_IS_ROOT, 18800),
Are you sure about these clock rates?
As per UM I have, these are having rates as 33 MHz, 25 MHz and 50 MHz
respectively.
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ /* MUX_SEL_AUD0 */
+ MUX(CLK_MOUT_AUD_PLL_USER, mout_aud_pll_user,
+ mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
+
+ /* MUX_SEL_AUD1 */
+ MUX(CLK_MOUT_SCLK_AUD_PCM, mout_sclk_aud_pcm, mout_sclk_aud_pcm_p,
+ MUX_SEL_AUD1, 8, 1),
+ MUX(CLK_MOUT_SCLK_AUD_I2S, mout_sclk_aud_i2s, mout_sclk_aud_i2s_p,
+ MUX_SEL_AUD1, 0, 1),
+};
+
Thanks,
Pankaj Dubey
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Re: [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 9 +
drivers/clk/samsung/clk-exynos5433.c | 465 -
include/dt-bindings/clock/exynos5433.h | 114 -
3 files changed, 577 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 27dd77b..8d3dad4 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -21,6 +21,8 @@ Required Properties:
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- samsung,exynos5433-cmu-g2d - clock controller compatible for CMU_G2D
which generates clocks for G2D/MDMA IPs.
+ - samsung,exynos5433-cmu-disp - clock controller compatible for CMU_DISP
+which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed
below.
#clock-cells = 1;
};
+ cmu_disp: clock-controller@0x13b9 {
+ compatible = samsung,exynos5433-cmu-disp;
+ reg = 0x13b9 0x0c04;
+ #clock-cells = 1;
+ };
+
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 10197a1..ec23e97 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { ioclk_audiocdclk1,
fin_pll,
PNAME(mout_sclk_audio0_p) = { ioclk_audiocdclk0, fin_pll,
mout_aud_pll_user_t,};
+PNAME(mout_sclk_hdmi_spdif_p) = { sclk_audio1, ioclk_spdif_extclk, };
+
static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata =
{
FFACTOR(0, sclk_bus_pll, fout_bus_pll, 1, 1, 0),
FFACTOR(0, sclk_mfc_pll, fout_mfc_pll, 1, 1, 0),
@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata
= {
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, mout_sclk_audio0, mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
+
+ /* MUX_SEL_TOP_DISP */
+ MUX(CLK_MOUT_SCLK_HDMI_SPDIF, mout_sclk_hdmi_spdif,
+ mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, aclk_bus2_400, div_aclk_bus2_400,
- ENABLE_ACLK_MIF3, 4, 0, 0),
+ ENABLE_ACLK_MIF3, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP_333, aclk_disp_333, div_aclk_disp_333,
- ENABLE_ACLK_MIF3, 1, 0, 0),
+ ENABLE_ACLK_MIF3, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CPIF_200, aclk_cpif_200, div_aclk_cpif_200,
ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),
@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[]
__initdata = {
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, sclk_dsim1_disp, div_sclk_dsim1,
- ENABLE_SCLK_MIF, 15, 0, 0),
+ ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, sclk_decon_tv_vclk_disp,
- div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF, 14, 0, 0),
+ div_sclk_decon_tv_vclk, ENABLE_SCLK_MIF,
+ 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, sclk_dsim0_disp, div_sclk_dsim0,
- ENABLE_SCLK_MIF, 9, 0, 0),
+ ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, sclk_dsd_disp, div_sclk_dsd,
- ENABLE_SCLK_MIF, 8, 0, 0),
+ ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, sclk_decon_tv_eclk_disp,
-
Re: [PATCH] dmaengine: pl330: Set residue in tx_status callback
On Mon, Dec 08, 2014 at 02:23:21PM +, Russell King - ARM Linux wrote: On Mon, Dec 08, 2014 at 06:37:27PM +0530, Vinod Koul wrote: I actually like the split model, you can also prepare txn ahead of time and submit them when needed. Actually, you can't - that's not permitted. I have email(s) from Dan explicitly stating that it is permitted for a driver to take a spinlock in their prepare callback, and release it when the descriptor is submitted. Several DMA engine drivers (particularly those in for async_tx) do exactly that. The reason that submit is separate from prepare is to allow DMA engine users to set a callback - if it weren't for that, there wouldn't be a submit step, prepare would have done everything. Yes thats right. Do you mind pointing to thread Dan replied, I would like to add these bits and anything else missing to Documentation Thanks -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
On Tuesday 09 December 2014 06:42 AM, Chanwoo Choi wrote:
Hi Pankaj,
On 12/08/2014 08:31 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 80
+-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 88e8cac..a48b36c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[]
__initdata = {
FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+/* XspiCLK[4:0] input clock for SPI */
+FRATE(0, ioclk_spi4_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi3_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi2_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi1_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi0_clk_in, NULL, CLK_IS_ROOT, 5000),
+/* Xi2s1SCLK input clock for I2S1_BCLK */
+FRATE(0, ioclk_i2s1_bclk_in, NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC0x0600
+#define DIV_STAT_PERIC0x0700
#define ENABLE_ACLK_PERIC0x0800
#define ENABLE_PCLK_PERIC00x0900
#define ENABLE_PCLK_PERIC10x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+DIV_STAT_PERIC,
IMO, this line should have been added in first place itself when you added
peric_clk_regs.
Why? I want to locate it according to address base.
Since DIV_PERIC and DIV_STAT_PERIC both has same address base, why not
to add DIV_STAT_PERIC at the same place when you added DIV_PERIC?
Anyways, this was just my opinion as I don't see any dependency why we
should add it here? I left this up to you.
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+/* DIV_PERIC */
+DIV(CLK_DIV_SCLK_SCI, div_sclk_sci, fin_pll, DIV_PERIC, 4, 8),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo Choi
Thanks,
Pankaj Dubey
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Re: [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
Hi Chanwoo, On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote: This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains the clocks for GPU(3D Graphics Engine). Cc: Sylwester Nawrocki s.nawro...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com Acked-by: Inki Dae inki@samsung.com Acked-by: Geunsik Lim geunsik@samsung.com Reviewed-by: Pankaj Dubey pankaj.du...@samsung.com Thanks, Pankaj Dubey -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
On 12/09/2014 03:13 PM, Pankaj Dubey wrote:
On Tuesday 09 December 2014 06:42 AM, Chanwoo Choi wrote:
Hi Pankaj,
On 12/08/2014 08:31 PM, Pankaj Dubey wrote:
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be
always on.]
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
drivers/clk/samsung/clk-exynos5433.c | 80
+-
include/dt-bindings/clock/exynos5433.h | 34 ++-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 88e8cac..a48b36c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock
top_fixed_clks[] __initdata = {
FRATE(0, ioclk_audiocdclk0, NULL, CLK_IS_ROOT, 1),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, ioclk_spdif_extclk, NULL, CLK_IS_ROOT, 1),
+/* XspiCLK[4:0] input clock for SPI */
+FRATE(0, ioclk_spi4_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi3_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi2_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi1_clk_in, NULL, CLK_IS_ROOT, 5000),
+FRATE(0, ioclk_spi0_clk_in, NULL, CLK_IS_ROOT, 5000),
+/* Xi2s1SCLK input clock for I2S1_BCLK */
+FRATE(0, ioclk_i2s1_bclk_in, NULL, CLK_IS_ROOT, 12288000),
};
static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC0x0600
+#define DIV_STAT_PERIC0x0700
#define ENABLE_ACLK_PERIC0x0800
#define ENABLE_PCLK_PERIC00x0900
#define ENABLE_PCLK_PERIC10x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif,
samsung,exynos5433-cmu-mif,
static unsigned long peric_clk_regs[] __initdata = {
DIV_PERIC,
+DIV_STAT_PERIC,
IMO, this line should have been added in first place itself when you added
peric_clk_regs.
Why? I want to locate it according to address base.
Since DIV_PERIC and DIV_STAT_PERIC both has same address base, why not to add
DIV_STAT_PERIC at the same place when you added DIV_PERIC?
I mean the register offset instead of address base.
DIV_PERIC(0x0600) is less than DIV_STAT_PERIC(0x0700).
So, I want to locate DIV_STAT_PERIC on behind DIV_PERIC in ascending order.
But, It is just minor issue.
Best Regards,
Chanwoo Choi
Anyways, this was just my opinion as I don't see any dependency why we should
add it here? I left this up to you.
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
ENABLE_IP_PERIC2,
};
+static struct samsung_div_clock peric_div_clks[] __initdata = {
+/* DIV_PERIC */
+DIV(CLK_DIV_SCLK_SCI, div_sclk_sci, fin_pll, DIV_PERIC, 4, 8),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo Choi
Thanks,
Pankaj Dubey
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Re: [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
Hi Chanwoo,
On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 144 +
include/dt-bindings/clock/exynos5433.h | 37 +-
3 files changed, 188 insertions(+), 1 deletion(-)
[snip]
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, samsung,exynos5433-cmu-g3d,
exynos5433_cmu_g3d_init);
+
+/*
+ * Register offset definitions for CMU_GSCL
+ */
+#define MUX_SEL_GSCL 0x0200
+#define MUX_ENABLE_GSCL0x0300
+#defineMUX_STAT_GSCL 0x0400
+#defineENABLE_ACLK_GSCL0x0800
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
+#defineENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
+#defineENABLE_PCLK_GSCL0x0900
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
+#defineENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
+#defineENABLE_IP_GSCL0 0x0b00
+#defineENABLE_IP_GSCL1 0x0b04
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL00x0b08
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL10x0b0c
+#defineENABLE_IP_GSCL_SECURE_SMMU_GSCL20x0b10
+
nit: tabspace after #define should be changed to one whitespace.
+static unsigned long gscl_clk_regs[] __initdata = {
+ MUX_SEL_GSCL,
+ MUX_ENABLE_GSCL,
+ MUX_STAT_GSCL,
+ ENABLE_ACLK_GSCL,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_PCLK_GSCL,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
+ ENABLE_IP_GSCL0,
+ ENABLE_IP_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
+ ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
+};
+
+/* list of all parent clock list */
+PNAME(aclk_gscl_111_user_p)= { fin_pll, aclk_gscl_111, };
+PNAME(aclk_gscl_333_user_p)= { fin_pll, aclk_gscl_333, };
+
+static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
+ /* MUX_SEL_GSCL */
+ MUX(CLK_MOUT_ACLK_GSCL_111_USER, mout_aclk_gscl_111_user,
+ aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
+ MUX(CLK_MOUT_ACLK_GSCL_333_USER, mout_aclk_gscl_333_user,
+ aclk_gscl_333_user_p, MUX_SEL_GSCL, 4, 1),
aclk_gscl_333_user mux clock has a shift of '0'.
+};
+
Thanks,
Pankaj Dubey
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