[RESEND PATCH v3] clocksource: exynos_mct: Add the support for Exynos 64bit SoC

[Chanwoo Choi]

This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.

Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
This patch set is tested on 64-bit Exynos SoC. I send only this patch from
following patchst[1].
[1] https://lkml.org/lkml/2014/12/2/134

Changes from v2:
- None
Changes from v1:
- Use CONFIG_ARM instead of CONFIG_ARM64

 drivers/clocksource/Kconfig  | 1 -
 drivers/clocksource/exynos_mct.c | 4 
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fc01ec2..be38119 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -135,7 +135,6 @@ config CLKSRC_METAG_GENERIC
 
 config CLKSRC_EXYNOS_MCT
def_bool y if ARCH_EXYNOS
-   depends on !ARM64
help
  Support for Multi Core Timer controller on Exynos SoCs.
 
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 9403061..b840ea1 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
 }
 
+#if defined(CONFIG_ARM)
 static struct delay_timer exynos4_delay_timer;
 
 static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
 cycles_t needs to move to 32-bit for ARM64 usage);
return exynos4_read_count_32();
 }
+#endif
 
 static void __init exynos4_clocksource_init(void)
 {
exynos4_mct_frc_start();
 
+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(exynos4_delay_timer);
+#endif
 
if (clocksource_register_hz(mct_frc, clk_rate))
panic(%s: can't register clocksource\n, mct_frc.name);
-- 
1.8.5.5

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Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 13/01/15 06:09, Linus Walleij wrote:

Hi Linus,

 On Mon, Jan 12, 2015 at 7:26 PM, Marc Zyngier marc.zyng...@arm.com wrote:
 
 IMX6 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the GPC block is actually the first
 interrupt controller in the chain, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs won't even boot.

 Tested-by: Stefan Agner ste...@agner.ch
 Acked-by: Stefan Agner ste...@agner.ch
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 
 (...)
 
 +static int imx_gpc_domain_alloc(struct irq_domain *domain,
 + unsigned int virq,
 
 Nutcase nitpick on this nice patch series: every time I see virq my
 OCD triggers, as I think the v in virq stand for virtual. These irqs
 are no more virtual than any other Linux irq numbers, hwirq is
 more to the point.
 
 I just refer to these as irq (sans v) in any code I write.

That's fair enough. I'll update that as I fix some other nits.

Thanks,

M.
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Re: [PATCH v3 14/21] ARM: imx6: convert GPC to stacked domains

[Marc Zyngier]

On 12/01/15 19:00, Stefan Agner wrote:
 Hi Marc,
 
 On 2015-01-12 19:26, Marc Zyngier wrote:
 IMX6 has been (ab)using the gic_arch_extn to provide
 wakeup from suspend, and it makes a lot of sense to convert
 this code to use stacked domains instead.

 This patch does just this, updating the DT files to actually
 reflect what the HW provides.

 BIG FAT WARNING: because the DTs were so far lying by not
 exposing the fact that the GPC block is actually the first
 interrupt controller in the chain, kernels with this patch
 applied wont have any suspend-resume facility when booted
 with old DTs, and old kernels with updated DTs won't even boot.

 Tested-by: Stefan Agner ste...@agner.ch
 Acked-by: Stefan Agner ste...@agner.ch
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 ---
  arch/arm/boot/dts/imx6qdl.dtsi  |   7 ++-
  arch/arm/boot/dts/imx6sl.dtsi   |   5 +-
  arch/arm/boot/dts/imx6sx.dtsi   |   5 +-
  arch/arm/mach-imx/common.h  |   1 -
  arch/arm/mach-imx/gpc.c | 127 
 
  arch/arm/mach-imx/mach-imx6q.c  |   1 -
  arch/arm/mach-imx/mach-imx6sl.c |   1 -
  arch/arm/mach-imx/mach-imx6sx.c |   1 -
  8 files changed, 117 insertions(+), 31 deletions(-)

 diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
 index 4fc03b7..aff9ded 100644
 --- a/arch/arm/boot/dts/imx6qdl.dtsi
 +++ b/arch/arm/boot/dts/imx6qdl.dtsi
 @@ -53,6 +53,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -82,7 +83,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   dma_apbh: dma-apbh@0011 {
 @@ -122,6 +123,7 @@
   compatible = arm,cortex-a9-twd-timer;
   reg = 0x00a00600 0x20;
   interrupts = 1 13 0xf01;
 + interrupt-parent = intc;
   clocks = clks IMX6QDL_CLK_TWD;
   };

 @@ -694,8 +696,11 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 + #interrupt-cells = 3;
   interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH,
0 90 IRQ_TYPE_LEVEL_HIGH;
 + interrupt-parent = intc;
   };

   gpr: iomuxc-gpr@020e {
 diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
 index 36ab8e0..35099b7 100644
 --- a/arch/arm/boot/dts/imx6sl.dtsi
 +++ b/arch/arm/boot/dts/imx6sl.dtsi
 @@ -72,6 +72,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -95,7 +96,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   ocram: sram@0090 {
 @@ -603,7 +604,9 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6sl-gpc, fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 
 GPC is in three base device trees, and missing in all of them. So the
 first is fixed
 
 this one...
 
   interrupts = 0 89 IRQ_TYPE_LEVEL_HIGH;
 + interrupt-parent = intc;
   };

   gpr: iomuxc-gpr@020e {
 diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
 index 7a24fee..c476e67 100644
 --- a/arch/arm/boot/dts/imx6sx.dtsi
 +++ b/arch/arm/boot/dts/imx6sx.dtsi
 @@ -88,6 +88,7 @@
   interrupt-controller;
   reg = 0x00a01000 0x1000,
 0x00a00100 0x100;
 + interrupt-parent = intc;
   };

   clocks {
 @@ -131,7 +132,7 @@
   #address-cells = 1;
   #size-cells = 1;
   compatible = simple-bus;
 - interrupt-parent = intc;
 + interrupt-parent = gpc;
   ranges;

   pmu {
 @@ -700,7 +701,9 @@
   gpc: gpc@020dc000 {
   compatible = fsl,imx6sx-gpc, fsl,imx6q-gpc;
   reg = 0x020dc000 0x4000;
 + interrupt-controller;
 
 
 ... and this one is still missing.
 
 Sorry I did not see that the first review.

I thought I had them fixed on Sunday, but it looks like I've dropped the
fixup 

Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem

[Javier Martinez Canillas]

On 01/14/2015 01:19 AM, Javier Martinez Canillas wrote:
 
 I dug further on this issue and found that the cause is that the exynos_mixer
 driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
 to be kept enabled after hdmi_poweroff (drivers/gpu/drm/exynos/exynos_hdmi.c).
 
 Otherwise, any access to mixer device registers leads to an imprecise external
 abort error. The following change [0] to the Exynos DRM HDMI driver makes the
 issue to not happen and I can successfully execute:
 
 # echo 1  /sys/devices/platform/exynos-drm/graphics/fb0/blank
 # echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank
 
 Only not disabling the hdmi clock [1]: is enough but doing so makes sometimes 
 the
 DISP1 power domain disabling fails. It doesn't seem to have side effect though
 since I also see the signal in the HDMI display to go standby and then on 
 again.
 
 # echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank
 # echo 1  /sys/devices/platform/exynos-drm/graphics/fb0/blank
 [   63.089080] Power domain disp1-power-domain disable failed
 # echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank
 #
 
 That error message when both clocks are not disabled on hdmi_poweroff() 
 though.
 

This should be: That error message is not shown when both clocks are disabled.

Best regards,
Javier
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Re: [PATCH v3] ARM: exynos_defconfig Enable CONFIG_LOCKUP_DETECTOR.

[Krzysztof Kozlowski]

On wto, 2015-01-13 at 00:20 +0530, Anand Moon wrote:
 On enabling CONFIG_LOCKUP_DETECTOR the kernel to act as a watchdog
 to detect hard and soft lockups. Enabling CONFIG_LOCKUP_DETECTOR
 don't introduce much overhead on exyons SOC.
 
 CONFIG_LOCKUP_DETECTOR is enabled on multi_v7_defconfig.
 
 Changes since v3:
  * Made commit message more clear
  * Corrected difference between CONFIG_LOCKUP_DETECTOR and CONFIG_LOCKDEP.
 
 Tested on Exynos5422 ODROID XU3 board.
 
 Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
 Signed-off-by: Anand Moon moon.li...@yahoo.com

Now it looks okay. My reviewed-by may stay on.

Best regards,
Krzysztof

 ---
  arch/arm/configs/exynos_defconfig | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/arch/arm/configs/exynos_defconfig 
 b/arch/arm/configs/exynos_defconfig
 index 5ef14de..64b2fe9 100644
 --- a/arch/arm/configs/exynos_defconfig
 +++ b/arch/arm/configs/exynos_defconfig
 @@ -182,6 +182,7 @@ CONFIG_DETECT_HUNG_TASK=y
  CONFIG_DEBUG_RT_MUTEXES=y
  CONFIG_DEBUG_SPINLOCK=y
  CONFIG_DEBUG_MUTEXES=y
 +CONFIG_LOCKUP_DETECTOR=y
  CONFIG_DEBUG_INFO=y
  CONFIG_DEBUG_USER=y
  CONFIG_CRYPTO_SHA256=y

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Re: [PATCHv3 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver

[Chanwoo Choi]

Dear Myungjoo,

On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
   
  This patch adds the generic exynos bus frequency driver for memory bus
 with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
 for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
 support the memory bus frequency driver for Exynos SoCs.

 Each memory bus block has a clock for memory bus speed and frequency
 table which is changed according to the utilization of memory bus on runtime.
 And then each memory bus group has the one more memory bus blocks and
 OPP table (including frequency and voltage), regulator, devfreq-event
 devices.

 There are a little difference about the number of memory bus because each 
 Exynos
 SoC have the different sub-IP and different memory bus speed. In spite of 
 this
 difference among Exynos SoCs, we can support almost Exynos SoC by adding
 unique data of memory bus to devicetree file.

 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Cc: Kukjin Kim kg...@kernel.org
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---
  drivers/devfreq/Kconfig  |  15 +
  drivers/devfreq/Makefile |   1 +
  drivers/devfreq/exynos-busfreq.c | 589 
 +++
  3 files changed, 605 insertions(+)
  create mode 100644 drivers/devfreq/exynos-busfreq.c
 
 Exynos drivers are located at drivers/devfreq/exynos/
 Please relocate/rename exynos-busfreq.c

OK. I'll move it at drivers/devfreq/exynos directory.
Do you prefer 'exynos-bus.c' instead of 'exynos-busfreq.c'?
If you reply, I'll change it.

 
 []
 
 diff --git a/drivers/devfreq/exynos-busfreq.c 
 b/drivers/devfreq/exynos-busfreq.c
 new file mode 100644
 index 000..b180f43
 --- /dev/null
 +++ b/drivers/devfreq/exynos-busfreq.c
 
 []
 
 +
 +#define BUS_SATURATION_RATIO40
 
 In order to be a common driver, this should be tunable.
 
 Because .dts is supposed to have hardware configuration only,
 you may keep a table of { chip-name, saturation ratio} in this
 driver and look up the saturation ratio based on the chip-name.

OK, I'll add new property for saturation_ratio.

I'll implement to use default saturation_ratio value ,
if dt node don't include saturation_ratio property.

 
 +#define SAFEVOLT5
 +
 +struct exynos_memory_bus_opp_info {
 +unsigned long rate;
 +unsigned long volt;
 +};
 +
 +struct exynos_memory_bus_block {
 +struct clk *clk;
 +struct exynos_memory_bus_opp_info *freq_table;
 +};
 +
 
 []
 
 +#ifdef CONFIG_PM_SLEEP
 +static int exynos_busfreq_resume(struct device *dev)
 +{
 +struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
 +int ret;
 +
 +ret = exynos_busfreq_enable_edev(data);
 +if (ret  0) {
 +dev_err(dev, failed to enable the devfreq-event devices\n);
 +return ret;
 +}
 +
 +return 0;
 +}
 +
 +static int exynos_busfreq_suspend(struct device *dev)
 +{
 +struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
 +int ret;
 +
 +ret = exynos_busfreq_disable_edev(data);
 +if (ret  0) {
 +dev_err(dev, failed to disable the devfreq-event devices\n);
 +return ret;
 +}
 +
 +return 0;
 +}
 +#endif
 
 Please disable regulator at suspend and resume it at resume.
 
 You may interfere with low-power mode of corresponding voltage line,
 which is often implemented to be activated if the regulator is
 explicitely disabled for alive regulators like this one.

OK, I'll modify it.

Thanks for your review.

Best Regards,
Chanwoo Choi
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Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem

[Joonyoung Shim]

On 01/13/2015 02:24 PM, Joonyoung Shim wrote:
 Hi,
 
 On 01/13/2015 01:09 AM, Javier Martinez Canillas wrote:
 Hello Joonyoung,

 On 01/12/2015 07:40 AM, Joonyoung Shim wrote:
 And also making changes to the clocks in the clk-exynos5420 driver. Can
 you please explain the rationale for those changes? I'm asking because
 without your clock changes (only adding the DISP1 pd and making the
 devices as consumers), I've HDMI output too but video is even worse. This
 [0] is the minimal change I have on top of 3.19-rc3 to have some output.


 I just refer below patches,
 http://comments.gmane.org/gmane.linux.kernel.samsung-soc/34576

 But i'm not sure whether DISP1 power domain is same case with MFC power 
 domain.


 Thanks a lot for sharing those patches, now your changes are much more
 clear to me.


 So there seems to be two issues here, one is the mixer and hdmi modules not
 being attached to the DISP1 power domain and another one is the clocks 
 setup
 not being correct to have proper HDMI video output.
  

 Hmm, i can see normal hdmi output still from latest upstream
 kernel(3.19-rc4) with my kernel changes and u-boot changes(DISP1 power
 domain disable) of prior mail on odroid xu3 board.


 I thought you said on another email that after commit 2ed127697eb1 which
 landed on 3.19-rc1 you had bad HDMI output?

 In your changes, it was missing the SW_ACLK_400_DISP1 and USER_ACLK_400_DISP1
 clock mux outputs that goes to internal buses in the DISP1. Adding IDs for
 these in the exynos5420 clock driver and to the parent and input clock paris
 list in the DISP1 power domain gives me a good HDMI output on 3.19-rc2.

 Also, the SW_ACLK_300_DISP1 and USER_ACLK_300_DISP1 are needed for the FIMD
 parent and input clock respectively. Adding those to the clocks list of the
 DISP1 power domain gives me working display + HDMI on my Exynos5800 Peach Pi.

 These are the changes I have now [0]. Please let me know what you think.

 
 Good, it's working with your patch without u-boot changes and reverting
 of commit 2ed127697eb.
 

But i also get stripe hdmi output if hdmi/mixer drivers aren't defered
probed, because DISP1 power domain isn't disabled on booting by defered
probe so is always on.

Thanks.
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Re: [PATCH v2 06/17] thermal: cpu_cooling: dts: Define device tree bindings for Exynos cpu cooling functionality

[Lukasz Majewski]

Hi Eduardo,

 
 On Mon, Jan 12, 2015 at 03:09:16PM +0100, Lukasz Majewski wrote:
  Hi Eduardo,
  
Presented patch aims to move data necessary for correct CPU
cooling device configuration from exynos_tmu_data.c to device
tree.  
   
   I believe the patch title is misleading. Looks like you are
   changing something at cpu cooling, but in fact, you are changing
   DTS files. I would suggest you to use a prefix like 'arm:
   dts: '
  
  Now this patch name is:
  thermal: cpu_cooling: dts: ..
  
  All the code in this patch adds bindings for 'thermal-zone' to map
  cooling device to proper trip points.
  In fact this is solely related to cpu_cooling...
  
  From the above, I think that the already provided convention is more
  suitable and arm: dts: cpu_cooling: thermal seems a bit awkward
  for me.
  
  If you don't regard my justification as valid, then I will fix this.
 
 Still, the naming is confusing. With that prefix you are saying this
 patch is something generic about cpu cooling and thermal dts. And that
 is not what this patch is about.
 
 Saying arm: dts: add cpu cooling bindings for Exynos is a short and
 direct subject. Besides, you have the plus to call the attention of
 the ARM and device tree maintainers. It will be also in my radar.

Fair enough. Thanks for clarification.

 
 
 The original subject also makes me think you are dealing with C code,
 while the former says already upfront that you are talking about arm
 dts bindings. 
 
 Cheers,
  
  -- 
  Best regards,
  
  Lukasz Majewski
  
  Samsung RD Institute Poland (SRPOL) | Linux Platform Group



-- 
Best regards,

Lukasz Majewski

Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: Re: [PATCHv3 2/8] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver

[MyungJoo Ham]

Acked-by: MyungJoo Ham myungjoo@samsung.com


Adding to Chanwoo's reply:

If I understand Chanwoo's intention correctly,
this patchset is to provide a common bus  memory-interface DVFS driver
for several Exynos SoCs, which allows DT to express per-SoC hardware
details so that we do not need to hardcode them with seperated drivers
(as it is now) or a driver with a lot of unused definitions (partly
as it is now).

Having that many looking ugly frequency definitions is
because Exynos SoCs that I've seen until today have many
on-SoC IPs that should change configurations (usually clock speed)
according to the clock speed of bus. Thus, they may look
duplicated.

We may hide such details IF we make one driver per SoC model; however,
it is very inefficient with DT supported kernels if we can write
such details in DTS and make the driver simple and unified.



Cheers,
MyungJoo.

  
 Hi Rob,

First of all, thanks for your review.

On 01/09/2015 06:18 AM, Rob Herring wrote:
 Adding Viresh.
 
 On Wed, Jan 7, 2015 at 7:40 PM, Chanwoo Choi cw00.c...@samsung.com wrote:
 This patch adds the documentation for generic exynos memory bus frequency
 driver.

 Cc: MyungJoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Cc: Kukjin Kim kg...@kernel.org
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---
  .../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 
 +
  1 file changed, 184 insertions(+)
  create mode 100644 
 Documentation/devicetree/bindings/devfreq/exynos-busfreq.txt

Re: Re: [PATCHv3 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver

[MyungJoo Ham]

  
 Dear Myungjoo,

On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
   
  This patch adds the generic exynos bus frequency driver for memory bus
 with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
 for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
 support the memory bus frequency driver for Exynos SoCs.

 Each memory bus block has a clock for memory bus speed and frequency
 table which is changed according to the utilization of memory bus on 
 runtime.
 And then each memory bus group has the one more memory bus blocks and
 OPP table (including frequency and voltage), regulator, devfreq-event
 devices.

 There are a little difference about the number of memory bus because each 
 Exynos
 SoC have the different sub-IP and different memory bus speed. In spite of 
 this
 difference among Exynos SoCs, we can support almost Exynos SoC by adding
 unique data of memory bus to devicetree file.

 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Cc: Kukjin Kim kg...@kernel.org
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---
  drivers/devfreq/Kconfig  |  15 +
  drivers/devfreq/Makefile |   1 +
  drivers/devfreq/exynos-busfreq.c | 589 
 +++
  3 files changed, 605 insertions(+)
  create mode 100644 drivers/devfreq/exynos-busfreq.c
 
 Exynos drivers are located at drivers/devfreq/exynos/
 Please relocate/rename exynos-busfreq.c

OK. I'll move it at drivers/devfreq/exynos directory.
Do you prefer 'exynos-bus.c' instead of 'exynos-busfreq.c'?
If you reply, I'll change it.

exynos-bus looks more pretty :)


 
 []
 
 diff --git a/drivers/devfreq/exynos-busfreq.c 
 b/drivers/devfreq/exynos-busfreq.c
 new file mode 100644
 index 000..b180f43
 --- /dev/null
 +++ b/drivers/devfreq/exynos-busfreq.c
 
 []
 
 +
 +#define BUS_SATURATION_RATIO   40
 
 In order to be a common driver, this should be tunable.
 
 Because .dts is supposed to have hardware configuration only,
 you may keep a table of { chip-name, saturation ratio} in this
 driver and look up the saturation ratio based on the chip-name.

OK, I'll add new property for saturation_ratio.

I'll implement to use default saturation_ratio value ,
if dt node don't include saturation_ratio property.

Yes. I didn't talk with DT maintainers and I do not have much
experience with DT; however, it appears that such values are not
recommended to be in DTS files and this value is determined by
the SoC model number without complications in the driver file.

Re: [PATCHv3 3/8] ARM: dts: Add memory bus node for Exynos3250

[MyungJoo Ham]

   
  This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
 following memory buses to translate data between DRAM and eMMC/sub-IPs.
 
 Following list specifies the detailed relation between memory bus clock and 
 DMC
 IP in MIF (Memory Interface) block:
 - DMC clock : DMC (Dynamic Memory Controller)
 
 Following list specifies the detailed relation between memory bus clock and
 sub-IPs in INT (Internal) block:
 - ACLK100 clock : PERIL
 - ACLK160 clock : LCD0
 - ACLK200 clock : FSYS
 - ACLK266 clock : ISP
 - GDL/GDR clock : leftbus/rightbus
 - SCLK_MFC clock : MFC
 
 Cc: Kukjin Kim kg...@kernel.org
 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 Acked-by: Kyungmin Park kyungmin.p...@samsung.com

Acked-by: MyungJoo Ham myungjoo@samsung.com



 ---
  arch/arm/boot/dts/exynos3250.dtsi | 125 
 ++
  1 file changed, 125 insertions(+)
 
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Re: [PATCHv3 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver

[MyungJoo Ham]

   
  This patch adds the generic exynos bus frequency driver for memory bus
 with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
 for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
 support the memory bus frequency driver for Exynos SoCs.
 
 Each memory bus block has a clock for memory bus speed and frequency
 table which is changed according to the utilization of memory bus on runtime.
 And then each memory bus group has the one more memory bus blocks and
 OPP table (including frequency and voltage), regulator, devfreq-event
 devices.
 
 There are a little difference about the number of memory bus because each 
 Exynos
 SoC have the different sub-IP and different memory bus speed. In spite of this
 difference among Exynos SoCs, we can support almost Exynos SoC by adding
 unique data of memory bus to devicetree file.
 
 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Cc: Kukjin Kim kg...@kernel.org
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---
  drivers/devfreq/Kconfig  |  15 +
  drivers/devfreq/Makefile |   1 +
  drivers/devfreq/exynos-busfreq.c | 589 
 +++
  3 files changed, 605 insertions(+)
  create mode 100644 drivers/devfreq/exynos-busfreq.c

Exynos drivers are located at drivers/devfreq/exynos/
Please relocate/rename exynos-busfreq.c

[]

 diff --git a/drivers/devfreq/exynos-busfreq.c 
 b/drivers/devfreq/exynos-busfreq.c
 new file mode 100644
 index 000..b180f43
 --- /dev/null
 +++ b/drivers/devfreq/exynos-busfreq.c

[]

 +
 +#define BUS_SATURATION_RATIO 40

In order to be a common driver, this should be tunable.

Because .dts is supposed to have hardware configuration only,
you may keep a table of { chip-name, saturation ratio} in this
driver and look up the saturation ratio based on the chip-name.

 +#define SAFEVOLT 5
 +
 +struct exynos_memory_bus_opp_info {
 + unsigned long rate;
 + unsigned long volt;
 +};
 +
 +struct exynos_memory_bus_block {
 + struct clk *clk;
 + struct exynos_memory_bus_opp_info *freq_table;
 +};
 +

[]

 +#ifdef CONFIG_PM_SLEEP
 +static int exynos_busfreq_resume(struct device *dev)
 +{
 + struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
 + int ret;
 +
 + ret = exynos_busfreq_enable_edev(data);
 + if (ret  0) {
 + dev_err(dev, failed to enable the devfreq-event devices\n);
 + return ret;
 + }
 +
 + return 0;
 +}
 +
 +static int exynos_busfreq_suspend(struct device *dev)
 +{
 + struct exynos_memory_bus_data *data = dev_get_drvdata(dev);
 + int ret;
 +
 + ret = exynos_busfreq_disable_edev(data);
 + if (ret  0) {
 + dev_err(dev, failed to disable the devfreq-event devices\n);
 + return ret;
 + }
 +
 + return 0;
 +}
 +#endif

Please disable regulator at suspend and resume it at resume.

You may interfere with low-power mode of corresponding voltage line,
which is often implemented to be activated if the regulator is
explicitely disabled for alive regulators like this one.

 +
 +static const struct dev_pm_ops exynos_busfreq_pm = {
 + SET_SYSTEM_SLEEP_PM_OPS(exynos_busfreq_suspend, exynos_busfreq_resume)
 +};
 +
 +static const struct of_device_id exynos_busfreq_of_match[] = {
 + { .compatible = samsung,exynos-memory-bus, },
 + { /* sentinel */ },
 +};
 +MODULE_DEVICE_TABLE(of, exynos_busfreq_of_match);
 +
 +static struct platform_driver exynos_busfreq_platdrv = {
 + .probe  = exynos_busfreq_probe,
 + .remove = exynos_busfreq_remove,
 + .driver = {
 + .name   = exynos-memory-bus,
 + .owner  = THIS_MODULE,
 + .pm = exynos_busfreq_pm,
 + .of_match_table = of_match_ptr(exynos_busfreq_of_match),
 + },
 +};
 +module_platform_driver(exynos_busfreq_platdrv);
 +
 +MODULE_DESCRIPTION(Generic Exynos Memory Bus Frequency driver);
 +MODULE_AUTHOR(Chanwoo Choi cw00.c...@samsung.com);
 +MODULE_LICENSE(GPL v2);
 -- 
 1.8.5.5
 
 

Re: [PATCH v2 1/6] ARM: Exynos: add support for sub-power domains

[Ulf Hansson]

On 13 January 2015 at 11:53, Marek Szyprowski m.szyprow...@samsung.com wrote:
 Hello,


 On 2015-01-13 11:44, Ulf Hansson wrote:

 On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com
 wrote:

 This patch adds support for making one power domain a sub-domain of
 other domain. This is useful for modeling power dependences for devices
 like TV Mixer or Camera ISP, which needs to have more than one power
 domain enabled to be operational.

 Based on previous work by Amit Daniel Kachhap amit.dan...@samsung.com.

 Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
 ---
   .../bindings/arm/exynos/power_domain.txt   |  2 ++
   arch/arm/mach-exynos/pm_domains.c  | 28
 ++
   2 files changed, 30 insertions(+)

 diff --git
 a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 index f4445e5..28918a9 100644
 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 @@ -22,6 +22,8 @@ Optional Properties:
  - pclkN, clkN: Pairs of parent of input clock and input clock to
 the
  devices in this power domain. Maximum of 4 pairs (N = 0
 to 3)
  are supported currently.
 +- power-domains: generic power domain binding pointing to a master power
 domain
 +that the given domain is a part of

 I would prefer this to be documented as a generic way to configure
 power domain parents, in
 Documentation/devicetree/bindings/power/power_domain.txt.


 Well, right now it is a specific feature of exynos power domains, however if
 you
 want I can add a note in
 Documentation/devicetree/bindings/power/power_domain.txt
 on defining child-parent relation. However it will be still up to the power
 domain
 providers to implement support for it.

We don't want one solution per provider to describe child-parent
relations of PM domains in DT, that why I think it's important that we
document this in
Documentation/devicetree/bindings/power/power_domain.txt

Kind regards
Uffe
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[PATCH v2 5/6] ARM: dts: exynos4210-universal_c210: enable hdmi support

[Marek Szyprowski]

From: Tomasz Stanislawski t.stanisl...@samsung.com

This patch adds configuration of hw modules required to enable HDMI
support on Universal C210 board.

Signed-off-by: Tomasz Stanislawski t.stanisl...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 arch/arm/boot/dts/exynos4210-universal_c210.dts | 57 +
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts 
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index aaf0cae..01f7d3c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -503,6 +503,63 @@
assigned-clock-rates = 0, 16000;
};
};
+
+   hdmi_en: voltage-regulator-hdmi-5v {
+   compatible = regulator-fixed;
+   regulator-name = HDMI_5V;
+   regulator-min-microvolt = 500;
+   regulator-max-microvolt = 500;
+   gpio = gpe0 1 0;
+   enable-active-high;
+   };
+
+   hdmi_ddc: i2c-ddc {
+   compatible = i2c-gpio;
+   gpios = gpe4 2 0 gpe4 3 0;
+   i2c-gpio,delay-us = 100;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   pinctrl-0 = i2c_ddc_bus;
+   pinctrl-names = default;
+   status = okay;
+   };
+
+   mixer@12C1 {
+   status = okay;
+   };
+
+   hdmi@12D0 {
+   hpd-gpio = gpx3 7 0;
+   pinctrl-names = default;
+   pinctrl-0 = hdmi_hpd;
+   hdmi-en-supply = hdmi_en;
+   vdd-supply = ldo3_reg;
+   vdd_osc-supply = ldo4_reg;
+   vdd_pll-supply = ldo3_reg;
+   ddc = hdmi_ddc;
+   status = okay;
+   };
+
+   i2c@138E {
+   status = okay;
+   };
+};
+
+pinctrl_1 {
+   hdmi_hpd: hdmi-hpd {
+   samsung,pins = gpx3-7;
+   samsung,pin-pud = 0;
+   };
+};
+
+pinctrl_0 {
+   i2c_ddc_bus: i2c-ddc-bus {
+   samsung,pins = gpe4-2, gpe4-3;
+   samsung,pin-function = 2;
+   samsung,pin-pud = 3;
+   samsung,pin-drv = 0;
+   };
 };
 
 mdma1 {
-- 
1.9.2

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[PATCH v2 6/6] ARM: dts: exynos5250: add display power domain

[Marek Szyprowski]

From: Andrzej Hajda a.ha...@samsung.com

The patch adds domain definition and references to it in appropriate devices.

Signed-off-by: Andrzej Hajda a.ha...@samsung.com
[mszyprow: rebased onto generic power domains dt bindings]
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 2b5a62c..cf4a6ec 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -102,6 +102,12 @@
#power-domain-cells = 0;
};
 
+   pd_disp1: disp1-power-domain@100440A0 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x100440A0 0x20;
+   #power-domain-cells = 0;
+   };
+
clock: clock-controller@1001 {
compatible = samsung,exynos5250-clock;
reg = 0x1001 0x3;
@@ -719,6 +725,7 @@
hdmi: hdmi {
compatible = samsung,exynos4212-hdmi;
reg = 0x1453 0x7;
+   power-domains = pd_disp1;
interrupts = 0 95 0;
clocks = clock CLK_HDMI, clock CLK_SCLK_HDMI,
 clock CLK_SCLK_PIXEL, clock CLK_SCLK_HDMIPHY,
@@ -731,6 +738,7 @@
mixer {
compatible = samsung,exynos5250-mixer;
reg = 0x1445 0x1;
+   power-domains = pd_disp1;
interrupts = 0 94 0;
clocks = clock CLK_MIXER, clock CLK_SCLK_HDMI;
clock-names = mixer, sclk_hdmi;
@@ -743,6 +751,7 @@
};
 
dp: dp-controller@145B {
+   power-domains = pd_disp1;
clocks = clock CLK_DP;
clock-names = dp;
phys = dp_phy;
@@ -750,6 +759,7 @@
};
 
fimd: fimd@1440 {
+   power-domains = pd_disp1;
clocks = clock CLK_SCLK_FIMD1, clock CLK_FIMD1;
clock-names = sclk_fimd, fimd;
};
-- 
1.9.2

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Re: [PATCH v2 1/6] ARM: Exynos: add support for sub-power domains

[Ulf Hansson]

On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com wrote:
 This patch adds support for making one power domain a sub-domain of
 other domain. This is useful for modeling power dependences for devices
 like TV Mixer or Camera ISP, which needs to have more than one power
 domain enabled to be operational.

 Based on previous work by Amit Daniel Kachhap amit.dan...@samsung.com.

 Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
 ---
  .../bindings/arm/exynos/power_domain.txt   |  2 ++
  arch/arm/mach-exynos/pm_domains.c  | 28 
 ++
  2 files changed, 30 insertions(+)

 diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
 b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 index f4445e5..28918a9 100644
 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
 @@ -22,6 +22,8 @@ Optional Properties:
 - pclkN, clkN: Pairs of parent of input clock and input clock to the
 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
 are supported currently.
 +- power-domains: generic power domain binding pointing to a master power 
 domain
 +that the given domain is a part of

I would prefer this to be documented as a generic way to configure
power domain parents, in
Documentation/devicetree/bindings/power/power_domain.txt.


  Node of a device using power domains must have a power-domains property
  defined with a phandle to respective power domain.
 diff --git a/arch/arm/mach-exynos/pm_domains.c 
 b/arch/arm/mach-exynos/pm_domains.c
 index 20f2671..37266a8 100644
 --- a/arch/arm/mach-exynos/pm_domains.c
 +++ b/arch/arm/mach-exynos/pm_domains.c
 @@ -161,6 +161,34 @@ no_clk:
 of_genpd_add_provider_simple(np, pd-pd);
 }

 +   /* Assign the child power domains to their parents */
 +   for_each_compatible_node(np, NULL, samsung,exynos4210-pd) {
 +   struct generic_pm_domain *child_domain, *parent_domain;
 +   struct of_phandle_args args;
 +
 +   args.np = np;
 +   args.args_count = 0;
 +   child_domain = of_genpd_get_from_provider(args);
 +   if (!child_domain)
 +   continue;
 +
 +   if (of_parse_phandle_with_args(np, power-domains,
 +#power-domain-cells, 0, args) != 
 0)
 +   continue;
 +
 +   parent_domain = of_genpd_get_from_provider(args);
 +   if (!parent_domain)
 +   continue;
 +
 +   if (pm_genpd_add_subdomain(parent_domain, child_domain))
 +   pr_warn(%s failed to add subdomain: %s\n,
 +   parent_domain-name, child_domain-name);
 +   else
 +   pr_info(%s has as child subdomain: %s.\n,
 +   parent_domain-name, child_domain-name);
 +   of_node_put(np);
 +   }

How do you maintain the order of how domains are being initialized?
For example, don't you need to initialize all parents prior their
children?

 +
 return 0;
  }
  arch_initcall(exynos4_pm_init_power_domain);
 --
 1.9.2


I noticed this patch wasn't sent to linux-arm, I guess it should?

Kind regards
Uffe
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Re: [PATCH v2 1/6] ARM: Exynos: add support for sub-power domains

[Marek Szyprowski]

Hello,

On 2015-01-13 11:44, Ulf Hansson wrote:

On 13 January 2015 at 10:39, Marek Szyprowski m.szyprow...@samsung.com wrote:

This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain enabled to be operational.

Based on previous work by Amit Daniel Kachhap amit.dan...@samsung.com.

Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
  .../bindings/arm/exynos/power_domain.txt   |  2 ++
  arch/arm/mach-exynos/pm_domains.c  | 28 ++
  2 files changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index f4445e5..28918a9 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
 - pclkN, clkN: Pairs of parent of input clock and input clock to the
 devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
 are supported currently.
+- power-domains: generic power domain binding pointing to a master power domain
+that the given domain is a part of

I would prefer this to be documented as a generic way to configure
power domain parents, in
Documentation/devicetree/bindings/power/power_domain.txt.


Well, right now it is a specific feature of exynos power domains, 
however if you
want I can add a note in 
Documentation/devicetree/bindings/power/power_domain.txt
on defining child-parent relation. However it will be still up to the 
power domain

providers to implement support for it.


  Node of a device using power domains must have a power-domains property
  defined with a phandle to respective power domain.
diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 20f2671..37266a8 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -161,6 +161,34 @@ no_clk:
 of_genpd_add_provider_simple(np, pd-pd);
 }

+   /* Assign the child power domains to their parents */
+   for_each_compatible_node(np, NULL, samsung,exynos4210-pd) {
+   struct generic_pm_domain *child_domain, *parent_domain;
+   struct of_phandle_args args;
+
+   args.np = np;
+   args.args_count = 0;
+   child_domain = of_genpd_get_from_provider(args);
+   if (!child_domain)
+   continue;
+
+   if (of_parse_phandle_with_args(np, power-domains,
+#power-domain-cells, 0, args) != 0)
+   continue;
+
+   parent_domain = of_genpd_get_from_provider(args);
+   if (!parent_domain)
+   continue;
+
+   if (pm_genpd_add_subdomain(parent_domain, child_domain))
+   pr_warn(%s failed to add subdomain: %s\n,
+   parent_domain-name, child_domain-name);
+   else
+   pr_info(%s has as child subdomain: %s.\n,
+   parent_domain-name, child_domain-name);
+   of_node_put(np);
+   }

How do you maintain the order of how domains are being initialized?
For example, don't you need to initialize all parents prior their
children?


All power domains, which have been added to the system were already 
initialized in
the previous loop (executed before the added code). Once all 
'exynos4210-pd' gets

initialized, they are scanned for child-parent relation.




+
 return 0;
  }
  arch_initcall(exynos4_pm_init_power_domain);
--
1.9.2


I noticed this patch wasn't sent to linux-arm, I guess it should?


Yes, I forgot about that. I will add it in the next version.

Best regards
--
Marek Szyprowski, PhD
Samsung RD Institute Poland

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[PATCH V2 3/3] clk: samsung: exynos7: add clocks for audio block

[Padmavathi Venna]

Add required clk support for I2S,PCM amd SPDIF

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 .../devicetree/bindings/clock/exynos7-clock.txt|9 ++
 drivers/clk/samsung/clk-exynos7.c  |  143 +++-
 include/dt-bindings/clock/exynos7-clk.h|   24 +++-
 3 files changed, 171 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 9282f71..6bf1e74 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -35,6 +35,7 @@ Required Properties for Clock Controller:
- samsung,exynos7-clock-fsys0
- samsung,exynos7-clock-fsys1
- samsung,exynos7-clock-mscl
+   - samsung,exynos7-clock-aud
 
  - reg: physical base address of the controller and the length of
memory mapped region.
@@ -54,6 +55,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+   - dout_sclk_aud_pll
 
 Input clocks for top1 clock controller:
- fin_pll
@@ -82,6 +84,9 @@ Input clocks for peric1 clock controller:
- sclk_spi2
- sclk_spi3
- sclk_spi4
+   - sclk_i2s1
+   - sclk_pcm1
+   - sclk_spdif
 
 Input clocks for peris clock controller:
- fin_pll
@@ -97,3 +102,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+   - fin_pll
+   - fout_aud_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c 
b/drivers/clk/samsung/clk-exynos7.c
index d40c09d..03d36e8 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -46,6 +46,7 @@ static struct samsung_fixed_factor_clock 
topc_fixed_factor_clks[] __initdata = {
 };
 
 /* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p) = { fin_pll, fout_aud_pll };
 PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
 PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
 PNAME(mout_cc_pll_ctrl_p)  = { fin_pll, fout_cc_pll };
@@ -105,6 +106,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata 
= {
 
MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+   MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
 
MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
 
@@ -129,6 +131,13 @@ static struct samsung_div_clock topc_div_clks[] __initdata 
= {
DIV_TOPC3, 12, 3),
DIV(DOUT_SCLK_MFC_PLL, dout_sclk_mfc_pll, mout_mfc_pll_ctrl,
DIV_TOPC3, 16, 3),
+   DIV(DOUT_SCLK_AUD_PLL, dout_sclk_aud_pll, mout_aud_pll_ctrl,
+   DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
+   PLL_36XX_RATE(49152, 20, 1, 0, 31457),
+   {},
 };
 
 static struct samsung_gate_clock topc_gate_clks[] __initdata = {
@@ -145,8 +154,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata 
= {
BUS1_DPLL_CON0, NULL),
PLL(pll_1452x, 0, fout_mfc_pll, fin_pll, MFC_PLL_LOCK,
MFC_PLL_CON0, NULL),
-   PLL(pll_1460x, 0, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
-   AUD_PLL_CON0, NULL),
+   PLL(pll_1460x, FOUT_AUD_PLL, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
+   AUD_PLL_CON0, pll1460x_24mhz_tbl),
 };
 
 static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -177,13 +186,16 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
samsung,exynos7-clock-topc,
 #define MUX_SEL_TOP00  0x0200
 #define MUX_SEL_TOP01  0x0204
 #define MUX_SEL_TOP03  0x020C
+#define MUX_SEL_TOP0_PERIC00x0230
 #define MUX_SEL_TOP0_PERIC10x0234
 #define MUX_SEL_TOP0_PERIC20x0238
 #define MUX_SEL_TOP0_PERIC30x023C
 #define DIV_TOP03  0x060C
+#define DIV_TOP0_PERIC00x0630
 #define DIV_TOP0_PERIC10x0634
 #define DIV_TOP0_PERIC20x0638
 #define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC00x0A30
 #define ENABLE_SCLK_TOP0_PERIC10x0A34
 #define ENABLE_SCLK_TOP0_PERIC20x0A38
 #define ENABLE_SCLK_TOP0_PERIC30x0A3C
@@ -193,6 +205,7 @@ PNAME(mout_bus0_pll_p)  = { fin_pll, 
dout_sclk_bus0_pll };
 PNAME(mout_bus1_pll_p) = { fin_pll, dout_sclk_bus1_pll };
 PNAME(mout_cc_pll_p)   = { fin_pll, dout_sclk_cc_pll };
 PNAME(mout_mfc_pll_p)  = { fin_pll, dout_sclk_mfc_pll };
+PNAME(mout_aud_pll_p)  = { fin_pll, dout_sclk_aud_pll };
 
 PNAME(mout_top0_half_bus0_pll_p) = {mout_top0_bus0_pll,
ffac_top0_bus0_pll_div2};
@@ -206,24 +219,34 @@ 

[PATCH V2 2/3] clk: samsung: exynos7: add clocks for SPI block

[Padmavathi Venna]

Add clock support for 5 SPI channels.

Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 .../devicetree/bindings/clock/exynos7-clock.txt|5 ++
 drivers/clk/samsung/clk-exynos7.c  |   73 
 include/dt-bindings/clock/exynos7-clk.h|   19 +-
 3 files changed, 95 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index d0e048c..9282f71 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -77,6 +77,11 @@ Input clocks for peric1 clock controller:
- sclk_uart1
- sclk_uart2
- sclk_uart3
+   - sclk_spi0
+   - sclk_spi1
+   - sclk_spi2
+   - sclk_spi3
+   - sclk_spi4
 
 Input clocks for peris clock controller:
- fin_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c 
b/drivers/clk/samsung/clk-exynos7.c
index d01d766..d40c09d 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -177,9 +177,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
samsung,exynos7-clock-topc,
 #define MUX_SEL_TOP00  0x0200
 #define MUX_SEL_TOP01  0x0204
 #define MUX_SEL_TOP03  0x020C
+#define MUX_SEL_TOP0_PERIC10x0234
+#define MUX_SEL_TOP0_PERIC20x0238
 #define MUX_SEL_TOP0_PERIC30x023C
 #define DIV_TOP03  0x060C
+#define DIV_TOP0_PERIC10x0634
+#define DIV_TOP0_PERIC20x0638
 #define DIV_TOP0_PERIC30x063C
+#define ENABLE_SCLK_TOP0_PERIC10x0A34
+#define ENABLE_SCLK_TOP0_PERIC20x0A38
 #define ENABLE_SCLK_TOP0_PERIC30x0A3C
 
 /* List of parent clocks for Muxes in CMU_TOP0 */
@@ -205,9 +211,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+   MUX_SEL_TOP0_PERIC1,
+   MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+   DIV_TOP0_PERIC1,
+   DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+   ENABLE_SCLK_TOP0_PERIC1,
+   ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
 };
 
@@ -229,10 +241,16 @@ static struct samsung_mux_clock top0_mux_clks[] 
__initdata = {
MUX(0, mout_aclk_peric1_66, mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, mout_aclk_peric0_66, mout_top0_group1, MUX_SEL_TOP03, 20, 2),
 
+   MUX(0, mout_sclk_spi1, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+   MUX(0, mout_sclk_spi0, mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+   MUX(0, mout_sclk_spi3, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+   MUX(0, mout_sclk_spi2, mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, mout_sclk_uart3, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, mout_sclk_uart2, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, mout_sclk_uart1, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, mout_sclk_uart0, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+   MUX(0, mout_sclk_spi4, mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
 };
 
 static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -241,13 +259,29 @@ static struct samsung_div_clock top0_div_clks[] 
__initdata = {
DIV(DOUT_ACLK_PERIC0, dout_aclk_peric0_66, mout_aclk_peric0_66,
DIV_TOP03, 20, 6),
 
+   DIV(0, dout_sclk_spi1, mout_sclk_spi1, DIV_TOP0_PERIC1, 8, 12),
+   DIV(0, dout_sclk_spi0, mout_sclk_spi0, DIV_TOP0_PERIC1, 20, 12),
+
+   DIV(0, dout_sclk_spi3, mout_sclk_spi3, DIV_TOP0_PERIC2, 8, 12),
+   DIV(0, dout_sclk_spi2, mout_sclk_spi2, DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, dout_sclk_uart3, mout_sclk_uart3, DIV_TOP0_PERIC3, 4, 4),
DIV(0, dout_sclk_uart2, mout_sclk_uart2, DIV_TOP0_PERIC3, 8, 4),
DIV(0, dout_sclk_uart1, mout_sclk_uart1, DIV_TOP0_PERIC3, 12, 4),
DIV(0, dout_sclk_uart0, mout_sclk_uart0, DIV_TOP0_PERIC3, 16, 4),
+   DIV(0, dout_sclk_spi4, mout_sclk_spi4, DIV_TOP0_PERIC3, 20, 12),
 };
 
 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+   GATE(CLK_SCLK_SPI1, sclk_spi1, dout_sclk_spi1,
+   ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+   GATE(CLK_SCLK_SPI0, sclk_spi0, dout_sclk_spi0,
+   ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+   GATE(CLK_SCLK_SPI3, sclk_spi3, dout_sclk_spi3,
+   ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+   GATE(CLK_SCLK_SPI2, sclk_spi2, dout_sclk_spi2,
+   ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, sclk_uart3, dout_sclk_uart3,
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, sclk_uart2, 

[PATCH V2 0/3] Add clk support for PDMA, SPI and audio on Exynos7

[Padmavathi Venna]

Add PDMA0,PDMA1 gate clock, required clks for 5 SPI channels and 
for clks in audio block.

This patchset is dependent on usb clk support from Vivek in below link.
http://www.spinics.net/lists/linux-samsung-soc/msg39342.html

Changes since V1:
- Added documentation for source clks of peric1 block.
- Changed the parent of sclk_i2s1_user,sclk_pcm1_user and 
sclk_spdif_user
  from divider clk to gate clk.
- Removed unused clk IDs

Padmavathi Venna (3):
  clk: samsung: exynos7: add gate clock for DMA block
  clk: samsung: exynos7: add clocks for SPI block
  clk: samsung: exynos7: add clocks for audio block

 .../devicetree/bindings/clock/exynos7-clock.txt|   14 ++
 drivers/clk/samsung/clk-exynos7.c  |  220 +++-
 include/dt-bindings/clock/exynos7-clk.h|   43 -
 3 files changed, 271 insertions(+), 6 deletions(-)

-- 
1.7.4.4

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[PATCH 1/3] clk: samsung: exynos7: add gate clock for DMA block

[Padmavathi Venna]

Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna padm...@samsung.com
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
---
 drivers/clk/samsung/clk-exynos7.c   |4 
 include/dt-bindings/clock/exynos7-clk.h |4 +++-
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c 
b/drivers/clk/samsung/clk-exynos7.c
index 945f41c..d01d766 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -722,6 +722,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] 
__initdata = {
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, aclk_axius_usbdrd30x_fsys0x,
mout_aclk_fsys0_200_user,
ENABLE_ACLK_FSYS00, 19, 0, 0),
+   GATE(ACLK_PDMA1, aclk_pdma1, mout_aclk_fsys0_200_user,
+   ENABLE_ACLK_FSYS00, 3, 0, 0),
+   GATE(ACLK_PDMA0, aclk_pdma0, mout_aclk_fsys0_200_user,
+   ENABLE_ACLK_FSYS00, 4, 0, 0),
 
GATE(ACLK_USBDRD300, aclk_usbdrd300, mout_aclk_fsys0_200_user,
ENABLE_ACLK_FSYS01, 29, 0, 0),
diff --git a/include/dt-bindings/clock/exynos7-clk.h 
b/include/dt-bindings/clock/exynos7-clk.h
index e33d0ca..05e2a47 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -91,7 +91,9 @@
 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER7
 #define OSCCLK_PHY_CLKOUT_USB30_PHY8
-#define FSYS0_NR_CLK   9
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK   11
 
 /* FSYS1 */
 #define ACLK_MMC1  1
-- 
1.7.4.4

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Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem

[Javier Martinez Canillas]

Hello Joonyoung,

On 01/13/2015 09:40 AM, Joonyoung Shim wrote:
  These are the changes I have now [0]. Please let me know what you think.
 
  
  Good, it's working with your patch without u-boot changes and reverting
  of commit 2ed127697eb.
 
 But i also get stripe hdmi output if hdmi/mixer drivers aren't defered
 probed, because DISP1 power domain isn't disabled on booting by defered
 probe so is always on.

Could you please elaborate on this? I'm not sure I undestood what you meant
so it would be great if you can give me the steps to reproduce your issue.

Best regards,
Javier
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Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block

[Vivek Gautam]

Hi Padma,


On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna padm...@samsung.com wrote:
 Add required clk support for I2S,PCM amd SPDIF

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---

verified from Exynos7 datasheet. The patch looks good.
Reviewed-by: Vivek Gautam gautam.vi...@samsung.com

  .../devicetree/bindings/clock/exynos7-clock.txt|6 +
  drivers/clk/samsung/clk-exynos7.c  |  144 
 +++-
  include/dt-bindings/clock/exynos7-clk.h|   24 +++-
  3 files changed, 169 insertions(+), 5 deletions(-)

 diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt 
 b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
 index 6d3d5f8..3b439ed 100644
 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
 @@ -34,6 +34,7 @@ Required Properties for Clock Controller:
 - samsung,exynos7-clock-peris
 - samsung,exynos7-clock-fsys0
 - samsung,exynos7-clock-fsys1
 +   - samsung,exynos7-clock-aud

   - reg: physical base address of the controller and the length of
 memory mapped region.
 @@ -53,6 +54,7 @@ Input clocks for top0 clock controller:
 - dout_sclk_bus1_pll
 - dout_sclk_cc_pll
 - dout_sclk_mfc_pll
 +   - dout_sclk_aud_pll

  Input clocks for top1 clock controller:
 - fin_pll
 @@ -91,3 +93,7 @@ Input clocks for fsys1 clock controller:
 - dout_aclk_fsys1_200
 - dout_sclk_mmc0
 - dout_sclk_mmc1
 +
 +Input clocks for aud clock controller:
 +   - fin_pll
 +   - fout_aud_pll
 diff --git a/drivers/clk/samsung/clk-exynos7.c 
 b/drivers/clk/samsung/clk-exynos7.c
 index cf5e50e..e4bc241 100644
 --- a/drivers/clk/samsung/clk-exynos7.c
 +++ b/drivers/clk/samsung/clk-exynos7.c
 @@ -45,6 +45,7 @@ static struct samsung_fixed_factor_clock 
 topc_fixed_factor_clks[] __initdata = {
  };

  /* List of parent clocks for Muxes in CMU_TOPC */
 +PNAME(mout_aud_pll_ctrl_p) = { fin_pll, fout_aud_pll };
  PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
  PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
  PNAME(mout_cc_pll_ctrl_p)  = { fin_pll, fout_cc_pll };
 @@ -104,6 +105,7 @@ static struct samsung_mux_clock topc_mux_clks[] 
 __initdata = {

 MUX(0, mout_sclk_bus0_pll_out, mout_sclk_bus0_pll_out_p,
 MUX_SEL_TOPC1, 16, 1),
 +   MUX(0, mout_aud_pll_ctrl, mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),

 MUX(0, mout_aclk_ccore_133, mout_topc_group2, MUX_SEL_TOPC2, 4, 2),

 @@ -125,6 +127,13 @@ static struct samsung_div_clock topc_div_clks[] 
 __initdata = {
 DIV_TOPC3, 12, 3),
 DIV(DOUT_SCLK_MFC_PLL, dout_sclk_mfc_pll, mout_mfc_pll_ctrl,
 DIV_TOPC3, 16, 3),
 +   DIV(DOUT_SCLK_AUD_PLL, dout_sclk_aud_pll, mout_aud_pll_ctrl,
 +   DIV_TOPC3, 28, 3),
 +};
 +
 +static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
 +   PLL_36XX_RATE(49152, 20, 1, 0, 31457),
 +   {},
  };

  static struct samsung_pll_clock topc_pll_clks[] __initdata = {
 @@ -136,8 +145,8 @@ static struct samsung_pll_clock topc_pll_clks[] 
 __initdata = {
 BUS1_DPLL_CON0, NULL),
 PLL(pll_1452x, 0, fout_mfc_pll, fin_pll, MFC_PLL_LOCK,
 MFC_PLL_CON0, NULL),
 -   PLL(pll_1460x, 0, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
 -   AUD_PLL_CON0, NULL),
 +   PLL(pll_1460x, FOUT_AUD_PLL, fout_aud_pll, fin_pll, AUD_PLL_LOCK,
 +   AUD_PLL_CON0, pll1460x_24mhz_tbl),
  };

  static struct samsung_cmu_info topc_cmu_info __initdata = {
 @@ -166,13 +175,16 @@ CLK_OF_DECLARE(exynos7_clk_topc, 
 samsung,exynos7-clock-topc,
  #define MUX_SEL_TOP00  0x0200
  #define MUX_SEL_TOP01  0x0204
  #define MUX_SEL_TOP03  0x020C
 +#define MUX_SEL_TOP0_PERIC00x0230
  #define MUX_SEL_TOP0_PERIC10x0234
  #define MUX_SEL_TOP0_PERIC20x0238
  #define MUX_SEL_TOP0_PERIC30x023C
  #define DIV_TOP03  0x060C
 +#define DIV_TOP0_PERIC00x0630
  #define DIV_TOP0_PERIC10x0634
  #define DIV_TOP0_PERIC20x0638
  #define DIV_TOP0_PERIC30x063C
 +#define ENABLE_SCLK_TOP0_PERIC00x0A30
  #define ENABLE_SCLK_TOP0_PERIC10x0A34
  #define ENABLE_SCLK_TOP0_PERIC20x0A38
  #define ENABLE_SCLK_TOP0_PERIC30x0A3C
 @@ -182,6 +194,8 @@ PNAME(mout_bus0_pll_p)  = { fin_pll, 
 dout_sclk_bus0_pll };
  PNAME(mout_bus1_pll_p) = { fin_pll, dout_sclk_bus1_pll };
  PNAME(mout_cc_pll_p)   = { fin_pll, dout_sclk_cc_pll };
  PNAME(mout_mfc_pll_p)  = { fin_pll, dout_sclk_mfc_pll };
 +PNAME(mout_aud_pll_p)  = { fin_pll, dout_sclk_aud_pll };
 +

nit: unnecessary additional line.


  PNAME(mout_top0_half_bus0_pll_p) = 

Re: [PATCHv3 1/8] devfreq: exynos: Add generic exynos memory bus frequency driver

[Chanwoo Choi]

On 01/13/2015 06:07 PM, MyungJoo Ham wrote:
  
 Dear Myungjoo,

 On 01/13/2015 05:42 PM, MyungJoo Ham wrote:
   
  This patch adds the generic exynos bus frequency driver for memory bus
 with DEVFREQ framework. The Samsung Exynos SoCs have the common 
 architecture
 for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
 support the memory bus frequency driver for Exynos SoCs.

 Each memory bus block has a clock for memory bus speed and frequency
 table which is changed according to the utilization of memory bus on 
 runtime.
 And then each memory bus group has the one more memory bus blocks and
 OPP table (including frequency and voltage), regulator, devfreq-event
 devices.

 There are a little difference about the number of memory bus because each 
 Exynos
 SoC have the different sub-IP and different memory bus speed. In spite of 
 this
 difference among Exynos SoCs, we can support almost Exynos SoC by adding
 unique data of memory bus to devicetree file.

 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Cc: Kukjin Kim kg...@kernel.org
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
 ---
  drivers/devfreq/Kconfig  |  15 +
  drivers/devfreq/Makefile |   1 +
  drivers/devfreq/exynos-busfreq.c | 589 
 +++
  3 files changed, 605 insertions(+)
  create mode 100644 drivers/devfreq/exynos-busfreq.c

 Exynos drivers are located at drivers/devfreq/exynos/
 Please relocate/rename exynos-busfreq.c

 OK. I'll move it at drivers/devfreq/exynos directory.
 Do you prefer 'exynos-bus.c' instead of 'exynos-busfreq.c'?
 If you reply, I'll change it.
 
 exynos-bus looks more pretty :)

OK, I'll change the driver name according to your comment.

Best Regards,
Chanwoo Choi

 


 []

 diff --git a/drivers/devfreq/exynos-busfreq.c 
 b/drivers/devfreq/exynos-busfreq.c
 new file mode 100644
 index 000..b180f43
 --- /dev/null
 +++ b/drivers/devfreq/exynos-busfreq.c

 []

 +
 +#define BUS_SATURATION_RATIO  40

 In order to be a common driver, this should be tunable.

 Because .dts is supposed to have hardware configuration only,
 you may keep a table of { chip-name, saturation ratio} in this
 driver and look up the saturation ratio based on the chip-name.

 OK, I'll add new property for saturation_ratio.

 I'll implement to use default saturation_ratio value ,
 if dt node don't include saturation_ratio property.
 
 Yes. I didn't talk with DT maintainers and I do not have much
 experience with DT; however, it appears that such values are not
 recommended to be in DTS files and this value is determined by
 the SoC model number without complications in the driver file.
 

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[PATCH v2 4/6] ARM: dts: exynos4412-odroid: enable hdmi support

[Marek Szyprowski]

This patch adds nodes specific to Exynos4412 based Odroid X/X2/U2/U3
boards required for enabling HDMI display.

Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 44 +
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi 
b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 3fbf588..e10efa8 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -231,6 +231,20 @@
regulator-always-on;
};
 
+   ldo8_reg: ldo@8 {
+   regulator-compatible = LDO8;
+   regulator-name = VDD10_HDMI_1.0V;
+   regulator-min-microvolt = 100;
+   regulator-max-microvolt = 100;
+   };
+
+   ldo10_reg: ldo@10 {
+   regulator-compatible = LDO10;
+   regulator-name = VDDQ_MIPIHSI_1.8V;
+   regulator-min-microvolt = 180;
+   regulator-max-microvolt = 180;
+   };
+
ldo11_reg: LDO11 {
regulator-name = VDD18_ABB1_1.8V;
regulator-min-microvolt = 180;
@@ -389,6 +403,31 @@
ehci: ehci@1258 {
status = okay;
};
+
+   mixer: mixer@12C1 {
+   status = okay;
+   };
+
+   hdmi@12D0 {
+   hpd-gpio = gpx3 7 0;
+   pinctrl-names = default;
+   pinctrl-0 = hdmi_hpd;
+   vdd-supply = ldo8_reg;
+   vdd_osc-supply = ldo10_reg;
+   vdd_pll-supply = ldo8_reg;
+   ddc = hdmi_ddc;
+   status = okay;
+   };
+
+   hdmi_ddc: i2c@1388 {
+   status = okay;
+   pinctrl-names = default;
+   pinctrl-0 = i2c2_bus;
+   };
+
+   i2c@138E {
+   status = okay;
+   };
 };
 
 pinctrl_1 {
@@ -403,4 +442,9 @@
samsung,pin-pud = 0;
samsung,pin-drv = 0;
};
+
+   hdmi_hpd: hdmi-hpd {
+   samsung,pins = gpx3-7;
+   samsung,pin-pud = 1;
+   };
 };
-- 
1.9.2

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[PATCH v2 2/6] ARM: dts: exynos4: add hdmi related nodes

[Marek Szyprowski]

This patch adds entries for HDMI, Mixer and i2c with hdmi-phy modules
found in Exynos 4210 and 4x12 SoCs.

Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi| 40 +++
 arch/arm/boot/dts/exynos4210.dtsi |  8 
 arch/arm/boot/dts/exynos4x12.dtsi | 11 +++
 3 files changed, 59 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index c5dc2ef..d951647 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -38,6 +38,7 @@
i2c5 = i2c_5;
i2c6 = i2c_6;
i2c7 = i2c_7;
+   i2c8 = i2c_8;
csis0 = csis_0;
csis1 = csis_1;
fimc0 = fimc_0;
@@ -544,6 +545,22 @@
status = disabled;
};
 
+   i2c_8: i2c@138E {
+   #address-cells = 1;
+   #size-cells = 0;
+   compatible = samsung,s3c2440-hdmiphy-i2c;
+   reg = 0x138E 0x100;
+   interrupts = 0 93 0;
+   clocks = clock CLK_I2C_HDMI;
+   clock-names = i2c;
+   status = disabled;
+
+   hdmi_i2c_phy: hdmiphy@38 {
+   compatible = exynos4210-hdmiphy;
+   reg = 0x38;
+   };
+   };
+
spi_0: spi@1392 {
compatible = samsung,exynos4210-spi;
reg = 0x1392 0x100;
@@ -652,4 +669,27 @@
samsung,sysreg = sys_reg;
status = disabled;
};
+
+   hdmi: hdmi@12D0 {
+   compatible = samsung,exynos4210-hdmi;
+   reg = 0x12D0 0x7;
+   interrupts = 0 92 0;
+   clock-names = hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy,
+   mout_hdmi;
+   clocks = clock CLK_HDMI, clock CLK_SCLK_HDMI,
+   clock CLK_SCLK_PIXEL, clock CLK_SCLK_HDMIPHY,
+   clock CLK_MOUT_HDMI;
+   phy = hdmi_i2c_phy;
+   power-domains = pd_tv;
+   samsung,syscon-phandle = pmu_system_controller;
+   status = disabled;
+   };
+
+   mixer: mixer@12C1 {
+   compatible = samsung,exynos4210-mixer;
+   interrupts = 0 91 0;
+   reg = 0x12C1 0x2100, 0x12c0 0x300;
+   power-domains = pd_tv;
+   status = disabled;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index 6728aaa..fc17cdf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -193,4 +193,12 @@
samsung,lcd-wb;
};
};
+
+   mixer: mixer@12C1 {
+   clock-names = mixer, sclk_hdmi, vp, mout_mixer,
+   sclk_mixer;
+   clocks = clock CLK_MIXER, clock CLK_SCLK_HDMI,
+   clock CLK_VP, clock CLK_MOUT_MIXER,
+   clock CLK_SCLK_MIXER;
+   };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi 
b/arch/arm/boot/dts/exynos4x12.dtsi
index da8734e..e577bd0 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -283,4 +283,15 @@
clock-names = tmu_apbif;
status = disabled;
};
+
+   hdmi: hdmi@12D0 {
+   compatible = samsung,exynos4212-hdmi;
+   };
+
+   mixer: mixer@12C1 {
+   compatible = samsung,exynos4212-mixer;
+   clock-names = mixer, sclk_hdmi, vp;
+   clocks = clock CLK_MIXER, clock CLK_SCLK_HDMI,
+   clock CLK_VP;
+   };
 };
-- 
1.9.2

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[PATCH v2 1/6] ARM: Exynos: add support for sub-power domains

[Marek Szyprowski]

This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain enabled to be operational.

Based on previous work by Amit Daniel Kachhap amit.dan...@samsung.com.

Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 .../bindings/arm/exynos/power_domain.txt   |  2 ++
 arch/arm/mach-exynos/pm_domains.c  | 28 ++
 2 files changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index f4445e5..28918a9 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently.
+- power-domains: generic power domain binding pointing to a master power domain
+that the given domain is a part of
 
 Node of a device using power domains must have a power-domains property
 defined with a phandle to respective power domain.
diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 20f2671..37266a8 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -161,6 +161,34 @@ no_clk:
of_genpd_add_provider_simple(np, pd-pd);
}
 
+   /* Assign the child power domains to their parents */
+   for_each_compatible_node(np, NULL, samsung,exynos4210-pd) {
+   struct generic_pm_domain *child_domain, *parent_domain;
+   struct of_phandle_args args;
+
+   args.np = np;
+   args.args_count = 0;
+   child_domain = of_genpd_get_from_provider(args);
+   if (!child_domain)
+   continue;
+
+   if (of_parse_phandle_with_args(np, power-domains,
+#power-domain-cells, 0, args) != 0)
+   continue;
+
+   parent_domain = of_genpd_get_from_provider(args);
+   if (!parent_domain)
+   continue;
+
+   if (pm_genpd_add_subdomain(parent_domain, child_domain))
+   pr_warn(%s failed to add subdomain: %s\n,
+   parent_domain-name, child_domain-name);
+   else
+   pr_info(%s has as child subdomain: %s.\n,
+   parent_domain-name, child_domain-name);
+   of_node_put(np);
+   }
+
return 0;
 }
 arch_initcall(exynos4_pm_init_power_domain);
-- 
1.9.2

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[PATCH v2 0/6] Enable HDMI support on Exynos platforms

[Marek Szyprowski]

Hi all,

This is yet another approach to submit patches, which enables HDMI
support for two Exynos based platforms: UniversalC210 and Odroid X2/U3.

Beside DTS changes, this patchset adds parent domain support for Exynos
PM domains. This was the most controversial patch in the previous
attempts, but I hope I fixes all reported issues and made it really
generic. For more details see individual patches.

The patchset is based on my previous patch:
'ARM: DTS: Exynos: convert to generic power domain bindings'
(http://www.spinics.net/lists/linux-samsung-soc/msg40584.html)
and requires 2 patches that have been merged to v3.19-rc4:
'clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi'
(commit df019a5c0f7083001cb694f44821ca506425bda2) and
'PM / Domains: Export of_genpd_get_from_provider function'
(commit 7496fcbe8a643097efc061160e1c3b65ee2fa350).

Regards
Marek Szyprowski

Change log:

v2:
- rewrote subdomains patch according to suggestions from Geert
  Uytterhoeven and Amit Daniel Kachhap.

v1 resend: (http://www.spinics.net/lists/linux-samsung-soc/msg39428.html)
- added handling of generic 'power-domains' binding in subdomains

v1: (http://www.spinics.net/lists/linux-samsung-soc/msg38914.html)
- resolved power domain on/off issue with 'clk: samsung: exynos4: set
  parent of mixer gate clock to hdmi' patch

v0: (http://www.spinics.net/lists/linux-samsung-soc/msg33498.html)
- first attempt, used 'always on' power domains hack


Andrzej Hajda (1):
  ARM: dts: exynos5250: add display power domain

Marek Szyprowski (4):
  ARM: Exynos: add support for sub-power domains
  ARM: dts: exynos4: add hdmi related nodes
  ARM: dts: exynos4: add dependency between TV and LCD0 power domains
  ARM: dts: exynos4412-odroid: enable hdmi support

Tomasz Stanislawski (1):
  ARM: dts: exynos4210-universal_c210: enable hdmi support

 .../bindings/arm/exynos/power_domain.txt   |  2 +
 arch/arm/boot/dts/exynos4.dtsi | 41 
 arch/arm/boot/dts/exynos4210-universal_c210.dts| 57 ++
 arch/arm/boot/dts/exynos4210.dtsi  |  8 +++
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi| 44 +
 arch/arm/boot/dts/exynos4x12.dtsi  | 11 +
 arch/arm/boot/dts/exynos5250.dtsi  | 10 
 arch/arm/mach-exynos/pm_domains.c  | 28 +++
 8 files changed, 201 insertions(+)

-- 
1.9.2

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Re: [PATCHv3 5/8] ARM: dts: Add memory bus node for Exynos4x12

[MyungJoo Ham]

   
  This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
 two memory bus to translate data between DRAM and eMMC/sub-IPs.
 
 Following list specifies the detailed relation between memory bus clock and 
 DMC
 IP in MIF (Memory Interface) block:
 - DMC/ACP clock : DMC (Dynamic Memory Controller)
 
 Following list specifies the detailed relation between memory bus clock and
 sub-IPs in INT (Internal) block:
 - ACLK100 clock : PERIL/PERIR/MFC(PCLK)
 - ACLK160 clock : CAM/TV/LCD
 - ACLK133 clock : FSYS
 - GDL/GDR clock : leftbus/rightbus
 - SCLK_MFC clock : MFC
 
 Cc: Kukjin Kim kg...@kernel.org
 Cc: Myungjoo Ham myungjoo@samsung.com
 Cc: Kyungmin Park kyungmin.p...@samsung.com
 Signed-off-by: Chanwoo Choi cw00.c...@samsung.com

Acked-by: MyungJoo Ham myungjoo@samsung.com for all the other dts file 
patch with Exynos*.


Off Topic. Not urgent. Just out of curiousity:
  Do you have some idea on how to express voltage variations
with device tree? (not runtime-AVS, but boottime-AVS. runtime-AVS is rather
trivial)

  I think you remember that we often had multiple set of OPP tables and
we chose one of them based on the value extracted at boot time in order to
use lower voltage values without deteriorating the reliability.

  Basically, such a feature requires to express multiple OPP lists and let
the kernel choose one of the lists at the boot time, which I doubt the
expressiveness in the current device tree technique.

 ---
  arch/arm/boot/dts/exynos4x12.dtsi | 121 
 ++
  1 file changed, 121 insertions(+)
 

Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem

[Javier Martinez Canillas]

Hello Joonyoung,

On 01/13/2015 06:24 AM, Joonyoung Shim wrote:
 
 Also, the SW_ACLK_300_DISP1 and USER_ACLK_300_DISP1 are needed for the FIMD
 parent and input clock respectively. Adding those to the clocks list of the
 DISP1 power domain gives me working display + HDMI on my Exynos5800 Peach Pi.
 
 These are the changes I have now [0]. Please let me know what you think.
 
 
 Good, it's working with your patch without u-boot changes and reverting
 of commit 2ed127697eb.


Perfect, I'll split the the clk and DTS changes in different patches and
post the series once we figure out the power-domain disable failed issue.

 
 Yes, I was not able to trigger that by running modetest but by turning off
 my HDMI monitor and then turning it on again. When the monitor is turned
 on then I see a Power domain power-domain disable failed and the imprecise
 external abort error.
 
 I had to disable CONFIG_DRM_EXYNOS_DP in order to trigger though and that
 is why I was not able to reproduce it before.
 
 I think though that this is a separate issue of the HDMI not working since
 power domains should be able to have many consumers devices and I see that
 other power domains are used that way.
 
 
 OK, we need more investigation.
 

Agreed, since even though I think this is a separate issue, I'll prefer
to not add a known bug as a side effect of having a working HDMI.

Best regard,
Javier
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[PATCH v2 3/6] ARM: dts: exynos4: add dependency between TV and LCD0 power domains

[Marek Szyprowski]

TV Mixer needs both TV and LCD0 domains enabled to be fully operational.
This dependency is modelled by making TV power domains a sub-domain of
LCD0 power domain.

Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index d951647..a59b3fae 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -101,6 +101,7 @@
compatible = samsung,exynos4210-pd;
reg = 0x10023C20 0x20;
#power-domain-cells = 0;
+   power-domains = pd_lcd0;
};
 
pd_cam: cam-power-domain@10023C00 {
-- 
1.9.2

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Re: [PATCH] i2c: exynos5: Move initialization code to subsys_initcall()

[Tomi Valkeinen]

On 12/01/15 10:43, Joonyoung Shim wrote:
 +Cc Tomi Valkeinen,
 
 Hi Uwe,
 
 On 01/12/2015 04:50 PM, Uwe Kleine-König wrote:
 Hello,

 On Mon, Jan 12, 2015 at 11:53:02AM +0900, Joonyoung Shim wrote:
 This is required in order to ensure that core system devices such as
 voltage regulators attached via I2C are available early in boot.
 Deferred probing isn't an option? If so I suggest adding the reasoning
 in a comment to stop the next person converting it to that.
 (And if not, please fix accordingly to use deferred probing.)

 
 I couldn't get penguin logo since the commit 92b004d (video/logo:
 prevent use of logos after they have been freed) and i just tried old
 way because i missed the flow to move to deferred probing.
 
 Fb driver probe seems to be ran between fb_logo_late_init late_initcall
 and the freeing of the logos.
 
 Any ideas?

Thierry mentioned on IRC that he encountered the same issue. And I
encountered it also.

So... I'd rather not revert the fix, as it's quite a nasty one, and it
happens while console lock is held, so it looks like the machine just
froze. But I don't know how it could be improved with the current kernel.

We could make the logos non-initdata, but I don't much like that option.
Or we could perhaps implement some new way to catch the freeing of initdata.

Any other ideas?

 Tomi




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Re: [RFC v2 0/4] Add basic support for ASV

[Kevin Hilman]

On Tue, Dec 3, 2013 at 10:00 PM, Sachin Kamat sachin.ka...@linaro.org wrote:
 Hi Abhilash,

 On 3 December 2013 20:16, Abhilash Kesavan kesavan.abhil...@gmail.com wrote:
 Hi Yadwinder and Sachin,

 CC'ing Doug and Andrew who have also worked on ASV.

 I tested these patches on a 5250 Chromebook after modifying the
 cpufreq code and a few other changes for booting the board. The driver
 is retrieving the ASV fused group correctly. The behavior on an
 unfused SMDK5250 is also fine.
 I have a few minor comments on the patches.


 Thank you for testing and reviewing the patchset.
 Will incorporate your comments in the next version.

Has there been an updated version of this series posted?I can't
seem to find one.

Kevin
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Re: [PATCH RESEND v2 4/7] platform/chrome: Add Chrome OS EC userspace device interface

[Gwendal Grignou]

On Fri, Jan 2, 2015 at 5:32 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:

 From: Bill Richardson wfric...@chromium.org

 This patch adds a device interface to access the
 Chrome OS Embedded Controller from user-space.

 Signed-off-by: Bill Richardson wfric...@chromium.org
 Reviewed-by: Simon Glass s...@google.com
 Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Gwendal Grignou gwen...@chromium.org
 ---

 Changes since v1:
  - The cros_ec_dev driver does not belong to drivers/mfd (Lee Jones)
  - Don't call class_create in the probe function (Gwendal Grignou)
  - Don't use the deprecated register_chrdev() function (Gwendal Grignou)
  - Remove struct cros_ec_device *ec global variable (Lee Jones)
  - Arrange structures to be 64-bit safe instead using the IOCTL compact API
(Alan Cox)
  - Use _CHARDEV instead of _DEV as a postfix to denote that is a character
device user-space interface (Lee Jones)
  - Remove the CROS_CLASS_NAME define and just use the name directly (Lee 
 Jones)
  - Remove unncessary include headers (Lee Jones)
  - Add a newline when appropiate and remove double new lines (Lee Jones)
  - If *offset == 0, there is no need to do *offset +=, just use = (Lee Jones)
  - Use dev_err() instead of pr_err() when possible (Lee Jones)
  - Remove unnecesary goto and just return an error instead (Lee Jones)
  - Don't set .owner to THIS_MODULE since that is made by the core (Lee Jones)
  - Document the ioctl number used in Documentation/ioctl/ioctl-number.txt

  Documentation/ioctl/ioctl-number.txt  |   1 +
  drivers/platform/chrome/Kconfig   |  14 +-
  drivers/platform/chrome/Makefile  |   1 +
  drivers/platform/chrome/cros_ec_dev.c | 268 
 ++
  drivers/platform/chrome/cros_ec_dev.h |  47 ++
  5 files changed, 328 insertions(+), 3 deletions(-)
  create mode 100644 drivers/platform/chrome/cros_ec_dev.c
  create mode 100644 drivers/platform/chrome/cros_ec_dev.h

 diff --git a/Documentation/ioctl/ioctl-number.txt 
 b/Documentation/ioctl/ioctl-number.txt
 index 8136e1f..51f4221 100644
 --- a/Documentation/ioctl/ioctl-number.txt
 +++ b/Documentation/ioctl/ioctl-number.txt
 @@ -321,6 +321,7 @@ Code  Seq#(hex) Include FileComments
  0xDB   00-0F   drivers/char/mwave/mwavepub.h
  0xDD   00-3F   ZFCP device driver  see drivers/s390/scsi/
 mailto:aherr...@de.ibm.com
 +0xEC   00-01   drivers/platform/chrome/cros_ec_dev.h   ChromeOS EC driver
  0xF3   00-3F   drivers/usb/misc/sisusbvga/sisusb.h sisfb (in development)
 mailto:tho...@winischhofer.net
  0xF4   00-1F   video/mbxfb.h   mbxfb
 diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
 index 440ed77..75dc514 100644
 --- a/drivers/platform/chrome/Kconfig
 +++ b/drivers/platform/chrome/Kconfig
 @@ -4,7 +4,7 @@

  menuconfig CHROME_PLATFORMS
 bool Platform support for Chrome hardware
 -   depends on X86
 +   depends on X86 || ARM
 ---help---
   Say Y here to get to see options for platform support for
   various Chromebooks and Chromeboxes. This option alone does
 @@ -16,8 +16,7 @@ if CHROME_PLATFORMS

  config CHROMEOS_LAPTOP
 tristate Chrome OS Laptop
 -   depends on I2C
 -   depends on DMI
 +   depends on I2C  DMI  X86
 ---help---
   This driver instantiates i2c and smbus devices such as
   light sensors and touchpads.
 @@ -27,6 +26,7 @@ config CHROMEOS_LAPTOP

  config CHROMEOS_PSTORE
 tristate Chrome OS pstore support
 +   depends on X86
 ---help---
   This module instantiates the persistent storage on x86 ChromeOS
   devices. It can be used to store away console logs and crash
 @@ -38,5 +38,13 @@ config CHROMEOS_PSTORE
   If you have a supported Chromebook, choose Y or M here.
   The module will be called chromeos_pstore.

 +config CROS_EC_CHARDEV
 +tristate Chrome OS Embedded Controller userspace device interface
 +depends on MFD_CROS_EC
 +---help---
 +  This driver adds support to talk with the ChromeOS EC from 
 userspace.
 +
 +  If you have a supported Chromebook, choose Y or M here.
 +  The module will be called cros_ec_dev.

  endif # CHROMEOS_PLATFORMS
 diff --git a/drivers/platform/chrome/Makefile 
 b/drivers/platform/chrome/Makefile
 index 2b860ca..10f1361 100644
 --- a/drivers/platform/chrome/Makefile
 +++ b/drivers/platform/chrome/Makefile
 @@ -1,3 +1,4 @@

  obj-$(CONFIG_CHROMEOS_LAPTOP)  += chromeos_laptop.o
  obj-$(CONFIG_CHROMEOS_PSTORE)  += chromeos_pstore.o
 +obj-$(CONFIG_CROS_EC_CHARDEV)  += cros_ec_dev.o
 diff --git a/drivers/platform/chrome/cros_ec_dev.c 
 b/drivers/platform/chrome/cros_ec_dev.c
 new file mode 100644
 index 000..04cc8eb
 --- /dev/null
 +++ b/drivers/platform/chrome/cros_ec_dev.c
 @@ -0,0 

[PATCH] ARM: dts: exynos5422-odroidxu3: add INA2xx sensors

[Kevin Hilman]

From: Kevin Hilman khil...@linaro.org

The odroid-xu3 has 4 INA231 current sensors on board which can be
accessed from the Linux via the hwmon interface.

There is one sensor for each of these power rails:

- A15 cluster: VDD_ARM
- A7 cluster: VDD_KFC
- GPU: VDD_G3D
- memory: VDD_MEM

In addition to adding the sensors, LDO26 from the PMIC needs to be
enabled because it's powering these sensor.

Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Sjoerd Simons sjoerd.sim...@collabora.co.uk
Signed-off-by: Kevin Hilman khil...@linaro.org
---
Applies on top of ARM: dts: Add dts file for odroid XU3 board from Sjoerd 
Simons.

 arch/arm/boot/dts/exynos5422-odroidxu3.dts | 39 ++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts 
b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index c29123c0734d..7874da20939f 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -174,6 +174,13 @@
regulator-always-on;
};
 
+   ldo26_reg: LDO26 {
+   regulator-name = vdd_ldo26;
+   regulator-min-microvolt = 300;
+   regulator-max-microvolt = 300;
+   regulator-always-on;
+   };
+
buck1_reg: BUCK1 {
regulator-name = vdd_mif;
regulator-min-microvolt = 80;
@@ -257,6 +264,38 @@
};
};
 
+   i2c_0: i2c@12C6 {
+   status = okay;
+
+   /* A15 cluster: VDD_ARM */
+   ina220@40 {
+   compatible = ti,ina230;
+   reg = 0x40;
+   shunt-resistor = 1;
+   };
+
+   /* memory: VDD_MEM */
+   ina220@41 {
+   compatible = ti,ina230;
+   reg = 0x41;
+   shunt-resistor = 1;
+   };
+
+   /* GPU: VDD_G3D */
+   ina220@44 {
+   compatible = ti,ina230;
+   reg = 0x44;
+   shunt-resistor = 1;
+   };
+
+   /* A7 cluster: VDD_KFC */
+   ina220@45 {
+   compatible = ti,ina230;
+   reg = 0x45;
+   shunt-resistor = 1;
+   };
+   };
+
i2c_2: i2c@12C8 {
samsung,i2c-sda-delay = 100;
samsung,i2c-max-bus-freq = 66000;
-- 
2.1.3

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Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem

[Javier Martinez Canillas]

Hello Joonyoung,

On 01/13/2015 06:24 AM, Joonyoung Shim wrote:
 
 Yes, I was not able to trigger that by running modetest but by turning off
 my HDMI monitor and then turning it on again. When the monitor is turned
 on then I see a Power domain power-domain disable failed and the imprecise
 external abort error.
 
 I had to disable CONFIG_DRM_EXYNOS_DP in order to trigger though and that
 is why I was not able to reproduce it before.
 
 I think though that this is a separate issue of the HDMI not working since
 power domains should be able to have many consumers devices and I see that
 other power domains are used that way.
 
 
 OK, we need more investigation.


I dug further on this issue and found that the cause is that the exynos_mixer
driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
to be kept enabled after hdmi_poweroff (drivers/gpu/drm/exynos/exynos_hdmi.c).

Otherwise, any access to mixer device registers leads to an imprecise external
abort error. The following change [0] to the Exynos DRM HDMI driver makes the
issue to not happen and I can successfully execute:

# echo 1  /sys/devices/platform/exynos-drm/graphics/fb0/blank
# echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank

Only not disabling the hdmi clock [1]: is enough but doing so makes sometimes 
the
DISP1 power domain disabling fails. It doesn't seem to have side effect though
since I also see the signal in the HDMI display to go standby and then on again.

# echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank
# echo 1  /sys/devices/platform/exynos-drm/graphics/fb0/blank
[   63.089080] Power domain disp1-power-domain disable failed
# echo 0  /sys/devices/platform/exynos-drm/graphics/fb0/blank
#

That error message when both clocks are not disabled on hdmi_poweroff() though.

I tried different things like set parent of mixer clock to hdmi clock instead
of aclk200_disp1 or make the Exynos DRM mixer driver to grab the hdmi clock
from  DT and prepare_enable from mixer_poweron() but in all cases the same
imprecise external abort error was triggered by mixer_poweron() trying to access
the mixer registers.

Any ideas?

Thanks a lot and best regards,
Javier

[0]:
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5765a161abdd..0887911cfdd5 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -2084,8 +2084,8 @@ static void hdmi_poweroff(struct exynos_drm_display 
*display)
 
cancel_delayed_work(hdata-hotplug_work);
 
-   clk_disable_unprepare(res-sclk_hdmi);
-   clk_disable_unprepare(res-hdmi);
 
/* reset pmu hdmiphy control bit to disable hdmiphy */
regmap_update_bits(hdata-pmureg, PMU_HDMI_PHY_CONTROL,


[1]:
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5765a161abdd..628bff96d543 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -2085,7 +2085,7 @@ static void hdmi_poweroff(struct exynos_drm_display 
*display)
cancel_delayed_work(hdata-hotplug_work);
 
clk_disable_unprepare(res-sclk_hdmi);
-   clk_disable_unprepare(res-hdmi);
 
/* reset pmu hdmiphy control bit to disable hdmiphy */
regmap_update_bits(hdata-pmureg, PMU_HDMI_PHY_CONTROL,
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